Method for preparing semiconductor device and semiconductor device

Abstract

The present application discloses a method for preparing a semiconductor device and a semiconductor device, the method comprising: providing a substrate, wherein the substrate has a first shallow trench isolation region and a second shallow trench isolation region, wherein the trench width of the second shallow trench isolation region is greater than the trench width of the first shallow trench isolation region; forming a plurality of mutually isolated polysilicon pseudo gates above the first shallow trench isolation region, above the second shallow trench isolation region, and above the active regions on both sides of the first shallow trench isolation region; using a metal gate to replace the polysilicon pseudo gate above the first shallow trench isolation region and above the active regions on both sides of the first shallow trench isolation region, and using the remaining polysilicon pseudo gate above the second shallow trench isolation region as a polysilicon gate; forming contact holes above the metal gate and above the polysilicon gate. Compared with the prior art, the present application has the unexpected technical effect that the metal gate and the polysilicon gate can be formed simultaneously, reducing the process complexity and improving the process integration.

Description

Technical Field

[0001] The present application generally relates to the field of semiconductor device manufacturing technology. More specifically, the present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] The semiconductor industry has made significant progress as the wafer process line width has been upgraded to 28nm or even 22nm. In this process, high-dielectric metal gate technology has replaced traditional polysilicon gates, and this change has greatly improved the device density in integrated circuits. However, this increase in density has also brought new challenges. As the device size decreases, the resistance and capacitance effects become more significant in a smaller space, which slows down the switching speed of the device and reduces the performance of the device.

[0003] In the prior art, in order to solve the above problems, a titanium nitride (TiN) film is additionally added above the passive area of ​​the device during the device preparation process to form a high-resistance (Hi-Z or Hi-R) layer structure to achieve the purpose of dividing the gate voltage and improving device performance.

[0004] However, in the process of preparing titanium nitride (TiN) film, a mask is required, which increases the process steps such as etching, and further increases the process cost. Moreover, titanium nitride (TiN) film is an interlayer structure, and the surface is uneven after coating, which requires an additional interlayer structure chemical mechanical polishing process, which increases the non-uniformity of the process, thereby affecting the non-uniformity of the device speed inside the wafer. In addition, the titanium nitride (TiN) film is very thin, and there is a risk of over-etching when forming the connection contact hole, which compresses the contact hole etching process window.

[0005] In view of this, there is an urgent need to provide a semiconductor device preparation solution so as to simultaneously form a metal gate and a polysilicon gate, reduce process complexity, improve process integration, and avoid over-etching problems in the process of forming contact holes. Summary of the invention

[0006] In order to at least solve one or more of the technical problems mentioned above, the present application proposes a semiconductor device preparation scheme and a corresponding semiconductor device in multiple aspects.

[0007] In a first aspect, the present application provides a method for preparing a semiconductor device, comprising: Providing a substrate, wherein the substrate has a first shallow trench isolation region and a second shallow trench isolation region, wherein the trench width of the second shallow trench isolation region is greater than the trench width of the first shallow trench isolation region; forming a plurality of mutually isolated polysilicon dummy gates above the first shallow trench isolation region, above the second shallow trench isolation region, and above the active regions on both sides of the first shallow trench isolation region; Using a metal gate to replace the polysilicon dummy gate above the first shallow trench isolation region and above the active area on both sides of the first shallow trench isolation region, and using the remaining polysilicon dummy gate above the second shallow trench isolation region as a polysilicon gate; Contact holes are formed over the metal gate and over the polysilicon gate.

[0008] In some embodiments, an upper surface of the second shallow trench isolation region is lower than an upper surface of the substrate, and a distance between an upper surface of the second shallow trench isolation region and an upper surface of the substrate is 250Å-350Å.

[0009] In some embodiments, using a metal gate to replace the polysilicon dummy gate above the first shallow trench isolation region and above the active regions on both sides of the first shallow trench isolation region includes: forming an etching stop layer covering all polysilicon dummy gates and areas between the polysilicon dummy gates; forming a first interlayer dielectric layer above the etch stop layer in the region between each polysilicon dummy gate; The polysilicon dummy gates above the first shallow trench isolation region and above the active regions on both sides of the first shallow trench isolation region are removed, and metal gates are formed in the regions where the polysilicon dummy gates are removed.

[0010] In some embodiments, forming a first interlayer dielectric layer above the etch stop layer in the region between each polysilicon dummy gate includes: depositing a first interlayer dielectric layer material over the etch stop layer in all regions; Planarizing the first interlayer dielectric layer material, the etch stop layer above the polysilicon dummy gate above the first shallow trench isolation region, and the etch stop layer above the polysilicon dummy gate above the active area on both sides of the first shallow trench isolation region, so as to form a first interlayer dielectric layer above the etch stop layer in the area between each polysilicon dummy gate; Wherein, the upper surface of the first interlayer dielectric layer is flush with the upper surface of the first shallow trench isolation region and the polysilicon dummy gate above the active regions on both sides of the first shallow trench isolation region; The upper surface of the first interlayer dielectric layer is flush with the upper surface of the etch stop layer above the polysilicon dummy gate above the second shallow trench isolation region.

[0011] In some embodiments, forming contact holes above the metal gate and above the polysilicon gate comprises: forming a second interlayer dielectric layer above the first interlayer dielectric layer, above the exposed etch stop layer, and above the metal gate; The second interlayer dielectric layer above the metal gate is etched, and the etching stop layer and the second interlayer dielectric layer above the polysilicon gate are etched to form contact holes respectively arranged above the metal gate and above the polysilicon gate.

[0012] In a second aspect, the present application further provides a semiconductor device, comprising: A substrate having a first shallow trench isolation region and a second shallow trench isolation region, wherein a trench width of the second shallow trench isolation region is greater than a trench width of the first shallow trench isolation region; at least one metal gate, the metal gate being disposed above the first shallow trench isolation region and above active regions on both sides of the first shallow trench isolation region; at least one polysilicon gate, the polysilicon gate being disposed above the second shallow trench isolation region; A contact hole is disposed above the metal gate and the polysilicon gate.

[0013] In some embodiments, an upper surface of the second shallow trench isolation region is lower than an upper surface of the substrate, and a distance between an upper surface of the second shallow trench isolation region and an upper surface of the substrate is 250Å-350Å.

[0014] In some embodiments, the semiconductor device further includes an etch stop layer, which covers the sidewalls of the metal gate, the sidewalls and a portion of the upper surface of the polysilicon gate, and at least covers the area between the metal gate and the polysilicon gate.

[0015] In some embodiments, the semiconductor device also includes a first interlayer dielectric layer, the first interlayer dielectric layer at least covers the upper surface of the etch stop layer in the area between the metal gate and the polysilicon gate, the upper surface of the first interlayer dielectric layer is flush with the upper surface of the metal gate and is flush with the upper surface of the etch stop layer above the polysilicon gate; a second interlayer dielectric layer, the second interlayer dielectric layer covers the upper surface of the first interlayer dielectric layer and covers a portion of the upper surface of the metal gate and the upper surface of the etch stop layer above the polysilicon gate.

[0016] In some embodiments, the contact hole is disposed in an area on the metal gate surface not covered by the second interlayer dielectric layer, and in an area on the polysilicon gate surface not covered by the etch stop layer and the second interlayer dielectric layer above the etch stop layer. Compared with the prior art, the unexpected technical effect of the present application is that the trench width of the second shallow trench isolation region is set to be greater than the trench width of the first shallow trench isolation region, which can meet the width requirements of the shallow trench isolation structure for semiconductor devices including different functional areas. Metal gates and polysilicon gates can be formed at the same time, reducing process complexity and improving process integration. When forming contact holes, there is no need to consider the problem of over-etching, which widens the process window of the contact hole manufacturing process.

[0017] The embodiment of the present application simultaneously forms a metal gate above the first shallow trench isolation region and above the active areas on both sides of the first shallow trench isolation region, and forms a polysilicon gate above the second shallow trench isolation region, which can reduce manufacturing costs, and can form different resistivities in different functional areas of the semiconductor device, increase the selectable range of resistivities of the semiconductor device, and improve the diversification of components. In the process of forming the metal gate, the etch stop layer is still retained above the polysilicon pseudo-gate in the second shallow trench isolation region, thereby avoiding damage to the polysilicon pseudo-gate in the second shallow trench isolation region. The polysilicon gate replaces titanium nitride as a high resistance area, which can reduce the cost of material use. By using a metal gate and a polysilicon gate, there is no need to consider the problem of over-etching when forming a contact hole, and the process window of the contact hole process can be widened. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] By reading the detailed description below with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present application will become easy to understand. In the accompanying drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein: Figure 1 An exemplary flowchart of a method for preparing a semiconductor device according to an embodiment of the present application is shown; Figure 2A A schematic cross-sectional structure diagram of a substrate provided with a shallow trench isolation region according to an embodiment of the present application is shown; Figure 2B A schematic cross-sectional structure diagram of forming a polysilicon dummy gate according to an embodiment of the present application is shown; Figure 2C A schematic cross-sectional structure diagram of forming an etch stop layer in an embodiment of the present application is shown; Figure 2D A schematic cross-sectional structure diagram of depositing a first interlayer dielectric layer material according to an embodiment of the present application is shown; Figure 2E A schematic cross-sectional structure diagram of planarizing the first interlayer dielectric layer material and a portion of the etch stop layer according to an embodiment of the present application is shown; Figure 2F A schematic cross-sectional structure diagram of an etched portion of a polysilicon dummy gate according to an embodiment of the present application is shown; Figure 2G A schematic cross-sectional structure diagram of a deposited metal gate material according to an embodiment of the present application is shown; Figure 2H A schematic cross-sectional structure diagram of a planarization process for a metal gate material according to an embodiment of the present application is shown; Fig.2I A schematic cross-sectional structure diagram of forming a second interlayer dielectric layer and a contact hole according to an embodiment of the present application is shown; Figure 2J A schematic cross-sectional structure diagram of forming a contact column according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0020] It should be understood that the terms "include" and "comprising" used in the specification and claims of the present application indicate the presence of described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0021] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in this application specification and claims, unless the context clearly indicates otherwise, the singular forms of "a", "an" and "the" are intended to include plural forms. It should also be further understood that the term "and / or" used in this application specification and claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0022] It should also be understood that, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," "on," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. When an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0023] The specific implementation of the present application is described in detail below with reference to the accompanying drawings.

[0024] Figure 1 An exemplary flowchart of a method 100 for preparing a semiconductor device according to an embodiment of the present application is shown.

[0025] like Figure 1 As shown, in step S110, a substrate is provided, wherein the substrate has a first shallow trench isolation region and a second shallow trench isolation region, wherein the trench width of the aforementioned second shallow trench isolation region is greater than the trench width of the aforementioned first shallow trench isolation region. Then, in step S120, a plurality of mutually isolated polysilicon dummy gates are formed above the first shallow trench isolation region, above the second shallow trench isolation region, and above the active regions on both sides of the first shallow trench isolation region. In step S130, a metal gate is used to replace the polysilicon dummy gate above the first shallow trench isolation region and above the active regions on both sides of the first shallow trench isolation region, and the remaining polysilicon dummy gate is used as a polysilicon gate. Then, in step S140, contact holes are formed above the metal gate and above the polysilicon gate.

[0026] based on Figure 1 The preparation method of the semiconductor device is as follows: Figure 2A-2J The schematic diagram of the semiconductor cross-sectional structure is shown, and an exemplary process flow of a method for preparing a semiconductor device using some embodiments of the present application is described in detail.

[0027] Figure 2A A schematic cross-sectional structure diagram of a substrate provided with a shallow trench isolation region according to an embodiment of the present application is shown.

[0028] like Figure 2A As shown, a substrate 210 is provided, wherein the substrate 210 has a first shallow trench isolation region 220 and a second shallow trench isolation region 230 . The first shallow trench isolation region 220 and the second shallow trench isolation region 230 are spaced apart from each other, so as to separate the substrate into a plurality of active regions 211 .

[0029] Specifically, the substrate 210 can provide an operating platform for subsequent processes, and can be any base material for carrying semiconductor integrated circuit components known to those skilled in the art, and can be a bare chip or a wafer processed by an epitaxial growth process.

[0030] Specifically, the substrate 210 may be a planar device or a fin-type device. For the fin-type device, fins are formed in the substrate 210 .

[0031] In one embodiment of the present application, the material of the substrate 210 is a material containing Si element, and specifically can be at least one of the following materials: Si, SiGe, SiC, SiGeC or other compound semiconductors containing Si element. The substrate 210 can be a semiconductor single-layer structure or a multi-layer structure composed of these materials. The substrate 210 can also be silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), etc.

[0032] In another embodiment of the present application, the material of the substrate 210 may also be a material that does not contain the Si element. The substrate 210 may be a germanium substrate, a silicon germanium substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate, etc.

[0033] Specifically, the first shallow trench isolation region 220 and the second shallow trench isolation region 230 may use the same dielectric material or different dielectric materials. The dielectric material used in the first shallow trench isolation region 220 and the second shallow trench isolation region 230 may be any suitable dielectric material known in the art, for example, it may be a combination of one or more of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), fluorosilicate glass, undoped silicate glass (USG) or tetraethyl orthosilicate, and this embodiment is not limited here.

[0034] In an embodiment of the present application, the first shallow trench isolation region 220 and the second shallow trench isolation region 230 can be made by various known processes, and the embodiments of the present application are not limited in this respect. For example, a buffer oxide layer (oxide) is first formed on the substrate, such as a silicon dioxide (SiO2) layer, and a nitride layer (nitride) is formed on the buffer oxide layer, such as a silicon nitride (Si3N4) layer. Then, a photoresist layer is formed on the nitride layer, and after exposure, development and other processes, a patterned photoresist layer is formed, and the patterned photoresist layer includes a first opening and a second opening. Among them, the width of the second opening is greater than the width of the first opening, and the first opening is used to locate the position of the first shallow trench isolation region 220, and the second opening is used to locate the position of the second shallow trench isolation region 230. Next, the patterned photoresist layer is used as a mask, and etching is performed toward the substrate 210 by dry etching or wet etching, for example, to form a first shallow trench and a second shallow trench, and the etching gas includes, for example, chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6) or hydrogen bromide (HBr), etc., or a mixture of them and oxygen (O2). After the first shallow trench and the second shallow trench are formed, the patterned photoresist layer is removed by wet cleaning or ashing. Due to the process loading effect, the deposition speed of the second shallow trench with a larger width is slower when the dielectric material is deposited, resulting in the upper surface of the second shallow trench isolation region 230 being lower than the upper surface of the substrate 210 during the formation of the second shallow trench isolation region 230. Thus, the upper surface of the first shallow trench isolation region 220 is flush with the upper surface of the substrate 210 (that is, the lower surface of the buffer oxide layer), and the upper surface of the second shallow trench isolation region 230 is lower than the upper surface of the substrate 210 (that is, the lower surface of the buffer oxide layer). After forming the first shallow trench isolation region 220 and the second shallow trench isolation region 230, the buffer oxide layer and the nitride layer on the surface of the substrate are removed.

[0035] Specifically, the distance between the upper surface of the second shallow trench isolation region 230 and the upper surface of the substrate 210 is 250Å-350Å.

[0036] Because the upper surface of the second shallow trench isolation region 230 is lower than the upper surface of the substrate 210, an etch stop layer can be retained above the polysilicon dummy gate of the second shallow trench isolation region 230 during the subsequent preparation of the metal gate, thereby avoiding damage to the polysilicon dummy gate above the second shallow trench isolation region 230.

[0037] In addition, it should be noted that due to the load effect, changes in the size, shape or pattern density of the etched area will cause changes in the etching rate, that is, the first shallow trench isolation area and the second shallow trench isolation area of ​​different widths will have depth differences. The load effect can be effectively suppressed and the consistency of etching depth can be improved by adjusting the composition and flow rate of the etching gas, ensuring sufficient supply of reactants, and using advanced etching technologies such as reactive ion etching (RIE) or plasma enhanced chemical vapor deposition (PECVD) to improve the accuracy and stability of etching.

[0038] The above-mentioned preparation process of the first shallow trench isolation region 220 and the second shallow trench isolation region 230 makes the trench width of the second shallow trench isolation region 230 greater than the trench width of the first shallow trench isolation region 220 .

[0039] By making the trench width of the second shallow trench isolation region 230 greater than the trench width of the first shallow trench isolation region 220, the substrate 210 is divided into different regions. When the finally formed semiconductor device has different functional areas, the width requirement of the finally formed semiconductor device for the shallow trench isolation structure can be met, and different semiconductor structures can be arranged in different shallow trench isolation regions according to the requirements of the finally formed semiconductor device.

[0040] In one embodiment of the present application, the substrate 210 may also undergo some other preparation processes or manufacturing processes, and may also have other semiconductor structures thereon, and the embodiment of the present application is not limited in this regard.

[0041] Figure 2B A schematic cross-sectional structure diagram of forming a polysilicon dummy gate according to an embodiment of the present application is shown.

[0042] like Figure 2B As shown, a plurality of mutually isolated polysilicon dummy gates 240 are formed above the first shallow trench isolation region 220 , above the second shallow trench isolation region 230 , and above the active regions 211 on both sides of the first shallow trench isolation region 220 .

[0043] In the embodiments of the present application, the polysilicon pseudo gate 240 can be made by various known processes, and the embodiments of the present application are not limited in this respect. For example, first, a polysilicon pseudo gate layer is deposited above the first shallow trench isolation region 220, above the second shallow trench isolation region 230, and above the active area 211 on both sides of the first shallow trench isolation region 220, wherein the polysilicon pseudo gate layer can be a one-layer or multi-layer structure, and the polysilicon pseudo gate layer can be formed by a chemical vapor deposition (CVD) process. Then, a photoresist layer is formed on the polysilicon pseudo gate layer, and the photoresist layer is exposed and developed to form a patterned photoresist layer. Then, using the patterned photoresist layer as a mask, and using the first shallow trench isolation region 220, the second shallow trench isolation region 230, and the active region 211 on both sides of the first shallow trench isolation region 220 as etching stop layers, the polysilicon dummy gate layer is etched by, for example, a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process to form a plurality of mutually isolated polysilicon dummy gates 240. After the polysilicon dummy gates 240 are formed, the patterned photoresist layer is removed.

[0044] Specifically, the height of the polysilicon dummy gate above the first shallow trench isolation region 220 is the same as the height of the polysilicon dummy gate above the active area 211 on both sides of the first shallow trench isolation region 220, and the height of the polysilicon dummy gate above the second shallow trench isolation region 230 may be the same as or different from the height of the polysilicon dummy gate above the first shallow trench isolation region 220 and the height of the polysilicon dummy gate above the active area 211 on both sides of the first shallow trench isolation region 220.

[0045] Specifically, the upper surface of the polysilicon dummy gate above the first shallow trench isolation region 220 is flush with the upper surface of the polysilicon dummy gate above the active area 211 on both sides of the first shallow trench isolation region 220, and the distance between the upper surface of the polysilicon dummy gate above the second shallow trench isolation region 230 and the upper surface of the polysilicon dummy gate above the first shallow trench isolation region 220 is h. As described below, in one embodiment, the thickness of h can be 200Å-300Å.

[0046] After forming the polysilicon pseudo gate, the following Figure 2C-2H The schematic diagram of the semiconductor cross-sectional structure shown in FIG. 1 describes in detail an exemplary process flow of replacing the polysilicon dummy gate above the first shallow trench isolation region 220 and above the active region 211 on both sides of the first shallow trench isolation region 220 with a metal gate.

[0047] Figure 2C A schematic cross-sectional structure diagram of forming an etch stop layer according to an embodiment of the present application is shown.

[0048] like Figure 2C As shown, an etch stop layer 250 is formed to cover all polysilicon dummy gates 240 and the regions between the polysilicon dummy gates.

[0049] Specifically, the material of the etch stop layer 250 may be silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), or the like.

[0050] Specifically, the thickness of the etch stop layer 250 is equal to the distance between the upper surface of the polysilicon dummy gate above the second shallow trench isolation region 230 and the upper surface of the polysilicon dummy gate above the first shallow trench isolation region 220, that is, the thickness of the etch stop layer 250 is equal to h.

[0051] The thickness of the etch stop layer 250 is equal to the distance between the polysilicon dummy gate above the second shallow trench isolation region 230 and the polysilicon dummy gate above the first shallow trench isolation region 220. In the subsequent process of preparing the metal gate, the etching can be stopped on the etch stop layer above the polysilicon dummy gate of the second shallow trench isolation region 230, on the polysilicon dummy gate above the first shallow trench isolation region 220, and on the polysilicon dummy gate above the active area 211 on both sides of the first shallow trench isolation region 220. The complexity of the etching process can be reduced, and the etch stop layer is retained above the polysilicon dummy gate of the second shallow trench isolation region 230, thereby avoiding damage to the polysilicon dummy gate above the second shallow trench isolation region 230.

[0052] Specifically, when the height of the polysilicon dummy gate above the second shallow trench isolation region 230 is the same as the height of the polysilicon dummy gate above the first shallow trench isolation region 220 and the height of the polysilicon dummy gate above the active region 211 on both sides of the first shallow trench isolation region 220, the thickness of the etch stop layer 250 is also equal to the distance between the upper surface of the second shallow trench isolation region 230 and the upper surface of the substrate 210. When the height of the polysilicon dummy gate above the second shallow trench isolation region 230 is different from the height of the polysilicon dummy gate above the first shallow trench isolation region 220 and the height of the polysilicon dummy gate above the active region 211 on both sides of the first shallow trench isolation region 220, the thickness of the etch stop layer 250 is not equal to the distance between the upper surface of the second shallow trench isolation region 230 and the upper surface of the substrate 210.

[0053] Figure 2D A schematic cross-sectional structure diagram of depositing a first interlayer dielectric layer material according to an embodiment of the present application is shown.

[0054] like Figure 2D As shown, a first interlayer dielectric material 260 is deposited over the etch stop layer 250 .

[0055] Specifically, the first interlayer dielectric layer material 260 may be phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), a silicon oxide layer (formed using tetraethyl orthosilicate (TEOS)), or a combination thereof. The first interlayer dielectric layer material 260 may also be carbon silicon oxyhydride (SiCOH), which may include porous SiCOH.

[0056] Specifically, the first interlayer dielectric layer material 260 can be deposited by spin coating, atomic layer deposition (ALD), flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.

[0057] Figure 2E A schematic cross-sectional structure diagram of planarizing the first interlayer dielectric layer material and a portion of the etch stop layer according to an embodiment of the present application is shown.

[0058] like Figure 2E As shown, the deposited first interlayer dielectric layer material 260, the etch stop layer above the polysilicon dummy gate above the first shallow trench isolation region 220, and the etch stop layer above the polysilicon dummy gate above the active area 211 on both sides of the first shallow trench isolation region 220 are planarized, thereby forming a first interlayer dielectric layer 260 above the etch stop layer in the area between each polysilicon dummy gate 240.

[0059] Specifically, the upper surface of the first interlayer dielectric layer 260 is flush with the upper surface of the polysilicon dummy gate above the first shallow trench isolation region 220, the upper surface of the polysilicon dummy gate above the active area 211 on both sides of the first shallow trench isolation region 220, and the upper surface of the etch stop layer above the polysilicon dummy gate of the second shallow trench isolation region 230.

[0060] Specifically, the deposited first interlayer dielectric layer material 260, the etch stop layer above the polysilicon dummy gate above the first shallow trench isolation region 220, and the etch stop layer above the polysilicon dummy gate above the active area 211 on both sides of the first shallow trench isolation region 220 are planarized at the same time. While forming the first interlayer dielectric layer 260, the etch stop layer above the polysilicon dummy gate above the first shallow trench isolation region 220 and the etch stop layer above the polysilicon dummy gate above the active area 211 on both sides of the first shallow trench isolation region 220 are removed.

[0061] Specifically, since the thickness of the etch stop layer 250 is equal to the distance between the polysilicon dummy gate above the second shallow trench isolation region 230 and the polysilicon dummy gate above the first shallow trench isolation region 220, during the planarization process, the etch stop layer is retained above the polysilicon dummy gate of the second shallow trench isolation region 230, thereby avoiding damage to the polysilicon dummy gate above the second shallow trench isolation region 230.

[0062] Specifically, in the process of planarizing the first interlayer dielectric layer material and a portion of the etch stop layer, a chemical mechanical polishing (CMP) process may be used.

[0063] Figure 2F A schematic cross-sectional structure diagram of an etched portion of a polysilicon dummy gate according to an embodiment of the present application is shown.

[0064] like Figure 2F As shown, the polysilicon dummy gate above the first shallow trench isolation region 220 and the polysilicon dummy gate above the active area 211 on both sides of the first shallow trench isolation region 220 are etched away by a dummy poly remove (DPRM) process, and the remaining polysilicon dummy gate is used as the polysilicon gate 240.

[0065] Specifically, in the process of etching and removing the polysilicon dummy gate above the first shallow trench isolation region 220 and the polysilicon dummy gate above the active area 211 on both sides of the first shallow trench isolation region 220, etching is stopped on the upper surface of the first shallow trench isolation region 220, the etch stop layer on both sides of the polysilicon dummy gate above the first shallow trench isolation region 220, the upper surface of the active area 211 on both sides of the first shallow trench isolation region 220, and the etch stop layer on both sides of the polysilicon dummy gate above the active area 211 on both sides of the first shallow trench isolation region 220.

[0066] The etching area in the aforementioned etching process can be better defined by the upper surface of the first shallow trench isolation region 220, the etching stop layer on both sides of the polysilicon pseudo gate above the first shallow trench isolation region 220, the upper surface of the active area 211 on both sides of the first shallow trench isolation region 220, and the etching stop layer on both sides of the polysilicon pseudo gate above the active area 211 on both sides of the first shallow trench isolation region 220, thereby reducing the difficulty of etching.

[0067] Figure 2G A schematic cross-sectional structure diagram of a deposited metal gate material according to an embodiment of the present application is shown.

[0068] like Figure 2GAs shown, in the area where the polysilicon dummy gate above the first shallow trench isolation area 220 is etched and removed, and in the area where the polysilicon dummy gate above the active area 211 on both sides of the first shallow trench isolation area 220 is etched and removed, a metal gate material 270 is deposited above the etch stop layer above the first shallow trench isolation area 220, above the first interlayer dielectric layer above the first shallow trench isolation area 220, above the etch stop layer above the active area 211 on both sides of the first shallow trench isolation area 220, above the first interlayer dielectric layer above the active area 211 on both sides of the first shallow trench isolation area 220, above the etch stop layer above the polysilicon gate 240, and above the first interlayer dielectric layer above the second shallow trench isolation area 230.

[0069] In some embodiments of the present application, the metal gate material may be deposited only in the area where the polysilicon dummy gate above the first shallow trench isolation area 220 is etched away, and in the area where the polysilicon dummy gate above the active area 211 on both sides of the first shallow trench isolation area 220 is etched away, or the metal gate material may be deposited only in the area where the polysilicon dummy gate above the first shallow trench isolation area 220 is etched away, and in the area where the polysilicon dummy gate above the active area 211 on both sides of the first shallow trench isolation area 220 is etched away, and in other parts of the area, but it is necessary to ensure that the deposited metal gate material covers the area where the polysilicon dummy gate above the first shallow trench isolation area 220 is etched away, and the area where the polysilicon dummy gate above the active area 211 on both sides of the first shallow trench isolation area 220 is etched away.

[0070] Specifically, the metal gate material 270 may include at least one of copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tungsten (W), tungsten nitride (WN) and molybdenum nitride (MoN).

[0071] Figure 2H A schematic cross-sectional structure diagram of planarizing a metal gate material according to an embodiment of the present application is shown.

[0072] like Figure 2H As shown, the deposited metal gate material 270 is planarized to form a metal gate 270 in the area where the polysilicon dummy gate above the first shallow trench isolation area 220 is etched away and in the area where the polysilicon dummy gate above the active area 211 on both sides of the first shallow trench isolation area 220 is etched away.

[0073] Specifically, the upper surface of the metal gate 270 is flush with the upper surface of the first interlayer dielectric layer 260 above the first shallow trench isolation region 220 and the upper surface of the first interlayer dielectric layer 260 above the active regions 211 on both sides of the first shallow trench isolation region 220 .

[0074] A metal gate 270 is formed in the region where the polysilicon pseudo gate above the first shallow trench isolation region 220 is etched away, and in the region where the polysilicon pseudo gate above the active region 211 on both sides of the first shallow trench isolation region 220 is etched away. The metal gate 270 can be used to replace the polysilicon pseudo gate above the first shallow trench isolation region and above the active region on both sides of the first shallow trench isolation region, and the remaining polysilicon pseudo gate is used as the polysilicon gate, thereby realizing the simultaneous formation of the metal gate and the polysilicon gate, reducing the process complexity and improving the process integration. Different resistivities can be formed in different functional areas of the semiconductor device, specifically, a smaller resistivity is formed in the first shallow trench isolation region 220 of the semiconductor device, and a larger resistivity is formed in the second shallow trench isolation region 230. As a result, the selectable range of resistivity of the semiconductor device is increased, and the diversification of components is improved.

[0075] At the same time, by forming a metal gate 270 in the area where the polysilicon dummy gate above the first shallow trench isolation area 220 is etched away and in the area where the polysilicon dummy gate above the active area 211 on both sides of the first shallow trench isolation area 220 is etched away, there is no need to perform additional chemical mechanical polishing on the first interlayer dielectric layer 260, thereby reducing the non-uniformity of the internal structure of the wafer and increasing the uniformity of the speed of the devices inside the wafer.

[0076] Specifically, a chemical mechanical polishing (CMP) process may be used during the planarization process of the metal gate material.

[0077] After the metal gate 270 is formed, a contact hole is formed over the metal gate 270 and over the polysilicon gate 240 .

[0078] Fig.2I A schematic cross-sectional structure diagram of forming a second interlayer dielectric layer and a contact hole according to an embodiment of the present application is shown.

[0079] like Fig.2I As shown, a second interlayer dielectric layer 280 is formed above the first interlayer dielectric layer 260, above the exposed etch stop layer 250 and above the metal gate 270, and the second interlayer dielectric layer 280 above the metal gate 270, the etch stop layer and the second interlayer dielectric layer 280 above the polysilicon gate 240 are etched to form a contact hole 290 above the metal gate 270 and above the polysilicon gate 240.

[0080] Specifically, the material used in the second interlayer dielectric layer 280 may be the same as or different from the material used in the first interlayer dielectric layer 260. The material used in the second interlayer dielectric layer 280 may be phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), a silicon oxide layer (formed using tetraethyl orthosilicate (TEOS)), or a combination thereof. The second interlayer dielectric layer 280 may also be carbon silicon oxyhydride (SiCOH), which may include porous SiCOH.

[0081] Specifically, the process used in the formation of the second interlayer dielectric layer 280 may be the same as the process used in the formation of the first interlayer dielectric layer 260 , and will not be repeated here.

[0082] Specifically, the contact hole 290 is made by various known processes, and the embodiments of the present application are not limited in this respect. For example, first, a photoresist is spin-coated on the second interlayer dielectric layer 280 and the photoresist is exposed and developed to form a mask pattern. Under the protection of the mask pattern, the second interlayer dielectric layer 280 and the etching stop layer above the polysilicon gate 240 are etched by etching liquid or plasma gas to form the contact hole 290.

[0083] Specifically, since a metal gate and a polysilicon gate are used, there is no need to consider the over-etching problem when forming the contact hole 290 , and the process window of the contact hole manufacturing process can be widened.

[0084] In one embodiment of the present application, after the contact hole is formed, the contact hole is filled to form a contact column.

[0085] Figure 2J A schematic cross-sectional structure diagram of forming a contact column according to an embodiment of the present application is shown.

[0086] like Figure 2J As shown, after the contact hole is formed, the contact hole is filled to form a contact column 291.

[0087] Specifically, a metal material may be deposited in the contact hole by chemical vapor deposition to form the contact pillar 291, and the deposited metal material may be copper metal or aluminum metal, etc. In the process of filling the contact hole, the metal material may be deposited to overflow the contact hole. Then, the surface of the metal material is flattened by chemical mechanical polishing (CMP) so that the upper surface of the formed contact pillar 291 is flush with the upper surface of the second interlayer dielectric layer 280.

[0088] Specifically, the contact pillar 291 is connected to the metal gate 270 and the polysilicon gate 240 .

[0089] In the embodiment of the present application, after the contact pillar 291 is formed, a metal interconnection structure may be formed on the second interlayer dielectric layer 280 to complete the subsequent preparation of the device.

[0090] In summary, compared with the prior art, the unexpected technical effect of the present application is that by setting the trench width of the second shallow trench isolation region to be greater than the trench width of the first shallow trench isolation region, the width requirements of the shallow trench isolation structure for semiconductor devices including different functional areas can be met. Metal gates and polysilicon gates can be formed simultaneously, reducing process complexity and improving process integration. When forming contact holes, there is no need to consider the problem of over-etching, which widens the process window of the contact hole manufacturing process.

[0091] The embodiment of the present application forms a metal gate simultaneously above the first shallow trench isolation region and above the active regions on both sides of the first shallow trench isolation region, and forms a polysilicon gate above the second shallow trench isolation region, thereby reducing manufacturing costs, forming different resistivities in different functional regions of the semiconductor device, increasing the selectable range of resistivities of the semiconductor device, and improving the diversification of components. In the process of forming the metal gate, an etch stop layer is still retained above the polysilicon pseudo-gate in the second shallow trench isolation region, thereby avoiding damage to the polysilicon pseudo-gate in the second shallow trench isolation region. By replacing titanium nitride as a high resistance region with a polysilicon gate, the cost of using materials can be reduced. By using a metal gate and a polysilicon gate, there is no need to consider the problem of over-etching when forming a contact hole, and the process window of the contact hole process can be widened.

[0092] An embodiment of the present application also provides a semiconductor device, which includes: a substrate, having a first shallow trench isolation region and a second shallow trench isolation region, wherein the trench width of the second shallow trench isolation region is greater than the trench width of the first shallow trench isolation region; at least one metal gate, the metal gate being arranged above the first shallow trench isolation region and above the active areas on both sides of the first shallow trench isolation region; at least one polysilicon gate, the polysilicon gate being arranged above the second shallow trench isolation region; and a contact hole, the contact hole being arranged above the metal gate and the polysilicon gate.

[0093] In an embodiment of the present application, an upper surface of the aforementioned second shallow trench isolation region is lower than an upper surface of the substrate.

[0094] Specifically, the distance between the upper surface of the aforementioned second shallow trench isolation region and the upper surface of the substrate is 250Å-350Å.

[0095] In an embodiment of the present application, the semiconductor device may further include an etch stop layer, which covers the sidewalls of the aforementioned metal gate, the sidewalls and a portion of the upper surface of the aforementioned polysilicon gate, and at least covers the area between the metal gate and the polysilicon gate.

[0096] Specifically, when the number of metal gates and the number of polysilicon gates are both one, the etch stop layer covers the side walls of the metal gate, the side walls and a portion of the upper surface of the polysilicon gate, and the area between the metal gate and the polysilicon gate; when the number of metal gates is one and the number of polysilicon gates is multiple, the etch stop layer covers the side walls of the metal gate, the side walls and a portion of the upper surface of the polysilicon gate, and also covers the area between the metal gate and the polysilicon gate, and the area between each polysilicon gate; when the number of metal gates is multiple and the number of polysilicon gates is one, the etch stop layer covers the side walls of the metal gate, the side walls and a portion of the upper surface of the polysilicon gate, and also covers the area between the metal gate and the polysilicon gate, and the area between each metal gate; when the number of metal gates and polysilicon gates are both multiple, the etch stop layer covers the side walls of the metal gate, the side walls and a portion of the upper surface of the polysilicon gate, and also covers the area between the metal gate and the polysilicon gate, the area between each metal gate, and the area between each polysilicon gate.

[0097] Specifically, the thickness of the aforementioned etch stop layer is equal to the distance between the upper surface of the polysilicon gate and the upper surface of the metal gate. More specifically, the thickness of the etch stop layer is 200Å-300Å.

[0098] In an embodiment of the present application, the semiconductor device may further include a first interlayer dielectric layer, wherein the first interlayer dielectric layer at least covers an upper surface of the etch stop layer in a region between the metal gate and the polysilicon gate.

[0099] Specifically, when the number of metal gates and the number of polysilicon gates are both one, the first interlayer dielectric layer covers the upper surface of the etch stop layer in the area between the aforementioned metal gate and the aforementioned polysilicon gate; when the number of metal gates is one and the number of polysilicon gates is multiple, the first interlayer dielectric layer covers the upper surface of the etch stop layer in the area between the metal gate and the polysilicon gate, and also covers the upper surface of the etch stop layer in the area between each polysilicon gate; when the number of metal gates is multiple and the number of polysilicon gates is one, the first interlayer dielectric layer covers the upper surface of the etch stop layer in the area between the metal gate and the polysilicon gate, and also covers the upper surface of the etch stop layer in the area between each metal gate; when the number of metal gates and polysilicon gates are both multiple, the first interlayer dielectric layer covers the upper surface of the etch stop layer in the area between the metal gate and the polysilicon gate, and also covers the upper surface of the etch stop layer in the area between each metal gate and the upper surface of the etch stop layer in the area between each polysilicon gate.

[0100] Specifically, the upper surface of the first interlayer dielectric layer is flush with the upper surface of the metal gate, and is flush with the upper surface of the etching stop layer above the polysilicon gate.

[0101] In an embodiment of the present application, the semiconductor device may further include a second interlayer dielectric layer, which covers the upper surface of the first interlayer dielectric layer and covers a portion of the upper surface of the metal gate and the upper surface of the etch stop layer above the polysilicon gate.

[0102] Specifically, the contact hole is arranged in an area on the upper surface of the metal gate not covered by the second interlayer dielectric layer, and also in an area on the upper surface of the polysilicon gate not covered by the etch stop layer and the second interlayer dielectric layer above the etch stop layer.

[0103] In one embodiment of the present application, the aforementioned semiconductor device can be manufactured by using a semiconductor device manufacturing method 100 provided in an embodiment of the present application.

[0104] Specifically, the structure diagram of the semiconductor device can be referred to Figure 2A-2JThe semiconductor device comprises: a substrate 210, wherein the substrate 210 has a first shallow trench isolation region 220 and a second shallow trench isolation region 230, wherein the trench width of the second shallow trench isolation region 230 is greater than the trench width of the first shallow trench isolation region 220, wherein the upper surface of the second shallow trench isolation region 230 is lower than the upper surface of the substrate 210; a plurality of metal gates 270, wherein the metal gates 270 are arranged above the first shallow trench isolation region 220 and above the active regions on both sides of the first shallow trench isolation region 220; a plurality of polysilicon The gate 240, the polysilicon gate 240 is arranged above the second shallow trench isolation region 230; the etch stop layer 250, the etch stop layer 250 covers the sidewalls of the metal gate 270, the sidewalls and a portion of the upper surface of the polysilicon gate 240, and covers the areas between the multiple metal gates 270, between the multiple polysilicon gates 240, and between the metal gate 270 and the polysilicon gate 240, wherein the thickness of the etch stop layer 250 is equal to the distance between the upper surface of the polysilicon gate and the upper surface of the metal gate; the first interlayer dielectric layer 260, the first interlayer dielectric layer 261, the second interlayer dielectric layer 262, the second interlayer dielectric layer 263, the second interlayer dielectric layer 264, the second interlayer dielectric layer 265, the second interlayer dielectric layer 266, the second interlayer dielectric layer 267, the second interlayer dielectric layer 268, the second interlayer dielectric layer 269, the second interlayer dielectric layer 270, the second interlayer dielectric layer 271, the second interlayer dielectric layer 272, the second interlayer dielectric layer 273, the second interlayer dielectric layer 274, the second interlayer dielectric layer 275, the second interlayer dielectric layer 276, the second interlayer dielectric layer 277, the second interlayer dielectric layer 278, the second interlayer dielectric layer 279, the second interlayer dielectric layer 280, the second interlayer dielectric layer 281, the second interlayer dielectric layer 282, the second interlayer dielectric layer 283, the second interlayer dielectric layer 284, An interlayer dielectric layer 260 covers the upper surface of the etch stop layer 250 in the area between each metal gate 270, the upper surface of the etch stop layer 250 in the area between the metal gate 270 and the polysilicon gate 240, and the upper surface of the etch stop layer 250 in the area between each polysilicon gate 240, wherein the upper surface of the first interlayer dielectric layer 260 is flush with the upper surface of the metal gate 270 and is flush with the upper surface of the etch stop layer 250 above the polysilicon gate 240; a second interlayer dielectric layer 280, the second interlayer dielectric layer 280 covers the front The upper surface of the first interlayer dielectric layer 260 is covered, and covers a portion of the upper surface of the aforementioned metal gate 270 and the upper surface of the etching stop layer 250 above the aforementioned polysilicon gate 240; the contact hole 290 is arranged above the metal gate 270 and the aforementioned polysilicon gate 240, specifically arranged in the area where the upper surface of the metal gate 270 is not covered by the second interlayer dielectric layer 280, and arranged in the area where the upper surface of the aforementioned polysilicon gate 240 is not covered by the etching stop layer 250 and the second interlayer dielectric layer 280 above the etching stop layer 250.

[0105] After the semiconductor device is obtained, the contact holes can be filled on the basis of this structure to form contact pillars, and then a metal interconnection structure can be formed on the second interlayer dielectric layer to obtain a further semiconductor device.

[0106] Although multiple embodiments of the present application have been shown and described herein, it is obvious to those skilled in the art that such embodiments are provided only by way of example. Those skilled in the art can think of many changes, modifications and alternatives without departing from the thought and spirit of the present application. It should be understood that in the process of practicing the present application, various alternatives to the embodiments of the present application described herein can be adopted. The attached claims are intended to limit the scope of protection of the present application, and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, wherein the substrate has a first shallow trench isolation region and a second shallow trench isolation region, wherein the trench width of the second shallow trench isolation region is greater than the trench width of the first shallow trench isolation region; forming a plurality of mutually isolated polysilicon dummy gates above the first shallow trench isolation region, above the second shallow trench isolation region, and above the active regions on both sides of the first shallow trench isolation region; Using a metal gate to replace the polysilicon dummy gate above the first shallow trench isolation region and above the active area on both sides of the first shallow trench isolation region, and using the remaining polysilicon dummy gate above the second shallow trench isolation region as a polysilicon gate; Contact holes are formed over the metal gate and over the polysilicon gate.

2. The preparation method according to claim 1, characterized in that: The upper surface of the second shallow trench isolation region is lower than the upper surface of the substrate, and the distance between the upper surface of the second shallow trench isolation region and the upper surface of the substrate is 250Å-350Å.

3. The preparation method according to claim 1, characterized in that: Using a metal gate to replace the polysilicon dummy gate above the first shallow trench isolation region and above the active regions on both sides of the first shallow trench isolation region includes: forming an etching stop layer covering all polysilicon dummy gates and areas between the polysilicon dummy gates; forming a first interlayer dielectric layer above the etch stop layer in the region between each polysilicon dummy gate; The polysilicon dummy gates above the first shallow trench isolation region and above the active regions on both sides of the first shallow trench isolation region are removed, and metal gates are formed in the regions where the polysilicon dummy gates are removed.

4. The preparation method according to claim 3, characterized in that: Forming a first interlayer dielectric layer above the etch stop layer in the region between each polysilicon dummy gate comprises: depositing a first interlayer dielectric layer material over the etch stop layer in all regions; Planarizing the first interlayer dielectric layer material, the etch stop layer above the polysilicon dummy gate above the first shallow trench isolation region, and the etch stop layer above the polysilicon dummy gate above the active area on both sides of the first shallow trench isolation region, so as to form a first interlayer dielectric layer above the etch stop layer in the area between each polysilicon dummy gate; Wherein, the upper surface of the first interlayer dielectric layer is flush with the upper surface of the first shallow trench isolation region and the polysilicon dummy gate above the active regions on both sides of the first shallow trench isolation region; The upper surface of the first interlayer dielectric layer is flush with the upper surface of the etch stop layer above the polysilicon dummy gate above the second shallow trench isolation region.

5. The preparation method according to claim 3, characterized in that: Forming contact holes above the metal gate and above the polysilicon gate includes: forming a second interlayer dielectric layer above the first interlayer dielectric layer, above the exposed etch stop layer, and above the metal gate; The second interlayer dielectric layer above the metal gate is etched, and the etching stop layer and the second interlayer dielectric layer above the polysilicon gate are etched to form contact holes respectively arranged above the metal gate and above the polysilicon gate.

6. A semiconductor device, characterized in that: The semiconductor device comprises: A substrate having a first shallow trench isolation region and a second shallow trench isolation region, wherein a trench width of the second shallow trench isolation region is greater than a trench width of the first shallow trench isolation region; at least one metal gate, the metal gate being disposed above the first shallow trench isolation region and above active regions on both sides of the first shallow trench isolation region; at least one polysilicon gate, the polysilicon gate being disposed above the second shallow trench isolation region; A contact hole is disposed above the metal gate and the polysilicon gate.

7. The semiconductor device according to claim 6, characterized in that The upper surface of the second shallow trench isolation region is lower than the upper surface of the substrate, and the distance between the upper surface of the second shallow trench isolation region and the upper surface of the substrate is 250Å-350Å.

8. The semiconductor device according to claim 6, characterized in that The method further comprises an etch stop layer, wherein the etch stop layer covers the sidewall of the metal gate, the sidewall and a part of the upper surface of the polysilicon gate, and at least covers the area between the metal gate and the polysilicon gate.

9. The semiconductor device according to claim 8, characterized in that Also includes: a first interlayer dielectric layer, wherein the first interlayer dielectric layer at least covers an upper surface of the etch stop layer in a region between the metal gate and the polysilicon gate, and an upper surface of the first interlayer dielectric layer is flush with an upper surface of the metal gate and flush with an upper surface of the etch stop layer above the polysilicon gate; A second interlayer dielectric layer, wherein the second interlayer dielectric layer covers an upper surface of the first interlayer dielectric layer and covers a portion of an upper surface of the metal gate and an upper surface of the etching stop layer above the polysilicon gate.

10. The semiconductor device according to claim 9, characterized in that The contact hole is arranged in an area on the upper surface of the metal gate that is not covered by the second interlayer dielectric layer, and in an area on the upper surface of the polysilicon gate that is not covered by the etch stop layer and the second interlayer dielectric layer above the etch stop layer.

Images