Semiconductor device and preparation method thereof, power switch device and electronic equipment

Abstract

The invention provides a semiconductor device, a preparation method thereof and electronic equipment, relates to the technical field of semiconductors, and aims to improve the reliability of the semiconductor device. The semiconductor device comprises a substrate, an epitaxial layer, an etching stop layer, a channel layer and a barrier layer which are stacked in sequence, a first doped region and a second doped region are arranged in the epitaxial layer, the doping type of one of the first doped region and the second doped region is N type, and the doping type of the other one is P type. The semiconductor device further comprises a grid electrode, a source electrode, a drain electrode, a first connecting structure and a second connecting structure, wherein the grid electrode, the source electrode and the drain electrode are located on the barrier layer, and the first connecting structure and the second connecting structure penetrate through the barrier layer, the channel layer and the etch stop layer to one side surface, away from the substrate, of the epitaxial layer. One end of the first connection structure close to the substrate is electrically connected with the first doped region, and one end away from the substrate is electrically connected with the source electrode; one end of the second connection structure close to the substrate is electrically connected with the second doped region, and one end away from the substrate is electrically connected with the drain electrode or the grid electrode. The semiconductor device is applied to the power switching device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof, a power switching device, a power conversion circuit, and an electronic device. Background Art

[0002] A high-electron-mobility transistor (HEMT) device is a semiconductor electronic device that is widely used as a radio frequency device or a power device due to its advantages such as high breakdown electric field, high channel electron concentration, high electron mobility and high temperature stability.

[0003] However, the reliability of HEMT devices is currently low, which has adverse effects on radio frequency devices or power devices used by HEMT devices. Therefore, how to improve the reliability of HEMT devices has become a technical problem that needs to be solved urgently in the field. Summary of the invention

[0004] The embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, a power switching device, a power conversion circuit, and an electronic device, aiming to improve the reliability of the semiconductor device.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In a first aspect, a semiconductor device is provided, which includes: a substrate, an epitaxial layer, an etch stop layer, a channel layer, a barrier layer, a gate, a source, a drain, a first connection structure, and a second connection structure. The epitaxial layer is located on the substrate. A first doping region and a second doping region are provided in the epitaxial layer, and the doping type of one of the first doping region and the second doping region is N-type, and the doping type of the other is P-type. The etch stop layer is located on the epitaxial layer. The channel layer is located on the etch stop layer. The barrier layer is located on the channel layer. The gate, the source, and the drain are all located on the barrier layer, and the gate is located between the source and the drain. The first connection structure and the second connection structure both penetrate the barrier layer, the channel layer, and the etch stop layer to the side surface of the epitaxial layer away from the substrate. Among them, the end of the first connection structure close to the substrate is electrically connected to the first doping region, and the end away from the substrate is electrically connected to the source. The end of the second connection structure close to the substrate is electrically connected to the second doping region, and the end away from the substrate is electrically connected to the target electrode, and the target electrode is the drain or the gate.

[0007] The semiconductor device provided by some embodiments of the present disclosure can form a PN junction diode in the epitaxial layer by stacking an epitaxial layer between a substrate and a channel layer and setting a first doping region and a second doping region in the epitaxial layer, so that the diode is integrated in the semiconductor device, avoiding increasing the cost and complexity of the structure, and avoiding increasing the parasitic inductance.

[0008] Moreover, by providing an etching stop layer between the epitaxial layer and the channel layer, and providing a first connection structure and a second connection structure penetrating the barrier layer, the channel layer and the etching stop layer to the surface of the epitaxial layer on the side away from the substrate, the first connection structure connects the first doped region and the source, and the second connection structure connects the second doped region and the target electrode (i.e., the drain or the gate), not only can the parallel connection of the diode and the HEMT be realized, but also when the HEMT is subjected to a transient overshoot of the source-drain voltage or the gate-source voltage, the diode undergoes avalanche breakdown, the source and the drain, or the gate and the source are effectively voltage clamped, the HEMT is prevented from being broken down, the HEMT is protected, and the reliability of the semiconductor device is improved; the etching stop layer can also be used to protect the surface of the epitaxial layer on the side away from the substrate, so as to avoid affecting the roughness of the surface of the epitaxial layer on the side away from the substrate (especially the part of the surface in contact with the first connection structure and the second connection structure) during the process of preparing and forming the first connection structure and the second connection structure, reduce the contact resistance between the first connection structure and the first doped region, and between the second connection structure and the second doped region, and optimize the current-voltage characteristic.

[0009] In addition, since the first connection structure and the second connection structure do not extend into structures such as the epitaxial layer and the substrate, it is beneficial to protect the finer doping structure in the substrate.

[0010] In some embodiments, in a direction parallel to a surface of the substrate close to the epitaxial layer, the etch stop layer and the first connection structure, and the etch stop layer and the second connection structure are separated by gaps.

[0011] In some embodiments, the orthographic projection of the first connection structure on the substrate is located within the orthographic projection range of the first doping region on the substrate. The orthographic projection of the second connection structure on the substrate is located within the orthographic projection range of the second doping region on the substrate.

[0012] In some embodiments, the roughness of a portion of the surface of the epitaxial layer on one side away from the substrate, located within the first doping region and the second doping region, is the same as the roughness of a portion of the surface located outside the first doping region and the second doping region.

[0013] In some embodiments, the thickness of the etch stop layer ranges from 10 nm to 100 nm.

[0014] In some embodiments, the material of the etch stop layer includes aluminum, and the content of aluminum in the etch stop layer is greater than or equal to a preset value.

[0015] In some embodiments, the material of the etch stop layer includes at least one of aluminum gallium nitride, aluminum nitride, aluminum indium nitride, and aluminum gallium indium nitride.

[0016] In some embodiments, the semiconductor device further comprises: a first interconnection portion and a second interconnection portion. The first interconnection portion is located on the first connection structure and the source electrode, and connects an end of the first connection structure away from the substrate and the source electrode. The second interconnection portion is located on the second connection structure and the target electrode, and connects an end of the second connection structure away from the substrate and the target electrode.

[0017] In some embodiments, the first connection structure includes a first ohmic contact portion and a first connection portion connected to each other, the first ohmic contact portion contacts the first doped region, and the first connection portion is located on a side of the first ohmic contact portion away from the substrate. The second connection structure includes a second ohmic contact portion and a second connection portion connected to each other, the second ohmic contact portion contacts the second doped region, and the second connection portion is located on a side of the second ohmic contact portion away from the substrate.

[0018] In some embodiments, the semiconductor device further comprises: a gate cap layer and a passivation layer. The gate cap layer is located between the barrier layer and the gate. The passivation layer is located on the barrier layer and between the gate cap layer and the gate. An opening is provided in the passivation layer, and the gate contacts the gate cap layer through the opening. The source electrode, the drain electrode, the first connection structure, and the second connection structure all penetrate the passivation layer.

[0019] In some embodiments, the semiconductor device further comprises: a buffer layer and / or an n-well region. The buffer layer is located between the etching stop layer and the channel layer, and the first connection structure and the second connection structure also penetrate the buffer layer. The n-well region is located in the epitaxial layer, and the second doped region is located in the n-well region.

[0020] In some embodiments, the material of the substrate and the epitaxial layer includes a wide bandgap semiconductor material.

[0021] In a second aspect, a method for preparing a semiconductor device is provided, the method comprising: forming an epitaxial layer on a substrate. Forming a first doping region and a second doping region on the epitaxial layer; one of the first doping region and the second doping region has an N-type doping type, and the other has a P-type doping type. Forming an etch stop layer, a channel layer, and a barrier layer in sequence on the epitaxial layer. Forming a first connection structure and a second connection structure that penetrate the barrier layer, the channel layer, and the etch stop layer to a surface of the epitaxial layer away from the substrate; an end of the first connection structure close to the substrate is electrically connected to the first doping region; an end of the second connection structure close to the substrate is electrically connected to the second doping region. Forming a gate, a source, and a drain on the barrier layer; the gate is located between the source and the drain; an end of the first connection structure away from the substrate is electrically connected to the source, and an end of the second connection structure away from the substrate is electrically connected to a target electrode, the target electrode being a drain or a gate.

[0022] In some embodiments, before forming the first connection structure and the second connection structure, the preparation method further includes: using the first plasma to etch and form a first through hole and a second through hole that penetrate the barrier layer and extend to the inside of the channel layer. Based on the first through hole and the second through hole, the first plasma and the second plasma are used to etch the channel layer to the side surface of the etching stop layer away from the substrate; the etching selectivity of the first plasma to the channel layer is greater than the etching selectivity of the first plasma to the second plasma and the reactants generated by the etching stop layer. The etching stop layer is etched through the first through hole and the second through hole to form a third through hole connected to the first through hole and a fourth through hole connected to the second through hole; the first through hole and the third through hole expose the first doped region, and the second through hole and the fourth through hole expose the second doped region; in the direction parallel to the side surface of the substrate close to the epitaxial layer, the size of the third through hole is larger than the size of the first through hole, and the size of the fourth through hole is larger than the size of the second through hole.

[0023] In some embodiments, the first plasma includes chlorine-based plasma, and the second plasma includes fluorine-based plasma. The material of the etch stop layer includes aluminum, and the aluminum content in the etch stop layer is greater than or equal to a preset value.

[0024] In some embodiments, forming a third through hole and a fourth through hole includes: using an etching solution to longitudinally etch the etch stop layer through the first through hole and the second through hole along the thickness direction of the substrate, and transversely etching the etch stop layer along a direction parallel to a surface of a side of the substrate close to the epitaxial layer, to form the third through hole and the fourth through hole.

[0025] In some embodiments, the roughness of a portion of the surface of the epitaxial layer on one side away from the substrate that is exposed by the third through hole and the fourth through hole is the same as the roughness of a portion of the surface that is not exposed by the third through hole and the fourth through hole.

[0026] In some embodiments, a first connection structure and a second connection structure are formed, including: forming a first connection structure in a first through hole and a third through hole, and forming a second connection structure in a second through hole and a fourth through hole; in a direction parallel to a surface of a side of the substrate close to the epitaxial layer, the etching stop layer and the first connection structure, and the etching stop layer and the second connection structure are separated by gaps.

[0027] In some embodiments, a first connection structure is formed in the first through hole and the third through hole, and a second connection structure is formed in the second through hole and the fourth through hole, including: forming a first ohmic contact in the third through hole, and forming a second ohmic contact in the fourth through hole; the first ohmic contact is in contact with the first doped region, and the second ohmic contact is in contact with the second doped region; in a direction parallel to the surface of the side of the substrate close to the epitaxial layer, the etching stop layer and the first ohmic contact, and the etching stop layer and the second ohmic contact are separated by gaps. A first connection connected to the first ohmic contact is formed in the first through hole, and a second connection connected to the second ohmic contact is formed in the second through hole.

[0028] In some embodiments, before forming the first through hole and the second through hole, the preparation method further includes: forming a gate cap layer on the barrier layer. Forming a passivation layer on the gate cap layer; the passivation layer covers the gate cap layer and the barrier layer. In the process of forming the first through hole and the second through hole, the first through hole and the second through hole also penetrate the passivation layer, and the first through hole and the second through hole are located on opposite sides of the gate cap layer.

[0029] In some embodiments, the preparation method also includes: forming a first interconnection portion and a second interconnection portion; the first interconnection portion is located on the first connection structure and the source electrode, and connects one end of the first connection structure away from the substrate and the source electrode; the second interconnection portion is located on the second connection structure and the target electrode, and connects one end of the second connection structure away from the substrate and the target electrode.

[0030] In a third aspect, a power switch device is provided, the power switch device comprising: a semiconductor device and a packaging substrate, wherein the packaging substrate is electrically connected to the semiconductor device. The semiconductor device is the semiconductor device as described in any one of the first aspects.

[0031] In a fourth aspect, a power conversion circuit is provided, the power conversion circuit comprising: a power switch device and a circuit board, the circuit board being electrically connected to the power switch device. The power switch device is the power switch device as described in any one of the third aspects.

[0032] In a fifth aspect, an electronic device is provided, the electronic device comprising: a power switch device and a circuit board, wherein the circuit board is electrically connected to the power switch device. The power switch device is the power switch device as described in any one of the third aspects.

[0033] The technical effects brought about by any embodiment of the second to fifth aspects can refer to the technical effects brought about by different embodiments of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure are briefly introduced below.

[0035] Figure 1 The structure of the electronic device according to some embodiments Figure 1 ;

[0036] Figure 2 is a structural diagram of an active antenna unit according to some embodiments;

[0037] Figure 3 The structure of the electronic device according to some embodiments Figure 2 ;

[0038] Figure 4 The structure of the semiconductor device according to some embodiments Figure 1 ;

[0039] Figure 5 The structure of the semiconductor device according to some embodiments Figure 2 ;

[0040] Figure 6 The structure of the semiconductor device according to some embodiments Figure 3 ;

[0041] Figure 7 The structure of the semiconductor device according to some embodiments Figure 4 ;

[0042] Figure 8 The structure of the semiconductor device according to some embodiments Figure 5 ;

[0043] Fig. 9 for Figure 6 An equivalent circuit diagram of the semiconductor device shown;

[0044] Fig.10 for Figure 7 An equivalent circuit diagram of the semiconductor device shown;

[0045] Fig.11 The structure of the semiconductor device according to some embodiments Figure 6 ;

[0046] Fig.12 is a flow chart of a method for preparing a semiconductor device according to some embodiments;

[0047] Figure 13a-13h The structures corresponding to the steps in the method for preparing a semiconductor device according to some embodiments are Figure 1 ;

[0048] Figure 14a-14d The structures corresponding to the steps in the method for preparing a semiconductor device according to some embodiments are Figure 2 ;

[0049] Fig.15 is an atomic force microscope (AFM) image of a surface of an epitaxial layer away from a substrate according to some embodiments;

[0050] Fig.16 is a current-voltage curve according to some embodiments Figure 1 ;

[0051] Fig.17 is a current-voltage curve according to some embodiments Figure 2 ;

[0052] Fig.18 is a structural diagram of a power switch device according to some embodiments;

[0053] Fig.19 is a structural diagram of a power conversion circuit according to some embodiments. DETAILED DESCRIPTION

[0054] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0055] In the description of the present disclosure, unless the context requires otherwise, throughout the specification and claims, the term "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0056] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0057] When describing some embodiments, the term "connected" and its derivative expressions may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0058] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0059] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0060] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0061] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0062] In the context of this disclosure, the meanings of “on,” “above,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “above” or “over” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0063] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0064] Some embodiments of the present disclosure provide an electronic device, which may be, for example, a charger, a charging small household appliance (such as a soymilk machine, a sweeping robot), an on-board charger (OBC), a drone, an aerospace equipment, a lidar driver, a laser, a detector, a radar, a 5G (the 5th generation mobile network, the fifth generation mobile communication technology) communication device, and other different types of user equipment or terminal equipment; the electronic device may also be a network device such as a base station. The embodiments of the present disclosure do not impose any special restrictions on the specific form of the electronic device. The electronic device can be widely used in systems such as civilian consumer electronics, vehicle-mounted electronics, data center power supplies, and photovoltaic inverters.

[0065] Figure 1 A structural diagram of an electronic device provided in an embodiment of the present disclosure, Figure 1 Take the electronic device as a base station as an example. Those skilled in the art can understand that: Figure 1 The structure of the electronic device shown in the figure does not constitute a limitation on the electronic device, and the electronic device may include, for example Figure 1 More or fewer components may be shown, or they may be combined as shown. Figure 1 Some of the components shown may be combined with Figure 1 The components shown are arranged differently.

[0066] like Figure 1 As shown, the base station includes a baseband processing unit (BBU) 100 and an active antenna unit (AAU) 200. The baseband processing unit 100 is mainly responsible for baseband digital signal processing, such as fast Fourier transform (FFT) / inverse fast Fourier transform (IFFT), modulation / demodulation, channel coding / decoding, etc.

[0067] Figure 2 A structural diagram of an active antenna unit 200 provided in an embodiment of the present disclosure.

[0068] like Figure 2As shown, the active antenna unit 200 includes a computing unit 210, a first transmission unit 220 and an antenna unit 230. The computing unit 210 includes a control unit 211, a second transmission unit 212, a baseband unit 213 and a power supply unit 214, wherein the control unit 211, the second transmission unit 212, the baseband unit 213 and the power supply unit 214 are electrically connected to each other, the control unit 211 is responsible for the control of the radio frequency signal, the second transmission unit 212 is responsible for the transmission of the radio frequency signal, the baseband unit 213 is responsible for the conversion of digital signals and analog signals, the baseband unit 213 is, for example, a digital to analog converter (DAC), the digital to analog converter can convert the digital signal output by the baseband processing unit 100 into an analog signal, and the power supply unit 214 is electrically connected to the power supply 240, and is used to supply power to the control unit 211, the second transmission unit 212 and the baseband unit 213 in the computing unit 210.

[0069] The first transmission unit 220 is responsible for the transmission and amplification of the radio frequency signal. The first transmission unit 220 includes a radio frequency (RF) unit 221 and a power amplifier (PA) 222. The radio frequency unit 221 is used to convert the analog signal into a low-power radio frequency signal, and the power amplifier 222 is used to amplify the low-power radio frequency signal and output it to the antenna unit 230. The power amplifier 222 is a radio frequency device, which can be a radio frequency chip. Exemplarily, the power amplifier 222 can be a HEMT device.

[0070] The antenna unit 230 is responsible for radiating the radio frequency signal outward. Figure 2 As shown, the active antenna unit 200 may include multiple radio frequency units 221 , multiple power amplifiers 222 , and multiple antenna units 230 .

[0071] Figure 3 A structural diagram of another electronic device provided in an embodiment of the present disclosure, Figure 3 Take the electronic device as a charger as an example. Those skilled in the art can understand that Figure 3 The structure of the electronic device shown in the figure does not constitute a limitation on the electronic device, and the electronic device may include, for example Figure 3 More or fewer components may be shown, or they may be combined as shown. Figure 3 Some of the components shown may be combined with Figure 3 The components shown are arranged differently.

[0072] like Figure 3As shown, the charger may include a power device 300, a resistor R, an inductor L, a capacitor C, etc. The power device 300 may be, for example, a HEMT device. The power device 300, the resistor R, the inductor L, and the capacitor C may all be electrically connected to a circuit board and interconnected through a circuit board (e.g., a printed circuit board).

[0073] The present disclosure provides a semiconductor device, which is applied to the above electronic device. The semiconductor device may be a HEMT device, and further, the semiconductor device is an enhanced HEMT device. The enhanced HEMT device is a normally-off device and can be applied to power devices. Figure 4 The structure of a semiconductor device is schematically shown.

[0074] In some examples, such as Figure 4 As shown, the semiconductor device 400 includes a substrate 1, a channel layer 2, a barrier layer 3, a gate cap layer 4, a gate 5, a source 6 and a drain 7. The channel layer 2, the barrier layer 3, the gate cap layer 4, the gate 5, the source 6 and the drain 7 can constitute a HEMT, for example.

[0075] The substrate 1 is, for example, a silicon substrate. Figure 4 As shown, the channel layer 2 is located on the substrate 1, and the barrier layer 3 is located on the channel layer 2. The barrier layer 3 is in contact with a surface of the channel layer 2 that is away from the substrate 1, for example.

[0076] Optionally, the material of the channel layer 2 includes a III-V semiconductor material, for example, the III-V semiconductor material includes but is not limited to gallium nitride (GaN), etc., and the doping condition in the material of the channel layer 2 can be determined according to the withstand voltage required by the semiconductor device 400. The material of the barrier layer 3 includes a III-V semiconductor material, for example, the III-V semiconductor material includes but is not limited to aluminum gallium nitride (AlGaN), aluminum nitride (AlN), aluminum indium nitride (AlInN), aluminum gallium indium nitride (AlInGaN), etc., and the components in the material of the barrier layer 3 can be determined according to the power level required by the semiconductor device 400.

[0077] Here, the material of the channel layer 2 is GaN, and the material of the barrier layer 3 is AlGaN. As GaN has polarity, no doping is required at the AlGaN / GaN interface. Therefore, the semiconductor device 400 can generate a high-concentration, high-confinement two-dimensional electron gas (2DEG) at the AlGaN / GaN interface through spontaneous polarization and piezoelectric polarization. The two-dimensional electron gas can be used to conduct electrons efficiently. The location of the two-dimensional electron gas can be used as the main conduction area for the operation of the semiconductor device 400.

[0078] like Figure 4 As shown, the gate cap layer 4 is located on the barrier layer 3, and the gate 5 is located on the gate cap layer 4, that is, the gate cap layer 4 is located between the barrier layer 3 and the gate 5. The gate cap layer 4, for example, contacts the surface of the barrier layer 3 on the side away from the substrate 1. The orthographic projection area of ​​the gate cap layer 4 on the substrate 1 is smaller than the orthographic projection area of ​​the barrier layer 3 on the substrate 1; the orthographic projection of the gate cap layer 4 on the substrate 1 is located within the orthographic projection range of the barrier layer 3 on the substrate 1; the gate cap layer 4 only covers a portion of the barrier layer 3. The gate 5, for example, contacts the surface of the gate cap layer 4 on the side away from the substrate 1 to form a Schottky contact. The orthographic projection of the gate 5 on the substrate 1 at least partially overlaps with the orthographic projection of the gate cap layer 4 on the substrate 1.

[0079] Optionally, the gate cap layer 4 includes p-GaN or P-type metal, and the gate 5 includes metal material. The gate cap layer 4 can raise the energy band at the channel position, so that the two-dimensional electron gas under the gate 5 is depleted, thereby realizing a normally-off semiconductor device.

[0080] like Figure 4 As shown, along the second direction X, the source 6 and the drain 7 are respectively located on the opposite sides of the gate cap layer 4. Correspondingly, the source 6 and the drain 7 are also respectively located on the opposite sides of the gate 5. Further, the source 6 and the drain 7 can respectively penetrate the barrier layer 3 to the channel layer 2 to contact the channel layer 2 and form an ohmic contact. Alternatively, the source 6 and the drain 7 can also respectively penetrate a part of the barrier layer 3, and the source 6 and the drain 7 are respectively embedded in the barrier layer 3. Among them, the second direction X is the arrangement direction of the source 6, the gate 5 and the drain 7, and the second direction X is parallel to the surface of one side of the substrate 1 close to the channel layer 2.

[0081] Optionally, the materials of the source 6 and the drain 7 may be the same or different. For example, the material of either the source 6 or the drain 7 includes but is not limited to copper, aluminum, tungsten, nickel, iron, cobalt, silver, gold or platinum.

[0082] The working principle of the semiconductor device 400 is as follows: a two-dimensional electron gas channel is generated at the contact interface between the channel layer 2 and the barrier layer 3 due to the polarization effect, and the two-dimensional electron gas can be used to efficiently conduct electrons. When the gate 5 does not receive a voltage signal, that is, when there is no bias voltage, the two-dimensional electron gas is in a pinch-off state to achieve cutoff between the source 6 and the drain 7, and the semiconductor device 400 is in a closed state. When the gate 5 receives a voltage signal, that is, when a bias voltage is applied, the two-dimensional electron gas is allowed to pass through to achieve conduction between the source 6 and the drain 7, and the semiconductor device 400 is in an open state. Therefore, in the absence of a bias voltage, the semiconductor device 400 is a normally-off device.

[0083] It is understandable that the semiconductor device 400 has advantages such as high breakdown electric field, high channel electron concentration, high electron mobility and high temperature stability, but has low reliability. For example, the semiconductor device 400 lacks avalanche breakdown capability; moreover, the semiconductor device 400 is easily broken down by transient overshoot of gate-source voltage or source-drain voltage, resulting in damage to the semiconductor device 400.

[0084] In one possible implementation, a diode can be connected in parallel between the source 6 and the drain 7 of the semiconductor device 400 through an external circuit, or a diode can be connected in parallel between the gate 5 and the source 6 of the semiconductor device 400 to provide avalanche breakdown capability and suppress transient voltage to prevent the semiconductor device 400 from being broken down.

[0085] However, since the diode is not integrated in the semiconductor device 400, this will not only increase the cost and complexity of the structure, but also increase the parasitic inductance.

[0086] Based on this, some embodiments of the present disclosure further improve the semiconductor device 400, that is, an epitaxial layer is stacked between the substrate 1 and the channel layer 2, and a first doping region and a second doping region are provided in the epitaxial layer, and the doping type of one of the first doping region and the second doping region is N-type, and the doping type of the other is P-type, so that a PN junction diode can be formed in the epitaxial layer, so that the diode is integrated in the semiconductor device 400; and an etch stop layer is provided between the epitaxial layer and the channel layer 2, and a first connection structure and a connection structure are provided that penetrate the barrier layer 3, the channel layer 2 and the etch stop layer to the surface of the side of the epitaxial layer away from the substrate 1. The second connection structure enables the first connection structure to connect the first doped region and the source, and the second connection structure to connect the second doped region and the target electrode (i.e., the drain or the gate), which can not only realize the parallel connection of the diode and the HEMT in the semiconductor device and protect the semiconductor device to prevent the semiconductor device 400 from being broken down; but also can use the etching stop layer to protect the side surface of the epitaxial layer away from the substrate 1, avoid affecting the roughness of the side surface of the epitaxial layer away from the substrate 1 during the process of preparing the first connection structure and the second connection structure, and reduce the contact resistance between the first connection structure and the first doped region and between the second connection structure and the second doped region.

[0087] in, Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig.11 The structure diagram of a semiconductor device is shown respectively. Fig. 9 and Fig.10 The equivalent circuit diagrams of a semiconductor device are shown in FIG. Figure 5In the figure, the curve may represent an intermediate structure, not shown, between the first connection structure and the second connection structure.

[0088] In some examples, such as Figure 5 , Figure 6 and Figure 7 As shown, the semiconductor device 400 may further include an epitaxial layer 9 , wherein the epitaxial layer 9 is located between the substrate 1 and the channel layer 2 , and the epitaxial layer 9 separates the substrate 1 and the channel layer 2 .

[0089] Exemplarily, in this example, the materials of the substrate 1 and the epitaxial layer 9 both include wide bandgap semiconductor materials. Optionally, the material of the substrate 1 includes but is not limited to nitride semiconductor materials such as silicon carbide and gallium nitride, and the material of the epitaxial layer 9 includes but is not limited to nitride semiconductor materials such as silicon carbide and gallium nitride. For example, the material of the substrate 1 is the same as the material of the epitaxial layer 9, and the material of the substrate 1 and the material of the epitaxial layer 9 are both silicon carbide.

[0090] It is understandable that, compared with silicon, nitride semiconductor materials such as silicon carbide and gallium nitride have greater dielectric breakdown electric field strength and bandgap width, and therefore can provide the semiconductor device 400 with lower on-resistance and higher dielectric withstand voltage.

[0091] Continue reading Figure 5 The epitaxial layer 9 is provided with a first doping region DR1 and a second doping region DR2, and both the first doping region DR1 and the second doping region DR2 extend from a surface of the epitaxial layer 9 away from the substrate 1 to the inside of the epitaxial layer 9. In addition, the first doping region DR1 and the second doping region DR2 are arranged at intervals, and the two regions are not in direct contact to avoid short circuit.

[0092] The doping type of one of the first doping region DR1 and the second doping region DR2 is N-type, and the doping type of the other is P-type. For example, the doping type of the first doping region DR1 is N-type, and the doping type of the second doping region DR2 is P-type. For another example, the doping type of the first doping region DR1 is P-type, and the doping type of the second doping region DR2 is N-type. The first doping region DR1 and the second doping region DR2 form a PN junction to form a diode.

[0093] For example, Figure 8 As shown, the semiconductor device 400 further has an n-well region NW, which is located in the epitaxial layer 9. For example, the doping type of the first doping region DR1 is P-type, and the doping type of the second doping region DR2 is N-type, which is also located in the n-well region NW.

[0094] In some examples, such as Figure 5As shown, the semiconductor device 400 may further include an etch stop layer 10, and the etch stop layer 10 is located on the epitaxial layer 9. Specifically, the etch stop layer 10 is located between the epitaxial layer 9 and the channel layer 2, and the etch stop layer 10 separates the epitaxial layer 9 and the channel layer 2.

[0095] The etch stop layer 10 is used to stop etching on one side of the etch stop layer 10. For example, the etch stop layer 10 is used to stop etching the barrier layer 3 and the channel layer 2 on one side of the etch stop layer 10 away from the substrate 1.

[0096] In some examples, such as Figure 5 , Figure 6 and Figure 7 As shown, the semiconductor device 400 may further include a first connection structure 11 and a second connection structure 12 , and the first connection structure 11 and the second connection structure 12 are arranged at intervals.

[0097] The first connection structure 11 and the second connection structure 12 both penetrate the barrier layer 3, the channel layer 2 and the etching stop layer 10 to the surface of the epitaxial layer 9 on the side away from the substrate 1. The surface of the epitaxial layer 9 on the side away from the substrate 1 is, for example, a plane, and the first connection structure 11 and the second connection structure 12 are both in contact with the plane, and the first connection structure 11 and the second connection structure 12 do not extend into the interior of the epitaxial layer 9.

[0098] Here, before forming the first connection structure 11 and the second connection structure 12, for example, two through holes penetrating the barrier layer 3 and the channel layer 2 can be formed first, and the etching of the two through holes stops at the side surface of the etch stop layer 10 away from the substrate 1; then the etch stop layer 10 is further etched and stops at the side surface of the epitaxial layer 9 away from the substrate 1; thereafter, the first connection structure 11 and the second connection structure 12 can be respectively formed in the two through holes.

[0099] In this way, in the process of forming the above-mentioned two through holes, at least two etching processes can be used, and then the process of etching to form the above-mentioned two through holes can be appropriately selected, and the etching stop layer 10 is used to protect the side surface of the epitaxial layer 9 away from the substrate 1, so as to avoid affecting the roughness of the side surface of the epitaxial layer 9 away from the substrate 1 during the etching of the etching stop layer 10, thereby reducing the contact resistance between the first connecting structure 11 and the first doping region DR1 and between the second connecting structure 12 and the second doping region DR2.

[0100] Continue reading Figure 5 , Figure 6 and Figure 7The first connection structure 11 has one end close to the substrate 1 electrically connected to the first doping region DR1, and one end away from the substrate 1 electrically connected to the source 6. That is, the first connection structure 11 realizes electrical connection between the first doping region DR1 and the source 6.

[0101] The second connection structure 12 is electrically connected to the second doping region DR2 at one end close to the substrate 1, and is electrically connected to the target electrode at one end away from the substrate 1, which is the drain 7 or the gate 5. That is, the second connection structure 12 realizes the electrical connection between the second doping region DR2 and the drain 7, or the second connection structure 12 realizes the electrical connection between the second doping region DR2 and the gate 5.

[0102] In this way, the parallel connection between the HEMT and the diode in the semiconductor device 400 is achieved.

[0103] exist Fig. 9 and Fig.10 In the equivalent circuit diagrams shown, the doping type of the first doping region DR1 is P type, and the doping type of the second doping region DR2 is N type.

[0104] exist Fig. 9 In the embodiment, the diode is connected in parallel between the source 6 and drain 7 of the HEMT. Figure 6 The source electrode 6 is electrically connected to the first doping region DR1 through a first connection structure 11 , and the drain electrode 7 is electrically connected to the second doping region DR2 through a second connection structure 12 .

[0105] In this way, when the HEMT is subjected to a transient overshoot of the source-drain voltage, the diode undergoes avalanche breakdown before the voltage exceeds the withstand voltage of the HEMT, so that the voltage between the source 6 and the drain 7 is clamped. That is, the diode can effectively clamp the voltage of the source 6 and the drain 7 to prevent the HEMT from being broken down, thereby protecting the HEMT.

[0106] exist Fig.10 In the embodiment, the diode is connected in parallel between the source 6 and the gate 5 of the HEMT. Figure 7 The source electrode 6 is electrically connected to the first doping region DR1 through a first connection structure 11 , and the gate electrode 5 is electrically connected to the second doping region DR2 through a second connection structure 12 .

[0107] In this way, when the HEMT is subjected to a transient overshoot gate-source voltage, the diode undergoes avalanche breakdown before the voltage exceeds the withstand voltage of the HEMT, so that the voltage between the gate 5 and the source 6 is clamped. That is, the diode can effectively clamp the voltage of the gate 5 and the source 6 to prevent the HEMT from being broken down, thereby protecting the HEMT.

[0108] Therefore, the semiconductor device 400 provided in some embodiments of the present disclosure can form a PN junction diode in the epitaxial layer 9 by stacking an epitaxial layer 9 between the substrate 1 and the channel layer 2, and setting a first doping region DR1 and a second doping region DR2 in the epitaxial layer 9, so that the diode is integrated in the semiconductor device 400, avoiding increasing the cost and complexity of the structure, and avoiding increasing the parasitic inductance.

[0109] Moreover, by providing an etching stop layer 10 between the epitaxial layer 9 and the channel layer 2, and providing a first connection structure 11 and a second connection structure 12 penetrating the barrier layer 3, the channel layer 2 and the etching stop layer 10 to the surface of the epitaxial layer 9 on the side away from the substrate 1, so that the first connection structure 11 connects the first doping region DR1 and the source 6, and the second connection structure 12 connects the second doping region DR2 and the target electrode (that is, the drain 7 or the gate 5), not only can the parallel connection of the diode and the HEMT be realized, but also when the HEMT is subjected to a transient overshoot of the source-drain voltage or the gate-source voltage, the diode undergoes avalanche breakdown, and the source 6 and the drain 7, or the gate 5 and The source 6 is effectively voltage clamped to prevent the HEMT from being broken down, thereby protecting the HEMT and improving the reliability of the semiconductor device 400. The etching stop layer 10 can also be used to protect the surface of the epitaxial layer 9 away from the substrate 1 to avoid affecting the roughness of the surface of the epitaxial layer 9 away from the substrate 1 (especially the surface in contact with the first connection structure 11 and the second connection structure 12) during the process of preparing the first connection structure 11 and the second connection structure 12, thereby reducing the contact resistance between the first connection structure 11 and the first doped region DR1 and between the second connection structure 12 and the second doped region DR2, and optimizing the current-voltage characteristics.

[0110] In addition, since the first connection structure 11 and the second connection structure 12 do not extend into the epitaxial layer 9 , the substrate 1 and other structures, it is beneficial to protect the finer doping structure in the substrate 1 .

[0111] In some embodiments, the roughness of a portion of the surface of the epitaxial layer 9 located within the first doping region DR1 and the second doping region DR2 on one side of the surface away from the substrate 1 is the same as the roughness of a portion of the surface located outside the first doping region DR1 and the second doping region DR2.

[0112] Furthermore, the roughness of the surface of the epitaxial layer 9 on one side away from the substrate 1 , the surface contacting the first connection structure 11 and the second connection structure 12 , and the roughness of the remaining surface are the same.

[0113] Here, due to unavoidable factors such as process error and measurement error, the above “same” is not the same in a strict sense. Within the acceptable deviation range, they can be considered the same.

[0114] This means that in the process of preparing the first connection structure 11 and the second connection structure 12, the roughness of the surface of the epitaxial layer 9 away from the substrate 1 will not be affected. Accordingly, the provision of the etching stop layer 10 can effectively protect the surface of the epitaxial layer 9 away from the substrate 1. In this way, the contact resistance between the first connection structure 11 and the first doping region DR1 and between the second connection structure 12 and the second doping region DR2 can be effectively reduced, and the current-voltage characteristics can be effectively optimized (for example, the current-voltage curve has a linear characteristic).

[0115] In some embodiments, Figure 6-Figure 8 As shown, in the direction parallel to the side surface of the substrate 1 close to the epitaxial layer 9, the etch stop layer 10 and the first connection structure 11, and the etch stop layer 10 and the second connection structure 12 are separated by gaps. The direction parallel to the side surface of the substrate 1 close to the epitaxial layer 9 may refer to any direction parallel to the side surface of the substrate 1 close to the epitaxial layer 9.

[0116] The gap between the etch stop layer 10 and the first connection structure 11 is, for example, in the form of an annular shape (e.g., a circular ring or a square ring, etc.), surrounding the first connection structure 11, so that there is no direct contact between any position of the first connection structure 11 and the etch stop layer 10. The gap between the etch stop layer 10 and the second connection structure 12 is, for example, in the form of an annular shape (e.g., a circular ring or a square ring, etc.), surrounding the second connection structure 12, so that there is no direct contact between any position of the second connection structure 12 and the etch stop layer 10.

[0117] Here, there may be a large number of interface defects between the etch stop layer 10 and the epitaxial layer 9 , and the interface defects may easily lead to an increase in leakage current at the contact interface between the etch stop layer 10 and the epitaxial layer 9 .

[0118] By setting a gap, the etching stop layer 10 and the first connecting structure 11 are separated, and the etching stop layer 10 and the second connecting structure 12 are separated, thereby separating the contact interface between the first connecting structure 11 and the first doped region DR1 and the etching stop layer 10, and separating the contact interface between the second connecting structure 12 and the second doped region DR2 and the etching stop layer 10, thereby reducing interface leakage and improving the performance of the semiconductor device 400.

[0119] The above-mentioned gap is filled with air, for example. Of course, the gap can also be filled with other gases, which is not limited in the embodiments of the present disclosure. In the direction parallel to the surface of one side of the substrate 1 close to the epitaxial layer 9, the size of the gap can be selected and set according to actual needs, and can separate the etching stop layer 10 and the first connecting structure 11, and separate the etching stop layer 10 and the second connecting structure 12, so as to reduce interface leakage.

[0120] In some embodiments, the thickness of the etch stop layer 10 (ie, the dimension along the thickness direction of the substrate 1 ) is in the range of 10 nm-100 nm.

[0121] Exemplarily, the thickness of the etch stop layer 10 may range from 10 nm to 90 nm, 15 nm to 80 nm, 30 nm to 70 nm, 50 nm to 100 nm, 30 nm to 85 nm, or 40 nm to 60 nm, etc. Optionally, the thickness of the etch stop layer 10 may range from 10 nm to 20 nm, 35 nm, 55 nm, 79 nm, or 100 nm, etc.

[0122] Since the etch stop layer 10 is located between the epitaxial layer 9 and the channel layer 2, and the first connecting structure 11 and the second connecting structure 12 both penetrate the etch stop layer 10, therefore, by setting the thickness of the etch stop layer 10 within the above range, it is possible to avoid the etch stop layer 10 being difficult to withstand the etching due to the thickness being too small, and to avoid the etch stop layer 10 and the crystal quality formed in the channel layer 2 being affected due to the thickness being too large.

[0123] In some embodiments, the material of the etch stop layer 10 includes aluminum, and the aluminum component in the etch stop layer 10 is relatively large.

[0124] In the technical field, considering the convenience in the actual production process, in the process of etching the barrier layer 3 and the channel layer 2 on the etch stop layer 10, the plasma used generally includes chlorine (Cl)-based plasma, fluorine (F)-based plasma, etc. Fluorine-based plasma and aluminum-containing materials will chemically react to generate aluminum fluoride (AlF3), and aluminum fluoride is difficult to be removed by chlorine-based plasma.

[0125] Based on this, in the process of preparing the first connection structure 11 and the second connection structure 12, the embodiment of the present disclosure may consider first using chlorine-based plasma to etch a portion of the barrier layer 3 and the channel layer 2, and then using a mixed plasma including chlorine-based and fluorine-based plasma to etch the remaining portion of the channel layer 2, so that the etching stops at the surface of the side of the etching stop layer 10 away from the substrate 1. Then, an appropriate etching process can be selected to etch the etching stop layer 10 to avoid affecting the roughness of the surface of the side of the epitaxial layer 9 away from the substrate 1.

[0126] Optionally, the aluminum component in the etch stop layer 10 is greater than or equal to a preset value. The "aluminum component" refers, for example, to the molar ratio or number ratio of the aluminum element. The "preset value" refers, for example, to the minimum value with a self-terminating etching effect. Specifically, when the aluminum component in the etch stop layer 10 is greater than or equal to the preset value, the aluminum fluoride generated by the aluminum in the etch stop layer 10 and the fluorine-based plasma can achieve a self-terminating etching effect on the chlorine-based plasma; when the aluminum component in the etch stop layer 10 is less than the preset value, the self-terminating etching effect on the chlorine-based plasma fails.

[0127] Exemplarily, the preset value may be 80%. In this case, the aluminum content in the etch stop layer 10 may be 80%, 81%, 85%, 88%, 90% or 92%, etc. Of course, within the range allowed by the process error, the preset value is not strictly 80%.

[0128] The materials of the etching stop layer 10 include various materials, which can be selected and set according to actual needs.

[0129] Optionally, the material of the etch stop layer 10 includes at least one of aluminum gallium nitride, aluminum nitride, aluminum indium nitride, and aluminum gallium indium nitride. That is, the material of the etch stop layer 10 can be composed of one or a combination of aluminum gallium nitride, aluminum nitride, aluminum indium nitride, and aluminum gallium indium nitride.

[0130] For example, taking the material of the etch stop layer 10 as aluminum indium nitride and the aluminum component as 80%, the ratio of the aluminum component to the indium component in the etch stop layer 10 is 8:2.

[0131] Of course, the material of the etching stop layer 10 may also include other elements, which can be specifically selected and set according to the actual production design. For example, plasma of other elements is selected for etching the barrier layer 3 and the channel layer 2, and accordingly, other elements included in the material of the etching stop layer 10 can cooperate with the plasma of the other elements to achieve a self-termination etching effect.

[0132] In some embodiments, Figure 6-Figure 8 As shown, the orthographic projection of the first connection structure 11 on the substrate 1 is located within the orthographic projection range of the first doping region DR1 on the substrate 1 . The orthographic projection of the second connection structure 12 on the substrate 1 is located within the orthographic projection range of the second doping region DR2 on the substrate 1 .

[0133] Accordingly, the orthographic projection area of ​​the first doping region DR1 on the substrate 1 is larger than the orthographic projection area of ​​the first connection structure 11 on the substrate 1. The orthographic projection boundary of the first doping region DR1 on the substrate 1 surrounds the orthographic projection boundary of the first connection structure 11 on the substrate 1. The first connection structure 11 and the first doping region DR1 are not offset.

[0134] The orthographic projection area of ​​the second doping region DR2 on the substrate 1 is larger than the orthographic projection area of ​​the second connection structure 12 on the substrate 1. The orthographic projection boundary of the second doping region DR2 on the substrate 1 surrounds the orthographic projection boundary of the second connection structure 12 on the substrate 1. The second connection structure 12 and the second doping region DR2 are not staggered.

[0135] In this way, the contact interface between the first connection structure 11 and the first doping region DR1 can be located in the first doping region DR1, and the contact interface between the second connection structure 12 and the second doping region DR2 can be located in the second doping region DR2, which can not only ensure that the first connection structure 11 and the first doping region DR1 can be electrically connected, and the second connection structure 12 and the second doping region DR2 can be electrically connected, but also avoid the first connection structure 11 and the second connection structure 12 from being short-circuited due to not being misaligned with the first doping region DR1 and the second doping region DR2 respectively. In addition, it is also beneficial to reduce the alignment accuracy between the first connection structure 11 and the first doping region DR1, and between the second connection structure 12 and the second doping region DR2, and reduce the difficulty of preparing and forming the first connection structure 11 and the second connection structure 12.

[0136] The first connection structure 11 and the second connection structure 12 may have various structures, which may be selected and set according to actual needs.

[0137] In some embodiments, Figure 6-Figure 8 As shown, the first connection structure 11 includes a first ohmic contact portion 111 and a first connection portion 112 connected to each other. The first ohmic contact portion 111 contacts the first doping region DR1 to form an ohmic contact. The first connection portion 112 is located on a side of the first ohmic contact portion 111 away from the substrate 1 .

[0138] Continue reading Figure 6-Figure 8 The second connection structure 12 includes a second ohmic contact portion 121 and a second connection portion 122 connected to each other. The second ohmic contact portion 121 contacts the second doping region DR2 to form an ohmic contact. The second connection portion 122 is located on a side of the second ohmic contact portion 121 away from the substrate 1 .

[0139] This is beneficial to achieving ohmic contact between the first connection structure 11 and the first doping region DR1 and between the second connection structure 12 and the second doping region DR2 to reduce contact resistance, and is also beneficial to reducing the resistivity of the first connection structure 11 and the second connection structure 12 themselves.

[0140] The semiconductor device 400 may further include other structures, which are schematically described below with reference to the accompanying drawings.

[0141] In some embodiments, Figure 6-Figure 8As shown, the semiconductor device 400 may further include a passivation layer 13 .

[0142] The passivation layer is located on the barrier layer 3 and covers the barrier layer 3. Furthermore, the barrier layer 3 is also located between the gate cap layer 4 and the gate 5, contacts the sidewall of the gate cap layer 4, and covers a portion of the gate cap layer 4. An opening is provided in the barrier layer 3, and the gate 5 contacts the gate cap layer 4 through the opening.

[0143] Furthermore, if Figure 6-Figure 8 As shown, the source electrode 6 , the drain electrode 7 , the first connection structure 11 and the second connection structure 12 all penetrate the passivation layer 13 .

[0144] By providing the passivation layer 13 , dangling bonds on the sidewalls of the gate cap layer 4 can be terminated and passivated to limit the number of interface traps, thereby reducing gate leakage and improving the performance of the semiconductor device 400 .

[0145] In addition, during the process of preparing and forming the first connection structure 11 and the second connection structure 12 , the passivation layer 13 may be used to protect the sidewall of the gate cap layer 4 and the surface of the barrier layer 3 away from the substrate 1 .

[0146] In some embodiments, Figure 6-Figure 8 As shown, the semiconductor device 400 may further include: a first interconnection portion 14 and a second interconnection portion 15 .

[0147] The first interconnection portion 14 is located on the first connection structure 11 and the source electrode 6, and connects one end of the first connection structure 11 away from the substrate 1 and the source electrode 6. For example, the first interconnection portion 14 is in direct contact with both the surface of the first connection structure 11 away from the substrate 1 and the surface of the source electrode 6 away from the substrate 1.

[0148] The second interconnection portion 15 is located on the second connection structure 12 and the target electrode, and connects the end of the second connection structure 12 away from the substrate 1 and the target electrode. Figure 6 In the embodiment, the second interconnection portion 15 is in direct contact with the surface of the second connection structure 12 away from the substrate 1 and the surface of the drain electrode 7 away from the substrate 1. Figure 7 In the case where the second interconnection portion 15 is connected to the gate 5, the first portion of the second interconnection portion 15 can be in direct contact with the surface of the side of the second connection structure 12 away from the substrate 1, the second portion can be in direct contact with the surface of the side of the gate 5 away from the substrate 1, and the third portion can be located on the side of the first portion and the second portion away from the substrate 1, and connected to the first portion and the second portion.

[0149] In this way, the interconnection between the HEMT and the diode in the semiconductor device 400 can be achieved, and the structure for achieving the interconnection is relatively simple and easy to prepare.

[0150] In some examples, when the second interconnection 15 is connected to the drain electrode 7 , the first interconnection 14 and the second interconnection 15 are made of the same material and are disposed in the same layer.

[0151] Here, "same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask plate through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0152] That is to say, the first interconnection portion 14 and the second interconnection portion 15 can be formed based on the same film layer and in the same patterning process, which is helpful to simplify the manufacturing process of the semiconductor device 400 .

[0153] It can be understood that the above drawings only schematically illustrate the positional relationship and connection relationship between the first interconnecting portion 14 and the second interconnecting portion 15 and the structures to which they are connected.

[0154] In some embodiments, Fig.11 As shown, the semiconductor device 400 may further include a buffer layer 16 . The buffer layer 16 is located between the etch stop layer 10 and the channel layer 2 , and the first connection structure 11 and the second connection structure 12 also penetrate the buffer layer 16 .

[0155] The number of the buffer layer 16 can be one or more. Optionally, the material of the buffer layer 16 includes but is not limited to gallium nitride, aluminum nitride, aluminum gallium nitride, and the like.

[0156] By providing the buffer layer 16 , the strain caused by the lattice mismatch between the etch stop layer 10 and the channel layer 2 can be relieved, and the formation of defects can be reduced or even avoided.

[0157] Some embodiments of the present disclosure also provide a method for preparing a semiconductor device, which is used, for example, to prepare the semiconductor device 400 in some of the above embodiments. Fig.12 A flow chart of a method for preparing a semiconductor device is shown; Figure 13a-13h , Figure 14a-14d The structures corresponding to the steps in a method for preparing a semiconductor device are schematically shown. It should be understood that Fig.12 The steps shown are not exclusive and can also be Fig.12 Other steps may be performed before, after or between any of the steps shown. In addition, some of the steps may be performed simultaneously, or may be performed in different order. Fig.17 Executed in the order shown.

[0158] The following is a schematic illustration of the method for preparing the semiconductor device described above in conjunction with the accompanying drawings. Fig.12 As shown, the preparation method includes: S100-S500.

[0159] S100, such as Fig.13a As shown, an epitaxial layer 9 is formed on a substrate 1 .

[0160] Illustratively, the embodiment of the present disclosure may adopt an epitaxial growth process to grow an epitaxial layer 9 on a surface of one side of the substrate 1 .

[0161] The materials of the substrate 1 and the epitaxial layer 9 include, for example, wide bandgap semiconductor materials. Optionally, the material of the substrate 1 includes silicon carbide, and the material of the epitaxial layer 9 includes P-type lightly doped (p-) silicon carbide.

[0162] S200, such as Fig.13b As shown, a first doping region DR1 and a second doping region DR2 are formed on the epitaxial layer 9. The doping type of one of the first doping region DR1 and the second doping region DR2 is N-type, and the doping type of the other is P-type.

[0163] Exemplarily, the disclosed embodiment may adopt an ion implantation process to implant ions from the surface of the epitaxial layer 9 away from the substrate 1, and perform annealing activation to obtain an N-type heavily doped (n+) region and a P-type heavily doped (p+) region. Among them, one of the N-type heavily doped (n+) region and the P-type heavily doped (p+) region may be used as the first doping region DR1; the other may be used as the second doping region DR2. The first doping region DR1 and the second doping region DR2 are arranged at intervals to form a PN junction to form a diode.

[0164] Optionally, taking the doping type of the first doping region DR1 as P type and the doping type of the second doping region DR2 as N type as an example, Fig.13b As shown, before forming the second doping region DR2, an n-well region NW may be formed in the epitaxial layer 9, and then the second doping region DR2 may be formed in the n-well region NW.

[0165] The breakdown electric field of silicon carbide is much higher than the breakdown field strength of silicon. When the first doping region DR1 and the second doping region DR2 are formed in the silicon carbide epitaxial layer 9, the withstand voltage capability of the PN junction can be greatly improved at the same drift region width.

[0166] S300, such as Fig.13c As shown, an etch stop layer 10 , a channel layer 2 and a barrier layer 3 are sequentially formed on the epitaxial layer 9 .

[0167] For example, the embodiment of the present disclosure may adopt an epitaxial growth process to sequentially grow the etch stop layer 10, the channel layer 2 and the barrier layer 3. The materials of the channel layer 2 and the barrier layer 3 can refer to the relevant description above, which will not be repeated here.

[0168] The etching stop layer 10 is used to stop etching on one side surface of the etching stop layer 10 .

[0169] In some instances, such as Figure 13d-Figure 13f As shown, after the barrier layer 3 is formed, the above preparation method further includes: S310-S320.

[0170] S310, such as Fig.13d and Fig.13e As shown, a gate cap layer 4 is formed on the barrier layer 3 .

[0171] Exemplarily, the method for forming the gate cap layer 4 includes: epitaxially growing a gate cap film 4a on the barrier layer 3, and then etching the gate cap film 4a using a photolithography process or other suitable etching process to obtain the gate cap layer 4. The structure and materials of the gate cap layer 4 can be found in the above description, and will not be repeated here.

[0172] S320, such as Fig.13f As shown, a passivation layer 13 is formed on the gate cap layer 4 . The passivation layer 13 covers the gate cap layer 4 and the barrier layer 3 .

[0173] For example, the embodiment of the present disclosure may adopt a deposition process to form the above passivation layer 13. The material of the passivation layer 13 includes but is not limited to silicon nitride, aluminum nitride, aluminum oxide, silicon oxide, etc. The passivation layer 13 may be composed of a single thin film or a stack of multiple thin films.

[0174] S400, such as Figure 13g As shown, a first connection structure 11 and a second connection structure 12 are formed penetrating the barrier layer 3, the channel layer 2 and the etch stop layer 10 to the surface of the epitaxial layer 9 away from the substrate 1. One end of the first connection structure 11 close to the substrate 1 is electrically connected to the first doped region DR1, and one end of the second connection structure 12 close to the substrate 1 is electrically connected to the second doped region DR2.

[0175] Exemplarily, the first connection structure 11 and the second connection structure 12 are arranged at intervals. The first connection structure 11 and the second connection structure 12 are both columnar and extend along the thickness direction of the substrate 1 .

[0176] For example, when the passivation layer 13 is formed, the first connection structure 11 and the second connection structure 12 also penetrate the passivation layer 13 .

[0177] S500, such as Fig.13hAs shown, a gate 5, a source 6 and a drain 7 are formed on the barrier layer 3. The gate 5 is located between the source 6 and the drain 7. The end of the first connection structure 11 away from the substrate 1 is electrically connected to the source 6, and the end of the second connection structure 12 away from the substrate 1 is electrically connected to the target electrode, which is the drain 7 or the gate 5.

[0178] For example, Fig.13h As shown, in the case where a gate cap layer 4 and a passivation layer 13 are formed, a method for forming a gate 5, a source 6 and a drain 7 includes: first, using a suitable etching process such as a photolithography process to form two openings that penetrate the passivation layer 13 to the inside of the barrier layer 3, and then depositing metal materials in the two openings respectively to form a source 6 and a drain 7, and making the source 6 and the drain 7 form ohmic contacts with the barrier layer 3 respectively; then, using a suitable etching process such as a photolithography process to open an opening in the portion of the passivation layer 13 covering the gate cap layer 4 to expose a portion of the gate cap layer 4, and then depositing metal materials in the opening, and then using a suitable etching process such as a photolithography process to define the gate 5.

[0179] The beneficial effects that can be achieved by the method for preparing a semiconductor device provided in some embodiments of the present application are the same as the beneficial effects that can be achieved by the semiconductor device 400 in some of the above embodiments, and will not be repeated here.

[0180] In some embodiments, before the above S400 , that is, before forming the first connection structure 11 and the second connection structure 12 , the above preparation method further includes: S350 - S370 .

[0181] S350, such as Fig.14a As shown, a first plasma is used to etch and form a first through hole H1 and a second through hole H2 that penetrate the barrier layer 3 and extend to the inside of the channel layer 2 .

[0182] For example, Fig.14a As shown, before forming the first through hole H1 and the second through hole H2, a mask layer 17 may be deposited and formed. The mask layer 17 is, for example, a hard mask layer. In the case where the passivation layer 13 is formed, the mask layer 17 is located on the passivation layer 13. Two openings are provided in the mask layer 17, and the two openings are respectively arranged opposite to the first doping region DR1 and the second doping region DR2. In the process of forming the first through hole H1 and the second through hole H2, the passivation layer 13, the barrier layer 3 and the channel layer 2 may be etched based on the mask layer 17, and by controlling the etching time, the etching may be stopped inside the channel layer 2. The first through hole H1 and the second through hole H2 are located on opposite sides of the gate cap layer 4.

[0183] For example, the mask layer 17 may be a single-layer thin film, in which case the material of the mask layer 17 includes but is not limited to metal materials such as nickel (Ni), titanium (Ti), chromium (Cr), and other suitable materials. For another example, the mask layer 17 may include a plurality of thin films stacked in layers, and taking two thin films as an example, the material of the thin film on the side relatively close to the substrate 1 includes but is not limited to dielectric materials such as silicon oxide (SiO2), and the material of the thin film on the side relatively far from the substrate 1 includes but is not limited to metal materials such as nickel (Ni), titanium (Ti), chromium (Cr), and other suitable materials.

[0184] Exemplarily, the first plasma includes chlorine-based plasma. The atmosphere for generating the chlorine-based plasma may include, for example, chlorine (Cl 2 ), boron trichloride (BCl 3 ) or a mixed gas thereof with argon (Ar).

[0185] S360, such as Fig.14b As shown, based on the first through hole H1 and the second through hole H2 , the first plasma and the second plasma are used to etch the channel layer 2 to a surface of the etching stop layer 10 away from the substrate 1 .

[0186] The etching selectivity of the first plasma to the channel layer 2 is greater than the etching selectivity of the first plasma to the reactants generated by the second plasma and the etching stop layer 10. That is, when etching to the side surface of the etching stop layer 10 away from the substrate 1, the second plasma will chemically react with the etching stop layer 10 and generate reactants, which are attached to the side surface of the etching stop layer 10 away from the substrate 1; while the first plasma is difficult to etch and remove the reactants, so that the etching automatically stops at the side surface of the etching stop layer 10 away from the substrate 1.

[0187] Exemplarily, the second plasma includes a fluorine-based plasma. The generation atmosphere of the mixed plasma composed of the first plasma and the second plasma may include, for example, a mixed gas of chlorine, boron trichloride, sulfur hexafluoride, and argon. Furthermore, the material of the etching stop layer 10 includes aluminum. The fluorine-based plasma and the etching stop layer 10 will chemically react to generate aluminum fluoride, and it is difficult for the chlorine-based plasma to etch and remove the aluminum fluoride. In addition, the aluminum component in the etching stop layer is greater than or equal to a preset value. In this way, a self-termination etching effect can be achieved for the chlorine-based plasma, and the problem of failure of the self-termination etching effect can be avoided. Regarding the "preset value", please refer to the relevant description above, which will not be repeated here.

[0188] Optionally, the etching of the channel layer 2 by the chlorine-based plasma can be stopped at any position in the channel layer 2. For example, Fig.14aIn the embodiment, the etching stop position is closer to the etching stop layer 10. It is understandable that the chlorine-based plasma has a faster etching rate than the chlorine-based and fluorine-based mixed plasma. Stopping the etching of the channel layer 2 at a position closer to the etching stop layer 10 is beneficial to improving the etching efficiency.

[0189] S370, such as Fig.14c As shown, the etching stop layer 10 is etched through the first through hole H1 and the second through hole H2 to form a third through hole H3 connected to the first through hole H1 and a fourth through hole H4 connected to the second through hole H2. The first through hole H1 and the third through hole H3 expose the first doping region DR1, and the second through hole H2 and the fourth through hole H4 expose the second doping region DR2. In a direction parallel to the side surface of the substrate 1 close to the epitaxial layer 9, the size of the third through hole H3 is larger than the size of the first through hole H1, and the size of the fourth through hole H4 is larger than the size of the second through hole H2.

[0190] Exemplarily, before forming the third through hole H3 and the fourth through hole H4, the mask layer 17 may be removed by using dilute sulfuric acid, hydrofluoric acid or a special etching solution, or other suitable processes. Alternatively, when the mask layer 17 includes the above two films, the above process may be used to remove the film on one side relatively far from the substrate 1. This can avoid adverse effects in the subsequent process of forming the third through hole H3 and the fourth through hole H4.

[0191] exist Fig.14c In the structure shown, the first through hole H1 and the third through hole H3 are inverted T-shaped structures, and the second through hole H2 and the fourth through hole H4 are inverted T-shaped structures. The first through hole H1 and the third through hole H3 are used to accommodate the first connection structure 11, and the second through hole H2 and the fourth through hole H4 are used to accommodate the second connection structure 12.

[0192] By forming the interconnected first through hole H1 and the third through hole H3, and the interconnected second through hole H2 and the fourth through hole H4 in the above manner, it is possible to avoid etching the epitaxial layer 9 and the substrate 1 on the basis of electrically connecting the subsequently formed first connection structure 11 to the first doped region DR1 located in the epitaxial layer 9 and electrically connecting the subsequently formed second connection structure 12 to the second doped region DR2 located in the epitaxial layer 9, thereby avoiding affecting the surface roughness and interface state of the first doped region DR1 and the second doped region DR2.

[0193] Moreover, when the material of the epitaxial layer 9 includes silicon carbide, it is also possible to avoid leaving a large amount of carbon (C) deposition on the surface of the epitaxial layer 9 away from the substrate 1, thereby avoiding affecting the ohmic contact between the first connecting structure 11 and the first doping region DR1, and the ohmic contact between the second connecting structure 12 and the second doping region DR2.

[0194] In addition, by making the size of the third through hole H3 larger than the size of the first through hole H1, and the size of the fourth through hole H4 larger than the size of the second through hole H2, gaps can be provided between the etching stop layer 10 and the first connecting structure 11, and between the etching stop layer 10 and the second connecting structure 12, thereby avoiding leakage at the heterogeneous interface.

[0195] Therefore, in some examples, in the above S400 , forming the first connection structure 11 and the second connection structure 12 includes: S410 .

[0196] S410, combined Fig.14c and Figure 13g A first connection structure 11 is formed in the first through hole H1 and the third through hole H3, and a second connection structure 12 is formed in the second through hole H2 and the fourth through hole H4. In a direction parallel to the surface of the substrate 1 close to the epitaxial layer 9, the etch stop layer 10 and the first connection structure 11, and the etch stop layer 10 and the second connection structure 12 are separated by gaps.

[0197] Accordingly, in a direction parallel to the side surface of the substrate 1 close to the epitaxial layer 9, the size of the first connection structure 11 is smaller than the size of the third through hole H3, and the size of the second connection structure 12 is smaller than the size of the fourth through hole H4. Further, the side wall of the third through hole H3 surrounds the first connection structure 11, and there is a gap between the first connection structure 11; the side wall of the fourth through hole H4 surrounds the second connection structure 12, and there is a gap between the second connection structure 12. The gap between the side wall of the third through hole H3 and the first connection structure 11 is filled with air, for example, and the gap between the fourth through hole H4 and the second connection structure 12 is filled with air, for example.

[0198] This can reduce interface leakage and improve the performance of the semiconductor device 400 formed.

[0199] Illustratively, in the above S410 , forming the first connection structure 11 and the second connection structure 12 includes: S411 - S412 .

[0200] S411, combined Fig.14c and Fig.14d , a first ohmic contact portion 111 is formed in the third through hole H3, and a second ohmic contact portion 121 is formed in the fourth through hole H4. The first ohmic contact portion 111 contacts the first doping region DR1, and the second ohmic contact portion 121 contacts the second doping region DR2. In a direction parallel to the surface of the substrate 1 close to the epitaxial layer 9, the etching stop layer 10 and the first ohmic contact portion 111, and the etching stop layer 10 and the second ohmic contact portion 121 are separated by the above-mentioned gap.

[0201] Illustratively, the embodiment of the present disclosure may use a deposition process to simultaneously deposit metal material in the third through hole H3 and the fourth through hole H4 to form a first ohmic contact portion 111 and a second ohmic contact portion 121; then an annealing treatment may be performed to form an ohmic contact between the first ohmic contact portion 111 and the first doped region DR1, and to form an ohmic contact between the second ohmic contact portion 121 and the second doped region DR2.

[0202] like Fig.14d As shown, the orthographic projection of the first ohmic contact portion 111 on the substrate 1 and the orthographic projection of the first through hole H1 on the substrate 1, for example, overlap. The orthographic projection of the second ohmic contact portion 121 on the substrate 1 and the orthographic projection of the second through hole H2 on the substrate 1, for example, overlap. In the direction parallel to the side surface of the substrate 1 close to the epitaxial layer 9, the size of the first ohmic contact portion 111 is smaller than the size of the third through hole H3, and the size of the second ohmic contact portion 121 is smaller than the size of the fourth through hole H4.

[0203] The thickness of the first ohmic contact portion 111 and the second ohmic contact portion 121 can be set according to actual production needs. Fig.14d In the embodiment, along the thickness direction of the substrate 1 , the thickness of the first ohmic contact portion 111 is greater than the depth of the third through hole H3 , and the thickness of the second ohmic contact portion 121 is greater than the depth of the fourth through hole H4 .

[0204] S412, combined Fig.14d and Fig.13h A first connection portion 112 connected to the first ohmic contact portion 111 is formed in the first through hole H1 , and a second connection portion 122 connected to the second ohmic contact portion 121 is formed in the second through hole H2 .

[0205] For example, the embodiment of the present disclosure may use a deposition process to simultaneously deposit metal materials in the first through hole H1 and the second through hole H2 to form the first connection portion 112 and the second connection portion 122. The first connection portion 112 and the first ohmic contact portion 111 constitute the first connection structure 11, and the second connection portion 122 and the second ohmic contact portion 121 constitute the second connection structure 12.

[0206] In some examples, in the above S370, the third through hole H3 and the fourth through hole H4 are formed, including: using an etching solution, through the first through hole H1 and the second through hole H2, the etching stop layer 10 is longitudinally etched along the thickness direction of the substrate 1, and the etching stop layer 10 is transversely etched along a direction parallel to the side surface of the substrate 1 close to the epitaxial layer 9, to form the third through hole H3 and the fourth through hole H4.

[0207] Exemplarily, the etching solution is, for example, an alkaline solution. That is, the embodiment of the present disclosure can use a wet etching process to etch the etching stop layer 10. Since wet etching is isotropic etching, while the etching stop layer 10 is longitudinally etched to expose the first doping region DR1 and the second doping region DR2, the etching stop layer 10 is also transversely etched. After the longitudinal etching is completed, the transverse etching is stopped.

[0208] Optionally, the alkaline solution includes but is not limited to potassium hydroxide solution, tetramethylammonium hydroxide (TMAH) solution, etc. The temperature range for wet etching the etch stop layer 10 may be 60° C.-90° C.

[0209] The alkaline solution has a wet etching effect on the specific crystal orientation of the side wall of the gallium nitride structure. In the embodiment of the present disclosure, before forming the third through hole H3 and the fourth through hole H4, the mask layer 17 is processed to retain the passivation layer 13 (even retaining the thin film of dielectric materials such as silicon oxide in the mask layer 17), which can protect the side surface of the barrier layer 3 away from the substrate 1 and the side wall of the gate cap layer 4.

[0210] In addition, the material of the epitaxial layer has a high tolerance to the etching solution. By etching the etching stop layer 10 with the etching solution, it is possible to avoid affecting the roughness of the surface of the epitaxial layer 9 on the side away from the substrate 1, which is exposed by the third through hole H3 and the fourth through hole H4, and avoid affecting the ohmic contact between the first connection structure 11 and the first doping region DR1, and between the second connection structure 12 and the second doping region DR2.

[0211] Exemplarily, the roughness of the surface of the epitaxial layer 9 on one side away from the substrate 1, which is exposed by the third through hole H3 and the fourth through hole H4, is the same as the roughness of the surface of the portion not exposed by the third through hole H4 and the fourth through hole H4. For the same roughness, please refer to the relevant description above, which will not be repeated here.

[0212] The embodiment of the present disclosure measures the roughness of the surface of the epitaxial layer 9 away from the substrate 1 after etching using the method shown in S350-S370 above; and then also measures the roughness of the surface of the epitaxial layer 9 away from the substrate 1 after plasma etching of the barrier layer and the channel layer without an etching stop layer. It can be understood that in the case where an etching stop layer is not provided, in order to ensure etching efficiency, the etching rate of the through hole is relatively fast, so it is difficult to stop etching more accurately on the surface of the epitaxial layer away from the substrate 1, and a certain amount of over-etching will be formed on the epitaxial layer.

[0213] Wherein, the AFM image of the morphology of the surface of the epitaxial layer away from the substrate 1 is as follows: Fig.15 As shown in (a) in Fig.15 As can be seen from (a) in the figure, the surface is severely etched and the atomic-level surface is destroyed. After measurement, the surface roughness (Rq) reaches 5.58nm.

[0214] After etching to the surface of the epitaxial layer 9 away from the substrate 1 by the method shown in S350-S370 above, the AFM image of the morphology of the surface is as follows: Fig.15 As shown in (b) in Fig.15 As can be seen from (b) in FIG. 1 , the surface is basically not etched and the atomic-level surface is relatively flat. The surface roughness (Rq) is measured to be 0.15 nm, which is basically consistent with the roughness of the surface of the epitaxial layer 9 before the epitaxial growth of the etching stop layer 10 (or the surface of the epitaxial layer 9 that is not exposed by the third through hole H4 and the fourth through hole H4).

[0215] In addition, the ohmic contact characteristics after the first ohmic contact portion 111 and the second ohmic contact portion 121 are formed are calculated.

[0216] After the epitaxial layer 9 is overetched and the first ohmic contact portion 111 and the second ohmic contact portion 121 are formed, the current-voltage curve is as follows: Fig.16 As shown, from Fig.16 It can be seen that after the ohmic contact is formed through annealing, the contact resistance is relatively large, and the curve has nonlinear characteristics.

[0217] After etching to the surface of the epitaxial layer 9 away from the substrate 1 by the method shown in S350-S370 above and forming the first ohmic contact portion 111 and the second ohmic contact portion 121, the current-voltage curve is as follows: Fig.17 As shown, from Fig.17 It can be seen that after annealing to form an ohmic contact, the contact resistance is relatively small, the current becomes larger, and the curve has a linear characteristic.

[0218] That is, the method shown in S350-S370 provided in the embodiment of the present disclosure can effectively protect the epitaxial layer 9, so that the roughness of the surface of the epitaxial layer 9 away from the substrate 1 remains substantially unchanged. Further, it is helpful to reduce the contact resistance and optimize the current-voltage characteristics.

[0219] In some embodiments, Fig.13h As shown, the method for preparing a semiconductor device provided by the present disclosure further includes: forming a first interconnection 14 and a second interconnection 15. The first interconnection 14 is located on the first connection structure 11 and the source 6, and connects one end of the first connection structure 11 away from the substrate 1 and the source 6. The second interconnection 15 is located on the second connection structure 12 and the target electrode, and connects one end of the second connection structure 12 away from the substrate 1 and the target electrode.

[0220] Take the second interconnection 15 connecting the second connection structure 12 and the drain 7 as an example. The method of forming the first interconnection 14 and the second interconnection 15 includes, for example, depositing metal material on the side of the first connection structure 11 and the source 6 away from the substrate 1, and on the side of the second connection structure 12 and the drain 7 away from the substrate 1, to obtain the first interconnection 14 and the second interconnection 15.

[0221] The present disclosure also provides a power switch device, such as Fig.18 As shown, the power switch device 500 includes a package substrate 510 and a semiconductor device 400 . The semiconductor device 400 is, for example, any one of the semiconductor devices 400 described in the above embodiments. The semiconductor device 400 is electrically connected to the package substrate 510 .

[0222] Exemplarily, the power switch device 500 may further include a first connector 520, and the semiconductor device 400 may be connected to the package substrate 510 through the first connector 520. The first connector 520 is, for example, a controlled collapse chip connection bump (C4 bump) or a micro bump. Further, the power switch device 500 may further include a second connector 530, and the package substrate 510 in the power switch device 500 may be connected to other electronic devices, such as being electrically connected to a printed circuit board, through the second connector 530. The second connector 530 is, for example, a solder ball or a micro bump.

[0223] In this way, communication between the semiconductor device 400 and other electronic devices can be achieved.

[0224] The present disclosure also provides a power conversion circuit. Fig.19 As shown, the power conversion circuit 600 includes a circuit board 610 and a power switch device 500. The power switch device 500 is, for example, any of the power switch devices 500 described in the above embodiments. The power switch device 500 and the circuit board 610 are electrically connected.

[0225] Exemplarily, the circuit board 610 may be a printed circuit board. The power conversion circuit 600 may be a step-down Buck power conversion circuit, a step-up Boots power conversion circuit, a voltage regulator circuit WS, a low-dropout regulator (LDO), or other power conversion circuits. The disclosed embodiment does not impose any special restrictions on the specific form of the power conversion circuit 600.

[0226] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: substrate; An epitaxial layer is located on the substrate; a first doping region and a second doping region are provided in the epitaxial layer, and the doping type of one of the first doping region and the second doping region is N-type, and the doping type of the other is P-type; An etch stop layer, located on the epitaxial layer; A channel layer, located on the etch stop layer; A barrier layer, located on the channel layer; The gate, source and drain are all located on the barrier layer; the gate is located between the source and the drain; The first connection structure and the second connection structure both penetrate the barrier layer, the channel layer and the etching stop layer to a surface of the epitaxial layer away from the substrate; Among them, the first connection structure has an end close to the substrate electrically connected to the first doped region, and an end away from the substrate electrically connected to the source; the second connection structure has an end close to the substrate electrically connected to the second doped region, and an end away from the substrate electrically connected to the target electrode, and the target electrode is the drain or the gate.

2. The semiconductor device according to claim 1, wherein: In a direction parallel to a surface of the substrate close to the epitaxial layer, the etch stop layer and the first connection structure, as well as the etch stop layer and the second connection structure are separated by gaps.

3. The semiconductor device according to claim 1, wherein: The orthographic projection of the first connection structure on the substrate is located within the orthographic projection range of the first doped region on the substrate; The orthographic projection of the second connection structure on the substrate is located within the orthographic projection range of the second doping region on the substrate.

4. The semiconductor device according to claim 1, wherein: The roughness of a portion of the surface of the epitaxial layer on one side away from the substrate, which is located within the first doping region and the second doping region, is the same as the roughness of a portion of the surface located outside the first doping region and the second doping region.

5. The semiconductor device according to claim 1, wherein: The thickness of the etching stop layer is in the range of 10 nm to 100 nm.

6. The semiconductor device according to claim 1, wherein: The material of the etch stop layer includes aluminum, and the aluminum component in the etch stop layer is greater than or equal to a preset value.

7. The semiconductor device according to claim 6, characterized in that The material of the etching stop layer includes at least one of aluminum gallium nitride, aluminum nitride, aluminum indium nitride, and aluminum gallium indium nitride.

8. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: A first interconnection portion, located on the first connection structure and the source electrode, and connecting an end of the first connection structure away from the substrate and the source electrode; The second interconnection portion is located on the second connection structure and the target electrode, and connects an end of the second connection structure away from the substrate and the target electrode.

9. The semiconductor device according to claim 1, wherein: The first connection structure includes a first ohmic contact portion and a first connection portion connected to each other, the first ohmic contact portion is in contact with the first doped region, and the first connection portion is located on a side of the first ohmic contact portion away from the substrate; The second connection structure includes a second ohmic contact portion and a second connection portion connected to each other, the second ohmic contact portion is in contact with the second doped region, and the second connection portion is located on a side of the second ohmic contact portion away from the substrate.

10. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: A gate cap layer, located between the barrier layer and the gate; A passivation layer is located on the barrier layer and between the gate cap layer and the gate; an opening is opened in the passivation layer, and the gate contacts the gate cap layer through the opening; the source, the drain, the first connection structure and the second connection structure all penetrate the passivation layer.

11. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: a buffer layer and / or an n-well region; The buffer layer is located between the etch stop layer and the channel layer, and the first connection structure and the second connection structure also penetrate the buffer layer; The n-well region is located in the epitaxial layer, and the second doped region is located in the n-well region.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that: Materials of the substrate and the epitaxial layer include wide bandgap semiconductor materials.

13. A method for preparing a semiconductor device, characterized in that: The preparation method comprises: forming an epitaxial layer on a substrate; forming a first doping region and a second doping region on the epitaxial layer; the doping type of one of the first doping region and the second doping region is N-type, and the doping type of the other is P-type; forming an etch stop layer, a channel layer and a barrier layer in sequence on the epitaxial layer; A first connection structure and a second connection structure are formed that penetrate the barrier layer, the channel layer and the etch stop layer to a surface of the epitaxial layer away from the substrate; an end of the first connection structure close to the substrate is electrically connected to the first doped region; an end of the second connection structure close to the substrate is electrically connected to the second doped region; A gate, a source and a drain are formed on the barrier layer; the gate is located between the source and the drain; an end of the first connection structure away from the substrate is electrically connected to the source, and an end of the second connection structure away from the substrate is electrically connected to a target electrode, and the target electrode is the drain or the gate.

14. The preparation method according to claim 13, characterized in that: Before forming the first connection structure and the second connection structure, the preparation method further includes: Using a first plasma, etching to form a first through hole and a second through hole penetrating the barrier layer and extending into the channel layer; Based on the first through hole and the second through hole, the first plasma and the second plasma are used to etch the channel layer to a surface of the etching stop layer away from the substrate; the etching selectivity of the first plasma to the channel layer is greater than the etching selectivity of the first plasma to the reactants generated by the second plasma and the etching stop layer; The etching stop layer is etched through the first through hole and the second through hole to form a third through hole connected to the first through hole and a fourth through hole connected to the second through hole; the first through hole and the third through hole expose the first doped region, and the second through hole and the fourth through hole expose the second doped region; in a direction parallel to a side surface of the substrate close to the epitaxial layer, a size of the third through hole is larger than a size of the first through hole, and a size of the fourth through hole is larger than a size of the second through hole.

15. The preparation method according to claim 14, characterized in that: The first plasma comprises a chlorine-based plasma, and the second plasma comprises a fluorine-based plasma; The material of the etch stop layer includes aluminum, and the aluminum component in the etch stop layer is greater than or equal to a preset value.

16. The preparation method according to claim 14, characterized in that: Forming the third through hole and the fourth through hole comprises: An etching solution is used to longitudinally etch the etch stop layer along the thickness direction of the substrate through the first through hole and the second through hole, and to transversely etch the etch stop layer along a direction parallel to a surface of one side of the substrate close to the epitaxial layer, so as to form the third through hole and the fourth through hole.

17. The preparation method according to claim 16, characterized in that: The roughness of a portion of the surface of the epitaxial layer on one side away from the substrate that is exposed by the third through hole and the fourth through hole is the same as the roughness of a portion of the surface that is not exposed by the third through hole and the fourth through hole.

18. The preparation method according to claim 14, characterized in that: Forming the first connection structure and the second connection structure includes: The first connection structure is formed in the first through hole and the third through hole, and the second connection structure is formed in the second through hole and the fourth through hole; in a direction parallel to the surface of the side of the substrate close to the epitaxial layer, the etching stop layer and the first connection structure, and the etching stop layer and the second connection structure are separated by gaps.

19. The preparation method according to claim 18, characterized in that: The forming of the first connection structure in the first through hole and the third through hole, and the forming of the second connection structure in the second through hole and the fourth through hole, comprises: A first ohmic contact is formed in the third through hole, and a second ohmic contact is formed in the fourth through hole; the first ohmic contact is in contact with the first doped region, and the second ohmic contact is in contact with the second doped region; in a direction parallel to a surface of the substrate close to the epitaxial layer, the etch stop layer and the first ohmic contact are separated by the gap, as are the etch stop layer and the second ohmic contact; A first connection portion connected to the first ohmic contact portion is formed in the first through hole, and a second connection portion connected to the second ohmic contact portion is formed in the second through hole.

20. The preparation method according to claim 14, characterized in that: Before forming the first through hole and the second through hole, the preparation method further includes: forming a gate cap layer on the barrier layer; forming a passivation layer on the gate cap layer; the passivation layer covers the gate cap layer and the barrier layer; In the process of forming the first through hole and the second through hole, the first through hole and the second through hole also penetrate the passivation layer, and the first through hole and the second through hole are located at two opposite sides of the gate cap layer.

21. The preparation method according to claim 13, characterized in that: The preparation method further comprises: A first interconnection portion and a second interconnection portion are formed; the first interconnection portion is located on the first connection structure and the source electrode, and connects one end of the first connection structure away from the substrate and the source electrode; the second interconnection portion is located on the second connection structure and the target electrode, and connects one end of the second connection structure away from the substrate and the target electrode.

22. A power switching device, characterized in that: The power switch device comprises: A semiconductor device, which is a semiconductor device as claimed in any one of claims 1 to 12; A packaging substrate is electrically connected to the semiconductor device.

23. A power conversion circuit, characterized in that: The power conversion circuit comprises: A power switching device, which is the power switching device as claimed in claim 22; A circuit board is electrically connected to the power switch device.

24. An electronic device, characterized in that: The electronic device comprises: A power switching device, which is the power switching device as claimed in claim 22; A circuit board is electrically connected to the power switch device.

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