Semiconductor devices

Abstract

The present invention discloses a semiconductor device, which includes: a substrate; a drift layer; a well layer; a groove; a source layer; a collector layer; a cathode layer; a plurality of fast recovery diode regions, wherein the plurality of fast recovery diode regions constitute at least two fast recovery diode region groups, wherein the spacing distance between two adjacent fast recovery diode regions in each fast recovery diode region group in the second direction is set to A, the spacing distance between two adjacent fast recovery diode region groups in the third direction is set to B, the length of the fast recovery diode region in the second direction is set to C, the length of the fast recovery diode region in the third direction is set to D, and A, B, C and D satisfy the relationship: 0.5C<A<2C, 0.5D<B<2D. Thus, the distribution of the plurality of fast recovery diode regions can be made more uniform and reasonable, the heat of the fast recovery diode regions can be dissipated in time, the heat dissipation performance of the semiconductor device can be improved, and heat accumulation can be effectively avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] RC-IGBT (reverse conducting-Insulated Gate Bipolar Transistor) refers to the integration of IGBT (Insulated Gate Bipolar Transistor) and FRD (Fast Recovery Diode) on a single chip. Generally speaking, the industry usually integrates IGBT and FRD in the active area of ​​the chip, and the two share terminals, thus realizing a highly integrated RC-IGBT, without the need to connect the two discrete devices IGBT and FRD through packaging.

[0003] In the related art, the layout of the insulated gate bipolar transistor region and the fast recovery diode region in the active area is not reasonable enough, which easily leads to heat accumulation or uneven heat dissipation, resulting in a decrease in the working performance of the RC-IGBT, a decrease in reliability and stability, and a shortened service life of the RC-IGBT. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor device with better heat dissipation performance.

[0005] According to an embodiment of the present invention, a semiconductor device comprises: a substrate, the substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface and the second main surface being spaced apart in a first direction; a drift layer of a first conductivity type, the drift layer being disposed on the substrate and between the first main surface and the second main surface; a well layer of a second conductivity type, the well layer being disposed on a side of the drift layer facing the first main surface, a surface of the well layer on a side of the first direction away from the drift layer constituting a part of the first main surface, the thickness of the well layer extending from the first main surface along the first direction toward the second main surface; a groove, the groove thickness direction penetrating the well layer from the first main surface to reach the drift layer, the length direction of the groove extending in the second direction, the groove being a plurality of grooves, the plurality of grooves being spaced apart in a third direction, wherein the first direction, the second direction and the third direction are perpendicular to each other; an active layer of a first conductivity type, the semiconductor device comprising an active region and a terminal region, the terminal region being circumferentially disposed outside the active region, the active region comprising a fast recovery diode region and an insulated gate bipolar crystal region. a transistor region, the insulated gate bipolar transistor region is circumferentially arranged in the fast recovery diode region, the source layer is arranged in the well layer corresponding to the insulated gate bipolar transistor region, a surface of the source layer on one side away from the drift layer in a first direction constitutes a part of the first main surface, the thickness of the source layer extends from the first main surface toward the second main surface along the first direction, and the thickness of the source layer is less than the thickness of the well layer; a collector layer of a second conductivity type, the collector layer is arranged on a side of the drift layer facing the second main surface and corresponding to the insulated gate bipolar transistor region, a surface of the collector layer on one side away from the drift layer in a first direction constitutes a part of the second main surface, and the thickness of the collector layer extends from the second main surface toward the first main surface along the first direction; a cathode layer of a first conductivity type, the cathode layer is arranged on a side of the drift layer facing the second main surface and corresponding to the fast recovery diode region, a surface of the cathode layer on one side away from the drift layer in a first direction constitutes a part of the second main surface, and the thickness of the cathode layer extends from the second main surface toward the first main surface along the first direction;There are multiple fast recovery diode regions, and the insulated gate bipolar transistor region is arranged around the outside of the multiple fast recovery diode regions. The multiple fast recovery diode regions constitute at least two fast recovery diode region groups spaced apart in the third direction. The fast recovery diode region group includes at least two fast recovery diode regions spaced apart in the second direction. The spacing distance between two adjacent fast recovery diode regions in each fast recovery diode region group in the second direction is set to A, the spacing distance between two adjacent fast recovery diode region groups in the third direction is set to B, the length of the fast recovery diode region in the second direction is set to C, and the length of the fast recovery diode region in the third direction is set to D. A, B, C and D satisfy the relationship: 0.5C<A<2C, 0.5D<B<2D. ;

[0006] Therefore, by providing multiple fast recovery diode regions and making A, B, C and D satisfy the relationship: 0.5C<A<2C, 0.5D<B<2D, multiple fast recovery diode regions can be dispersedly arranged in the active area of ​​the semiconductor device, and the distribution of the multiple fast recovery diode regions can be more uniform and reasonable, so that the heat of the fast recovery diode region can be dissipated in time while ensuring the miniaturization of the semiconductor device, thereby improving the heat dissipation performance of the semiconductor device and effectively avoiding heat accumulation.

[0007] In some examples of the present invention, A satisfies the relationship: 200 μm<A<800 μm.

[0008] In some examples of the present invention, B satisfies the relationship: 200 μm<B<800 μm.

[0009] In some examples of the present invention, A, B, C and D satisfy the relationship: A=B, C=D.

[0010] In some examples of the present invention, the length C of the fast recovery diode region in the second direction is proportional to the spacing distance A between two adjacent fast recovery diode regions in each fast recovery diode region group in the second direction; and / or the length D of the fast recovery diode region in the third direction is proportional to the spacing distance B between two adjacent fast recovery diode region groups in the third direction.

[0011] In some examples of the present invention, the length of the active region in the second direction is E, and E and C satisfy the relationship: 5.2<E / C<20.

[0012] In some examples of the present invention, the length of the active region in the third direction is F, and F and D satisfy the relationship: 5.2<F / D<20.

[0013] In some examples of the present invention, from a top-down perspective, the fast recovery diode area is rectangular, and any two of the multiple fast recovery diode areas that are spaced apart in the second direction are set as the first fast recovery diode area and the second fast recovery diode area, and the multiple fast recovery diode areas that are adjacent to the first fast recovery diode area in the third direction are set as the third fast recovery diode area, and the multiple fast recovery diode areas that are adjacent to the second fast recovery diode area in the third direction are set as the fourth fast recovery diode area, and the third fast recovery diode area and the fourth fast recovery diode area are adjacently arranged in the second direction; the diagonal lengths of the first fast recovery diode area, the second fast recovery diode area, the third fast recovery diode area and the fourth fast recovery diode area are set as G; the first fast recovery diode area is closest to the first fast recovery diode area. The spacing distance between the end of the fourth fast recovery diode region and the end of the fourth fast recovery diode region closest to the first fast recovery diode region is H, and the spacing distance between the end of the second fast recovery diode region closest to the third fast recovery diode region and the end of the third fast recovery diode region closest to the second fast recovery diode region is H; the spacing distance between the end of the first fast recovery diode region farthest from the fourth fast recovery diode region and the end of the fourth fast recovery diode region farthest from the first fast recovery diode region is I, and the spacing distance between the end of the second fast recovery diode region farthest from the third fast recovery diode region and the end of the third fast recovery diode region farthest from the second fast recovery diode region is I, and I, G, and H satisfy the relationship: 2.5<I / G<4, 1.7<I / H<3.3.

[0014] In some examples of the present invention, one of the two adjacent fast recovery diode region groups is set as a first fast recovery diode region group, and the other is set as a second fast recovery diode region group, the projection of the fast recovery diode region in the first fast recovery diode region group in the third direction is a first projection portion, the projection of the fast recovery diode region in the second fast recovery diode region group in the third direction is a second projection portion, and the first projection portion and the second projection portion overlap with each other.

[0015] In some examples of the present invention, one of the two adjacent fast recovery diode region groups is set as a first fast recovery diode region group, and the other is set as a second fast recovery diode region group, the projection of the fast recovery diode region in the first fast recovery diode region group in the third direction is a first projection portion, and the projection of the fast recovery diode region in the second fast recovery diode region group in the third direction is a second projection portion, and the first projection portion and the second projection portion at least partially overlap with each other and are at least partially staggered with each other.

[0016] In some examples of the present invention, there are at least two fast recovery diode region groups, and at least two of the fast recovery diode region groups include at least one long fast recovery diode region group and at least one short fast recovery diode region group; an avoidance gap is provided at the end of the active area, and the semiconductor device also includes a gate pad, and the gate pad is provided in the avoidance gap, the long fast recovery diode region group and the gate pad are spaced apart in a third direction, and at least part of the short fast recovery diode region group and the gate pad are spaced apart in a second direction; the long fast recovery diode region group includes at least three of the fast recovery diode regions, the short fast recovery diode region group includes at least two of the fast recovery diode regions, and the number of the fast recovery diode regions in the long fast recovery diode region group is greater than the number of the fast recovery diode regions in the short fast recovery diode region group, so that the short fast recovery diode region group avoids the gate pad in the second direction.

[0017] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 2 is a schematic diagram of a semiconductor device according to another embodiment of the present invention; Figure 3 yes Figure 1 Middle A area or Figure 2 Schematic diagram of area B in the middle; Figure 4 is a partial cross-sectional view of a semiconductor device along the AA direction according to an embodiment of the present invention; Figure 5 is a partial cross-sectional view of a semiconductor device along direction BB according to an embodiment of the present invention; Figure 6 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention; Figure 7 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention; Figure 8 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention; Fig. 9 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention; Fig.10 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention; Fig.11 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention; Fig.12 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention; Fig.13 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention; Fig.14 is a schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0019] Reference numerals: 100. Semiconductor devices; 110, active region; 111, insulated gate bipolar transistor region; 112, fast recovery diode region; 1121, fast recovery diode region group; 1122, first fast recovery diode region group; 1123, second fast recovery diode region group; 1124, fast recovery diode main conductive region; 1125, transition region; 1126, long fast recovery diode region group; 1127, short fast recovery diode region group; 1128, first fast recovery diode region; 1129, second fast recovery diode region; 1130, third fast recovery diode region; 1131, fourth fast recovery diode region; 113, avoidance gap; 120, terminal region; 130, gate pad; 10. substrate; 101. first main surface; 102. second main surface; 11. drift layer; 12. well layer; 13. source layer; 14. field stop layer; 15. collector layer; 16. cathode layer; 17. trench; 20. Oxidation insulating layer; 30. Polysilicon; 40. Dielectric layer; 41. Contact hole; 50. Emitter metal layer; 60. Collector metal layer. DETAILED DESCRIPTION

[0020] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0021] Reference below Figure 1-Figure 14The semiconductor device according to the embodiment of the present invention is described. The semiconductor device 100 may adopt the manufacturing method of the semiconductor device 100. The semiconductor device 100 may be an RC-IGBT (reverse conducting-insulated gate bipolar transistor). In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is set to N type and the second conductivity type is set to P type for description. In addition, the first direction, the second direction and the third direction are perpendicular to each other.

[0022] Combination Figure 1-Figure 5 As shown, the semiconductor device 100 according to the present invention may mainly include: a substrate 10, a drift layer 11 of a first conductivity type, a well layer 12 of a second conductivity type, a trench 17, a source layer 13 of a first conductivity type, a collector layer 15 of a second conductivity type and a cathode layer 16 of a first conductivity type.

[0023] The semiconductor device 100 may include an active region 110 and a terminal region 120, wherein the terminal region 120 is circumferentially arranged outside the active region 110, and the active region 110 may mainly include an insulated gate bipolar transistor region 111 and a fast recovery diode region 112, wherein the insulated gate bipolar transistor region 111 is circumferentially arranged outside the fast recovery diode region 112, so that the insulated gate bipolar transistor region 111 and the fast recovery diode region 112 may share the terminal region 120. In this way, the insulated gate bipolar transistor region 111 may realize forward conduction of the semiconductor device 100, and the fast recovery diode region 112 may realize reverse conduction of the semiconductor device 100, so that the semiconductor device 100 has the characteristics of both forward conduction and reverse conduction.

[0024] Specifically, the substrate 10 has a first main surface 101 and a second main surface 102 on the opposite side of the first main surface 101, the first main surface 101 and the second main surface 102 are arranged at intervals in the first direction, the drift layer 11 is arranged on the substrate 10 and is located between the first main surface 101 and the second main surface 102, the well layer 12 is arranged on the side of the drift layer 11 facing the first main surface 101, the upper surface of the well layer 12 constitutes a part of the first main surface 101, and the thickness of the well layer 12 extends from the first main surface 101 along the first direction toward the second main surface 102.

[0025] Furthermore, a groove 17 is provided in the substrate 10, and the groove 17 penetrates the well layer 12 from the first main surface 101 in the thickness direction to reach the drift layer 11. The length direction of the groove 17 extends in the second direction of the semiconductor device 100. There are multiple grooves 17, and the multiple grooves 17 are arranged at intervals in the third direction of the semiconductor device 100.

[0026] Part of the plurality of trenches 17 is located in the insulated gate bipolar transistor region 111, and an oxidized insulating layer 20 and polysilicon 30 are sequentially arranged in the trenches 17 of the part, so that a gate can be formed at the trenches 17, and the plurality of trenches 17 are electrically connected to the gate pad 130. Also, another part of the plurality of trenches 17 is located in the fast recovery diode region 112, and an oxidized insulating layer 20 and polysilicon 30 are arranged in the trenches 17 of the part, and the trenches 17 are electrically connected to the emitter metal layer 50.

[0027] Furthermore, the source layer 13 is arranged on both sides of the groove 17 of the well layer 12 located in the insulated gate bipolar transistor region 111, and the side surface of the source layer 13 in the first direction away from the drift layer 11 constitutes a part of the first main surface 101. The thickness of the source layer 13 extends from the first main surface 101 along the first direction toward the second main surface 102, and the thickness of the source layer 13 in the first direction is less than the thickness of the well layer 12 in the first direction.

[0028] The collector layer 15 is arranged on the side of the drift layer 11 facing the second main surface 102 and corresponds to the insulated gate bipolar transistor region 111. The surface of the collector layer 15 on the side away from the drift layer 11 in the first direction constitutes a part of the second main surface 102. The thickness of the collector layer 15 extends from the second main surface 102 along the first direction toward the first main surface 101. The collector layer 15 corresponds to the insulated gate bipolar transistor region 111 in the first direction.

[0029] The cathode layer 16 is arranged on the side of the drift layer 11 facing the second main surface 102 and corresponds to the fast recovery diode region 112. The surface of the cathode layer 16 on the side away from the drift layer 11 in the first direction constitutes a part of the second main surface 102. The thickness of the cathode layer 16 extends from the second main surface 102 along the first direction toward the first main surface 101. The cathode layer 16 corresponds to the fast recovery diode region 112 in the first direction.

[0030] Furthermore, the dielectric layer 40 is arranged on the first main surface 101, the emitter metal layer 50 is arranged on the side of the dielectric layer 40 away from the first main surface 101, the emitter metal layer 50 at least partially passes through the dielectric layer 40 to contact the well layer 12, the emitter metal layer 50 can not only serve as the emitter lead-in terminal of the insulated gate bipolar transistor region 111, but also serve as the anode lead-in terminal of the fast recovery diode region 112, and the second main surface 102 of the substrate 10 is also provided with a collector metal layer 60, the collector metal layer 60 can not only serve as the collector lead-in terminal of the insulated gate bipolar transistor region 111, but also serve as the cathode lead-in terminal of the fast recovery diode region 112.

[0031] It can be understood that the semiconductor device 100 can realize the integration of IGBT and FRD, which not only has the advantage of size reduction, but also has obvious advantages in working performance, such as high power density, high reliability, etc.

[0032] However, when the semiconductor device 100 is operating, the insulated gate bipolar transistor region 111 and the fast recovery diode region 112 will generate heat. Heat accumulation or uneven heat dissipation will lead to a decrease in the operating performance, reliability and stability of the semiconductor device 100, and a shortened service life of the semiconductor device 100.

[0033] In the prior art, the fast recovery diode region is often set as a whole, the fast recovery diode region is set in the middle of the active area of ​​the semiconductor device, or a plurality of fast recovery diode regions are set, but the area of ​​a single fast recovery diode region is large, and the insulated gate bipolar transistor region is surrounded by the fast recovery diode region. When the semiconductor device is working, the working heat of the fast recovery diode region cannot be dissipated in time, resulting in heat accumulation and poor heat dissipation performance.

[0034] In this application, combined Figure 1 and Figure 2 As shown, there are multiple fast recovery diode regions 112, and the insulated gate bipolar transistor region 111 is arranged around the outside of the multiple fast recovery diode regions 112. The multiple fast recovery diode regions 112 constitute at least two fast recovery diode region groups 1121 spaced apart in the third direction. The fast recovery diode region group 1121 may include at least two fast recovery diode regions 112 spaced apart in the second direction.

[0035] Specifically, by providing a plurality of fast recovery diode regions 112, the insulated gate bipolar transistor region 111 is arranged around the outer sides of the plurality of fast recovery diode regions 112. In this way, while ensuring that the total areas of the fast recovery diode region 112 and the insulated gate bipolar transistor region 111 remain unchanged and the basic working performance of the semiconductor device 100 is ensured, the fast recovery diode region 112 is avoided from being concentrated in the middle of the active region 110 of the semiconductor device 100, and the plurality of fast recovery diode regions 112 are dispersedly arranged in the active region 110 of the semiconductor device 100, thereby facilitating the heat dissipation of the fast recovery diode region 112 and the insulated gate bipolar transistor region 111, so that the heat of the fast recovery diode region 112 can be dissipated in time, thereby improving the heat dissipation performance of the semiconductor device 100, avoiding heat accumulation, and further improving the working performance of the semiconductor device 100.

[0036] Furthermore, a plurality of fast recovery diode regions 112 are defined to constitute at least two fast recovery diode region groups 1121 spaced apart in the third direction, and each fast recovery diode region group 1121 may include at least two fast recovery diode regions 112 spaced apart in the second direction, so that the fast recovery diode regions 112 are dispersed not only in the third direction but also in the second direction, thereby making the distribution of the plurality of fast recovery diode regions 112 in the active area 110 more dispersed and reasonable, so that heat can be dissipated in time at various locations in the active area 110, effectively avoiding heat accumulation, and further improving the heat dissipation performance of the semiconductor device 100, and further improving the working performance of the semiconductor device 100.

[0037] Combination Figure 1 and Figure 2 As shown, the spacing distance between two adjacent fast recovery diode regions 112 in each fast recovery diode region group 1121 in the second direction is set to A, the spacing distance between two adjacent fast recovery diode region groups 1121 in the third direction is set to B, the length of the fast recovery diode region 112 in the second direction is set to C, and the length of the fast recovery diode region 112 in the third direction is set to D. A, B, C and D satisfy the relationship: 0.5C<A<2C, 0.5D<B<2D.

[0038] Specifically, when the ratio of the spacing distance between two adjacent fast recovery diode regions 112 in each fast recovery diode region group 1121 in the second direction to the length of the fast recovery diode region 112 in the second direction is not greater than 0.5, the spacing distance between two adjacent fast recovery diode regions 112 in each fast recovery diode region group 1121 in the second direction is too small compared to the length of the fast recovery diode region 112 in the second direction, which will cause the heat generated by each fast recovery diode region 112 to fail to dissipate in time in the second direction through the surrounding insulated gate bipolar transistor region 111, resulting in excessive local temperature due to insufficient heat dissipation.

[0039] When the ratio of the spacing distance between two adjacent fast recovery diode regions 112 in each fast recovery diode region group 1121 in the second direction to the length of the fast recovery diode region 112 in the second direction is not less than 2, the spacing distance between two adjacent fast recovery diode regions 112 in each fast recovery diode region group 1121 in the second direction is too large compared to the length of the fast recovery diode region 112 in the second direction. Under the premise of ensuring the overall area of ​​the fast recovery diode region 112, the overall size of the semiconductor device 100 in the second direction will be too large.

[0040] In this way, by setting the ratio between the spacing distance between two adjacent fast recovery diode regions 112 in each fast recovery diode region group 1121 in the second direction and the length of the fast recovery diode region 112 in the second direction within a reasonable range, a balance between the heat dissipation performance and miniaturization of the semiconductor device 100 in the second direction can be achieved.

[0041] Furthermore, when the ratio of the spacing distance between two adjacent fast recovery diode region groups 1121 in the third direction to the length of the fast recovery diode region 112 in the third direction is not greater than 0.5, the spacing distance between two adjacent fast recovery diode region groups 1121 in the third direction is too small compared to the length of the fast recovery diode region 112 in the third direction, which will cause the heat generated by each fast recovery diode region 112 to be unable to be dissipated in time in the third direction through the surrounding insulated gate bipolar transistor region 111, resulting in insufficient heat dissipation causing excessive local temperature.

[0042] When the ratio of the spacing distance between two adjacent fast recovery diode region groups 1121 in the third direction to the length of the fast recovery diode region 112 in the third direction is not less than 2, the spacing distance between two adjacent fast recovery diode region groups 1121 in the third direction is too large compared to the length of the fast recovery diode region 112 in the third direction. Under the premise of ensuring the overall area of ​​the fast recovery diode region 112, the overall size of the semiconductor device 100 in the third direction will be too large.

[0043] Thus, by setting the ratio between the spacing between two adjacent fast recovery diode region groups 1121 in the third direction and the length of the fast recovery diode region 112 in the third direction within a reasonable range, a balance between heat dissipation performance and miniaturization of the semiconductor device 100 in the third direction can be achieved.

[0044] Therefore, by providing a plurality of fast recovery diode regions 112 and making A, B, C and D satisfy the relationship: 0.5C<A<2C, 0.5D<B<2D, the plurality of fast recovery diode regions 112 can be dispersedly arranged in the active area 110 of the semiconductor device 100, and the distribution of the plurality of fast recovery diode regions 112 can be made more uniform and reasonable, so that the heat of the fast recovery diode region 112 can be dissipated in time while ensuring the miniaturization of the semiconductor device 100, thereby improving the heat dissipation performance of the semiconductor device 100 and effectively avoiding heat accumulation.

[0045] In some embodiments of the present invention, A satisfies the relationship: 200 μm<A<800 μm. In this way, the spacing distance between two adjacent fast recovery diode regions 112 in each fast recovery diode region group 1121 in the second direction can be set within a reasonable range, which can not only avoid the spacing distance between two adjacent fast recovery diode regions 112 in each fast recovery diode region group 1121 in the second direction being too small, resulting in the heat generated by each fast recovery diode region 112 being unable to be dissipated in time in the second direction through the surrounding insulated gate bipolar transistor region 111, but also avoid the spacing distance between two adjacent fast recovery diode regions 112 in each fast recovery diode region group 1121 in the second direction being too large, resulting in the overall size of the semiconductor device 100 in the second direction being too large while ensuring the overall area of ​​the fast recovery diode region 112, thereby ensuring the heat dissipation performance of the semiconductor device 100 in the second direction while ensuring the miniaturization of the semiconductor device 100.

[0046] In some embodiments of the present invention, B satisfies the relationship: 200 μm<B<800 μm. Such a setting can set the spacing distance between two adjacent fast recovery diode region groups 1121 in the third direction within a reasonable range, which can not only avoid the spacing distance between two adjacent fast recovery diode region groups 1121 in the third direction being too small, resulting in the heat generated by each fast recovery diode region 112 being unable to be dissipated in time through the surrounding insulated gate bipolar transistor region 111 in the third direction, but also avoid the spacing distance between two adjacent fast recovery diode region groups 1121 in the third direction being too large, resulting in the overall size of the semiconductor device 100 in the third direction being too large while ensuring the overall area of ​​the fast recovery diode region 112, thereby ensuring the heat dissipation performance of the semiconductor device 100 in the third direction while ensuring the miniaturization of the semiconductor device 100.

[0047] Further, A, B, C and D satisfy the relationship: A=B, C=D. In this way, the size of each fast recovery diode region 112 in the second direction and the size in the third direction can be made the same, and the distances between two adjacent fast recovery diode regions 112 in the second direction and the third direction can be equal, so that the distribution of the fast recovery diode regions 112 in the active area 110 is more uniform and reasonable, and each fast recovery diode region 112 can be uniformly dissipated in the first direction and the second direction to the insulated gate bipolar transistor region 111 surrounding it, and the heat dissipation efficiency is the same, so that the heat dissipation uniformity of each fast recovery diode region 112 in each direction can be improved, the heat dissipation performance of the semiconductor device 100 can be improved, and the temperature consistency of the semiconductor device 100 can be ensured.

[0048] In some embodiments of the present invention, the length C of the fast recovery diode region 112 in the second direction is proportional to the spacing distance A between two adjacent fast recovery diode regions 112 in each fast recovery diode region group 1121 in the second direction. That is, the spacing distance between two adjacent fast recovery diode regions 112 in each fast recovery diode region group 1121 in the second direction increases as the length of the fast recovery diode region 112 in the second direction increases. In this way, the spacing distance between two adjacent fast recovery diode regions 112 in each fast recovery diode region group 1121 in the second direction can be adapted to the length of the fast recovery diode region 112 in the second direction, and it can be ensured that the heat generated by each fast recovery diode region 112 can be dissipated in the second direction in a timely manner through the surrounding insulated gate bipolar transistor region 111.

[0049] In some embodiments of the present invention, the length D of the fast recovery diode region 112 in the third direction is proportional to the spacing distance B between two adjacent fast recovery diode region groups 1121 in the third direction. That is, the spacing distance between two adjacent fast recovery diode region groups 1121 in the third direction increases as the length of the fast recovery diode region 112 in the third direction increases. In this way, the spacing distance between two adjacent fast recovery diode region groups 1121 in the third direction can be adapted to the length of the fast recovery diode region 112 in the third direction, and it can be ensured that the heat generated by each fast recovery diode region 112 can be dissipated in time in the third direction through the surrounding insulated gate bipolar transistor region 111.

[0050] Combination Figure 1 and Figure 2 As shown, the length of the active region 110 in the second direction is E, and E and C satisfy the relationship: 5.2<E / C<20.

[0051] Specifically, when the ratio of the length of the active area 110 in the second direction to the length of the fast recovery diode region 112 in the second direction is not greater than 5.2, the length of the active area 110 in the second direction is too small compared to the length of the fast recovery diode region 112 in the second direction, and the fast recovery diode region 112 is too densely arranged in the second direction, which will cause the heat generated by each fast recovery diode region 112 to be unable to be dissipated in time in the second direction through the surrounding insulated gate bipolar transistor region 111, causing the local temperature to be too high.

[0052] When the ratio between the length of the active area 110 in the second direction and the length of the fast recovery diode region 112 in the second direction is not less than 20, the length of the active area 110 in the second direction is too large compared to the length of the fast recovery diode region 112 in the second direction, which will cause the number of fast recovery diode regions 112 in the second direction to be set too much, resulting in the overall heat in the second direction being too high, which is not conducive to the thermal uniformity of the semiconductor device 100.

[0053] In this way, by setting the ratio between the length of the active area 110 in the second direction and the length of the fast recovery diode region 112 in the second direction within a reasonable range, the spacing and number of the fast recovery diode regions 112 in the second direction can be made more reasonable, the heat dissipation performance of the semiconductor device 100 in the second direction can be improved, and the thermal uniformity of the semiconductor device 100 can be improved.

[0054] Combination Figure 1 and Figure 2 As shown, the length of the active region 110 in the third direction is F, and F and D satisfy the relationship: 5.2<F / D<20.

[0055] Specifically, when the ratio of the spacing distance of the length of the active area 110 in the third direction in the third direction to the length of the fast recovery diode region 112 in the third direction is not greater than 5.2, the spacing distance of the length of the active area 110 in the third direction in the third direction is too small compared to the length of the fast recovery diode region 112 in the third direction, and the fast recovery diode region 112 is arranged too closely in the third direction, which will cause the heat generated by each fast recovery diode region 112 to fail to dissipate in time in the third direction through the surrounding insulated gate bipolar transistor region 111, causing the local temperature to be too high.

[0056] When the ratio of the spacing distance of the length of the active area 110 in the third direction in the third direction to the length of the fast recovery diode region 112 in the third direction is not less than 20, the spacing distance of the length of the active area 110 in the third direction in the third direction is too large compared to the length of the fast recovery diode region 112 in the third direction, which will cause the number of fast recovery diode regions 112 in the third direction to be set too much, resulting in the overall heat in the third direction being too high, which is not conducive to the thermal uniformity of the semiconductor device 100.

[0057] In this way, by setting the ratio between the length of the active area 110 in the third direction and the length of the fast recovery diode region 112 in the third direction within a reasonable range, the spacing and number of the fast recovery diode regions 112 in the third direction can be made more reasonable, the heat dissipation performance of the semiconductor device 100 in the third direction can be improved, and the thermal uniformity of the semiconductor device 100 can be improved.

[0058] Combination Fig.14 As shown, in a top view, the fast recovery diode region 112 is rectangular, and any two of the multiple fast recovery diode regions 112 are set to be spaced apart in the second direction as the first fast recovery diode region 1128 and the second fast recovery diode region 1129, and the multiple fast recovery diode regions 112 are set to be adjacent to the first fast recovery diode region 1128 in the third direction as the third fast recovery diode region 1130, and the multiple fast recovery diode regions 112 are adjacent to the second fast recovery diode region 1129 in the third direction as the fourth fast recovery diode region 1131, and the third fast recovery diode region 1130 and the fourth fast recovery diode region 1131 are adjacently arranged in the second direction; The diagonal lengths of the first fast recovery diode region 1128 , the second fast recovery diode region 1129 , the third fast recovery diode region 1130 , and the fourth fast recovery diode region 1131 are set to G; The spacing distance between the end of the first fast recovery diode region 1128 closest to the fourth fast recovery diode region 1131 and the end of the fourth fast recovery diode region 1131 closest to the first fast recovery diode region 1128 is H, and the spacing distance between the end of the second fast recovery diode region 1129 closest to the third fast recovery diode region 1130 and the end of the third fast recovery diode region 1130 closest to the second fast recovery diode region 1129 is H; The spacing distance between the end of the first fast recovery diode region 1128 farthest from the fourth fast recovery diode region 1131 and the end of the fourth fast recovery diode region 1131 farthest from the first fast recovery diode region 1128 is I, the spacing distance between the end of the second fast recovery diode region 1129 farthest from the third fast recovery diode region 1130 and the end of the third fast recovery diode region 1130 farthest from the second fast recovery diode region 1129 is I, and I, G, and H satisfy the relationship: 2.5<I / G<4, 1.7<I / H<3.3.

[0059] Specifically, when I / G is not greater than 2.5, the spacing distance between the end of the first fast recovery diode region 1128 farthest from the fourth fast recovery diode region 1131 and the end of the fourth fast recovery diode region 1131 farthest from the first fast recovery diode region 1128 will be too small compared to the diagonal length of the first fast recovery diode region 1128 and the diagonal length of the fourth fast recovery diode region 1131, and the spacing distance between the end of the second fast recovery diode region 1129 farthest from the third fast recovery diode region 1130 and the end of the third fast recovery diode region 1130 farthest from the second fast recovery diode region 1129 will be too small compared to the diagonal length of the second fast recovery diode region 1129 and the diagonal length of the third fast recovery diode region 1130.

[0060] This will cause the diagonal sizes of the first fast recovery diode region 1128 and the fourth fast recovery diode region 1131 to be relatively too large, and will cause the diagonal sizes of the second fast recovery diode region 1129 and the third fast recovery diode region 1130 to be relatively too large, which is not conducive to the dissipation of heat from the multiple fast recovery diode regions 112 and the thermal uniformity of the semiconductor device 100.

[0061] When I / G is not less than 4, the spacing distance between the end of the first fast recovery diode region 1128 farthest from the fourth fast recovery diode region 1131 and the end of the fourth fast recovery diode region 1131 farthest from the first fast recovery diode region 1128 is too large compared to the diagonal length of the first fast recovery diode region 1128 and the diagonal length of the fourth fast recovery diode region 1131, and the spacing distance between the end of the second fast recovery diode region 1129 farthest from the third fast recovery diode region 1130 and the end of the third fast recovery diode region 1130 farthest from the second fast recovery diode region 1129 is too large compared to the diagonal length of the second fast recovery diode region 1129 and the diagonal length of the third fast recovery diode region 1130.

[0062] This will cause the first fast recovery diode region 1128 and the fourth fast recovery diode region 1131 to be arranged too closely, and will cause the second fast recovery diode region 1129 and the third fast recovery diode region 1130 to be arranged too closely, resulting in heat being unable to dissipate in time through the surrounding insulated gate bipolar transistor region 111, causing local excessive temperature.

[0063] When I / H is not greater than 1.7, the spacing distance between the end of the first fast recovery diode region 1128 farthest from the fourth fast recovery diode region 1131 and the end of the fourth fast recovery diode region 1131 farthest from the first fast recovery diode region 1128 is too small compared to the spacing distance between the end of the first fast recovery diode region 1128 closest to the fourth fast recovery diode region 1131 and the end of the fourth fast recovery diode region 1131 closest to the first fast recovery diode region 1128, and the spacing distance between the end of the second fast recovery diode region 1129 farthest from the third fast recovery diode region 1130 and the end of the third fast recovery diode region 1130 farthest from the second fast recovery diode region 1129 is too small compared to the spacing distance between the end of the second fast recovery diode region 1129 closest to the third fast recovery diode region 1130 and the end of the third fast recovery diode region 1130 closest to the second fast recovery diode region 1129.

[0064] This will cause the spacing distance between the end of the first fast recovery diode region 1128 closest to the fourth fast recovery diode region 1131 and the end of the fourth fast recovery diode region 1131 closest to the first fast recovery diode region 1128 to be too small, and will cause the spacing distance between the end of the second fast recovery diode region 1129 closest to the third fast recovery diode region 1130 and the end of the third fast recovery diode region 1130 closest to the second fast recovery diode region 1129 to be too small, which is not conducive to the dissipation of heat from the multiple fast recovery diode regions 112 and the thermal uniformity of the semiconductor device 100.

[0065] When I / G is not less than 3.3, the spacing distance between the end of the first fast recovery diode region 1128 farthest from the fourth fast recovery diode region 1131 and the end of the fourth fast recovery diode region 1131 farthest from the first fast recovery diode region 1128 is too large compared to the spacing distance between the end of the first fast recovery diode region 1128 closest to the fourth fast recovery diode region 1131 and the end of the fourth fast recovery diode region 1131 closest to the first fast recovery diode region 1128, and the spacing distance between the end of the second fast recovery diode region 1129 farthest from the third fast recovery diode region 1130 and the end of the third fast recovery diode region 1130 farthest from the second fast recovery diode region 1129 is too large compared to the spacing distance between the end of the second fast recovery diode region 1129 closest to the third fast recovery diode region 1130 and the end of the third fast recovery diode region 1130 closest to the second fast recovery diode region 1129.

[0066] This will cause the first fast recovery diode region 1128 and the fourth fast recovery diode region 1131 to be arranged too sparsely, which is not conducive to the miniaturization of the semiconductor device 100 .

[0067] In this way, by making I, G, and H satisfy the relationship: 2.5<I / G<4, 1.7<I / H<3.3, the first fast recovery diode region 1128, the second fast recovery diode region 1129, the third fast recovery diode region 1130, and the fourth fast recovery diode region 1131 can be arranged more evenly and reasonably, avoiding overly dense or sparse arrangement, thereby ensuring the compactness of the semiconductor device 100 and avoiding the semiconductor device 100 from being too large. The heat dissipation performance of the semiconductor device 100 can be improved, and the thermal uniformity of the semiconductor device 100 can be improved.

[0068] In some embodiments of the present invention, Figure 1 As shown, one of the two adjacent fast recovery diode region groups 1121 is set as the first fast recovery diode region group 1122, and the other is set as the second fast recovery diode region group 1123. The projection of the fast recovery diode region 112 in the first fast recovery diode region group 1122 in the third direction is the first projection portion, and the projection of the fast recovery diode region 112 in the second fast recovery diode region group 1123 in the third direction is the second projection portion. The first projection portion and the second projection portion overlap with each other.

[0069] Specifically, each first fast recovery diode region group 1122 includes a plurality of fast recovery diode regions 112 spaced apart in the second direction, and the projections of the plurality of fast recovery diode regions 112 in each first fast recovery diode region group 1122 in the second direction overlap with each other. Also, each second fast recovery diode region group 1123 includes a plurality of fast recovery diode regions 112 spaced apart in the second direction, and the projections of the plurality of fast recovery diode regions 112 in each second fast recovery diode region group 1123 in the second direction overlap with each other.

[0070] Furthermore, the projections of the plurality of first fast recovery diode region groups 1122 in the third direction overlap with each other, and the projections of the plurality of second fast recovery diode region groups 1123 in the third direction overlap with each other.

[0071] By making the first projection portion and the second projection portion overlap with each other, that is, by making multiple first projection portions and multiple second projection portions alternately arranged in sequence in the second direction, that is, the projections of the multiple fast recovery diode regions 112 in any one of the first fast recovery diode region groups 1122 in the third direction and the projections of the multiple fast recovery diode regions 112 in any one of the second fast recovery diode region groups 1123 in the third direction all overlap with each other in the second direction.

[0072] In this way, the multiple fast recovery diode regions 112 can be distributed in an array in the active area 110, and the multiple fast recovery diode regions 112 are aligned in the second direction and the third direction, so that the distribution of the multiple fast recovery diode regions 112 in the active area 110 can be more uniform and orderly, thereby further improving the heat dissipation performance of the semiconductor device 100.

[0073] In other embodiments of the present invention, Figure 2 As shown, one of the two adjacent fast recovery diode region groups 1121 is set as the first fast recovery diode region group 1122, and the other is set as the second fast recovery diode region group 1123. The projection of the fast recovery diode region 112 in the first fast recovery diode region group 1122 in the third direction is the first projection portion, and the projection of the fast recovery diode region 112 in the second fast recovery diode region group 1123 in the third direction is the second projection portion. The first projection portion and the second projection portion at least partially overlap with each other and are at least partially staggered with each other.

[0074] Specifically, each first fast recovery diode region group 1122 includes a plurality of fast recovery diode regions 112 spaced apart in the second direction, and the projections of the plurality of fast recovery diode regions 112 in each first fast recovery diode region group 1122 in the second direction overlap with each other. Also, each second fast recovery diode region group 1123 includes a plurality of fast recovery diode regions 112 spaced apart in the second direction, and the projections of the plurality of fast recovery diode regions 112 in each second fast recovery diode region group 1123 in the second direction overlap with each other.

[0075] Furthermore, the projections of the plurality of first fast recovery diode region groups 1122 in the third direction overlap with each other, and the projections of the plurality of second fast recovery diode region groups 1123 in the third direction overlap with each other.

[0076] By making the multiple first projection portions and the multiple second projection portions at least partially overlap with each other and at least partially staggered with each other in the second direction, that is, the projections of the multiple fast recovery diode regions 112 in any one of the first fast recovery diode region groups 1122 in the third direction and the projections of the multiple fast recovery diode regions 112 in any one of the second fast recovery diode region groups 1123 in the third direction at least partially overlap with each other and at least partially staggered with each other in the second direction.

[0077] In this way, the multiple fast recovery diode regions 112 can be distributed in an array in the active area 110, and the multiple fast recovery diode regions 112 are aligned in the second direction in the active area 110 and staggered in the third direction. In this way, the distribution of the multiple fast recovery diode regions 112 in the active area 110 can be more uniform and orderly, thereby further improving the heat dissipation performance of the semiconductor device 100.

[0078] Combination Figure 1 and Figure 2 As shown, there are at least two fast recovery diode region groups 1121 , and the at least two fast recovery diode region groups 1121 may include at least one long fast recovery diode region group 1126 and at least one short fast recovery diode region group 1127 .

[0079] Specifically, an avoidance notch 113 is provided at the end of the active region 110, and the semiconductor device 100 further includes a gate pad 130, which is provided at the avoidance notch 113. The long fast recovery diode region group 1126 is spaced apart from the gate pad 130 in the third direction, and at least part of the short fast recovery diode region group 1127 is spaced apart from the gate pad 130 in the second direction. In this way, the space in the active region 110 can be fully utilized, so that the distribution of at least two fast recovery diode region groups 1121 in the active region 110 is more uniform and reasonable, thereby further improving the heat dissipation performance of the semiconductor device 100.

[0080] Furthermore, the long fast recovery diode region group 1126 may include at least three fast recovery diode regions 112, the short fast recovery diode region group 1127 may include at least two fast recovery diode regions 112, and the number of fast recovery diode regions 112 in the long fast recovery diode region group 1126 is greater than the number of fast recovery diode regions 112 in the short fast recovery diode region group 1127. In this way, while ensuring the overall area of ​​the fast recovery diode region 112 and the heat dissipation performance of the semiconductor device 100, the short fast recovery diode region group 1121 can avoid the gate pad 130 in the second direction to avoid mutual interference between the fast recovery diode region 112 and the gate pad 130, thereby ensuring the normal operation of the semiconductor device 100.

[0081] Combination Figure 1-Figure 5As shown, the fast recovery diode region 112 may include a fast recovery diode main conductive region 1124 and a transition region 1125, wherein the transition region 1125 is circumferentially arranged outside the fast recovery diode main conductive region 1124, and the transition region 1125 is located between the fast recovery diode main conductive region 1124 and the insulated gate bipolar transistor region 111. The fast recovery diode main conductive region 1124 corresponds to the cathode layer 16, and the transition region 1125 corresponds to at least a portion of the collector layer 15. In this way, the transition region 1125 can separate the insulated gate bipolar transistor region 111 from the fast recovery diode main conductive region 1124, avoid mutual influence between the insulated gate bipolar transistor region 111 and the fast recovery diode main conductive region 1124, minimize the rebound phenomenon and ensure that the semiconductor device 100 can work stably under high current conditions, and further improve the working performance of the semiconductor device 100.

[0082] Combination Figure 6-Figure 13 As shown, the method for manufacturing the semiconductor device 100 according to the present invention can be applied to the manufacturing of the semiconductor device 100 described above.

[0083] Combination Figure 6-Figure 11 As shown, the manufacturing method of the semiconductor device 100 may mainly include the following steps: preparing a substrate 10, injecting a first conductive type dopant into the substrate 10 to form a drift layer 11; etching a groove 17 in the substrate 10, and growing an oxide insulating layer 20 on the surface of the substrate 10 and the groove 17; depositing polysilicon 30 on the surface of the oxide insulating layer 20; etching the polysilicon 30; injecting a second conductive type dopant into the substrate 10 to form a well layer 12, and injecting a first conductive type dopant on both sides of the well layer 12 corresponding to the groove 17 to form a source layer 13.

[0084] Specifically, when manufacturing the semiconductor device 100, a substrate 10 may be provided first, wherein the substrate 10 has a first main surface 101 and a second main surface 102. A first guide type dopant is implanted into a portion of the substrate 10 adjacent to the first main surface 101 to form a drift layer 11 of a first conductive type. Then, a groove 17 may be etched in the drift layer 11 so that the depth direction of the groove 17 penetrates the well layer 12 from the first main surface 101 along the first direction to reach the drift layer 11. The length direction of the groove 17 extends in the second direction of the semiconductor device 100. There are a plurality of grooves 17, and the plurality of grooves 17 are spaced apart in the third direction of the semiconductor device 100. Processes such as rounding and growth of an oxidized insulating layer 20 are completed, and an oxidized insulating layer 20 is grown on the surface of the substrate 10 and the groove 17.

[0085] Then, polysilicon 30 is deposited on the surface of the oxide insulating layer 20 and etched so that the polysilicon 30 is located in the groove 17. Then, the second conductive type dopant is injected into the substrate 10 to form a plurality of second conductive type well layers 12. Further, the first conductive type dopant is injected into both sides of the well layer 12 corresponding to the groove 17 to form a source layer 13. The source layer 13 can be used to be electrically connected to the emitter metal layer 50.

[0086] Combination Figure 6 , Fig.11 and Fig.12 As shown, after the steps of injecting a second conductive type dopant into the substrate 10 to form a well layer 12, and injecting a first conductive type dopant on both sides of the well layer 12 corresponding to the groove 17 to form the source layer 13, the manufacturing method of the semiconductor device 100 may also include: depositing a dielectric layer 40 on the surface of the oxidized insulating layer 20 and the polysilicon 30, and etching a contact hole 41 on the surface of the dielectric layer 40 and the oxidized insulating layer 20; arranging an emitter metal layer 50 on the upper surface of the dielectric layer 40 and the contact hole 41; injecting a first conductive type dopant and a second conductive type dopant in sequence on the side of the drift layer 11 facing the second main surface 102 to form a field stop layer 14 and a collector layer 15; injecting a first conductive type dopant into the collector layer 15 to form a cathode layer 16; and depositing a collector metal layer 60 on the second main surface 102.

[0087] Specifically, after the steps of implanting a second conductive type dopant into the substrate 10 to form a well layer 12, implanting a first conductive type dopant into both sides of the well layer 12 corresponding to the trench 17 to form a source layer 13, a dielectric layer 40 may be deposited on the oxidized insulating layer 20 and the polysilicon 30. The dielectric layer 40 may protect the oxidized insulating layer 20 and the polysilicon 30, thereby ensuring the first main surface 101 of the substrate 10 and reducing the risk of damage to the semiconductor device 100. Furthermore, a contact hole 41 is etched on the dielectric layer 40.

[0088] Then, an emitter metal layer 50 may be disposed on the upper surface of the dielectric layer 40 and at the contact hole 41 , so that the emitter metal layer 50 can contact the source layer 13 through the contact hole 41 , thereby ensuring the normal operation of the semiconductor device 100 .

[0089] Then, a field stop layer 14 and a collector layer 15 are formed by sequentially injecting the first conductive type dopant and the second conductive type dopant into the side of the drift layer 11 facing the second main surface 102 , and further, the first conductive type dopant is injected into the collector layer 15 to form a cathode layer 16 .

[0090] Finally, a collector metal layer 60 is deposited on the second main surface 102 .

[0091] In this way, the manufacturing of the semiconductor device 100 can be completed. In addition, the manufacturing of the semiconductor device 100 can also be compatible with existing processes, which can save process steps and time costs.

[0092] It should be noted that other structures and operations of the semiconductor device 100 according to the embodiment of the present invention are known to those skilled in the art and will not be described in detail here.

[0093] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0094] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0095] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: A substrate having a first main surface and a second main surface opposite to the first main surface, wherein the first main surface and the second main surface are spaced apart in a first direction; A drift layer of a first conductivity type, the drift layer being disposed on the substrate and located between the first main surface and the second main surface; a well layer of a second conductivity type, the well layer being arranged on a side of the drift layer facing the first main surface, a surface of the well layer on a side away from the drift layer in a first direction constituting a part of the first main surface, and a thickness of the well layer extending from the first main surface along a first direction toward the second main surface; A groove, wherein the groove penetrates the well layer from the first main surface to the drift layer in the thickness direction, the length direction of the groove extends in the second direction, the groove is multiple, and the multiple grooves are arranged at intervals in the third direction, wherein the first direction, the second direction and the third direction are perpendicular to each other; A source layer of a first conductivity type, the semiconductor device comprises an active region and a terminal region, the terminal region is circumferentially arranged outside the active region, the active region comprises a fast recovery diode region and an insulated gate bipolar transistor region, the insulated gate bipolar transistor region is circumferentially arranged around the fast recovery diode region, the source layer is arranged in the well layer corresponding to the insulated gate bipolar transistor region, a surface of the source layer on one side away from the drift layer in a first direction constitutes a part of the first main surface, the thickness of the source layer extends from the first main surface along the first direction toward the second main surface, and the thickness of the source layer is less than the thickness of the well layer; A collector layer of a second conductivity type, the collector layer being arranged on a side of the drift layer facing the second main surface and corresponding to the insulated gate bipolar transistor region, a surface of the collector layer on a side away from the drift layer in a first direction constituting a part of the second main surface, and a thickness of the collector layer extending from the second main surface along a first direction toward the first main surface; a cathode layer of a first conductivity type, the cathode layer being arranged on a side of the drift layer facing the second main surface and corresponding to the fast recovery diode region, a surface of the cathode layer on a side away from the drift layer in a first direction constituting a part of the second main surface, and a thickness of the cathode layer extending from the second main surface along a first direction toward the first main surface; There are multiple fast recovery diode regions, and the insulated gate bipolar transistor region is arranged around the outside of the multiple fast recovery diode regions. The multiple fast recovery diode regions constitute at least two fast recovery diode region groups spaced apart in the third direction. The fast recovery diode region group includes at least two fast recovery diode regions spaced apart in the second direction. The spacing distance between two adjacent fast recovery diode regions in each fast recovery diode region group in the second direction is set to A, the spacing distance between two adjacent fast recovery diode region groups in the third direction is set to B, the length of the fast recovery diode region in the second direction is set to C, and the length of the fast recovery diode region in the third direction is set to D. A, B, C and D satisfy the relationship: 0.5C<A<2C, 0.5D<B<2D.

2. The semiconductor device according to claim 1, wherein: A satisfies the relationship: 200μm<A<800μm.

3. The semiconductor device according to claim 2, wherein: B satisfies the relationship: 200μm<B<800μm.

4. The semiconductor device according to claim 3, wherein: A, B, C and D satisfy the relationship: A=B, C=D.

5. The semiconductor device according to claim 1, wherein: The length C of the fast recovery diode region in the second direction is proportional to the spacing distance A between two adjacent fast recovery diode regions in each fast recovery diode region group in the second direction; and / or The length D of the fast recovery diode region in the third direction is proportional to the spacing distance B between two adjacent fast recovery diode region groups in the third direction.

6. The semiconductor device according to claim 1, wherein: The length of the active region in the second direction is E, and E and C satisfy the relationship: 5.2<E / C<20.

7. The semiconductor device according to claim 6, wherein: The length of the active region in the third direction is F, and F and D satisfy the relationship: 5.2<F / D<20.

8. The semiconductor device according to claim 1, wherein: In a top view, the fast recovery diode region is rectangular, any two of the plurality of fast recovery diode regions that are spaced apart in the second direction are set as a first fast recovery diode region and a second fast recovery diode region, a plurality of the fast recovery diode regions that are adjacent to the first fast recovery diode region in the third direction are set as a third fast recovery diode region, a plurality of the fast recovery diode regions that are adjacent to the second fast recovery diode region in the third direction are set as a fourth fast recovery diode region, and the third fast recovery diode region and the fourth fast recovery diode region are adjacently arranged in the second direction; Setting the diagonal lengths of the first fast recovery diode region, the second fast recovery diode region, the third fast recovery diode region and the fourth fast recovery diode region to G; The spacing distance between the end of the first fast recovery diode region closest to the fourth fast recovery diode region and the end of the fourth fast recovery diode region closest to the first fast recovery diode region is H, and the spacing distance between the end of the second fast recovery diode region closest to the third fast recovery diode region and the end of the third fast recovery diode region closest to the second fast recovery diode region is H; The spacing distance between the end of the first fast recovery diode region farthest from the fourth fast recovery diode region and the end of the fourth fast recovery diode region farthest from the first fast recovery diode region is I, the spacing distance between the end of the second fast recovery diode region farthest from the third fast recovery diode region and the end of the third fast recovery diode region farthest from the second fast recovery diode region is I, and I, G, and H satisfy the relationship: 2.5<I / G<4, 1.7<I / H<3.

3.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that: One of the two adjacent fast recovery diode region groups is set as a first fast recovery diode region group, and the other is set as a second fast recovery diode region group, the projection of the fast recovery diode region in the first fast recovery diode region group in the third direction is a first projection portion, the projection of the fast recovery diode region in the second fast recovery diode region group in the third direction is a second projection portion, and the first projection portion and the second projection portion overlap with each other.

10. The semiconductor device according to any one of claims 1 to 8, characterized in that: One of the two adjacent fast recovery diode region groups is set as a first fast recovery diode region group, and the other is set as a second fast recovery diode region group, the projection of the fast recovery diode region in the first fast recovery diode region group in the third direction is a first projection portion, and the projection of the fast recovery diode region in the second fast recovery diode region group in the third direction is a second projection portion, and the first projection portion and the second projection portion at least partially overlap with each other and are at least partially staggered with each other.

11. The semiconductor device according to any one of claims 1 to 8, characterized in that: There are at least two fast recovery diode region groups, and the at least two fast recovery diode region groups include at least one long fast recovery diode region group and at least one short fast recovery diode region group; An avoidance gap is provided at the end of the active region, the semiconductor device further comprises a gate pad, the gate pad is provided at the avoidance gap, the long fast recovery diode region group is spaced apart from the gate pad in the third direction, and at least a portion of the short fast recovery diode region group is spaced apart from the gate pad in the second direction; The long fast recovery diode region group includes at least three fast recovery diode regions, the short fast recovery diode region group includes at least two fast recovery diode regions, and the number of the fast recovery diode regions in the long fast recovery diode region group is greater than the number of the fast recovery diode regions in the short fast recovery diode region group, so that the short fast recovery diode region group avoids the gate pad in the second direction.

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