Light-operated adjustable negative capacitance field effect transistor and preparation method thereof

Abstract

The invention discloses a light-operated adjustable negative capacitance field effect transistor and a preparation method thereof, and belongs to the technical field of transistors, the transistor comprises a gate structure correspondingly arranged on a semiconductor substrate, the gate structure comprises a gate oxide dielectric layer, a ferroelectric material layer, a unijunction solar cell layer and an enhancement layer which are sequentially arranged from bottom to top, the ferroelectric material layer and the unijunction solar cell layer are combined in series, and a sacrificial layer for electric isolation is introduced between the ferroelectric material layer and the unijunction solar cell layer; according to the transistor, the capacitance of the unijunction solar cell layer and the capacitance of the ferroelectric material layer are adjusted and controlled through illumination to be matched with each other, the acting effect of the grid voltage on a channel is amplified, the ratio of the grid capacitance to the channel capacitance is reduced, and the sub-threshold swing of the MOSFET transistor is reduced to 60 mv / dec or below; the thyristor is smaller in size and power consumption, the manufacturing cost is reduced, the service life of a battery is prolonged, the efficiency of electronic equipment is improved, and the energy consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the field of transistor technology, and in particular to a light-controlled adjustable negative capacitance field effect transistor and a preparation method thereof. Background Art

[0002] Negative capacitance field effect transistors are of great significance to mobile communication devices, Internet of Things devices, chips, embedded systems, medical electronic devices, artificial intelligence hardware, consumer electronics, aerospace and defense applications, and are closely related to social development and scientific and technological progress. Negative capacitance field effect transistors add a thin layer of ferroelectric material on the gate oxide dielectric layer of existing MOSFETS. Using negative capacitance field effect transistors is conducive to reducing subthreshold swing, reducing power consumption and improving working performance. Due to the stability problems such as fatigue or aging of ferroelectric materials, the long-term stability of negative capacitance field effect transistors is affected. When designing negative capacitance field effect transistors, it is necessary to connect the ferroelectric layer in series with other capacitor elements to obtain a stable total capacitance. The currently widely used negative capacitance field effect transistor uses a gate composite structure of two layers of ferroelectric material layers for capacitance matching, but this transistor structure has two serious defects in practical applications: one is that the laboratory process is poorly compatible with the semiconductor production process and has no control capability; the other is that it does not respond to light. Summary of the invention

[0003] Technical problem to be solved: In view of the deficiencies in the prior art, the present invention provides a light-controlled adjustable negative capacitance field effect transistor and a method for preparing the same. A light-transmitting window area is formed in the center of the top of the gate metal layer, and the capacitance of the single-junction solar cell layer is matched with the capacitance of the ferroelectric material layer by light regulation, so as to reduce the subthreshold swing value of the MOSFET device.

[0004] Technical solution: The light-controlled adjustable negative capacitance field effect transistor described in the present invention comprises a gate structure correspondingly arranged on a semiconductor substrate, the gate structure comprises a gate oxide dielectric layer, a ferroelectric material layer, a single junction solar cell layer and an enhancement layer arranged in sequence from bottom to top, the ferroelectric material layer and the single junction solar cell layer are combined in series, and a sacrificial layer for electrical isolation is introduced between the ferroelectric material layer and the single junction solar cell layer; the subthreshold swing value of the device is reduced by adjusting the capacitance of the single junction solar cell layer and the capacitance of the ferroelectric material layer by light illumination; The semiconductor substrate is located at both ends of the gate structure to form a source region and a drain region, respectively. The source region forms a source metal contact region and a source metal contact hole, and the drain region forms a drain metal contact region and a drain metal contact hole. A gate metal layer is applied on the top of the enhancement layer, and the gate metal layer at both ends is reserved except for the gate metal layer in the light-covered area. The first gate metal layer is photolithographically formed into a first gate metal contact hole, and the second gate metal layer is photolithographically formed into a second gate metal contact hole.

[0005] Preferably, the gate oxide dielectric layer material is HfO2, and its thickness is 10nm; The ferroelectric material layer material is Hf x Zr 1-x O2、Hf y Al 1-y O2、Hf z Si 1-z O2、Hf m G 1-m O2、Hf n Z 1-n O2; wherein 0.2≤x≤0.4 or 0.2≤y≤0.4 or 0.2≤z≤0.4 or 0.2≤m≤0.4 or 0.2≤n≤0.4; the thickness of the ferroelectric material layer is 10nm; The sacrificial layer material is polyethylene wax material, and its thickness is 2 μm; The reinforcement layer material is a transparent conductive oxide TCO, a two-dimensional perovskite layer or other organic / inorganic material, and its thickness is 12nm; The semiconductor substrate is made of InAs crystal material, wherein the thickness of the channel layer is 12 nm.

[0006] The present invention also discloses a method for preparing a light-controlled adjustable negative capacitance field effect transistor, the preparation method comprising the following steps: Step 1: preparing a semiconductor substrate and forming a gate oxide dielectric layer on the semiconductor substrate; Step 2: forming a source region and a drain region at both ends of the gate structure on the semiconductor substrate, and forming a source metal contact region and a source metal contact hole in the source region, and forming a drain metal contact region and a drain metal contact hole in the drain region; Step 3: forming a ferroelectric material layer on top of the gate oxide dielectric layer using a metal organic chemical vapor deposition method; Step 4: Cleaning the ferroelectric material layer and introducing a sacrificial layer; Step 5: Make single-junction solar cell layers and integrate them into transistor structures; Step 6: Clean the obtained sample, grow an enhancement layer on the single junction solar cell layer, and make a gate metal layer; Step 7: removing the gate metal layer from the light-covered area, leaving a first gate metal layer and a second gate metal layer at both ends thereof, photolithography the first gate metal layer to form a first gate metal contact hole, photolithography the second gate metal layer to form a second gate metal contact hole, and filling the first gate metal contact hole and the second gate metal contact hole; Step 8: Test and package the fabricated structure to form a complete light-controlled adjustable negative capacitance field effect transistor.

[0007] Preferably, the specific preparation steps of step 1 are as follows: Step 11: Use InAs material to make a semiconductor substrate, and dope Zn impurities into the semiconductor substrate by ion implantation to form a P-type substrate, where the doping concentration of the majority carrier is 1e 14 ~1e 18 cm -3 ; Step 12: Clean the P-type substrate to remove surface impurities, and deposit a HfO2 gate dielectric film on the cleaned P-type substrate; Step 13: Using a multi-frequency capacitive coupling / inductive coupling hybrid plasma discharge technology, nitriding the HfO2 gate dielectric film at room temperature to convert it into a HfNO film structure; Step 14: Annealing is performed at 800° C. in a hydrogen atmosphere to form a gate oxide dielectric layer with a thickness of 14 nm.

[0008] Preferably, the specific preparation steps of step 2 are as follows: Step 21: making source regions and drain regions on the left and right sides of the substrate; covering the semiconductor substrate at both ends of the gate structure with a layer of electron beam-sensitive photoresist HSQ, placing the semiconductor substrate covered with the photoresist in an oven and drying it at 300° C. for 4 minutes to remove the solvent in the photoresist, using an electron beam lithography machine SB254 to scan and expose the photoresist surface with a focused electron beam to make the source region and the drain region, placing the exposed source region and the drain region in a developer for development, thoroughly washing the photoresist and the developer adhering to the surface of the source region and the drain region with deionized water, and then using an etching technique to remove the area not protected by the photoresist to form source and drain grooves, and using an ion implantation method to inject a high dose of N-type dopant into the groove to form a highly doped source region and drain region; Step 22: using a metal organic chemical vapor deposition process in the source region and the drain region, introducing a certain amount of ammonia as a precursor, and reacting with oxygen in a gas reactor at a temperature of 400-600° C. through annealing to form a Cr / Au multilayer film layer with a thickness of 3 nm as a source metal contact layer and a drain metal contact layer, and using electron beam etching technology to etch the required source metal contact holes and drain metal contact holes at the corresponding positions of the source metal contact layer and the drain metal contact layer; wherein the diameter of the source metal contact hole and the drain metal contact hole region is 0.55 microns; Step 23: uniformly cover the source metal contact hole and the drain metal contact hole region with a layer of electron beam sensitive photoresist HSQ, place the source and drain covered with the photoresist in an oven and dry them at 300°C for 4 minutes to remove the solvent in the photoresist, use an electron beam lithography machine SB254 to use a focused electron beam to scan the photoresist surface to expose the source metal contact hole and the drain metal contact hole with a diameter of 0.55nm, place the exposed source metal contact hole and the drain metal contact hole region in a developer for development, wash away the photoresist and the developer adhering to the surface of the source metal contact hole and the drain metal contact hole region with deionized water, dry them at 100°C for 5 minutes, finally use a stripper to remove the remaining photoresist to leave the etched source metal contact hole and the drain metal contact hole with a diameter of 0.55nm, and use electroplating to deposit a metal layer Cr / Au in the corresponding contact holes.

[0009] Preferably, the specific preparation steps of step 3 are as follows: Step 31: treating the gate oxide dielectric layer in isopropanol at an ultrasonic power of 98W for 8 minutes to remove impurities on the top surface of the gate oxide dielectric layer, then placing the gate oxide dielectric layer in an APM solution mixed with ammonia water and hydrogen peroxide at an ultrasonic power of 108W for 8 minutes, and finally washing it in deionized water, and drying it in an oven at a temperature of 120°C for 5 minutes after washing; Step 32: forming a ferroelectric material layer on the side of the channel region away from the semiconductor substrate; the ferroelectric material layer adopts a high-K electron layer ferroelectric material Hf x Zr 1-x O2(HZO), film thickness is 15nm, ferroelectric material parameters coercive field is 0.6 MVcm -1 , the remnant polarization is 25µC cm -2 ; Through the metal organic chemical vapor deposition technology, lead zirconate titanate is selected as a precursor, and reacts with the reaction gas lead zirconate titanate in a metal organic chemical vapor deposition reactor at a temperature of 400~500℃ to form ferroelectric Hf x Zr 1-x O2(HZO) thin film, the Hf x Zr 1-xThe O2 (HZO) film was placed in a metal organic vapor phase precipitation reactor and annealed at 600°C in a hydrogen atmosphere. The Hf x Zr 1-x O2 (HZO) thin film, ultimately forming a ferroelectric material layer with a thickness of 15nm; Step 33: uniformly cover the surface of the ferroelectric thin film layer with a layer of photoresist HSQ, put the ferroelectric thin film covered with the photoresist into an oven and dry it at 300°C for 4 minutes to remove the solvent in the photoresist, use an electron beam lithography machine SB254 to use a focused electron beam to scan the surface of the photoresist to expose a ferroelectric material layer area with a thickness of 15nm, put the exposed ferroelectric material layer area into a developer for development, wash off the photoresist and developer adhering to the surface of the ferroelectric material layer with deionized water, dry it at 100°C for 5 minutes, use an electron beam lithography machine SB254 to etch it to remove the excess ferroelectric material layer, use a degumming agent to remove the remaining photoresist, and use a PVD electron beam evaporation table to evaporate Hf x Zr 1-x The O2(HZO) film leaves a uniform layer of ferroelectric material with a thickness of about 15nm.

[0010] Preferably, the specific preparation steps of step 4 are as follows: Step 41: Cleaning Hf Using Plasma Cleaning Method x Zr 1-x On the surface of the O2(HZO) ferroelectric material layer, Hf x Zr 1- x The O2 (HZO) ferroelectric material layer is placed in an oxygen environment with a pressure of 50-100 mT and a radio frequency power of 200 W for 4 minutes, wherein the oxygen flow rate is controlled by a flow controller to clean impurities on the ferroelectric material layer to ensure that the surface of the ferroelectric material layer is free of contamination, and annealing is performed to improve the interface properties; Step 42: After cleaning the surface of the ferroelectric material layer, add an appropriate amount of polyethylene wax particles to the n-hexane solvent, and stir the mixture until the wax is completely dissolved to form a transparent solution; place the ferroelectric material layer on a spin coater, drop a small amount of polyethylene wax solution, set the rotation speed to 800 rpm and the rotation time to 15 s so that the polyethylene wax solution is evenly distributed on the surface of the ferroelectric material layer, and quickly evaporate the solvent during the rotation process, leaving a uniform polyethylene wax film with a thickness of 18 nm; Step 43: Heat the ferroelectric material layer with the polyethylene wax layer in an oven at 600°C to allow the wax layer to better adhere to the ferroelectric material layer and eliminate residual solvent to form a polyethylene wax layer; place the polyethylene wax layer in isopropanol and treat it at an ultrasonic power of 108W for 8 minutes to clean impurities on the polyethylene wax layer, ensuring that the surface of the polyethylene wax layer is free of pollution, then place the polyethylene wax layer in an ethanol solution and treat it at an ultrasonic power of 108W for 8 minutes, and finally place it in deionized water for cleaning, and after cleaning, place it in an oven at a temperature of 120°C for drying for 5 minutes to form a sacrificial layer.

[0011] Preferably, the specific preparation steps of step 5 are as follows: Step 51: Invert the epitaxial growth structure, and grow the epitaxial structure of the single-junction solar cell on the N-type temporary GaAs substrate using an organic metal chemical vapor precipitation method to form an epitaxial layer on the N-type temporary GaAs substrate, and then place the solar cell epitaxial wafer and the temporary substrate GaAs wafer in isopropanol at an ultrasonic power of 108 W for 6 minutes, and then place them in an ethanol solution at an ultrasonic power of 108 W for 8 minutes, and finally place them in deionized water for cleaning, and after cleaning, place them in an oven at a temperature of 120° C. for drying for 5 minutes; Step 52: After cleaning, the bonding layer metal is evaporated by electron beam evaporation. After evaporation, the solar cell epitaxial wafer and the GaAs substrate are annealed at 400° C. for 8 minutes in a hydrogen environment; the solar cell epitaxial wafer and the GaAs substrate are bonded and stacked in two stages by metal hot pressing bonding under a pressure of 8000 kgf, the first stage is 200° C. for 6 minutes; the second stage is 280° C. for 12 minutes; Step 53: After bonding is completed, a chemical solution etching method is used to immerse the GaAs substrate of the cell epitaxial wafer in a solution with a ratio of 1:5 for 10 minutes to corrode and remove the GaAs substrate; the electrode structure of the N side and the P side is AuGe / Ti / Al / Ag / Au, wherein AuGe is the back electrode material of the solar cell, Ti is the adhesion layer in the electrode structure, Al is the front electrode material of the solar cell, Ag is the electrode material, and Au is the outer layer of the electrode. The overall thickness is 15 nm, of which the Al thickness accounts for 15%.

[0012] Preferably, the specific preparation steps of step 6 are as follows: Step 61: Place the single-junction solar cell layer in isopropanol and treat it with an ultrasonic power of 108W for 8 minutes to clean the impurities on the single-junction solar cell layer, then place the single-junction solar cell layer in an APM solution mixed with ammonia water and hydrogen peroxide and treat it with an ultrasonic power of 108W for 8 minutes, and finally place it in deionized water for cleaning, and after cleaning, place it in an oven at a temperature of 120°C for drying for 5 minutes to clean the surface of the single-junction solar cell layer; Step 62: using an atomic layer deposition method to deposit a uniform and dense transparent conductive oxide (TCO) film with a thickness of 12 nm on the single junction solar cell layer as an enhancement layer of the single junction solar cell layer, and after deposition, performing an annealing treatment at 1000° C. in a hydrogen atmosphere to reduce defects and improve the physical properties of the transparent conductive oxide film, and using a chemical-mechanical polishing technique to planarize the transparent conductive oxide; Step 63: placing the transparent conductive oxide film in isopropyl alcohol and treating it with an ultrasonic power of 108 W for 8 minutes to clean impurities on the transparent conductive oxide film, then placing the transparent conductive oxide film in an APM solution mixed with ammonia water and hydrogen peroxide and treating it with an ultrasonic power of 108 W for 8 minutes, and finally placing it in deionized water for cleaning, and after cleaning, placing it in an oven at a temperature of 120° C. for drying for 5 minutes to clean the surface of the transparent conductive oxide film; Step 64: uniformly cover the surface of the transparent conductive oxide film with a layer of photoresist HSQ, place the transparent conductive oxide film covered with the photoresist in an oven at a temperature of 500° C. and dry for 4 minutes to remove the solvent in the photoresist, use an electron beam lithography machine SB254 to directly scan the surface of the photoresist with a focused electron beam to expose the transparent conductive oxide film area, place the exposed transparent conductive oxide area in a developer for development, wash off the photoresist and the developer adhering to the surface of the transparent conductive oxide with deionized water, dry at 100° C. for 5 minutes, use an electron beam lithography machine SB254 to etch and remove excess transparent conductive oxide film area, finally use a stripper to remove the remaining photoresist, use a PVD electron beam evaporation table to evaporate the transparent conductive oxide film, and leave a transparent conductive oxide area with a final thickness of 12 nm; Step 65: using metal organic chemical vapor deposition technology, lead zirconate titanate is selected as a precursor, and reacts with a reaction gas lead zirconate titanate in a metal organic chemical vapor deposition reactor at a temperature of 500-600° C. to form a TiN film, placing the TiN film in the metal organic vapor deposition reactor, annealing at 800° C. in a hydrogen atmosphere, and etching the TiN film using an electron beam etching technology to form a gate metal layer with a thickness of 12 nm; Step 66: uniformly cover the surface of the TiN film with a layer of photoresist HSQ, place the TiN film covered with the photoresist in an oven and dry it at 500°C for 4 minutes, use an electron beam lithography machine SB254 to use a focused electron beam to directly scan the surface of the photoresist to expose the TiN gate metal layer area, place the exposed TiN gate metal layer area in a developer for development, use deionized water to wash away the photoresist and the developer adhering to the surface of the TiN gate metal layer, dry it at 100°C for 5 minutes, use an electron beam lithography machine SB254 to etch it, remove excess TiN gate metal layer area, finally use a stripper to remove the remaining photoresist, use a PVD electron beam evaporation table to evaporate the TiN film, and leave a TiN gate metal layer area with a thickness of 14 nm; place the prepared gate metal layer in an MOCVD reactor, and anneal it at 500°C in a hydrogen atmosphere.

[0013] Preferably, the specific preparation steps of step 7 are as follows: Step 71: design and manufacture a photolithography mask, which is opaque in the middle area of ​​the gate metal layer to allow electron beam exposure of the area; use an electron beam lithography machine SB254 to use a focused electron beam to coat a layer of photoresist HSQ on the gate metal layer, and only expose the middle area of ​​the gate metal layer that needs to be removed; place the unexposed gate metal layer area in a developer for development, use deionized water to wash away the photoresist and developer adhering to the surface of the gate metal layer, expose the middle area of ​​the gate metal layer, and dry it at 100°C for 5 minutes, and use an electron beam lithography machine SB254 to etch the exposed middle area of ​​the gate metal layer to remove the middle TiN gate metal layer area, and form a window on the gate metal layer to allow light to directly irradiate the single-junction solar cell layer; place the manufactured gate metal layer in an MOCVD reactor, and anneal at 400°C in a hydrogen atmosphere; Step 72: The middle part of the gate metal layer is completely removed, and the retained parts on both sides of the gate metal layer are the first gate metal layer and the second gate metal layer respectively; a layer of photoresist HSQ is further uniformly coated on the first gate metal layer and the second gate metal layer, and the TiN gate metal layer covered with the photoresist is placed in an oven and dried at 300°C for 4 minutes, and an electron beam lithography machine SB254 is used to directly scan the photoresist surface with a focused electron beam to expose the first gate metal contact area and the second gate metal contact area, and the exposed gate metal contact area is placed in a developer for development, and deionized water is used to wash away the surface of the gate metal contact area. The photoresist and developer are dried at 100°C for 5 minutes, and are etched using an electron beam lithography machine SB254 to remove excess gate contact areas. Finally, a stripper is used to remove the remaining photoresist, and a TiN gate metal layer film is evaporated using a PVD electron beam evaporation table, leaving a circular gate metal contact hole area with a diameter of 0.55nm. The prepared gate metal contact hole is placed in an MOCVD reactor, and annealed at 1000°C in a hydrogen atmosphere to form a contact hole, and filling metal Cr / Au is deposited in the contact hole. The deposited metal Cr / Au is polished to form a first gate metal contact hole and a second gate metal contact hole.

[0014] Compared with the prior art, the present invention has at least the following outstanding advantages: 1. The negative capacitance field effect transistor of the present invention inserts a single junction solar cell into a gate composite structure. The capacitance of the solar cell is affected by factors such as temperature, doping concentration, minority carrier concentration, frequency and light. In particular, light can change the diffusion capacitance in the solar cell, which is crucial for achieving capacitance matching with the ferroelectric material layer. When a forward bias is applied to both ends of the solar cell, the potential barrier is lowered, which promotes the diffusion of carriers from one side to the other, resulting in the accumulation of minority carriers near the solar cell layer, thereby increasing the diffusion capacitance; on the contrary, when a reverse bias is applied, the potential barrier is increased, the diffusion of carriers is hindered, and the diffusion capacitance is reduced. Light can be used to change the diffusion capacitance under the forward voltage of the solar cell, regulate the relationship between the capacitance and the ferroelectric material layer, and can perform good capacitance matching, increase the gate voltage, reduce the subthreshold swing value of the MOSFET device, and improve the switching speed and working stability of the transistor; the negative capacitance field effect transistor can achieve light response and is particularly suitable for the field of light.

[0015] 2. The present invention is based on the single-junction solar cell to play the best performance in the light-controlled adjustable negative capacitance field effect transistor. GaAs material is an ideal choice for manufacturing high-efficiency single-junction solar cells; GaAs material has a direct band gap, and electrons can directly jump from the valence band to the conduction band to generate photons, which can more effectively absorb light energy and convert it into electrical energy, and has an excellent advantage in photoelectric conversion efficiency. GaAs material also has a high light absorption coefficient, which can absorb more light energy in a thin layer, thereby improving the working performance of the light-controlled adjustable negative capacitance field effect transistor. In addition, GaAs material is stable at high temperatures, and the light-controlled adjustable negative capacitance field effect transistor can still maintain stable operation when operating outdoors for a long time.

[0016] 3. The substrate of the transistor of the present invention is InAs material, wherein the channel layer is also InAs material. InAs material has extremely high electron mobility, so that the device can have a faster response speed and a higher switching speed; and because InAs nanowires can show good thermal stability and extremely high electron mobility under electron beams, the use of InAs material to make MOS devices has a high cost-effectiveness.

[0017] 4. The transistor of the present invention can make good use of the negative capacitance effect of ferroelectric materials to increase the gate voltage. In theory, the subthreshold swing value can be reduced to below 60mv / dec, thereby improving the working performance of the field effect transistor. The ferroelectric material layer needs to be matched with other layers for capacitance to fully exert its potential. The single junction solar cell layer is inserted into the gate composite structure, and the ferroelectric material layer and the single junction solar cell layer are in series combination; since the ferroelectric material has a reversible polarization characteristic, when an appropriate voltage is applied, its polarization direction will be reversed, thereby changing the threshold voltage of the transistor. In addition, the fatigue of the ferroelectric material will also affect the overall performance. A sacrificial layer is introduced between the ferroelectric material layer and the single junction solar cell layer. This sacrificial layer can be melted by a heating process later, so that the ferroelectric layer and the single junction solar cell layer can be fused together, alleviating the fatigue phenomenon and degradation phenomenon of the ferroelectric negative capacitance field effect transistor, more effectively improving the working performance of the ferroelectric negative capacitance field effect transistor, and enhancing its working stability. A transparent conductive oxide is introduced as an enhancement layer on the single-junction solar cell layer, a gate metal layer is deposited on the enhancement layer, and the middle part of the gate metal layer is removed by a process so that light can penetrate the enhancement layer and irradiate the single-junction solar cell layer, thereby improving the photoelectric conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the structure of the light-controlled and adjustable ferroelectric negative capacitance field effect transistor of the present invention; Figure 2 It is a schematic diagram of the structure of a single-junction solar cell in the transistor of the present invention; Figure 3It is a schematic diagram of the structure of a conventional ferroelectric negative capacitance field effect transistor; Figure 4 It is a schematic diagram of the series connection structure of the ferroelectric material capacitor and the single junction solar cell layer capacitor of the present invention; Figure 5 A diagram showing the relationship between charge and potential of the ferroelectric material of the present invention; Figure 6 A diagram showing the relationship between voltage and charge of the ferroelectric material of the present invention; Figure 7 The single-junction solar cell layer manufacturing process flow chart of the present invention; Figure 8 A process flow chart for manufacturing the light-controlled adjustable negative capacitance field effect transistor of the present invention; Fig. 9 The diagram is a subthreshold swing diagram of the light-controlled adjustable negative capacitance field effect transistor of the present invention and a traditional negative capacitance field effect transistor.

[0019] Figure numerals: 100, transistor; 1, semiconductor substrate; 2, source region; 3, drain region; 4, source metal contact region; 5, drain metal contact region; 6, source metal contact hole; 7, drain metal contact hole; 8, gate oxide dielectric layer; 9, ferroelectric material layer; 10, sacrificial layer; 11, single junction solar cell layer; 12, first gate metal layer; 13, second gate metal layer; 14, first gate metal contact region; 15, second gate metal contact region; 16, first gate metal contact hole; 17, second gate metal contact hole; 18, enhancement layer. DETAILED DESCRIPTION

[0020] To make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the following will be combined with the attached Figures 1 to 9 The technical solutions of the embodiments of the present invention are described clearly and completely. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0021] Example 1: Figures 1 to 4As shown, a light-controlled adjustable negative capacitance field effect transistor of the present invention, the transistor 100 includes a gate structure correspondingly arranged on a semiconductor substrate 1, the gate structure includes a gate oxide dielectric layer 8, a ferroelectric material layer 9, a single junction solar cell layer 11 and an enhancement layer 18 arranged in sequence from bottom to top, the ferroelectric material layer 9 and the single junction solar cell layer 11 are combined in series, and a sacrificial layer 10 for electrical isolation is introduced between the ferroelectric material layer 9 and the single junction solar cell layer 11; the capacitance of the single junction solar cell layer 11 and the capacitance of the ferroelectric material layer 9 are matched by light regulation to reduce the subthreshold swing value of the device. The semiconductor substrate 1 is located at both ends of the gate structure to form a source region 2 and a drain region 3 respectively, the source region 2 forms a source metal contact region 4 and a source metal contact hole 6, and the drain region 3 forms a drain metal contact region 5 and a drain metal contact hole 7. A gate metal layer is applied on the top of the enhancement layer 18. The gate metal layer removes the gate metal layer in the light-covered area to reserve the first gate metal layer 12 and the second gate metal layer 13 at both ends. The first gate metal layer 12 is photolithographically formed into a first gate metal contact hole 16, and the second gate metal layer 13 is photolithographically formed into a second gate metal contact hole 17.

[0022] The gate oxide dielectric layer 8 is made of HfO2 and has a thickness of 10 nm. The ferroelectric material layer 9 is made of Hf x Zr 1-x O2, 0.2≤x≤0.4; the ferroelectric material layer 9 can also be made of Hf y Al 1-y O2、Hf z Si 1-z O2、Hf m G 1-m O2、Hf n Z 1-n O2 and other similar substitutes, where 0.2≤y≤0.4 or 0.2≤z≤0.4 or 0.2≤m≤0.4 or 0.2≤n≤0.4; the thickness of the ferroelectric material layer 9 is 10nm. The sacrificial layer 10 material is polyethylene wax material, and metal material or insulating material can also be used as the sacrificial layer 10, and its thickness is 2μm. The enhancement layer 18 material is transparent conductive oxide TCO, and can also be replaced by a two-dimensional perovskite layer or other organic / inorganic materials, and its thickness is 12nm. The semiconductor substrate 1 is InAs crystal material, which has a high electron mobility, and its lighter effective mass makes the electrons move faster in the crystal, thereby improving the switching speed and overall performance of the transistor; the channel layer thickness is 12nm.

[0023] In the overall structure of the transistor of the present invention, the semiconductor substrate 1 is the basic material in the transistor and supports the entire transistor structure; the gate oxide dielectric layer 8 can reduce interface defects and control the carrier concentration in the channel; the capacitance of the ferroelectric material layer 9 is connected in series with the capacitance of the gate oxide dielectric layer 8 to increase the gate voltage; the capacitance of the single-junction solar cell layer 11 is matched with the capacitance of the ferroelectric material layer 9, and the capacitance relationship between the ferroelectric material layer 9 and the ferroelectric material layer 9 is regulated by light, so that the subthreshold threshold can be reduced to below 60mv / dec, thereby reducing power consumption and increasing the switching speed; the first gate metal layer 12 and the second gate metal layer 13 serve as the control center of the transistor to adjust the electron flow inside the entire transistor, thereby affecting the working state of the transistor.

[0024] The design principle or method of the transistor of the present invention: like Figures 4 to 6 As shown, for ferroelectric materials, a high voltage must be applied externally to rebuild the internal electric potential field and rearrange the internal charge. The relationship between charge and voltage is that the charge increases as the voltage increases. The light-controlled adjustable negative capacitance field effect transistor mentioned in the present invention has a charge that decreases as the voltage increases. According to the electric quantity formula: Q=UC, the charge can be increased by increasing the capacitance; by connecting the ferroelectric material capacitor in series with the high-k oxide capacitor, according to the total gate series capacitance C tot Calculation formula: ; In the formula, C ox is the oxide capacitance, C ox is a positive capacitor; C fe is the ferroelectric material capacitance, C fe It is a negative capacitor. The total capacitance increases after two capacitors are connected in series. When the voltage remains unchanged, the overall charge increases by increasing the capacitance. The increase in the overall charge leads to a decrease in the threshold voltage, making the leakage current in the subthreshold region more sensitive to changes in the gate voltage, thereby making the subthreshold slope steeper. The subthreshold threshold refers to the relationship between the drain current and the gate voltage, which refers to the minimum change range required to make the drain current change by ten orders of magnitude of the gate voltage.

[0025] By using the characteristics of the diffusion capacitance of a single-junction solar cell when the forward voltage is changed by light, the relationship between the diffusion capacitance and the ferroelectric material capacitance is regulated to make the capacitances match each other. The change in the minority carrier charge stored in the single-junction solar cell under forward bias as the voltage changes is the diffusion capacitance. Under forward bias, the diffusion capacitance value of the single-junction solar cell layer 11 is three to four orders of magnitude greater than the junction capacitance of the single-junction solar cell layer 11 under reverse bias. The diffusion capacitance of the single-junction solar cell is calculated mathematically. For example, the order of magnitude of the diffusion capacitance obtained by dividing it by the device area is roughly the same as the order of magnitude of the ferroelectric capacitance. Therefore, the ferroelectric material layer 9 and the single-junction solar cell layer 11 can be well matched in capacitance. The reason why solar cells choose single junctions instead of multi-junctions is that the capacitance of single-junction solar cells is theoretically larger than that of multi-junction solar cells. Multi-junction solar cells contain multiple nodes connected in series, each of which has its own capacitance. When the capacitances are connected in series, the total capacitance is calculated according to the formula: ; When capacitors are connected in series, their total capacitance will decrease. Therefore, a single-junction solar cell layer 11 is selected instead of a multi-junction solar cell layer.

[0026] A sacrificial layer 10 is introduced between the ferroelectric material layer 9 and the single junction solar cell layer 11. Since the ferroelectric material has a reversible polarization characteristic, when a voltage is applied, its polarization direction may be reversed, thereby changing the threshold voltage of the transistor. In addition, the fatigue of the ferroelectric material will also affect the overall performance. In order to optimize the performance of the ferroelectric negative capacitance field effect transistor, an easily removable polyethylene wax layer is introduced between the ferroelectric material layer 9 and the single junction solar cell layer 11 as a sacrificial layer 10. Subsequently, the wax layer can be melted by direct heating to separate it from the ferroelectric material layer 9, thereby realizing the series combination of the ferroelectric material layer 9 and the single junction solar cell layer 11. The introduction of the sacrificial layer 10 between the ferroelectric material layer 9 and the single junction solar cell layer 11 can alleviate the fatigue and degradation of the ferroelectric negative capacitance field effect transistor, thereby improving the working performance of the entire device.

[0027] Example 2: Figures 7-9 As shown, the present invention also discloses a method for preparing a light-controlled adjustable negative capacitance field effect transistor, the preparation method comprising the following steps: 1. Prepare a semiconductor substrate 1 and generate a gate oxide dielectric layer 8 on the semiconductor substrate 1. The specific preparation steps are as follows: (1) A semiconductor substrate 1 is made of InAs material, and Zn impurities are doped into the semiconductor substrate 1 by ion implantation to form a P-type substrate, in which the doping concentration of the majority carrier is 1e 14 ~1e 18 cm -3The substrate of the transistor is InAs material, and the channel layer is also made of InAs material. InAs material has extremely high electron mobility, which enables the device to have a faster response speed and higher switching speed; and because InAs nanowires can show good thermal stability under electron beams and have extremely high electron mobility, the use of InAs material to make MOS devices has a high cost-effectiveness.

[0028] (2) The P-type substrate is cleaned to remove surface impurities, and a HfO2 gate dielectric film is deposited on the cleaned P-type substrate.

[0029] (3) The HfO2 gate dielectric film is nitrided at room temperature using a multi-frequency capacitively coupled / inductively coupled hybrid plasma discharge technique to convert it into a HfNO film structure.

[0030] (4) Annealing treatment is performed at 800° C. in a hydrogen atmosphere to form a gate oxide dielectric layer 8 with a thickness of 14 nm.

[0031] 2. Forming a source region 2 and a drain region 3 at both ends of the gate structure on the semiconductor substrate 1, and forming a source metal contact region 4 and a source metal contact hole 6 in the source region 2, and forming a drain metal contact region 5 and a drain metal contact hole 7 in the drain region 3. The specific preparation steps are as follows: (1) A source region 2 and a drain region 3 are formed on the left and right sides of the substrate; a layer of electron beam-sensitive photoresist HSQ is coated on the semiconductor substrate 1 at both ends of the gate structure, the semiconductor substrate 1 covered with the photoresist is placed in an oven and dried at 300° C. for 4 minutes to remove the solvent in the photoresist, an electron beam lithography machine SB254 is used to scan and expose the photoresist surface with a focused electron beam to form the source region 2 and the drain region 3, the exposed source region 2 and the drain region 3 are placed in a developer for development, the photoresist and the developer adhering to the surface of the source region 2 and the drain region 3 are thoroughly washed off with deionized water, and then an etching technique is used to remove the area not protected by the photoresist to form source and drain grooves, and a high dose of N-type dopant is injected into the groove by an ion implantation method to form a highly doped source region 2 and drain region 3.

[0032] (2) A certain amount of ammonia is introduced as a precursor in the source region 2 and the drain region 3 by using a metal organic chemical vapor deposition process, and reacts with oxygen in a gas reactor at a temperature of 400-600°C through annealing to form a Cr / Au multilayer film with a thickness of 3 nm as a source metal contact layer and a drain metal contact layer, and the required source metal contact holes and drain metal contact holes are etched at the corresponding positions of the source metal contact layer and the drain metal contact layer by using electron beam etching technology; wherein the diameter of the source metal contact hole and the drain metal contact hole area is 0.55 microns.

[0033] (3) A layer of electron beam sensitive photoresist HSQ is uniformly covered on the source metal contact hole and the drain metal contact hole area, the source and drain covered with the photoresist are placed in an oven and dried at 300°C for 4 minutes to remove the solvent in the photoresist, and an electron beam lithography machine SB254 is used to scan the photoresist surface with a focused electron beam to expose the source metal contact hole and the drain metal contact hole with a diameter of 0.55 nm, and the exposed source metal contact hole and the drain metal contact hole area are placed in a developer for development, and the photoresist and the developer adhering to the surface of the source metal contact hole and the drain metal contact hole area are washed with deionized water, and the area is dried at 100°C for 5 minutes. Finally, the remaining photoresist is removed by a stripper to leave the source metal contact hole and the drain metal contact hole with a diameter of 0.55 nm after etching, and a metal layer Cr / Au is deposited in the corresponding contact holes by electroplating.

[0034] 3. Form a ferroelectric material layer 9 on top of the gate oxide dielectric layer 8 using a metal organic chemical vapor deposition method. The specific preparation steps are as follows: (1) The gate oxide dielectric layer 8 is treated in isopropanol at an ultrasonic power of 98 W for 8 minutes to remove impurities on the top surface of the gate oxide dielectric layer 8, and then the gate oxide dielectric layer 8 is placed in an APM solution mixed with ammonia water and hydrogen peroxide and treated at an ultrasonic power of 108 W for 8 minutes, and finally placed in deionized water for cleaning, and after cleaning, placed in an oven at a temperature of 120° C. for drying for 5 minutes.

[0035] (2) forming a ferroelectric material layer 9 on the side of the channel region away from the semiconductor substrate 1; the ferroelectric material layer 9 is made of a high-K electron layer ferroelectric material Hf x Zr 1-x O2(HZO), film thickness is 15nm, ferroelectric material parameters coercive field is 0.6 MVcm -1 , the remnant polarization is 25µC cm -2 ; Through the metal organic chemical vapor deposition technology, lead zirconate titanate is selected as a precursor, and reacts with the reaction gas lead zirconate titanate in a metal organic chemical vapor deposition reactor at a temperature of 400~500℃ to form ferroelectric Hf x Zr 1-x O2(HZO) thin film, the formed Hf x Zr 1-x The O2 (HZO) film was placed in a metal organic vapor phase precipitation reactor and annealed at 600°C in a hydrogen atmosphere. The Hf x Zr 1-x O2 (HZO) thin film, and finally form a ferroelectric material layer 9 with a thickness of 15nm.

[0036] (3) A layer of photoresist HSQ is uniformly coated on the surface of the ferroelectric thin film layer, and the ferroelectric thin film covered with the photoresist is placed in an oven and dried at 300°C for 4 minutes to remove the solvent in the photoresist. An electron beam lithography machine SB254 is used to scan and expose a ferroelectric material layer 9 region with a thickness of 15 nm using a focused electron beam on the surface of the photoresist. The exposed ferroelectric material layer 9 region is placed in a developer for development, and the photoresist and developer adhering to the surface of the ferroelectric material layer 9 are washed off with deionized water, and the layer is dried at 100°C for 5 minutes. The excess ferroelectric material layer 9 is etched by an electron beam lithography machine SB254, and the remaining photoresist is removed by a degumming agent. Hf is evaporated by a PVD electron beam evaporation table. x Zr 1-x The O2 (HZO) film leaves a uniform ferroelectric material layer 9 with a thickness of about 15 nm. The transistor can make good use of the negative capacitance effect of the ferroelectric material to increase the gate voltage, and theoretically can reduce the subthreshold swing value to below 60mv / dec, thereby improving the working performance of the field effect transistor.

[0037] 4. Clean the ferroelectric material layer 9 and introduce the sacrificial layer 10. The specific preparation steps are as follows: (1) Cleaning Hf using plasma cleaning method x Zr 1-x On the surface of the O2 (HZO) ferroelectric material layer 9, Hf x Zr 1-x The O2 (HZO) ferroelectric material layer 9 is placed in an oxygen environment with a pressure of 50-100 mT and a radio frequency power of 200 W for 4 minutes, wherein the oxygen flow rate is controlled by a flow controller to clean impurities on the ferroelectric material layer 9, ensure that the surface of the ferroelectric material layer 9 is free of contamination, and annealing is performed to improve the interface properties.

[0038] (2) After cleaning the surface of the ferroelectric material layer 9, add an appropriate amount of polyethylene wax particles into the n-hexane solvent, and stir the mixture until the wax is completely dissolved to form a transparent solution; place the ferroelectric material layer 9 on a spin coater, add a small amount of polyethylene wax solution, set the rotation speed to 800 rpm and the rotation time to 15 s so that the polyethylene wax solution is evenly distributed on the surface of the ferroelectric material layer 9, and quickly evaporate the solvent during the rotation process, leaving a uniform polyethylene wax film with a thickness of 18 nm.

[0039] (3) The ferroelectric material layer 9 with the polyethylene wax layer is heated in an oven at 600°C so that the wax layer adheres better to the ferroelectric material layer 9 and the residual solvent is eliminated to form a polyethylene wax layer; the polyethylene wax layer is placed in isopropanol and treated at an ultrasonic power of 108 W for 8 minutes to clean the impurities on the polyethylene wax layer and ensure that the surface of the polyethylene wax layer is free of contamination; the polyethylene wax layer is then placed in an ethanol solution and treated at an ultrasonic power of 108 W for 8 minutes, and finally placed in deionized water for cleaning, and after cleaning, placed in an oven at a temperature of 120°C for drying for 5 minutes to form a sacrificial layer 10.

[0040] A sacrificial layer 10 is introduced between the ferroelectric material layer 9 and the single junction solar cell layer 11. Since the ferroelectric material has a reversible polarization characteristic, when a voltage is applied, its polarization direction may be reversed, thereby changing the threshold voltage of the transistor. In addition, the fatigue of the ferroelectric material will also affect the overall performance. In order to optimize the performance of the ferroelectric negative capacitance field effect transistor, an easily removable polyethylene wax layer is introduced between the ferroelectric material layer 9 and the single junction solar cell layer 11 as a sacrificial layer 10. Subsequently, the wax layer can be melted by direct heating to separate it from the ferroelectric material layer 9, thereby realizing the series combination of the ferroelectric material layer 9 and the single junction solar cell layer 11. The introduction of the sacrificial layer 10 between the ferroelectric material layer 9 and the single junction solar cell layer 11 can alleviate the fatigue and degradation of the ferroelectric negative capacitance field effect transistor, thereby improving the working performance of the entire device.

[0041] 5. Fabricate a single-junction solar cell layer 11 and integrate it into a transistor structure. The specific preparation steps are as follows: (1) Inverted growth epitaxial structure, on the N-type temporary GaAs substrate, the single-junction solar cell epitaxial structure is grown using the organic metal chemical vapor deposition method to form an epitaxial layer on the N-type temporary GaAs substrate, and then the solar cell epitaxial wafer and the temporary substrate GaAs wafer are placed in isopropanol at an ultrasonic power of 108W for 6 minutes, and then placed in an ethanol solution at an ultrasonic power of 108W for 8 minutes, and finally placed in deionized water for cleaning, and then placed in an oven at a temperature of 120°C for drying for 5 minutes. Based on the best performance of single-junction solar cells in light-controlled adjustable negative capacitance field effect transistors, GaAs materials are ideal for manufacturing high-efficiency single-junction solar cells; GaAs materials have a direct band gap, and electrons can directly jump from the valence band to the conduction band to generate photons, which can more effectively absorb light energy and convert it into electrical energy, and have excellent advantages in photoelectric conversion efficiency. GaAs materials also have a high light absorption coefficient, which can absorb more light energy in a thin layer, thereby improving the working performance of light-controlled adjustable negative capacitance field effect transistors. In addition, GaAs materials are stable at high temperatures, and the light-controlled adjustable negative capacitance field-effect transistor can still maintain stable operation when operating outdoors for a long time.

[0042] (2) After cleaning, electron beam evaporation is used to evaporate the bonding layer metal. After evaporation, the solar cell epitaxial wafer and GaAs substrate are annealed at 400°C for 8 minutes in a hydrogen environment; the solar cell epitaxial wafer and GaAs substrate are bonded and stacked by metal hot pressing bonding under a pressure of 8000 kgf in two stages, the first stage is maintained at 200°C for 6 minutes; the second stage is maintained at 280°C for 12 minutes.

[0043] (3) After bonding is completed, the GaAs substrate of the cell epitaxial wafer is corroded and removed by soaking in a solution with a ratio of 1:5 for 10 minutes using a chemical solution corrosion method; the electrode structure of the N-side and P-side is AuGe / Ti / Al / Ag / Au, where AuGe is the back electrode material of the solar cell, Ti is the adhesion layer in the electrode structure, Al is the front electrode material of the solar cell, Ag is the electrode material, and Au is the outer layer of the electrode. The overall thickness is 15 nm, of which the Al thickness accounts for 15%.

[0044] The ferroelectric material layer 9 needs to be matched with other layers for capacitance in order to fully exert its potential. The single junction solar cell layer 11 is inserted into the gate composite structure, and the ferroelectric material layer 9 and the single junction solar cell layer 11 are combined in series. Since ferroelectric materials have reversible polarization characteristics, when an appropriate voltage is applied, their polarization direction will be reversed, thereby changing the threshold voltage of the transistor. In addition, the fatigue of ferroelectric materials will also affect the overall performance.

[0045] 6. Clean the obtained sample, grow an enhancement layer 18 on the single junction solar cell layer 11, and make a gate metal layer. The specific preparation steps are as follows: (1) The single-junction solar cell layer 11 is placed in isopropyl alcohol and treated with an ultrasonic power of 108 W for 8 minutes to clean the impurities on the single-junction solar cell layer 11. The single-junction solar cell layer 11 is then placed in an APM solution mixed with ammonia water and hydrogen peroxide and treated with an ultrasonic power of 108 W for 8 minutes. Finally, it is placed in deionized water for cleaning. After cleaning, it is placed in an oven at a temperature of 120°C for drying for 5 minutes to clean the surface of the single-junction solar cell layer 11.

[0046] (2) A uniform and dense transparent conductive oxide (TCO) film with a thickness of 12 nm is deposited on the single-junction solar cell layer 11 by atomic layer deposition as the enhancement layer 18 of the single-junction solar cell layer 11. After deposition, the film is annealed at 1000°C in a hydrogen atmosphere to reduce defects and improve the physical properties of the transparent conductive oxide film. The transparent conductive oxide is planarized by chemical-mechanical polishing technology.

[0047] (3) The transparent conductive oxide film is placed in isopropyl alcohol and treated with an ultrasonic power of 108 W for 8 minutes to clean impurities on the transparent conductive oxide film. The transparent conductive oxide film is then placed in an APM solution mixed with ammonia and hydrogen peroxide and treated with an ultrasonic power of 108 W for 8 minutes. Finally, the transparent conductive oxide film is placed in deionized water for cleaning. After cleaning, the film is placed in an oven at a temperature of 120° C. for drying for 5 minutes to clean the surface of the transparent conductive oxide film.

[0048] (4) A layer of photoresist HSQ is uniformly coated on the surface of the transparent conductive oxide film, and the transparent conductive oxide film covered with the photoresist is placed in an oven at a temperature of 500° C. and dried for 4 minutes to remove the solvent in the photoresist. An electron beam lithography machine SB254 is used to directly scan the photoresist surface with a focused electron beam to expose the transparent conductive oxide film area, and the exposed transparent conductive oxide area is placed in a developer for development, and the photoresist and developer adhering to the surface of the transparent conductive oxide are washed away with deionized water, and the film is dried at 100° C. for 5 minutes. The electron beam lithography machine SB254 is used to etch and remove the excess transparent conductive oxide film area, and finally a stripper is used to remove the remaining photoresist, and a transparent conductive oxide film is evaporated using a PVD electron beam evaporation table, leaving a transparent conductive oxide area with a final thickness of 12 nm.

[0049] (5) Lead zirconate titanate is selected as a precursor through metal organic chemical vapor deposition technology, and reacts with the reaction gas lead zirconate titanate in a metal organic chemical vapor deposition reactor at a temperature of 500~600°C to form a TiN film. The TiN film is placed in the metal organic vapor deposition reactor and annealed at 800°C in a hydrogen atmosphere. The TiN film is etched using electron beam etching technology to form a gate metal layer with a thickness of 12 nm.

[0050] (6) A layer of photoresist HSQ is uniformly coated on the surface of the TiN film, and the TiN film coated with the photoresist is placed in an oven and dried at 500°C for 4 minutes. An electron beam lithography machine SB254 is used to directly scan the photoresist surface with a focused electron beam to expose the TiN gate metal layer area, and the exposed TiN gate metal layer area is placed in a developer for development. The photoresist and developer adhering to the surface of the TiN gate metal layer are washed away with deionized water, and the film is dried at 100°C for 5 minutes. The film is etched by an electron beam lithography machine SB254 to remove excess TiN gate metal layer area, and finally a stripper is used to remove the remaining photoresist, and a TiN film is evaporated by a PVD electron beam evaporation table to leave a TiN gate metal layer area with a thickness of 14 nm; the prepared gate metal layer is placed in an MOCVD reactor and annealed at 500°C in a hydrogen atmosphere.

[0051] A transparent conductive oxide is introduced as an enhancement layer 18 on the single-junction solar cell layer 11, a gate metal layer is deposited on the enhancement layer 18, and the middle part of the gate metal layer is removed by a process so that light can penetrate the enhancement layer 18 and irradiate the single-junction solar cell layer 11, thereby improving the photoelectric conversion efficiency.

[0052] 7. Remove the gate metal layer from the light-covered area, and reserve the first gate metal layer 12 and the second gate metal layer 13 at both ends. Photolithography forms the first gate metal contact hole 16 in the first gate metal layer 12, and photolithography forms the second gate metal contact hole 17 in the second gate metal layer 13, and fill the first gate metal contact hole 16 and the second gate metal contact hole 17. The specific preparation steps are as follows: (1) Design and manufacture a photolithography mask, which is opaque in the middle area of ​​the gate metal layer to allow an electron beam to expose the area; use an electron beam lithography machine SB254 to use a focused electron beam to coat a layer of photoresist HSQ on the gate metal layer, and only expose the middle area of ​​the gate metal layer that needs to be removed; place the unexposed gate metal layer area in a developer for development, use deionized water to wash away the photoresist and developer adhering to the surface of the gate metal layer, expose the middle area of ​​the gate metal layer, and dry it at 100°C for 5 minutes. Use an electron beam lithography machine SB254 to etch the exposed middle area of ​​the gate metal layer to remove the middle TiN gate metal layer area, and form a window on the gate metal layer to allow light to directly irradiate the single-junction solar cell layer 11; place the manufactured gate metal layer in an MOCVD reactor and anneal it at 400°C in a hydrogen atmosphere.

[0053] (2) The middle part of the gate metal layer is completely removed, and the retained parts on both sides of the gate metal layer are the first gate metal layer 12 and the second gate metal layer 13; a layer of photoresist HSQ is evenly coated on the first gate metal layer 12 and the second gate metal layer 13, and the TiN gate metal layer covered with the photoresist is placed in an oven and dried at 300° C. for 4 minutes. An electron beam lithography machine SB254 is used to scan and expose the first gate metal contact area 14 and the second gate metal contact area 15 directly on the surface of the photoresist with a focused electron beam, and the exposed gate metal contact area is placed in a developer for development, and deionized water is used to wash away the adhesive on the gate metal contact area. The photoresist and developer on the surface of the contact area are dried at 100°C for 5 minutes, and are etched using an electron beam lithography machine SB254 to remove excess gate contact areas. Finally, a stripper is used to remove the remaining photoresist, and a TiN gate metal layer film is evaporated using a PVD electron beam evaporation table, leaving a circular gate metal contact hole area with a diameter of 0.55nm. The prepared gate metal contact hole is placed in an MOCVD reactor, and annealed at 1000°C in a hydrogen atmosphere to form a contact hole, and filling metal Cr / Au is deposited in the contact hole, and the deposited metal Cr / Au is polished to form a first gate metal contact hole and a second gate metal contact hole.

[0054] 8. The above-made structure is tested and packaged to form a complete light-controlled adjustable negative capacitance field effect transistor.

[0055] The above are preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A light-controlled adjustable negative capacitance field effect transistor, characterized in that: The transistor (100) comprises a gate structure correspondingly arranged on a semiconductor substrate (1), the gate structure comprising a gate oxide dielectric layer (8), a ferroelectric material layer (9), a single junction solar cell layer (11) and an enhancement layer (18) arranged in sequence from bottom to top, the ferroelectric material layer (9) and the single junction solar cell layer (11) being connected in series, and a sacrificial layer (10) for electrical isolation is introduced between the ferroelectric material layer (9) and the single junction solar cell layer (11); the capacitance of the single junction solar cell layer (11) and the capacitance of the ferroelectric material layer (9) are matched by light regulation to reduce the subthreshold swing value of the device; The semiconductor substrate (1) is located at both ends of the gate structure to form a source region (2) and a drain region (3), respectively; the source region (2) forms a source metal contact region (4) and a source metal contact hole (6); and the drain region (3) forms a drain metal contact region (5) and a drain metal contact hole (7); A gate metal layer is applied on the top of the enhancement layer (18), and the gate metal layer is removed from the light-covered area to reserve a first gate metal layer (12) and a second gate metal layer (13) at both ends thereof; the first gate metal layer (12) is photolithographically formed into a first gate metal contact hole (16), and the second gate metal layer (13) is photolithographically formed into a second gate metal contact hole (17).

2. The light-controlled adjustable negative capacitance field effect transistor according to claim 1, characterized in that: The gate oxide dielectric layer (8) is made of HfO2 and has a thickness of 10 nm; The ferroelectric material layer (9) is made of Hf x Zr 1-x O2、Hf y Al 1-y O2、Hf z Si 1-z O2、Hf m G 1-m O2、Hf n Z 1-n O2; wherein 0.2≤x≤0.4 or 0.2≤y≤0.4 or 0.2≤z≤0.4 or 0.2≤m≤0.4 or 0.2≤n≤0.4; the thickness of the ferroelectric material layer (9) is 10 nm; The sacrificial layer (10) is made of polyethylene wax material and has a thickness of 2 μm; The reinforcement layer (18) is made of transparent conductive oxide, two-dimensional perovskite layer or other organic / inorganic materials, and has a thickness of 12 nm; The semiconductor substrate (1) is made of InAs crystal material, wherein the channel layer thickness is 12 nm.

3. A method for preparing a light-controlled adjustable negative capacitance field effect transistor as claimed in claim 2, characterized in that: The preparation method comprises the following steps: Step 1: preparing a semiconductor substrate (1) and forming a gate oxide dielectric layer (8) on the semiconductor substrate (1); Step 2: forming a source region (2) and a drain region (3) at both ends of the gate structure on the semiconductor substrate (1), forming a source metal contact region (4) and a source metal contact hole (6) in the source region (2), and forming a drain metal contact region (5) and a drain metal contact hole (7) in the drain region (3); Step 3: forming a ferroelectric material layer (9) on top of the gate oxide dielectric layer (8) using a metal organic chemical vapor deposition method; Step 4: cleaning the ferroelectric material layer (9) and introducing a sacrificial layer (10); Step 5: fabricating a single junction solar cell layer (11) and integrating it into a transistor structure; Step 6: Cleaning the obtained sample, growing an enhancement layer (18) on the single-junction solar cell layer (11), and making a gate metal layer; Step 7: removing the gate metal layer from the light-covered area to reserve a first gate metal layer (12) and a second gate metal layer (13) at both ends of the gate metal layer, photolithography the first gate metal layer (12) to form a first gate metal contact hole (16), photolithography the second gate metal layer (13) to form a second gate metal contact hole (17), and filling the first gate metal contact hole (16) and the second gate metal contact hole (17); Step 8: Test and package the fabricated structure to form a complete light-controlled adjustable negative capacitance field effect transistor.

4. The method for preparing the light-controlled adjustable negative capacitance field effect transistor according to claim 3, characterized in that: The specific preparation steps of step 1 are as follows: Step 11: A semiconductor substrate (1) is prepared using an InAs material, and impurity Zn is doped into the semiconductor substrate (1) by ion implantation to form a P-type substrate, wherein the doping concentration of the majority carrier is 1e 14 ~1e 18 cm -3 ; Step 12: Clean the P-type substrate to remove surface impurities, and deposit a HfO2 gate dielectric film on the cleaned P-type substrate; Step 13: Using a multi-frequency capacitive coupling / inductive coupling hybrid plasma discharge technology, nitriding the HfO2 gate dielectric film at room temperature to convert it into a HfNO film structure; Step 14: Annealing is performed at 800° C. in a hydrogen atmosphere to form a gate oxide dielectric layer (8) with a thickness of 14 nm.

5. The method for preparing the light-controlled adjustable negative capacitance field effect transistor according to claim 3, characterized in that: The specific preparation steps of step 2 are as follows: Step 21: forming a source region (2) and a drain region (3) on the left and right sides of the substrate; covering the semiconductor substrate (1) at both ends of the gate structure with a layer of electron beam-sensitive photoresist HSQ, placing the semiconductor substrate (1) covered with the photoresist in an oven at 300° C. for 4 minutes to remove the solvent in the photoresist, using an electron beam lithography machine SB254 to perform scanning exposure on the surface of the photoresist using a focused electron beam to form the source region (2) and the drain region (3), placing the exposed source region (2) and the drain region (3) in a developer for development, thoroughly washing away the photoresist and the developer adhering to the surface of the source region (2) and the drain region (3) with deionized water, and then using an etching technique to remove the area not protected by the photoresist to form source and drain grooves, and using an ion implantation method to implant a high dose of N-type dopant in the groove to form a highly doped source region (2) and drain region (3); Step 22: using a metal organic chemical vapor deposition process to introduce a certain amount of ammonia as a precursor in the source region (2) and the drain region (3), and reacting with oxygen in a gas reactor at a temperature of 400-600° C. through an annealing process to form a Cr / Au multilayer film layer with a thickness of 3 nm as a source metal contact layer and a drain metal contact layer, and using electron beam etching technology to etch the required source metal contact holes and drain metal contact holes at the corresponding positions of the source metal contact layer and the drain metal contact layer; wherein the diameter of the source metal contact hole and the drain metal contact hole region is 0.55 microns; Step 23: uniformly cover the source metal contact hole and the drain metal contact hole region with a layer of electron beam sensitive photoresist HSQ, place the source and drain covered with the photoresist in an oven and dry them at 300°C for 4 minutes to remove the solvent in the photoresist, use an electron beam lithography machine SB254 to use a focused electron beam to scan the photoresist surface to expose the source metal contact hole and the drain metal contact hole with a diameter of 0.55nm, place the exposed source metal contact hole and the drain metal contact hole region in a developer for development, wash away the photoresist and the developer adhering to the surface of the source metal contact hole and the drain metal contact hole region with deionized water, dry them at 100°C for 5 minutes, finally use a stripper to remove the remaining photoresist to leave the etched source metal contact hole and the drain metal contact hole with a diameter of 0.55nm, and use electroplating to deposit a metal layer Cr / Au in the corresponding contact holes.

6. The method for preparing the light-controlled adjustable negative capacitance field effect transistor according to claim 3, characterized in that: The specific preparation steps of step 3 are as follows: Step 31: treating the gate oxide dielectric layer (8) in isopropanol at an ultrasonic power of 98W for 8 minutes to remove impurities on the top surface of the gate oxide dielectric layer (8), then placing the gate oxide dielectric layer (8) in an APM solution of ammonia and hydrogen peroxide at an ultrasonic power of 108W for 8 minutes, and finally washing it in deionized water, and drying it in an oven at a temperature of 120°C for 5 minutes; Step 32: forming a ferroelectric material layer (9) on the side of the channel region facing away from the semiconductor substrate (1); the ferroelectric material layer (9) is made of a high-K electron layer ferroelectric material Hf x Zr 1-x O2, film thickness is 15nm, ferroelectric material parameters coercive field is 0.6 MVcm -1 , the remnant polarization is 25µC cm -2 ; Through the metal organic chemical vapor deposition technology, lead zirconate titanate is selected as a precursor, and reacts with the reaction gas lead zirconate titanate in a metal organic chemical vapor deposition reactor at a temperature of 400~500℃ to form ferroelectric Hf x Zr 1-x O2 film, the Hf x Zr 1-x The O2 film was placed in a metal organic vapor deposition reactor and annealed at 600°C in a hydrogen atmosphere. The Hf x Zr 1-x O2 thin film, finally forming a ferroelectric material layer (9) with a thickness of 15nm; Step 33: uniformly cover the surface of the ferroelectric thin film layer with a layer of photoresist HSQ, place the ferroelectric thin film covered with the photoresist in an oven and dry it at 300°C for 4 minutes to remove the solvent in the photoresist, use an electron beam lithography machine SB254 to use a focused electron beam to scan the surface of the photoresist to expose a ferroelectric material layer (9) area with a thickness of 15 nm, place the exposed ferroelectric material layer (9) area in a developer for development, wash off the photoresist and developer adhering to the surface of the ferroelectric material layer (9) with deionized water, dry it at 100°C for 5 minutes, use an electron beam lithography machine SB254 to etch it to remove excess ferroelectric material layer (9), use a stripper to remove the remaining photoresist, and use a PVD electron beam evaporation table to evaporate Hf x Zr 1-x The O2 film leaves a uniform ferroelectric material layer (9) with a thickness of about 15 nm.

7. The method for preparing the light-controlled adjustable negative capacitance field effect transistor according to claim 3, characterized in that: The specific preparation steps of step 4 are as follows: Step 41: Cleaning Hf Using Plasma Cleaning Method x Zr 1-x On the surface of the O2 ferroelectric material layer (9), Hf x Zr 1-x The O2 ferroelectric material layer (9) is placed in an oxygen environment with a pressure of 50-100 mT and a radio frequency power of 200 W for 4 minutes, wherein the oxygen flow rate is controlled by a flow controller to clean impurities on the ferroelectric material layer (9) to ensure that the surface of the ferroelectric material layer (9) is free of contamination, and annealing is performed to improve interface properties; Step 42: After cleaning the surface of the ferroelectric material layer (9), add an appropriate amount of polyethylene wax particles into the n-hexane solvent, and stir the mixture until the wax is completely dissolved to form a transparent solution; place the ferroelectric material layer (9) on a spin coater, drop a small amount of polyethylene wax solution, set the rotation speed to 800 rpm and the rotation time to 15 s so that the polyethylene wax solution is evenly distributed on the surface of the ferroelectric material layer (9), and quickly evaporate the solvent during the rotation process, leaving a uniform polyethylene wax film with a thickness of 18 nm; Step 43: The ferroelectric material layer (9) with the polyethylene wax layer is heated in an oven at 600°C so that the wax layer adheres better to the ferroelectric material layer (9) and the residual solvent is eliminated to form a polyethylene wax layer; the polyethylene wax layer is placed in isopropanol and treated at an ultrasonic power of 108W for 8 minutes to clean the impurities on the polyethylene wax layer and ensure that the surface of the polyethylene wax layer is free of contamination; the polyethylene wax layer is then placed in an ethanol solution and treated at an ultrasonic power of 108W for 8 minutes; and finally, the polyethylene wax layer is placed in deionized water for cleaning and then placed in an oven at a temperature of 120°C for drying for 5 minutes to form a sacrificial layer (10).

8. The method for preparing the light-controlled adjustable negative capacitance field effect transistor according to claim 3, characterized in that: The specific preparation steps of step 5 are as follows: Step 51: Invert the epitaxial growth structure, and grow the epitaxial structure of the single-junction solar cell on the N-type temporary GaAs substrate using an organic metal chemical vapor precipitation method to form an epitaxial layer on the N-type temporary GaAs substrate, and then place the solar cell epitaxial wafer and the temporary substrate GaAs wafer in isopropanol at an ultrasonic power of 108 W for 6 minutes, and then place them in an ethanol solution at an ultrasonic power of 108 W for 8 minutes, and finally place them in deionized water for cleaning, and after cleaning, place them in an oven at a temperature of 120° C. for drying for 5 minutes; Step 52: After cleaning, the bonding layer metal is evaporated by electron beam evaporation. After evaporation, the solar cell epitaxial wafer and the GaAs substrate are annealed at 400° C. for 8 minutes in a hydrogen environment; the solar cell epitaxial wafer and the GaAs substrate are bonded and stacked in two stages by metal hot pressing bonding under a pressure of 8000 kgf, the first stage is 200° C. for 6 minutes; the second stage is 280° C. for 12 minutes; Step 53: After bonding is completed, a chemical solution etching method is used to immerse the GaAs substrate of the cell epitaxial wafer in a solution with a ratio of 1:5 for 10 minutes to corrode and remove the GaAs substrate; the electrode structure of the N side and the P side is AuGe / Ti / Al / Ag / Au, wherein AuGe is the back electrode material of the solar cell, Ti is the adhesion layer in the electrode structure, Al is the front electrode material of the solar cell, Ag is the electrode material, and Au is the outer layer of the electrode. The overall thickness is 15 nm, of which the Al thickness accounts for 15%.

9. The method for preparing the light-controlled adjustable negative capacitance field effect transistor according to claim 3, characterized in that: The specific preparation steps of step 6 are as follows: Step 61: placing the single-junction solar cell layer (11) in isopropanol and treating it with an ultrasonic power of 108 W for 8 minutes to clean the impurities on the single-junction solar cell layer (11); then placing the single-junction solar cell layer (11) in an APM solution mixed with ammonia water and hydrogen peroxide and treating it with an ultrasonic power of 108 W for 8 minutes; finally placing it in deionized water for cleaning; after cleaning, placing it in an oven at a temperature of 120° C. for drying for 5 minutes to clean the surface of the single-junction solar cell layer (11); Step 62: using an atomic layer deposition method to deposit a uniform and dense transparent conductive oxide film with a thickness of 12 nm on the single junction solar cell layer (11) as an enhancement layer (18) of the single junction solar cell layer (11), and after deposition, performing an annealing treatment at 1000° C. in a hydrogen atmosphere to reduce defects and improve the physical properties of the transparent conductive oxide film, and using a chemical-mechanical polishing technique to planarize the transparent conductive oxide; Step 63: placing the transparent conductive oxide film in isopropyl alcohol and treating it with an ultrasonic power of 108 W for 8 minutes to clean impurities on the transparent conductive oxide film, then placing the transparent conductive oxide film in an APM solution mixed with ammonia water and hydrogen peroxide and treating it with an ultrasonic power of 108 W for 8 minutes, and finally placing it in deionized water for cleaning, and after cleaning, placing it in an oven at a temperature of 120° C. for drying for 5 minutes to clean the surface of the transparent conductive oxide film; Step 64: uniformly cover the surface of the transparent conductive oxide film with a layer of photoresist HSQ, place the transparent conductive oxide film covered with the photoresist in an oven at a temperature of 500° C. and dry for 4 minutes to remove the solvent in the photoresist, use an electron beam lithography machine SB254 to directly scan the surface of the photoresist with a focused electron beam to expose the transparent conductive oxide film area, place the exposed transparent conductive oxide area in a developer for development, wash off the photoresist and the developer adhering to the surface of the transparent conductive oxide with deionized water, dry at 100° C. for 5 minutes, use an electron beam lithography machine SB254 to etch and remove excess transparent conductive oxide film area, finally use a stripper to remove the remaining photoresist, use a PVD electron beam evaporation table to evaporate the transparent conductive oxide film, and leave a transparent conductive oxide area with a final thickness of 12 nm; Step 65: using metal organic chemical vapor deposition technology, lead zirconate titanate is selected as a precursor, and reacts with a reaction gas lead zirconate titanate in a metal organic chemical vapor deposition reactor at a temperature of 500-600° C. to form a TiN film, placing the TiN film in the metal organic vapor deposition reactor, annealing at 800° C. in a hydrogen atmosphere, and etching the TiN film using an electron beam etching technology to form a gate metal layer with a thickness of 12 nm; Step 66: uniformly cover the surface of the TiN film with a layer of photoresist HSQ, place the TiN film covered with the photoresist in an oven and dry it at 500°C for 4 minutes, use an electron beam lithography machine SB254 to use a focused electron beam to directly scan the surface of the photoresist to expose the TiN gate metal layer area, place the exposed TiN gate metal layer area in a developer for development, use deionized water to wash away the photoresist and the developer adhering to the surface of the TiN gate metal layer, dry it at 100°C for 5 minutes, use an electron beam lithography machine SB254 to etch it, remove excess TiN gate metal layer area, finally use a stripper to remove the remaining photoresist, use a PVD electron beam evaporation table to evaporate the TiN film, and leave a TiN gate metal layer area with a thickness of 14 nm; place the prepared gate metal layer in an MOCVD reactor, and anneal it at 500°C in a hydrogen atmosphere.

10. The method for preparing the light-controlled adjustable negative capacitance field effect transistor according to claim 3, characterized in that: The specific preparation steps of step 7 are as follows: Step 71: design and manufacture a photolithography mask, which is opaque in the middle area of ​​the gate metal layer to allow electron beam exposure of the area; use an electron beam lithography machine SB254 to use a focused electron beam to coat a layer of photoresist HSQ on the gate metal layer, and only expose the middle area of ​​the gate metal layer that needs to be removed; place the unexposed gate metal layer area in a developer for development, use deionized water to wash away the photoresist and developer adhering to the surface of the gate metal layer, expose the middle area of ​​the gate metal layer, and dry it at 100° C. for 5 minutes, and use an electron beam lithography machine SB254 to etch the exposed middle area of ​​the gate metal layer to remove the middle TiN gate metal layer area, and form a window on the gate metal layer to allow light to directly irradiate the single-junction solar cell layer (11); place the manufactured gate metal layer in an MOCVD reactor and anneal at 400° C. in a hydrogen atmosphere; Step 72: The middle part of the gate metal layer is completely removed, and the retained parts on both sides of the gate metal layer are the first gate metal layer (12) and the second gate metal layer (13); a layer of photoresist HSQ is evenly coated on the first gate metal layer (12) and the second gate metal layer (13), and the TiN gate metal layer covered with the photoresist is placed in an oven and dried at 300° C. for 4 minutes. An electron beam lithography machine SB254 is used to scan and expose the first gate metal contact area (14) and the second gate metal contact area (15) directly on the photoresist surface with a focused electron beam, and the exposed gate metal contact area is placed in a developer for development, and the sticky residue is washed away with deionized water. The photoresist and developer attached to the surface of the gate metal contact area are dried at 100°C for 5 minutes, and are etched using an electron beam lithography machine SB254 to remove excess gate contact areas. Finally, a stripper is used to remove the remaining photoresist, and a TiN gate metal layer film is evaporated using a PVD electron beam evaporation table, leaving a circular gate metal contact hole area with a diameter of 0.55nm. The fabricated gate metal contact hole is placed in an MOCVD reactor, and annealed at 1000°C in a hydrogen atmosphere to form a contact hole, and filling metal Cr / Au is deposited in the contact hole, and the deposited metal Cr / Au is polished to form a first gate metal contact hole and a second gate metal contact hole.

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