HBC Solar Cell Structure and Fabrication Method

Abstract

The invention belongs to the technical field of solar power generation, and specifically relates to an HBC solar cell structure and a preparation method thereof, comprising the following steps: step S1, double-sided polishing of a silicon wafer; step S2, depositing a P-type semiconductor film layer on the back of the silicon wafer; step S3, laser oxidation of a P region on the back of the silicon wafer to form a patterned silicon oxide mask; step S4, alkaline polishing and cleaning of a mask-free region on the back of the silicon wafer and etching to obtain a silicon base; step S5, depositing an N-type semiconductor film layer on the back of the silicon wafer; step S6, laser oxidation of an N region on the back of the silicon wafer to form a patterned silicon oxide mask; step S7, forming a pyramid velvet surface, and removing the silicon oxide mask on the back of the silicon wafer; step S8, preparing an FSF field passivation region, depositing a laminated gradient silicon nitride anti-reflection passivation film, and depositing a TCO transparent conductive film on the back; step S9, laser etching on the back of the silicon wafer to isolate the N region from the P region, and preparing an interdigitated arrangement structure; and step S10, printing metal slurry.

Description

Technical Field

[0001] The invention belongs to the technical field of solar power generation, and in particular relates to an HBC solar cell structure and a preparation method thereof. Background Art

[0002] Photovoltaic power generation is a system that uses solar cells to directly convert sunlight energy into electrical energy based on the principle of the photovoltaic effect. The basic structure of a solar cell is a large-area planar PN junction. When sunlight shines on the PN junction, the PN junction absorbs light energy to excite electrons and holes, and then generates voltage in the PN junction to achieve photoelectric conversion. Therefore, the core structure for realizing the conversion of sunlight energy and electrical energy in crystalline silicon cells is the PN junction.

[0003] As Perc cells gradually approach the limit efficiency of 24.5%, the industry has begun to seek the next generation of crystalline silicon cell technology. The current mainstream technologies are Topcon (tunnel oxide passivation contact), HJT (heterojunction), and IBC (interdigitated back contact). Unlike Topcon and HJT, which improve cell efficiency by changing the passivation method, IBC cells transfer all the cell grid lines to the back, reduce the grid line shading area, increase current density, and increase cell efficiency. IBC cells are platform technologies, which are superimposed with Topcon technology to form TBC and with HJT technology to form HBC.

[0004] However, HBC batteries have the defect that the amorphous interdigitated structure is difficult to prepare. This is because it is difficult to accurately locate the depth of the opening area with traditional laser film opening, and amorphous passivation is easily damaged by laser film opening.

[0005] Therefore, how to provide a method for preparing HBC cells that is easy to laser process and position while causing little damage to amorphous silicon is a technical problem that urgently needs to be solved in this field.

[0006] It should be noted that the above information disclosed in this background technology section is only used to understand the background technology of the present application concept, and therefore, the above description is not considered to constitute information of the prior art. Summary of the invention

[0007] The embodiments of the present disclosure at least provide a HBC solar cell structure and a method for preparing the same.

[0008] In a first aspect, an embodiment of the present disclosure provides a method for preparing an HBC solar cell, comprising the following steps: step S1, double-sided polishing of a silicon wafer to prepare a clean silicon wafer surface with a lubricating alkali polishing tower base morphology; step S2, depositing a layer of i: a-Si layer from top to bottom on the back side of the silicon wafer, HPT cleaning the deposited surface and then depositing a P: a-Si layer from top to bottom; step S3, laser oxidation of the P region on the back side of the silicon wafer to form a patterned silicon oxide mask; step S4, alkaline polishing cleaning and etching of the mask-free region on the back side of the silicon wafer to obtain a silicon base; step S5, depositing a layer of i: a-Si layer from top to bottom on the back side of the silicon wafer, HPT cleaning the deposited surface After washing, a N: a-Si layer is deposited from top to bottom; step S6, laser oxidation is performed on the N region on the back of the silicon wafer to form a patterned silicon oxide mask; step S7, a pyramid velvet surface is formed on the front of the silicon wafer, and the silicon oxide mask on the back of the silicon wafer is removed at the same time; step S8, an FSF field passivation area is prepared on the front of the silicon wafer, and a laminated gradient silicon nitride anti-reflection passivation film is deposited on the front, and a TCO transparent conductive film is deposited on the back; step S9, laser etching is performed on the back of the silicon wafer to isolate the N region from the P region, and a finger arrangement structure is prepared; step S10, metal slurry is printed on the TCO transparent conductive film in the N region and the P region on the back of the silicon wafer to form a metal electrode to complete the preparation of the HBC battery.

[0009] In an optional implementation, the reflectivity of the surface of the silicon wafer after polishing in step S1 is 30-40%; and the size of the tower base is 3-8 μm.

[0010] In an optional embodiment, in step S2, the thickness of the i:a-Si layer is 2-10 nm; the P:a-Si layer includes P:a-Si layer and P-uc-SiO x C y Layering; wherein the thickness of the P: a-Si layer is 10-20nm and the doping concentration is 1E+18cm -3 ~5E+18cm -3 :The P-uc-SiO x C y The layer thickness is 20-50nm and the doping concentration is 5E+18cm -3 ~2E+19cm -3 .

[0011] In an optional implementation, in step S3, the thickness of the silicon oxide mask is 5-15 nm, and the width of the oxidized region is 150-500 μm; in step S6, the thickness of the silicon oxide mask is 5-15 nm, and the width of the oxidized region is 150-500 μm.

[0012] In an optional implementation, the reflectivity of the corroded area in step S4 is 35-45%; the tower base size of the corroded area is 8-15 μm; and the corrosion depth of the corroded area is 0.5-2 μm.

[0013] In an optional embodiment, in step S5, the thickness of the i: a-Si layer is 2-10 nm; the N: a-Si layer includes a N: a-Si layer and a N-uc-Si layer; wherein the thickness of the N: a-Si layer is 10-20 nm, and the doping concentration is 1E+18 cm -3 ~5E+18cm -3 :The thickness of the N-uc-Si layer is 20-50nm, and the doping concentration is 5E+18cm -3 ~2E+19cm -3 .

[0014] In an optional implementation, the reflectivity of the suede surface in step S7 is 9-12%.

[0015] In an optional embodiment, the doping concentration of the FSF field passivation region in step S8 is 1E+18cm -3 ~1E+19cm -3 ; The thickness of the laminated gradient silicon nitride anti-reflection passivation film is 75nm-105nm, and the refractive index is 1.8-2.2; the thickness of the TCO transparent conductive film is 70nm-150nm, and the square resistance is 50-120.

[0016] In an optional embodiment, the etching in step S9 specifically involves etching the TCO transparent conductive film, N:a-Si layer and N-uc-Si layer at the junction of the P region and the N region on the back of the silicon wafer, retaining the i:a-Si layer; the etching width is 10-50 μm.

[0017] In a second aspect, the present disclosure also provides an HBC solar cell structure prepared by the method described above, wherein the front side of the cell is a laminated gradient silicon nitride anti-reflection passivation film, and after the P is injected into the front side to prepare the N+ region, a high-low junction field passivation structure of the N+ / FSF layer is formed; the P region on the back side of the cell is doped with amorphous silicon to form a P-uc-SiO x C y Layering; the back P region of the battery has a low-reflection alkaline-polished tower-based morphology, and the N region has a high-reflection alkaline-polished tower-based morphology.

[0018] The beneficial effect of the present invention is that the HBC solar cell structure and its preparation method use substrates with different morphologies in the N region and the P region to prepare an amorphous interdigitated arrangement structure, thereby reducing the difficulty of laser etching, improving the process window and reducing the risk of battery leakage; at the same time, the amorphous silicon mask is prepared based on laser oxidation technology, and the "laser oxidation-wet etching" process replaces the traditional "mask preparation-laser etching-wet etching", which greatly simplifies the process flow, improves the process cleanliness, reduces the damage of laser etching to amorphous passivation, and improves battery efficiency.

[0019] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0020] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A schematic diagram of a battery structure provided in an embodiment of the present disclosure; Figure 2 A schematic diagram of a process flow provided for an embodiment of the present disclosure; Figure 3 A schematic diagram of a battery structure provided in an embodiment of the present disclosure; Figure 4 A schematic diagram of a process flow provided for an embodiment of the present disclosure; Figure 5 A schematic diagram of a battery structure provided in an embodiment of the present disclosure; Figure 6 A schematic diagram of a battery structure provided in an embodiment of the present disclosure; Figure 7 A schematic diagram of a process flow provided for an embodiment of the present disclosure; Figure 8 A schematic diagram of a battery structure provided in an embodiment of the present disclosure; Fig. 9 A schematic diagram of a process flow provided for an embodiment of the present disclosure; Fig.10 A schematic diagram of a battery structure provided in an embodiment of the present disclosure; Fig.11 A schematic diagram of a battery structure provided in an embodiment of the present disclosure; Fig.12 A schematic diagram of a process flow provided for an embodiment of the present disclosure; Fig.13 A schematic diagram of a battery structure provided in an embodiment of the present disclosure; Fig.14 A schematic diagram of a process flow provided for an embodiment of the present disclosure; Fig.15 A schematic diagram of a battery structure provided in an embodiment of the present disclosure; Fig.16 A schematic diagram of a battery structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] As used herein, the phrases "in one embodiment," "according to one embodiment," "in some embodiments," and the like generally refer to the fact that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure. Therefore, a particular feature, structure, or characteristic may be included in more than one embodiment of the present disclosure, so that these phrases do not necessarily refer to the same embodiment. As used herein, the terms "example," "exemplary," and the like are used to "serve as an example, instance, or illustration." Any implementation, aspect, or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or superior to other implementations, aspects, or designs. On the contrary, the use of the terms "example," "exemplary," and the like is intended to present concepts in a concrete manner.

[0025] Herein, example embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. As used herein, expressions such as "at least one of..." modify the entire list of elements when following a list of elements, rather than modifying individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0026] The terms used herein are only used to describe specific exemplary configurations and are not intended to be limited. As used herein, the singular articles "one", "an" and "the" may also be intended to include plural forms, unless it is clearly indicated above that this is not the case. The terms "comprise", "include" and "have" are inclusive, and therefore specify the presence of features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or combinations thereof. The method steps, processes and operations described herein should not be interpreted as necessarily requiring them to be performed in the specific order discussed or shown, unless specifically identified as an execution order. Additional or alternative steps may be adopted.

[0027] Terminology explanation: HBC: The Chinese name of IBC battery is cross-finger back contact battery. The emitter, back field and corresponding positive and negative electrodes are integrated on the back of the battery in a cross-finger shape. This structure avoids the metal grid electrode from blocking light, maximizes the use of incident light, and increases the short-circuit current of the battery. HBC technology is a combination of HJT technology and IBC technology, which can increase current density and battery efficiency without losing passivation.

[0028] Existing technology 1: Xuzhou Pule New Energy (patent number CN 115050855 A) Scheme steps: 1. Double-sided texturing; 2. Back-side polishing; 3. Double-sided deposition of i:a-Si; 4. Back-side patterned boron paste printing and drying; 5. Back-side patterned phosphorus paste printing and drying; 6. Laser doping of N-zone and P-zone; 7. Ultrasonic cleaning of slurry with organic water mixed solution; 8. Back-side TCO deposition; 9. Laser grooving to isolate N-zone and P-zone; 10. Front-side deposition of SiO / SiON / SiN stacked film; 11. Screen printing, curing and sintering.

[0029] Concept: 1. From top to bottom: SiN / SiON / SiO---i: a-Si---suede surface---silicon base---polished surface---i: a-Si---P: a-Si---N: a-Si---TCO---silver paste HBC battery structure; 2. i: a-Si is deposited on the back of the battery, and the boron slurry and phosphorus slurry are cross-printed using a screen. After drying, laser doping, and cleaning, the poly interdigitated arrangement structure of the N and P regions on the back of the battery is completed.

[0030] shortcoming: 1. Use doping slurry as the doping source. Due to its special fluidity and corrosiveness, it requires the use of professional scrapers, scrapers, special non-metallic mesh, and non-market mass production auxiliary materials; 2. In order to meet the printing requirements, the doping slurry often adds more organic solvents to achieve curing. Organic solvents will affect the diffusion effect of boron and phosphorus doping, and the diffusion uniformity is poor; 3. To meet the printing requirements, more organic solvents are often added to the doped slurry, which has a strong odor, requires high ventilation on site, and requires high protective measures for employees; 4. It is difficult to control the doping amount and doping depth of amorphous silicon by laser boron-phosphorus slurry, which can easily damage the underlying hydrogenated amorphous silicon and affect the passivation of the battery. 5. The ARC anti-reflection film is prepared at a high temperature of >200°C on the front side, which can easily lead to a decrease in the passivation of amorphous silicon; 6. The front side adopts the anti-reflection passivation film design of SiNx+i:a-Si, which has large parasitic absorption and large battery current loss; 7. In this process, amorphous silicon is exposed for a long time without a protective film, which affects the passivation of the battery.

[0031] Prior art 2: Aikang (CN 218849510 U ) Scheme steps: 1. Cleaning and texturing; 2. Preparation of silicon oxide and intrinsic amorphous silicon on the back; 3. High-temperature phosphorus diffusion, crystallization of the amorphous on the back into phosphorus-doped polysilicon; 4. Laser etching; 5. Poly cleaning, de-plating and expansion, alkali polishing and cleaning of the laser ablation area until the N-type silicon base is washed; 6. Front intrinsic amorphous silicon deposition; 7. Front silicon nitride preparation; 8. Preparation of intrinsic amorphous silicon and P: a-Si by back mask-grooving-deposition-etching technology; 9. Preparation of TCO by back mask-grooving-deposition-etching technology; 10. Screen electrode printing and curing.

[0032] concept: The back N and P regions are prepared by the traditional mask-groove-deposition-etching method, and the N region adopts a polo passivation contact structure of SiO and N+poly to replace the i:a-Si+N:a-Si battery structure.

[0033] shortcoming: 1. The front side adopts the anti-reflection passivation film design of SiNx+i:a-Si, which has large parasitic absorption and large battery current loss; 2. The H passivation effect of the polo passivation contact structure interface of SiO and N+poly in the back N region is poor; 3. The N+poly preparation of the back N region uses high-temperature tubular equipment, which involves wrapping, expansion and plating.

[0034] The defects existing in the above solutions are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the present disclosure for the above problems below should be the contributions made by the inventor to the present disclosure during the disclosure process.

[0035] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0036] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0037] Step S1, double-sided polishing of the silicon wafer to prepare a smooth alkali polishing tower base morphology and a clean silicon wafer surface, Figure 1 See the silicon wafer shown. Figure 2 , the specific process is as follows: Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-15%) to clean the surface of the silicon wafer to remove dirt on the surface of the silicon wafer. The process temperature is 55℃-70℃ and the process time is 2min-5min. Use water washing to remove drug residues and dirt on the surface. The cleaning time is 2min-3min. A mixed solution of potassium hydroxide (1%-10%) and additives (0.5%-5%) is used to polish the surface of the silicon wafer to form an alkali polishing tower base morphology and remove cutting damage. The process temperature is 60℃-85℃ and the process time is 3min-5min. Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min; Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the surface of the silicon wafer to remove additive residues. The process temperature is 55℃-70℃ and the process time is 2min-5min. Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min; A mixed solution of hydrofluoric acid (0.1%-2%), hydrochloric acid (0.1%-2%) and O3 (10ppm-50ppm) is used to clean the surface of the silicon wafer. At the same time, the weak etching system of O3 and HF lubricates the surface of the silicon wafer, reduces burr defects on the surface of the silicon wafer, and is more conducive to the passivation of amorphous silicon. The process temperature is 15℃-25℃, and the process time is 2min-3min. Use water washing to remove drug residues and dirt on the surface. The cleaning time is 2min-3min. Use a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%) to clean the surface of the silicon wafer. The process temperature is room temperature and the process time is 3min-5min. Use water washing to remove drug residues and dirt on the surface. The cleaning time is 2min-3min. Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃. Place the silicon wafer in a drying tank, purge at high temperature to dry the surface of the silicon wafer. Purge gas: nitrogen or compressed air, temperature: 80℃-100℃, drying time: 5min-15min; Wafer weight reduction: 0.3g-0.6g; (taking 182.2 size wafer as an example) Surface reflectivity: 30%-40%; Tower base size: 3um-8um.

[0038] Step S2, ia:Si / P:a-Si deposition on the back of the silicon wafer to obtain Figure 3 For the battery structure shown, see Figure 4 , the specific process is as follows: The flat-plate PECVD method is used to deposit a layer of i: a-Si from top to bottom on the back of the double-sided alkaline polished silicon wafer, and then the deposited surface is cleaned by HPT (H ion cleaning). Finally, the flat-plate PECVD method is used to deposit P: a-Si on the back of the silicon wafer from top to bottom. The deposition includes a layer of P: a-Si layer, a layer of P-uc-SiO x C y Layering; After double-sided alkaline polishing, the silicon wafer is placed on a hollow carrier, gate valve 1 is opened, and the wafer is transferred into the loading chamber 1 for evacuation, gate valve 2 is opened, and the wafer is transferred into the buffer preheating chamber 1, and then transferred to the PECVD1 reaction chamber 1 to deposit ia:Si from top to bottom, and then transferred to the buffer HPT cleaning chamber 2, where H ions clean the deposited surface to complete the i:a-Si preparation; Open gate valve 3, transfer the carrier into transition chamber 1 (gas isolation), open gate valve 4, first transfer to buffer 3, then transfer to PECVD2 reaction chamber 2 to deposit a layer of P: a-Si layer, a layer of P-uc-SiO from top to bottom x C y Layering, and then transfer to buffer 4 to complete the P: a-Si preparation; Open gate valve 5, transfer the carrier to unloading chamber 1, close gate valve 5, fill unloading chamber 1 with N2, open gate valve 6, transfer the carrier out; PECVD1 reaction chamber 1: Preparation of i: a-Si by PECVD method, using SiH4 and H2 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2 flow ratio: 1:10-1:30, power: 50W-300W; PECVD2 reaction chamber 3: PECVD method to prepare P: a-Si, P: a-Si is divided into two layers: conventional B-doped amorphous silicon (Pa:Si), B-doped microcrystalline carbon oxide silicon (P-uc-SiO x C y ); Conventional B-doped amorphous silicon (P: a-Si) preparation uses SiH4, H2, and B2H6 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2:B2H6 (2%) flow ratio: 1:20:5-1:30:15, power: 50W-300W; B-doped microcrystalline silicon oxycarbide (P-uc-SiO x C y ), with SiH4, H2, B2H6, CO2, and TMB as process gases, process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, SiH4:H2:B2H6 (2%) flow ratio: 1:30:10-1:60:30, CO2 and TMB as slightly doped gas flow: 5sccm-20sccm, power: 300w-500W; HPT cleaning buffer chamber 2: PECVD method is used to ionize H to clean the deposited surface of the silicon wafer, with H2 as the process gas, process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, power: 50W-400W; i: a-Si thickness: 2nm-10nm, freely adjustable; P: a-Si thickness: 10nm-20nm, P-uc-SiO x C y Thickness: 20nm-50nm, thickness can be freely adjusted; P: a-Si doping concentration: 1E+18cm -3 ~5E+18cm -3 : P-uc-SiO x C y Doping concentration: 5E+18cm -3 ~2E+19cm -3 , the doping amount can be freely adjusted; Specifically, in step S2, the vacuum blocking technology of "transition-isolation-coating-isolation" is adopted to meet the process pressure of different film layer preparations, and at the same time avoid process abnormalities caused by "cross-talk" between process gases of different film layer preparations. A single machine can meet the preparation of different film layers, combining i: a-Si deposition & P: a-Si deposition & HPT cleaning into one.

[0039] Specifically, the transition chamber is used to adjust the pressure to meet the switching of different process pressure conditions / blocking of gas media in different process chambers.

[0040] Specifically, the buffer chamber functions as a secondary isolation and blocking of different gas media.

[0041] Specifically, i: a-Si deposition, P: a-Si deposition and HPT cleaning are combined into one / i: a-Si deposition, N: a-Si deposition and HPT cleaning are combined into one / HPT cleaning, FSF preparation, SiNx deposition and TCO deposition are combined into one. At the same time, amorphous silicon masks are prepared based on laser oxidation technology, and the "laser oxidation-wet etching" process is used to replace the traditional "mask preparation-laser etching-wet etching" process. The HBC battery preparation process is reduced from 16 to 10, which greatly simplifies the process flow and reduces equipment costs. At the same time, the frequency of "breaking vacuum" in film preparation is reduced to improve the process cleanliness, and laser oxidation replaces laser etching to reduce amorphous passivation damage, which greatly improves battery efficiency and is suitable for industrial production.

[0042] Step S3, laser oxidation of the back P region to prepare a patterned mask, Figure 5 The battery structure shown in the figure has the following specific processes: Laser induced oxidation technology is used to form P-uc-SiO on the P region on the back of the silicon wafer. x C y A patterned silicon oxide mask is formed on the surface, the battery is placed on a horizontal platform, and a pulsed ultraviolet nanosecond laser is used to locally oxidize the amorphous silicon to prepare a patterned silicon oxide mask; Laser power: 300w-600w; Silicon oxide mask: thickness: 5nm-15nm, oxidation area width: 150um-500um, can be freely adjusted.

[0043] Step S4, alkali polishing to remove the unmasked area on the back side i: a-Si / P: a-Si / P-uc-SiO x C y , and corrode the silicon base to a certain depth, and obtain Figure 6 For the battery structure shown, see Figure 7 , the specific process is as follows: Use a mixed solution of potassium hydroxide (1%-10%) and alkaline polishing additive (0.5%-5%) to clean. Potassium hydroxide corrodes the unmasked area on the back i: a-Si / P: a-Si / P-uc-SiO x C y , process temperature: 55℃-70℃, process time: 0.5min-1.5min; Use water washing to remove drug residues and dirt on the surface. The cleaning time is 2min-3min. Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the surface of the silicon wafer to remove additive residues. The process temperature is 55℃-70℃ and the process time is 2min-5min. Use water washing to remove drug residues and dirt on the surface. The cleaning time is 2min-3min. Use hydrochloric acid (1%-10%) solution to clean the silicon wafer surface to remove alkali residue; process temperature: room temperature, process time: 3min-5min; Use water washing to remove drug residues and dirt on the surface. The cleaning time is 2min-3min. Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃. Place the silicon wafer in a drying tank, purge at high temperature to dry the surface of the silicon wafer. Purge gas: nitrogen or compressed air, temperature: 80℃-100℃, drying time: 5min-15min; Cleaning method: The silicon wafer enters the solution vertically, the direction of the silicon wafer laser line is perpendicular to the solution surface, and the detachment of drug residues on the silicon wafer surface is not affected by the morphology of the back groove; Reflectivity of corroded area: 35%-45%; The size of the tower base in the corroded area: 8um-15um; Corrosion depth of corroded area: 0.5um-2um.

[0044] Specifically, the N-region and the P-region use substrates with different morphologies, which is more conducive to laser oxidation and laser grooving isolation positioning identification, and the preparation of an amorphous forked-finger arrangement structure in the N-region and the P-region, reducing the risk of battery leakage and offset.

[0045] Step S5, ia:Si / N:a-Si / N-uc-Si deposition on the back of the silicon wafer to obtain Figure 8 For the battery structure shown, please refer to Fig. 9 , the specific process is as follows: First, the back surface of the silicon wafer after alkali washing is HPT-cleaned (H ion-cleaned) by a flat-plate PECVD method, and then a layer of i: a-Si is deposited from top to bottom by a flat-plate PECVD method, and then the deposited surface is HPT-cleaned (H ion-cleaned), and finally, N: a-Si is deposited from top to bottom on the back surface of the silicon wafer by a flat-plate PECVD method, including a layer of N: a-Si layer and a layer of N-uc-Si layer; After alkali washing, the silicon wafer is placed on a hollow carrier plate, the gate valve 7 is opened, and the wafer is transferred to the loading chamber 2 for evacuation, the gate valve 8 is opened, and the wafer is transferred to the buffer preheating chamber 5, and then transferred to the HPT cleaning buffer chamber 6, the H ions clean the deposition surface, and then transferred to the PECVD3 reaction chamber 3, ia:Si is deposited from top to bottom, and then transferred to the HPT cleaning buffer chamber 7, the H ions clean the deposition surface, and the i:a-Si preparation is completed; Open the gate valve 9, transfer the carrier into the transition chamber 2 (gas isolation), open the gate valve 10, first transfer to the buffer 8, then transfer to the PECVD4 reaction chamber 4 to deposit a layer of N: a-Si layer and a layer of N-uc-Si layer from top to bottom, and then transfer to the buffer 9 to complete the N: a-Si preparation; Open the gate valve 11, transfer the carrier to the unloading chamber 2, close the gate valve 11, fill the unloading chamber 2 with N2, open the gate valve 12, and transfer the carrier out; PECVD3 reaction chamber 3: Preparation of i:a-Si by PECVD method, using SiH4 and H2 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2 flow ratio: 1:10-1:30, power: 50W-300W; PECVD4 reaction chamber 4: N:a-Si is prepared by PECVD method. N:a-Si is divided into two layers: conventional P-doped amorphous silicon (Na:Si) and P-doped microcrystalline silicon (N-uc-Si); Conventional P-doped amorphous silicon (N: a-Si) preparation, with SiH4, H2, PH3 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2:PH3 (2%) flow ratio: 1:20:5-1:30:15, power: 50W-300W; Preparation of P-doped microcrystalline silicon (N-uc-Si), using SiH4, H2, PH3 as process gases, process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, SiH4:H2; PH3 (2%) flow ratio: 1:30:10-1:60:30, power: 300w-500W; HPT cleaning buffer chamber 6: PECVD method is used to ionize H to clean the deposited surface of the silicon wafer, with H2 as the process gas. Process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, power: 50W-400W; HPT cleaning buffer chamber 7: PECVD method is used to ionize H to clean the deposited surface of the silicon wafer, with H2 as the process gas. Process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, power: 50W-400W; i: a-Si thickness: 2nm-10nm, freely adjustable; N: a-Si thickness: 10nm-20nm, N-uc-Si thickness: 20nm-50nm, thickness can be freely adjusted; N: a-Si doping concentration: 1E+18cm -3 ~5E+18cm -3 ,N-uc-Si doping concentration: 5E+18cm -3 ~2E+19cm-3, the doping amount can be freely adjusted; Step S6, laser oxidation of the back N region to prepare a patterned mask, Fig.10 The battery structure shown in the figure has the following specific processes: Laser-induced oxidation technology is used to form a patterned silicon oxide mask on the surface of the N-doped microcrystalline silicon (N-uc-Si) on the back of the silicon wafer. The battery is placed on a horizontal platform and a pulsed ultraviolet nanosecond laser is used to locally oxidize the polysilicon to prepare a patterned silicon oxide mask. Laser power: 300w-600w; Silicon oxide mask: thickness: 5nm-15nm, oxidation area width: 150um-500um, freely adjustable; Laser oxidation precision requirements: The N area (groove area) is fully covered with laser oxidation, and the P area can be appropriately extended by 1-5um, which has no effect on the subsequent removal of the P area i: a-Si&N: a-Si&N-uc-Si.

[0046] Step S7, the front side is textured, and the back side SiO2 mask is removed to obtain Fig.11 For the battery structure shown, see Fig.12 , the specific process is as follows: Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-15%) to clean the surface of the silicon wafer to remove dirt on the surface of the silicon wafer. The process temperature is 55℃-70℃ and the process time is 1min-3min. Use water washing to remove drug residues and dirt on the surface. The cleaning time is 2min-3min. A mixed solution of potassium hydroxide (1%-10%) and a texturing additive (0.5%-5%) is used to form a pyramid velvet surface on the front side of the silicon wafer. The process temperature is 70℃-85℃ and the process time is 3min-5min. Use water washing to remove drug residues and dirt on the surface. The cleaning time is 2min-3min. Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the surface of the silicon wafer to remove additive residues. The process temperature is 55℃-70℃ and the process time is 1min-3min. Use water washing to remove drug residues and dirt on the surface. The cleaning time is 2min-3min. Use a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%) to clean the surface of the silicon wafer. The process temperature is room temperature and the process time is 3min-5min. Use water washing to remove drug residues and dirt on the surface. The cleaning time is 2min-3min. Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃. Place the silicon wafer in a drying tank, purge at high temperature to dry the surface of the silicon wafer. Purge gas: nitrogen or compressed air, temperature: 80℃-100℃, drying time: 5min-15min; Wafer weight reduction: 0.2g-0.3g; (taking 182.2 size wafer as an example) Suede reflectivity: 9%-12%; Cleaning method: The silicon wafer enters the solution vertically, the direction of the silicon wafer laser line is perpendicular to the solution surface, and the detachment of drug residues on the silicon wafer surface is not affected by the groove morphology on the back side.

[0047] Step S8, prepare the FSF field passivation area on the front side of the silicon wafer, deposit a laminated gradient silicon nitride anti-reflection passivation film on the front side, and deposit a TCO transparent conductive film on the back side to obtain Fig.13 For the battery structure shown, see Fig.14 , the specific process is as follows: The front side of the silicon wafer is cleaned with H ions by flat-plate PECVD, and P atoms are injected at the same time. Then, a silicon nitride laminated gradient film is deposited on the front side of the silicon wafer by PECVD. Finally, a layer of TCO transparent conductive film is deposited on the back side of the silicon wafer by PVD. The textured silicon wafer is placed on a hollow carrier with the textured surface facing upwards, the gate valve 13 is opened, the wafer is transferred into the loading chamber 3 for evacuation, the gate valve 14 is opened, the wafer is transferred into the ion deposition preheating buffer chamber 10, H ion cleaning is performed, and then P ion implantation is performed to complete the preparation of the front FSF field passivation area; The carrier is transferred to the PECVD5 reaction chamber 5 to deposit a layer of high H content SiN from top to bottom. x , a layer of high Si content SiN x , a layer of high N content SiN x , and then transmitted to the buffer cavity 11 to complete the preparation of the laminated gradient silicon nitride anti-reflection passivation film; Open the gate valve 15, transfer the carrier to the transition chamber 3 (gas isolation), open the gate valve 16, first transfer to the buffer chamber 12, then transfer to the PVD1 reaction chamber 6, deposit a layer of TCO from bottom to top, and then transfer to the buffer chamber 13 to complete the preparation of the TCO transparent conductive film; Open the gate valve 17, transfer the carrier to the unloading chamber 3, close the gate valve 17, fill the unloading chamber 3 with N2, open the gate valve 18, and transfer the carrier out; Ion deposition preheating buffer chamber 10: firstly, PECVD method is used to ionize H2, H ions are used to clean the deposited surface of the silicon wafer, H2 is used as process gas, process temperature: 100℃-250℃, process pressure: 50Pa-100Pa; then PECVD method is used to ionize PH3 and H2 mixed gas, P ions are implanted into the front side of the silicon wafer, PH3 and H2 are used as process gas, process temperature: 100℃-250℃, process pressure: 50Pa-100Pa; PECVD5 reaction chamber 5: SiN prepared by PECVD x Laminated gradient passivation anti-reflection film, divided into three layers; S N x -1: SiH4, H2, NH3 are used as process gases, high H2 ratio, high pressure and high power are used to prepare high H content silicon nitride, and passivate the silicon wafer interface. The process temperature is 100℃-250℃, the process pressure is 80Pa-120Pa, the SiH4 / NH3 / H2 flow ratio is 1:1:6-2:2:20; the power is 200W-300W; S N x -2: Using SiH4 and NH3 as process gases, high SiH4 ratio, low pressure and low power are used to prepare high Si content and high density silicon nitride, protecting high H content silicon nitride. At the same time, low power coating reduces SiN x -1 passivation damage, process temperature: 100℃-250℃, process pressure: 30Pa-50Pa, SiH4 / NH3 flow ratio: 2:1-6:1; S N x -3: Using SiH4 and NH3 as process gases, high NH3 ratio, low pressure and low power to prepare high N content silicon nitride, reduce the overall film refractive index, reduce the front reflectivity of the battery, and increase the current density. The process temperature is 100℃-250℃, the process pressure is 30Pa-50Pa, and the SiH4 / NH3 flow ratio is 1:2-1:6; PVD1 reaction chamber 6: When TCO is prepared by PVD method, ITO target material (In2O3 / SnO2 mass ratio: 90:10-97:3) is used, and argon and oxygen are used as working gases, process temperature: 100-250℃, process pressure: 0.2Pa-2Pa, Ar / O2 flow ratio: 200:1-100:1, power: 5000W-40000W FSF doping concentration: 1E+18cm -3 ~1E+19cm -3 ; S N x Thickness: 75nm-105nm; S N x Refractive index: 1.8-2.2; TCO thickness: 70nm-150nm; TCO square resistance: 50-120.

[0048] Step S9, laser etching on the back side to isolate the P region and the N region, and prepare an interdigitated arrangement structure to obtain Fig.15 The battery structure shown in the figure has the following specific processes: Laser ablation technology is used to pattern-etch the TCO / N: a-Si / N-uc-Si at the junction of the P-zone and N-zone on the back, retaining i: a-Si. The battery is placed on a horizontal platform, and a pulsed ultraviolet nanosecond laser is used to pattern-etch the TCO / N: a-Si / N-uc-Si at the junction of the P-zone and N-zone on the back, retaining i: a-Si. Laser power: 300w-600w; Etching width: 10um-50um, freely adjustable.

[0049] Specifically, the N region and the P region adopt different surface morphologies, which is conducive to laser etching to isolate different semiconductors in the N region and the P region, reducing the risk of offset leakage; at the same time, the finger arrangement structure of the N region and the P region is prepared based on laser oxidation instead of laser etching, which reduces the risk of offset laterally and does not need to consider the over-etching and under-etching problems similar to laser etching in the vertical direction.

[0050] Step S10, screen printing curing light injection, to obtain Fig.16 The battery structure shown in the figure has the following specific processes: Printing metal paste on the amorphous silicon film layer in the N and P regions on the back side; After printing, the silicon wafer is transferred to a curing oven, dried and cured to form an ohmic contact with the TCO; The battery is transferred to the annealing furnace, where annealing light is injected to excite H and improve passivation; Complete HBC battery preparation.

[0051] In summary, the HBC solar cell structure and its preparation method use substrates with different morphologies to prepare an amorphous interdigitated structure in the N region and the P region, thereby reducing the difficulty of laser etching, improving the process window and reducing the risk of battery leakage; at the same time, the amorphous silicon mask is prepared based on laser oxidation technology, and the "laser oxidation-wet etching" process replaces the traditional "mask preparation-laser etching-wet etching", which greatly simplifies the process flow, improves the process cleanliness, reduces the damage of laser etching to amorphous passivation, and improves battery efficiency.

[0052] Based on the above ideal embodiments of the present invention, the relevant staff can make various changes and modifications without departing from the technical concept of the present invention through the above description. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A method for preparing a HBC solar cell, characterized in that: The steps include: Step S1, double-sided polishing of the silicon wafer to prepare a clean silicon wafer surface with a lubricating alkali polishing tower base morphology; Step S2, depositing an i: a-Si layer from top to bottom on the back side of the silicon wafer, performing HPT cleaning on the deposited surface, and then depositing a P: a-Si layer from top to bottom; Step S3, laser oxidation is performed on the P region on the back side of the silicon wafer to form a patterned silicon oxide mask; Step S4, performing alkaline polishing and etching on the unmasked area on the back side of the silicon wafer to obtain a silicon base; Step S5, depositing an i: a-Si layer from top to bottom on the back side of the silicon wafer, performing HPT cleaning on the deposited surface, and then depositing an N: a-Si layer from top to bottom; Step S6, laser oxidation is performed on the N region on the back side of the silicon wafer to form a patterned silicon oxide mask; Step S7, forming a pyramid velvet surface on the front side of the silicon wafer, and removing the silicon oxide mask on the back side of the silicon wafer; Step S8, preparing a FSF field passivation region on the front side of the silicon wafer, and depositing a laminated gradient silicon nitride anti-reflection passivation film on the front side, and depositing a TCO transparent conductive film on the back side; Step S9, performing laser etching on the back side of the silicon wafer to isolate the N region from the P region and prepare an interdigitated arrangement structure; Step S10, printing metal paste on the TCO transparent conductive film in the N region and the P region on the back side of the silicon wafer to form metal electrodes to complete the preparation of the HBC battery.

2. The method for preparing a HBC solar cell according to claim 1, characterized in that: The reflectivity of the surface of the silicon wafer after polishing in step S1 is 30-40%; The size of the tower base is 3-8 μm.

3. The method for preparing a HBC solar cell according to claim 1, characterized in that: In step S2, i: the thickness of the a-Si layer is 2-10 nm; The P:a-Si layer includes a P:a-Si layer and a P-uc-SiO x C y Layering; in The thickness of the P:a-Si layer is 10-20nm, and the doping concentration is 1E+18cm -3 ~5E+18cm -3 : The P-uc-SiO x C y The layer thickness is 20-50nm and the doping concentration is 5E+18cm -3 ~2E+19cm -3 .

4. The method for preparing a HBC solar cell according to claim 1, characterized in that: In step S3, the thickness of the silicon oxide mask is 5-15 nm, and the width of the oxidized region is 150-500 μm; In step S6, the thickness of the silicon oxide mask is 5-15 nm, and the width of the oxidized region is 150-500 μm.

5. The method for preparing a HBC solar cell according to claim 1, characterized in that: The reflectivity of the corroded area in step S4 is 35-45%; The size of the tower base in the corroded area is 8-15 μm; The corrosion depth of the corroded area is 0.5-2μm.

6. The method for preparing a HBC solar cell according to claim 1, characterized in that: In step S5, i: the thickness of the a-Si layer is 2-10 nm; The N:a-Si layer includes N:a-Si layer and N-uc-Si layer; wherein The thickness of the N:a-Si layer is 10-20 nm, and the doping concentration is 1E+18 cm -3 ~5E+18cm -3 : The thickness of the N-uc-Si layer is 20-50nm, and the doping concentration is 5E+18cm -3 ~2E+19cm -3 .

7. The method for preparing a HBC solar cell according to claim 1, characterized in that: The reflectivity of the suede surface in step S7 is 9-12%.

8. The method for preparing a HBC solar cell according to claim 1, characterized in that: The doping concentration of the FSF field passivation region in step S8 is 1E+18cm -3 ~1E+19cm -3 ; The thickness of the laminated gradient silicon nitride anti-reflection passivation film is 75nm-105nm, and the refractive index is 1.8-2.2; The TCO transparent conductive film has a thickness of 70nm-150nm and a sheet resistance of 50-120.

9. The method for preparing a HBC solar cell according to claim 1, wherein: The etching in step S9 specifically includes etching the TCO transparent conductive film, N: a-Si layer and N-uc-Si layer at the junction of the P region and the N region on the back of the silicon wafer, and retaining the i: a-Si layer; The width of the etching is 10-50 μm.

10. A HBC solar cell structure prepared by the method according to any one of claims 1 to 9, characterized in that: The front side of the battery is a laminated gradient silicon nitride anti-reflection passivation film, and after P is injected into the front side to prepare the N+ region, a high-low junction field passivation structure of the N+ / FSF layer is formed; The P region on the back of the cell is doped with amorphous silicon to form P-uc-SiO x C y Layering; The back P region of the battery has a low-reflection alkali-powder-based morphology, and the N region has a high-reflection alkali-powder-based morphology.

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