HBC solar cell structure and amorphous-damage-free preparation method thereof

Abstract

The invention belongs to the technical field of crystalline silicon solar cells, and particularly relates to an HBC solar cell structure and an amorphous-damage-free preparation method thereof, and the method comprises the following steps: S1, carrying out the double-side polishing of a silicon wafer; s2, depositing an i: a-Si layer, a P: a-Si layer, a high-work-function TCO layer and an i: a-Si mask layer on the back surface of the silicon wafer from top to bottom; s3, carrying out laser oxidation on a P region on the back surface of the silicon wafer; s4, carrying out wet cleaning on the back surface of the silicon wafer; s5, depositing an i: a-Si layer, an N: a-Si layer, a low work function TCO layer and an i: a-Si mask layer on the back surface of the silicon wafer from top to bottom; s6, carrying out laser oxidation on the N region on the back surface of the silicon wafer; s7, cleaning the back surface of the silicon wafer and texturing the front surface of the silicon wafer; s8, preparing an aluminum oxide layer and a silicon nitride layer on the front and back surfaces of the silicon wafer, and filling an isolation region for isolating the interdigital arrangement structure; step S9, performing laser film opening on the back surface of the silicon wafer; and S10, printing metal slurry in the windowing area to complete the preparation of the battery.

Description

Technical Field

[0001] The invention belongs to the technical field of crystalline silicon solar cells, and in particular relates to an HBC solar cell structure and a method for preparing the same without amorphous damage. Background Art

[0002] Photovoltaic power generation is a system that uses solar cells to directly convert sunlight energy into electrical energy based on the principle of the photovoltaic effect. The basic structure of a solar cell is a large-area planar PN junction. When sunlight shines on the PN junction, the PN junction absorbs light energy to excite electrons and holes, and then generates voltage in the PN junction to achieve photoelectric conversion. Therefore, the core structure that realizes the conversion of sunlight energy and electrical energy in crystalline silicon cells is the PN junction.

[0003] As PERC cells gradually approach the limit efficiency of 24.5%, the industry has begun to seek the next generation of crystalline silicon cell technology. The current mainstream technologies are Topcon (tunneling oxide passivation contact), HJT (heterojunction), and IBC (interdigitated back contact). Unlike Topcon and HJT, which improve cell efficiency by changing the passivation method, IBC cells transfer all the cell grid lines to the back, reduce the grid line shading area, increase current density, and increase cell efficiency. IBC cells are platform technologies, which are superimposed with Topcon technology to form TBC and with HJT technology to form HBC.

[0004] However, the preparation process of existing HBC batteries is complicated, and the amorphous interdigitated structures of the N and P regions on the back are particularly difficult and easily damaged. Therefore, how to provide a preparation method for HBC batteries that can reduce damage to the amorphous interdigitated structures is a technical problem that urgently needs to be solved in this field.

[0005] It should be noted that the above information disclosed in this background technology section is only used to understand the background technology of the present application concept, and therefore, the above description is not considered to constitute information of the prior art. Summary of the invention

[0006] The embodiments of the present disclosure at least provide a HBC solar cell structure and a method for preparing the same without amorphous damage.

[0007] In a first aspect, an embodiment of the present disclosure provides a method for preparing an HBC solar cell without amorphous damage, comprising the following steps: step S1, double-sided polishing of a silicon wafer to prepare a clean silicon wafer surface with a lubricating alkali polishing tower base morphology; step S2, depositing a layer of i: a-Si layer on the back side of the silicon wafer from top to bottom, performing HPT cleaning on the deposited surface, and then depositing a P: a-Si layer, a high work function TCO layer and an i: a-Si mask layer from top to bottom in sequence; step S3, laser oxidation of the P region on the back side of the silicon wafer to form a patterned silicon oxide mask on the outside of the outer i: a-Si mask layer; step S4, wet cleaning of the back side of the silicon wafer to remove the patterned silicon oxide mask and the deposited layer in the mask-free area, and etching the silicon base and cleaning the silicon wafer; step S5, depositing a layer of i: a-Si layer on the back side of the silicon wafer from top to bottom, performing HPT cleaning on the deposited surface After T cleaning, N: a-Si layer, low work function TCO layer and i: a-Si mask layer are deposited in sequence from top to bottom; step S6, laser oxidation of the N region on the back of the silicon wafer is performed, and a patterned silicon oxide mask is formed on the outside of the outer i: a-Si mask layer; step S7, cleaning the back of the silicon wafer to expose the TCO layer in the N region and the P region and preparing an isolation finger arrangement structure of an amorphous high work function TCO layer in the P region and an amorphous low work function TCO layer in the N region, and at the same time, the front of the silicon wafer is textured; step S8, aluminum oxide layer and silicon nitride layer are prepared on the front and back of the silicon wafer in sequence, and the isolation area of ​​the isolation finger arrangement structure is filled; step S9, laser film opening is performed on the back of the silicon wafer, and windows are opened locally to expose the high work function TCO layer and the low work function TCO layer; step S10, metal slurry is printed in the window opening area on the back of the silicon wafer and cured by light injection to complete the preparation of the battery.

[0008] In an optional implementation, the reflectivity of the surface of the silicon wafer after polishing in step S1 is 30-45%; and the size of the tower base is 5-15 μm.

[0009] In an optional embodiment, the thickness of the i:a-Si layer in step S2 is 2-10 nm; the P:a-Si layer includes P:a-Si layer and P-uc-SiO x C y Layering; wherein the thickness of the P: a-Si layer is 10-20nm and the doping concentration is 1E+18cm -3 ~5E+18cm -3 :The P-uc-SiO x C y The layer thickness is 20-50nm and the doping concentration is 5E+18cm -3 ~2E+19cm -3; The thickness of the high work function TCO layer is 70-150nm, and the square resistance is 50-120; the target material of the high work function TCO layer includes In2O3 and SnO2 with a mass ratio of (90-95): (5-10); the thickness of the i:a-Si mask layer is 20-40nm.

[0010] In an optional implementation, the thickness of the patterned silicon oxide mask in steps S3 and S6 is 5-15 nm, and the width of the oxidized region is 150-500 μm.

[0011] In an optional implementation, the reflectivity of the corroded area in step S4 is 35-45%; the tower base size of the corroded area is 8-15 μm; and the corrosion depth of the corroded area is 0.5-2 μm.

[0012] In an optional embodiment, the thickness of the i: a-Si layer in step S5 is 2-10 nm; the N: a-Si layer includes a N: a-Si layer and a N-uc-Si layer; wherein the thickness of the N: a-Si layer is 10-20 nm, and the doping concentration is 1E+18 cm -3 ~5E+18cm -3 :The thickness of the N-uc-Si layer is 20-50nm, and the doping concentration is 5E+18cm -3 ~2E+19cm -3 ; The thickness of the low work function TCO layer is 70-150nm, and the square resistance is 50-120; the target material of the low work function TCO layer includes In2O3 and SnO2 with a mass ratio of (95-98): (2-5); the thickness of the i:a-Si mask layer is 20-40nm.

[0013] In an optional implementation, in step S8, the thickness of the aluminum oxide layer is 2-20 nm, and the thickness of the silicon nitride layer is 10-40 nm.

[0014] In an optional implementation, the width of the film opened in step S9 is 10-50 μm.

[0015] In the second aspect, the embodiments of the present disclosure also provide an HBC solar cell structure prepared by the method as described above, wherein the back side of the cell includes an isolation finger arrangement structure of an amorphous high work function TCO layer in the P region and an amorphous low work function TCO layer in the N region, and the isolation area between the P region and the N region is filled with an aluminum oxide layer and a silicon nitride layer.

[0016] In a third aspect, the embodiments of the present disclosure further provide a photovoltaic module, which adopts the HBC solar cell structure as described above.

[0017] The beneficial effect of the present invention is that the HBC solar cell structure and its non-amorphous damage preparation method adopt the process of TCO layer + i: a-Si mask layer + laser oxidation and selective corrosion cleaning, which protects the amorphous TCO layer in the N area and the P area from any direct laser contact and acid-base contact, ensuring that the amorphous silicon is not damaged, greatly improving the upper limit of the battery efficiency, and the isolated interdigitated arrangement structure of the amorphous high work function TCO layer in the P area and the amorphous low work function TCO layer in the N area on the back side also overcomes the problem of matching the work function of the amorphous and TCO in the N area and the P area on the back side of the traditional HBC battery, thereby improving the current and fill factor of the battery and improving the bifaciality.

[0018] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description and the drawings.

[0019] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A process flow chart of a HBC solar cell provided in an embodiment of the present disclosure;

[0022] Figure 2 A schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0023] Figure 3 A process flow chart of a HBC solar cell provided in an embodiment of the present disclosure;

[0024] Figure 4 A schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0025] Figure 5 A schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0026] Figure 6 A process flow chart of a HBC solar cell provided in an embodiment of the present disclosure;

[0027] Figure 7 A schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0028] Figure 8 A process flow chart of a HBC solar cell provided in an embodiment of the present disclosure;

[0029] Fig. 9 A schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0030] Fig.10 A schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0031] Fig.11 A process flow chart of a HBC solar cell provided in an embodiment of the present disclosure;

[0032] Fig.12 A schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0033] Fig.13 A process flow chart of a HBC solar cell provided in an embodiment of the present disclosure;

[0034] Fig.14 A schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0035] Fig.15 A schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0036] Fig.16 A schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] As used herein, the phrases "in one embodiment," "according to one embodiment," "in some embodiments," and the like generally refer to the fact that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure. Therefore, a particular feature, structure, or characteristic may be included in more than one embodiment of the present disclosure, so that these phrases do not necessarily refer to the same embodiment. As used herein, the terms "example," "exemplary," and the like are used to "serve as an example, instance, or illustration." Any implementation, aspect, or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or superior to other implementations, aspects, or designs. On the contrary, the use of the terms "example," "exemplary," and the like is intended to present concepts in a concrete manner.

[0039] Herein, example embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. As used herein, expressions such as "at least one of..." modify the entire list of elements when following a list of elements, rather than modifying individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0040] The terms used herein are only used to describe specific exemplary configurations and are not intended to be limited. As used herein, the singular articles "one", "an" and "the" may also be intended to include plural forms, unless it is clearly indicated above that this is not the case. The terms "include", "comprise" and "have" are inclusive, and therefore specify the presence of features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or combinations thereof. The method steps, processes and operations described herein should not be interpreted as necessarily requiring them to be performed in the specific order discussed or shown, unless specifically identified as an execution order. Additional or alternative steps may be adopted.

[0041] The characteristics of IBC batteries are that there is no electrode on the front of the battery, and the positive and negative electrode grid lines are integrated on the back in a forked shape. The main features of the battery are: 1. Use high minority carrier lifetime silicon wafers to prevent carriers from being recombined before being transmitted to the PN junction; 2. The positive and negative electrodes are integrated on the back, and the grid line pattern morphology has a large design window; 3. The front anti-reflection stacking film & front surface field design maximizes optical utilization and reduces front surface recombination; 4. The back N and P regions are arranged in a forked pattern, the P region (emitter) collects holes, and the N region (back field) captures electrons; 5. Combined with thin film heterojunction (HJT) technology to prepare the N region field electrode and the P region emitter, improve the battery passivation level;

[0042] The advantages of IBC cells are: 1. There is no grid line blocking on the front, the photon absorption level is high, and the current density is high; 2. Combined with HJT technology, the battery current density and efficiency are improved without passivation loss; 3. Both the positive and negative electrodes are on the back, which can increase the grid line width, reduce contact resistance, and improve FF without significant impact on the current; 4. There is no grid line design on the front of the battery, the battery is beautiful, and the BIPV (building integrated photovoltaic) application scenario has obvious advantages;

[0043] The challenges of HBC batteries are: 1. Low bifaciality of the battery (the gate line is integrated on the back side, resulting in an increase in the back side shading area and a large difference in efficiency between the front and back sides); 2. Complex process, multiple steps, expensive equipment, high cost and low yield (the traditional HBC battery preparation process includes: texturing and cleaning--front i: a-Si--front SiNx--back i: a-Si--back P: a-Si--back mask--laser grooving--etching--back i: a-Si--back N: a-Si--laser film opening--etching--back TCO--laser film opening to isolate PN area--printing and curing--light injection); 3. The amorphous interdigitated structure of the back N and P regions is difficult to prepare (it is difficult for the laser to accurately locate the film opening area and film opening depth); 4. HBC batteries have high requirements for silicon wafer quality and front surface body passivation (carriers are separated from the PN junction and need to pass through the front surface and body of the silicon wafer to reach the back. Defects in the front surface of the battery will recombine the carriers before the carriers reach the PN junction).

[0044] Prior art 1: Patent No. CN 115050855 A

[0045] Scheme steps: 1. Double-sided texturing; 2. Back-side polishing; 3. Double-sided deposition of ia:Si; 4. Back-side patterned boron paste printing and drying; 5. Back-side patterned phosphorus paste printing and drying; 6. Laser doping of N-zone and P-zone; 7. Ultrasonic cleaning of slurry with organic water mixed solution; 8. Back-side TCO deposition; 9. Laser grooving to isolate N-zone and P-zone; 10. Front-side deposition of SiO / SiON / SiN stacked films; 11. Screen printing, curing and sintering.

[0046] Concept: 1. From top to bottom: SiN / SiON / SiO---ia: Si---suede surface---silicon base---polished surface---ia: Si---Pa: Si---Na: ​​Si---TCO---silver paste HBC battery structure;

[0047] 2. ia:Si is deposited on the back of the battery, and the boron slurry and phosphorus slurry are cross-printed using a screen. After drying, laser doping, and cleaning, the poly interdigitated arrangement structure of the N and P regions on the back of the battery is completed.

[0048] shortcoming:

[0049] 1. Use doping slurry as the doping source. Due to its special fluidity and corrosiveness, it requires the use of professional scrapers, scrapers, special non-metallic mesh, and non-market mass production auxiliary materials;

[0050] 2. In order to meet the printing requirements, the doping slurry often adds more organic solvents to achieve curing. Organic solvents will affect the diffusion effect of boron and phosphorus doping, and the diffusion uniformity is poor;

[0051] 3. To meet the printing requirements, more organic solvents are often added to the doped slurry, which has a strong odor, requires high ventilation on site, and requires high protective measures for employees;

[0052] 4. It is difficult to control the doping amount and doping depth of amorphous silicon by laser boron-phosphorus slurry, which can easily damage the underlying hydrogenated amorphous silicon and affect the passivation of the battery.

[0053] 5. The ARC anti-reflection film is prepared at a high temperature of >200°C on the front side, which can easily lead to a decrease in the passivation of amorphous silicon;

[0054] 6. The front side adopts the anti-reflection passivation film design of SiNx+ia:Si, which has large parasitic absorption and large battery current loss;

[0055] 7. In this process, amorphous silicon is exposed for a long time without a protective film, which affects the passivation of the battery.

[0056] Prior art 2: CN 218849510 U

[0057] Scheme steps: 1. Cleaning and texturing; 2. Preparation of silicon oxide and intrinsic amorphous silicon on the back; 3. High-temperature phosphorus diffusion, crystallization of the amorphous on the back into phosphorus-doped polysilicon; 4. Laser etching; 5. Poly cleaning, de-plating and expansion, alkali polishing and cleaning of the laser ablation area until the N-type silicon base is washed; 6. Intrinsic amorphous silicon deposition on the front; 7. Preparation of silicon nitride on the front; 8. Preparation of intrinsic amorphous silicon and P:a-Si by back mask-grooving-deposition-etching technology; 9. Preparation of TCO by back mask-grooving-deposition-etching technology; 10. Screen electrode printing and curing.

[0058] concept:

[0059] The back N-region and P-region are prepared by the traditional mask-groove-deposition-etching method, and the N-region adopts the polo passivation contact structure of SiO and N+poly to replace the i:a-Si+N:a:Si battery structure.

[0060] shortcoming:

[0061] 1. The front side adopts the anti-reflection passivation film design of SiNx+ia:Si, which has large parasitic absorption and large battery current loss;

[0062] 2. The H passivation effect of the polo passivation contact structure interface of SiO and N+poly in the back N region is poor;

[0063] 3. The N+poly preparation of the back N region uses high-temperature tubular equipment, which involves wrapping, expansion and plating.

[0064] The defects existing in the above solutions are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the present disclosure for the above problems below should be the contributions made by the inventor to the present disclosure during the disclosure process.

[0065] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0066] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0067] Step S1, double-sided polishing of the silicon wafer to prepare a smooth alkali polishing tower base morphology and a clean silicon wafer surface, please refer to Figure 1 The process flow shown in Figure 2 The specific process of the silicon wafer shown is as follows:

[0068] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-15%) to clean the surface of the silicon wafer to remove dirt on the surface of the silicon wafer. The process temperature is 55℃-70℃ and the process time is 2min-5min.

[0069] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0070] A mixed solution of potassium hydroxide (1%-10%) and additives (0.5%-5%) is used to polish the surface of the silicon wafer to form an alkali polishing tower base morphology and remove cutting damage. The process temperature is 60℃-85℃ and the process time is (3min-5min).

[0071] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0072] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the surface of the silicon wafer to remove additive residues. The process temperature is 55℃-70℃ and the process time is 2min-5min.

[0073] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0074] A mixed solution of hydrofluoric acid (0.1%-2%), hydrochloric acid (0.1%-2%) and O3 (10ppm-50ppm) is used to clean the surface of the silicon wafer. At the same time, the weak etching system of O3 and HF lubricates the surface of the silicon wafer, reduces burr defects on the surface of the silicon wafer, and is more conducive to the passivation of amorphous silicon. The process temperature is 15℃-25℃, and the process time is 2min-3min.

[0075] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0076] The surface of the silicon wafer is cleaned with a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%), the process temperature is room temperature, and the process time is 3min-5min;

[0077] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0078] Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃.

[0079] Place the silicon wafer in a drying tank, purge at high temperature to dry the surface of the silicon wafer. Purge gas: nitrogen or compressed air, temperature: 80℃-100℃, drying time: 5min-15min;

[0080] Wafer weight reduction: 0.3g-0.6g; (taking 182.2 size wafer as an example)

[0081] Surface reflectivity: 30%-45%;

[0082] Tower base size: 5um-15um.

[0083] Step S2, ia:Si / Pa:Si / high work function TCO-1 / ia:Si mask deposition on the back of silicon wafer, please refer to Figure 3 The process flow shown in Figure 4 The specific process of the silicon wafer shown is as follows:

[0084] The flat-plate PECVD method is used to deposit a layer of ia:Si from top to bottom on the back of the double-sided alkaline polished silicon wafer, and then the deposited surface is cleaned by HPT (H ion cleaning), and then the flat-plate PECVD method is used to deposit Pa:Si on the back of the silicon wafer from top to bottom. The deposition includes (a layer of Pa:Si, a layer of P-uc-SiO x C y ), then a layer of TCO is deposited on the back of the silicon wafer from top to bottom by a flat-plate PVD method, and finally a layer of ia:Si is deposited on the back of the silicon wafer by a flat-plate PECVD method;

[0085] After double-sided alkaline polishing, the silicon wafer is placed on a hollow carrier plate, gate valve 1 is opened, and the wafer is transferred into the loading chamber 1 for evacuation, gate valve 2 is opened, and the wafer is transferred into the buffer preheating chamber 1, and then transferred into the PECVD1 reaction chamber 1 to deposit ia:Si from top to bottom, and then transferred into the buffer HPT cleaning chamber 2, where H ions are used to clean the deposited surface, completing the preparation of ia:Si;

[0086] Open gate valve 3, transfer the carrier into transition chamber 1 (evacuate gas for isolation), open gate valve 4, first transfer to buffer 3, then transfer to PECVD2 reaction chamber 2 to deposit a layer of Pa:Si and a layer of P-uc-SiOxCy from top to bottom, and then transfer to buffer 4 to complete the preparation of Pa:Si;

[0087] Open gate valve 5, transfer the carrier to transition chamber 2 (evacuate gas for isolation), open gate valve 6, transfer to buffer 5 (secondary isolation), transfer to PVD1 reaction chamber 3 to deposit a layer of TCO from top to bottom, and then transfer to buffer 6 to complete TCO preparation;

[0088] Open the gate valve 7, transfer the carrier to the transition chamber 3 first, open the gate valve 8, transfer it to the buffer chamber 7, and then transfer it to the PECVD3 reaction chamber 4, deposit a layer of ia:Si mask from top to bottom, and finally transfer it to the buffer chamber 8 to complete the preparation of ia:Si mask;

[0089] Open the gate valve 9, transfer the carrier to the unloading chamber 1, use nitrogen to backfill the atmosphere, open the gate valve 10, and transfer the carrier out of the chamber;

[0090] PECVD1 reaction chamber 1: ia:Si is prepared by PECVD method, with SiH4 and H2 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2 flow ratio: 1:10-1:30, power: 50W-300W;

[0091] PECVD2 reaction chamber 2: Pa:Si is prepared by PECVD method. Pa:Si is divided into two layers: conventional B-doped amorphous silicon (Pa:Si), B-doped microcrystalline carbon oxide silicon (P-uc-SiO x C y );

[0092] Conventional B-doped amorphous silicon (Pa:Si) is prepared with SiH4, H2, and B2H6 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2:B2H6 (2%) flow ratio: 1:20:5-1:30:15, power: 50W-300W;

[0093] Preparation of B-doped microcrystalline silicon oxide (P-uc-SiOxCy), using SiH4, H2, B2H6, CO2, TMB as process gases, process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, SiH4:H2:B2H6 (2%) flow ratio: 1:30:10-1:60:30, CO2 and TMB as micro-doping gas flow: 5sccm-20sccm, power: 300w-500W;

[0094] HPT cleaning buffer chamber 2: PECVD method is used to ionize H to clean the deposited surface of the silicon wafer, with H2 as the process gas.

[0095] Process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, power: 50W-400W;

[0096] PVD1 reaction chamber 3: When the P-zone TCO-1 is prepared by PVD method, a high work function ITO target (In2O3 / SnO2 mass ratio: 90:10-95:5) is used, and argon and oxygen are used as working gases, process temperature: 100-250°C, process pressure: 0.2Pa-2Pa, Ar / O2 flow ratio: 200:1-100:1, power: 5000W-40000W;

[0097] PECVD3 reaction chamber 4: ia: Si mask is prepared by PECVD method, SiH4 and H2 are used as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2 flow ratio: 1:10-1:30, power: 50W-300W;

[0098] i: a-Si thickness: 2nm-10nm, freely adjustable;

[0099] P: a-Si thickness: 10nm-20nm, P-uc-SiO x C y Thickness: 20nm-50nm, thickness can be freely adjusted;

[0100] P: a-Si doping concentration: 1E+18cm -3 ~5E+18cm -3 :P-uc-SiO x C y Doping concentration: 5E+18cm -3 ~2E+19cm -3 , the doping amount can be freely adjusted;

[0101] i: a-Si mask thickness: 20nm-40nm, freely adjustable;

[0102] P zone TCO thickness: 70nm-150nm;

[0103] P-zone TCO square resistance: 50-120;

[0104] The material ratio of ITO target used in P zone TCO-1: high work function ITO target (In2O3 / SnO2 mass ratio: 90:10-95:5).

[0105] Specifically, the vacuum blocking technology of "transition-isolation-coating-isolation" is adopted to meet the process pressure of different film layer preparations, and avoid process abnormalities caused by "cross-gas" between process gases of different film layer preparations. A single machine can meet the preparation of different film layers, combining i: a-Si deposition & P: a-Si deposition & HPT cleaning & TCO deposition & i: a-Si mask deposition into one;

[0106] Specifically, the function of the transition chamber is to adjust the pressure to meet the switching of different process pressure conditions / block the gas medium of different process chambers.

[0107] Specifically, the function of the buffer chamber is to provide secondary isolation and blocking of different gas media.

[0108] Step S3, laser oxidation of the back P region to prepare a patterned mask, Figure 5 The specific process of the silicon wafer shown is as follows:

[0109] Laser-induced oxidation technology is used to form a patterned silicon oxide mask on the surface of the a-Si mask in the P region on the back of the silicon wafer. The battery is placed on a horizontal platform, the silicon wafer is positioned by a camera, and an ultraviolet picosecond laser is used to locally oxidize the amorphous silicon to prepare a patterned silicon oxide mask.

[0110] Laser power: 10w-30w;

[0111] Silicon oxide mask: thickness: 5nm-15nm, oxidation area width: 150um-500um, can be freely adjusted.

[0112] Step S4, wet cleaning, removing the i: a-Si mask / TCO-1 / P: a-Si / P-uc-SiO2 mask-free area x C y / i: a-Si and corrode the silicon base to a certain depth, and deeply clean the silicon wafer at the same time, please refer to Figure 6 The process flow shown in Figure 7 The specific process of the silicon wafer shown is as follows:

[0113] Use potassium hydroxide (1%-10%) solution for cleaning, and potassium hydroxide corrodes the back side without SiO2 mask area i: a-Si mask, process temperature: 55℃-70℃, process time: 0.5min-1.5min;

[0114] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0115] Use hydrochloric acid (1%-10%) solution to clean the silicon wafer surface to remove alkali residue and TCO-1 in the unmasked area; process temperature: room temperature, process time: 3min-5min;

[0116] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0117] Use a mixed solution of H2O:HCl:H2O2-4:1:1-6:1:1 to deeply clean the surface of the silicon wafer and remove the metal ion residues produced by the dissolution of TCO-1; process temperature: 60℃-85℃, cleaning time: 5min-10min;

[0118] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0119] Use potassium hydroxide (1%-10%) and alkaline polishing additive (0.5%-5%) mixed solution for cleaning, potassium hydroxide corrodes the back unmasked area i: a-Si / P: a-Si / P-uc-SiO x C y , and corrode to a certain depth, process temperature: 55℃-70℃, process time: 0.5min-1.5min;

[0120] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0121] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the surface of the silicon wafer to remove additive residues. The process temperature is 55℃-70℃ and the process time is 2min-5min.

[0122] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0123] Use hydrofluoric acid (1%-10%) solution to clean the silicon wafer surface to remove alkali residues and silicon oxide mask; process temperature: room temperature, process time: 3min-5min;

[0124] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0125] Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃.

[0126] Place the silicon wafer in a drying tank, purge at high temperature to dry the surface of the silicon wafer. Purge gas: nitrogen or compressed air, temperature: 80℃-100℃, drying time: 5min-15min;

[0127] Cleaning method: The silicon wafer enters the solution vertically, the direction of the silicon wafer laser line is perpendicular to the solution surface, and the detachment of drug residues on the silicon wafer surface is not affected by the morphology of the back groove;

[0128] Cleaning method: The silicon wafer enters the solution vertically, the direction of the silicon wafer laser line is perpendicular to the solution surface, and the detachment of drug residues on the silicon wafer surface is not affected by the morphology of the back groove;

[0129] By utilizing the selective corrosion of TCO to HCl and HF, TCO is soluble in HCl but insoluble in HF, and a P-region amorphous + high-function TCO-1 / N-region amorphous + low-function TCO-2 interdigital arrangement structure is prepared;

[0130] Reflectivity of corroded area: 35%-45%;

[0131] The size of the tower base in the corroded area: 8um-15um;

[0132] Corrosion depth of corroded area: 0.5um-2um.

[0133] Step S5, ia:Si / Na:Si / N-uc-Si / low work function TCO-2 / ia:Si mask deposition on the back of silicon wafer, please refer to Figure 8 The process flow shown in Fig. 9 The specific process of the silicon wafer shown is as follows:

[0134] A layer of ia:Si is first deposited from top to bottom on the back of the cleaned silicon wafer by a flat-plate PECVD method, and then the deposited surface is cleaned by HPT (H ion cleaning), and then a layer of Na:Si is first deposited from top to bottom on the back of the silicon wafer by a flat-plate PECVD method (a layer of Na:Si and a layer of N-uc-Si), and then a layer of TCO is deposited from top to bottom on the back of the silicon wafer by a flat-plate PVD method, and finally a layer of ia:Si is deposited on the back of the silicon wafer by a flat-plate PECVD method;

[0135] After double-sided alkaline polishing, the silicon wafer is placed on a hollow carrier plate, the gate valve 11 is opened, and the wafer is transferred into the loading chamber 2 to be evacuated, the gate valve 12 is opened, and the wafer is transferred into the buffer preheating chamber 9, and then transferred to the PECVD4 reaction chamber 5 to deposit ia:Si from top to bottom, and then transferred to the buffer HPT cleaning chamber 10, where H ions clean the deposited surface to complete the ia:Si preparation;

[0136] Open the gate valve 13, transfer the carrier into the transition chamber 4 (evacuate the gas for isolation), open the gate valve 14, first transfer to the buffer 11, then transfer to the PECVD5 reaction chamber 6 to deposit a layer of Na:Si and a layer of N-uc-Si from top to bottom, and then transfer to the buffer 12 to complete the preparation of Pa:Si;

[0137] Open the gate valve 15, transfer the carrier to the transition chamber 5 (evacuate gas isolation), open the gate valve 16, transfer to the buffer 13 (secondary isolation), transfer to the PVD2 reaction chamber 7 to deposit a layer of TCO from top to bottom, and then transfer to the buffer 14 to complete the TCO preparation;

[0138] Open the gate valve 17, transfer the carrier to the transition chamber 6 first, open the gate valve 18, transfer it to the buffer chamber 15, and then transfer it to the PECVD6 reaction chamber 8, deposit a layer of ia:Si mask from top to bottom, and finally transfer it to the buffer chamber 16 to complete the preparation of ia:Si mask;

[0139] Open the gate valve 19, transfer the carrier to the unloading chamber 2, use nitrogen to backfill the atmosphere, open the gate valve 20, and transfer the carrier out of the chamber;

[0140] PECVD4 reaction chamber 5: ia:Si is prepared by PECVD method, with SiH4 and H2 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2 flow ratio: 1:10-1:30, power: 50W-300W;

[0141] PECVD5 reaction chamber 6: Na:Si is prepared by PECVD method. Na:Si is divided into two layers: conventional P-doped amorphous silicon (Na:Si) and P-doped microcrystalline silicon (N-uc-Si);

[0142] Conventional P-doped amorphous silicon (Na:Si) is prepared with SiH4, H2, and PH3 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2:PH3 (2%) flow ratio: 1:20:5-1:30:15, power: 50W-300W;

[0143] Preparation of P-doped microcrystalline silicon (N-uc-Si), using SiH4, H2, PH3 as process gases, process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, SiH4:H2:PH3 (2%) flow ratio: 1:30:10-1:60:30, power: 300w-500W;

[0144] HPT cleaning buffer chamber 10: PECVD method is used to ionize H to clean the deposited surface of the silicon wafer, with H2 as the process gas.

[0145] Process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, power: 50W-400W;

[0146] PVD1 reaction chamber 3: When the N-zone TCO-2 is prepared by PVD method, a low work function ITO target (In2O3 / SnO2 mass ratio: 97:3) is used, and argon and oxygen are used as working gases, process temperature: 100-250°C, process pressure: 0.2Pa-2Pa, Ar / O2 flow ratio: 200:1-100:1, power: 5000W-40000W;

[0147] PECVD6 reaction chamber 8: ia: Si mask is prepared by PECVD method, SiH4 and H2 are used as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2 flow ratio: 1:10-1:30, power: 50W-300W;

[0148] i: a-Si thickness: 2nm-10nm, freely adjustable;

[0149] N: a-Si thickness: 10nm-20nm, N-uc-Si thickness: 20nm-50nm, thickness can be freely adjusted;

[0150] N: a-Si doping concentration: 1E+18cm -3 ~5E+18cm -3 ,N-uc-Si doping concentration: 5E+18cm -3 ~2E+19cm -3 , the doping amount can be freely adjusted;

[0151] i: a-Si mask thickness: 20nm-40nm, freely adjustable;

[0152] P zone TCO thickness: 70nm-150nm;

[0153] P-zone TCO square resistance: 50-120;

[0154] Material ratio of ITO target for TCO-2 in P zone: low work function ITO target (In2O3 / SnO2 mass ratio: 97:3).

[0155] Step S6, laser oxidation of the back N region to prepare a patterned mask, Fig.10 The specific process of the silicon wafer shown is as follows:

[0156] Laser-induced oxidation technology is used to form a patterned silicon oxide mask on the surface of the a-Si mask in the N region on the back of the silicon wafer. The battery is placed on a horizontal platform, the camera positions the silicon wafer, and an ultraviolet picosecond laser is used to locally oxidize the amorphous silicon to prepare a patterned silicon oxide mask.

[0157] Laser power: 10w-30w;

[0158] Silicon oxide mask: thickness: 5nm-15nm, oxidation area width: 150um-500um, can be freely adjusted.

[0159] Step S7, back side SiO2 mask free area i: a-Si mask / low work function TCO-2 removal, back side SiO2 mask removal, front side texturing, back side i: a-Si mask removal, preparation of P area amorphous + high work function TCO-1 / N area amorphous + low work function TCO-2 isolation interdigital arrangement structure, please refer to Fig.11 The process flow shown in Fig.12 The specific process of the silicon wafer shown is as follows:

[0160] Use potassium hydroxide (1%-10%) solution for cleaning, and potassium hydroxide corrodes the back side without SiO2 mask area i: a-Si mask, process temperature: 55℃-70℃, process time: 0.5min-1.5min;

[0161] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0162] Use hydrochloric acid (1%-10%) solution to clean the silicon wafer surface to remove alkali residue and TCO-2 in the unmasked area; process temperature: room temperature, process time: 3min-5min;

[0163] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0164] Use a mixed solution of H2O:HCl:H2O2-4:1:1-6:1:1 to deeply clean the surface of the silicon wafer and remove the metal ion residues produced by the dissolution of TCO-12; process temperature: 60℃-85℃, cleaning time: 5min-10min;

[0165] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0166] Use hydrofluoric acid (1%-10%) solution to clean the silicon wafer surface and remove the silicon oxide mask; process temperature: room temperature, process time: 3min-5min;

[0167] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0168] A mixed solution of potassium hydroxide (1%-10%) and a texturing additive (0.5%-5%) is used for cleaning to form a pyramid texturing morphology on the front side of the silicon wafer, while removing the i:a-Si mask on the back side, and forming an isolated interdigital arrangement structure of amorphous P-region + high work function TCO-1 / amorphous N-region + low work function TCO-2; process temperature: 55℃-70℃, process time: 0.5min-1.5min;

[0169] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0170] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the surface of the silicon wafer to remove additive residues. The process temperature is 55℃-70℃ and the process time is 2min-5min.

[0171] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0172] Use hydrofluoric acid (1%-10%) solution to clean the silicon wafer surface to remove alkali residue; process temperature: room temperature, process time: 3min-5min;

[0173] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0174] Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃.

[0175] Place the silicon wafer in a drying tank, purge at high temperature to dry the surface of the silicon wafer. Purge gas: nitrogen or compressed air, temperature: 80℃-100℃, drying time: 5min-15min;

[0176] Cleaning method: The silicon wafer enters the solution vertically, the direction of the silicon wafer laser line is perpendicular to the solution surface, and the detachment of drug residues on the silicon wafer surface is not affected by the morphology of the back groove;

[0177] Cleaning method: The silicon wafer enters the solution vertically, the direction of the silicon wafer laser line is perpendicular to the solution surface, and the detachment of drug residues on the silicon wafer surface is not affected by the morphology of the back groove;

[0178] By utilizing the fact that TCO is selectively corroded by HCl and HF, TCO dissolves in HCl but is insoluble in HF, and an isolated interdigitated arrangement structure of amorphous P region + high work function TCO-1 / amorphous N region + low work function TCO-2 is prepared.

[0179] Step S8, prepare aluminum oxide silicon nitride passivation anti-reflection film on the front and back of the silicon wafer, and fill the aluminum oxide silicon nitride insulation material in the P region amorphous + high work function TCO-1 / N region amorphous + low work function TCO-2 interdigital arrangement structure isolation area, please refer to Fig.13 The process flow shown in Fig.14 The specific process of the silicon wafer shown is as follows:

[0180] First, a layer of aluminum oxide is deposited on the front of the silicon wafer by using a flat plate or tubular ALD or plate PECVD method, and then a layer of front and back deposited silicon nitride stacked gradient film is deposited on the front and back of the silicon wafer by using a flat plate PECVD method, and the P region amorphous + high work function TCO-1 / N region amorphous + low work function TCO-2 interdigital arrangement structure isolation area is filled with aluminum oxide silicon nitride insulation material;

[0181] After cleaning, the silicon wafer is placed on a hollow carrier with the front side facing upwards, the gate valve 21 is opened, the carrier is transferred to the preheating loading chamber 3 for evacuation and preheating, the gate valve 22 is opened, the carrier is transferred to the PECVD 7 reaction chamber 9, and a layer of aluminum oxide is deposited from top to bottom on the front side and from top to bottom on the back side by PECVD method to complete the aluminum oxide preparation;

[0182] Open the gate valve 23, transfer the carrier to the transition chamber 7 first, evacuate (evacuate gas for isolation), open the gate valve 24, transfer to the buffer chamber 18, and then transfer to the PECVD8 reaction chamber 10, deposit a layer of high H content SiNx from top to bottom on the front side, a layer of high Si content SiNx, a layer of high N content SiNx from bottom to top on the back side, and then transfer to the buffer chamber 11 to complete the preparation of double-sided laminated gradient silicon nitride anti-reflection passivation film;

[0183] Open the gate valve 25, transfer the carrier to the unloading chamber 3, use nitrogen to backfill the atmosphere, open the gate valve 26, and transfer the carrier out of the chamber;

[0184] PECVD7 reaction chamber 9: Alumina is prepared by PECVD, with trimethylaluminum and laughing gas as working gases, process temperature: 150℃-250℃, process pressure: 20Pa-50Pa, trimethylaluminum / laughing gas flow ratio: 1:1-3:1, power: 100W-500W;

[0185] PECVD8 reaction chamber 10: SiNx laminated gradient passivation anti-reflection film is prepared by PECVD method, which is divided into three layers;

[0186] SiNx-1: SiH4, H2, and NH3 are used as process gases, and high H2 ratio, high pressure, and high power are used to prepare high H content silicon nitride and passivate the silicon wafer interface. The process temperature is 100℃-250℃, the process pressure is 80Pa-120Pa, and the SiH4 / NH3 / H2 flow ratio is 1:1:6-2:2:20; power is 200W-300W;

[0187] SiNx-2: SiH4 and NH3 are used as process gases, and high Si content and high density silicon nitride are prepared at low pressure and low power with high SiH4 ratio to protect high H content silicon nitride. At the same time, low power coating reduces SiNx-1 passivation damage. Process temperature: 100℃-250℃, process pressure: 30Pa-50Pa, SiH4 / NH3 flow ratio: 2:1-6:1;

[0188] SiNx-3: SiH4 and NH3 are used as process gases, and high NH3 ratio, low pressure and low power are used to prepare high N content silicon nitride, reduce the overall film refractive index, reduce the front reflectivity of the battery, and increase the current density. The process temperature is 100℃-250℃, the process pressure is 30Pa-50Pa, and the SiH4 / NH3 flow ratio is 1:2-1:6;

[0189] Alumina thickness: 2nm-20nm;

[0190] Silicon nitride thickness: 10nm-40nm.

[0191] Step S9, laser film opening, partially opening the N-region and P-region aluminum oxide and silicon nitride to expose TCO, and obtaining Fig.15 The specific process of the silicon wafer shown is as follows:

[0192] Laser film opening technology is used to partially open the N-zone and P-zone aluminum oxide and silicon nitride to expose the TCO. The battery is placed on a horizontal platform, the camera locates the silicon wafer, and an ultraviolet picosecond laser is used to partially pattern the aluminum oxide and silicon nitride film.

[0193] Laser power: 10w-30w;

[0194] Film opening width: 10um-50um.

[0195] Step S10, screen printing curing light injection, to obtain Fig.16 The specific process of the silicon wafer shown is as follows:

[0196] Print metal paste in the window area of ​​the N and P areas on the back side;

[0197] After printing, the silicon wafer is transferred to a curing oven, dried and cured to form an ohmic contact with the TCO;

[0198] The battery is transferred to the annealing furnace, where annealing light is injected to excite H and improve passivation;

[0199] Complete HBC battery preparation.

[0200] In summary, the HBC solar cell structure and its damage-free amorphous preparation method adopt the process of TCO layer + i: a-Si mask layer + laser oxidation and selective corrosion cleaning, which protects the amorphous TCO layer in the N area and the P area from any direct laser contact and acid-base contact, ensuring that the amorphous silicon is not damaged, greatly improving the upper limit of the battery efficiency, and the isolated interdigitated arrangement structure of the amorphous high work function TCO layer in the P area and the amorphous low work function TCO layer in the N area on the back also overcomes the problem of matching the work function of the amorphous and TCO in the N area and the P area on the back of the traditional HBC battery, thereby improving the current and fill factor of the battery and improving the bifaciality.

[0201] Based on the above ideal embodiments of the present invention, the relevant staff can make various changes and modifications without departing from the technical concept of the present invention through the above description. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A method for preparing a HBC solar cell without amorphous damage, characterized in that: The steps include: Step S1, double-sided polishing of the silicon wafer to prepare a clean silicon wafer surface with a lubricating alkali polishing tower base morphology; Step S2, depositing an i: a-Si layer from top to bottom on the back side of the silicon wafer, performing HPT cleaning on the deposited surface, and then depositing a P: a-Si layer, a high work function TCO layer and an i: a-Si mask layer from top to bottom in sequence; Step S3, laser oxidation of the back P region of the silicon wafer to form a patterned silicon oxide mask outside the outer i:a-Si mask layer; Step S4, wet cleaning the back side of the silicon wafer to remove the patterned silicon oxide mask and the deposited layer in the mask-free area, and to etch the silicon base and clean the silicon wafer; Step S5, depositing an i:a-Si layer from top to bottom on the back side of the silicon wafer, performing HPT cleaning on the deposited surface, and then depositing an N:a-Si layer, a low work function TCO layer and an i:a-Si mask layer from top to bottom in sequence; Step S6, laser oxidizing the N region on the back side of the silicon wafer to form a patterned silicon oxide mask outside the outer i:a-Si mask layer; Step S7, cleaning the back side of the silicon wafer to expose the TCO layers in the N region and the P region and preparing an isolated interdigitated arrangement structure of the amorphous high work function TCO layer in the P region and the amorphous low work function TCO layer in the N region, and texturing the front side of the silicon wafer at the same time; Step S8, preparing an aluminum oxide layer and a silicon nitride layer on the front and back sides of the silicon wafer in sequence, and filling the isolation area of ​​the isolation interdigital arrangement structure; Step S9, performing laser film opening on the back side of the silicon wafer, partially opening windows to expose the high work function TCO layer and the low work function TCO layer; Step S10, printing metal paste on the window area on the back side of the silicon wafer, curing and light injection, and completing the preparation of the battery.

2. The preparation method according to claim 1, characterized in that The reflectivity of the surface of the silicon wafer after polishing in step S1 is 30-45%; The size of the tower base is 5-15μm.

3. The preparation method according to claim 1, characterized in that: In step S2 The thickness of the i:a-Si layer is 2-10 nm; The P:a-Si layer includes a P:a-Si layer and a P-uc-SiO x C y Layering; in The thickness of the P:a-Si layer is 10-20nm, and the doping concentration is 1E+18cm -3 ~5E+18cm -3 : The P-uc-SiO x C y The layer thickness is 20-50nm and the doping concentration is 5E+18cm -3 ~2E+19cm -3 ; The high work function TCO layer has a thickness of 70-150 nm and a sheet resistance of 50-120 nm; The target material of the high work function TCO layer includes In2O3 and SnO2 in a mass ratio of (90-95):(5-10); The thickness of the i:a-Si mask layer is 20-40 nm.

4. The preparation method according to claim 1, characterized in that: In steps S3 and S6 The thickness of the patterned silicon oxide mask is 5-15 nm, and the width of the oxidized region is 150-500 μm.

5. The preparation method according to claim 1, characterized in that: In step S4 The reflectivity of the corroded area is 35-45%; The size of the tower base in the corroded area is 8-15 μm; The corrosion depth of the corroded area is 0.5-2μm.

6. The preparation method according to claim 1, characterized in that: In step S5 The thickness of the i:a-Si layer is 2-10 nm; The N:a-Si layer includes N:a-Si layer and N-uc-Si layer; wherein The thickness of the N:a-Si layer is 10-20 nm, and the doping concentration is 1E+18 cm -3 ~5E+18cm -3 : The thickness of the N-uc-Si layer is 20-50nm, and the doping concentration is 5E+18cm -3 ~2E+19cm -3 ; The low work function TCO layer has a thickness of 70-150 nm and a sheet resistance of 50-120 nm; The target material of the low work function TCO layer includes In2O3 and SnO2 in a mass ratio of (95-98): (2-5); The thickness of the i:a-Si mask layer is 20-40 nm.

7. The preparation method according to claim 1, characterized in that: In step S8 The thickness of the aluminum oxide layer is 2-20 nm, and the thickness of the silicon nitride layer is 10-40 nm.

8. The preparation method according to claim 1, characterized in that: In step S9 The width of the film is 10-50 μm.

9. A HBC solar cell structure prepared by the method according to any one of claims 1 to 8, characterized in that: The back side of the battery comprises an isolated interdigitated arrangement structure of a P-region amorphous high work function TCO layer and an N-region amorphous low work function TCO layer, and The isolation area between the P region and the N region is filled with an aluminum oxide layer and a silicon nitride layer.

10. A photovoltaic module, characterized in that: The HBC solar cell structure as claimed in claim 9 is adopted.

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