Selected devices and related products based on insulator-metal transition effect

Abstract

The present disclosure discloses a selection device based on the insulator-metal transition effect and related products thereof. The selection device comprises: a bottom electrode, a selection layer and a top electrode stacked in sequence; wherein the selection layer comprises: a first region and a second region, and the first region is prepared by an annealing process in an oxygen environment. Through the scheme of the embodiment of the present disclosure, the effective area and leakage current of the selection device can be suppressed by the annealing oxidation part of the selection layer, thereby alleviating the problem of large leakage current of the traditional IMT selection device.

Description

Technical Field

[0001] The present disclosure generally relates to the field of semiconductor integrated circuit technology. More specifically, the present disclosure relates to a selection device based on an insulator-metal transition effect, a memory cell, an integrated chip, and a method for preparing the selection device. Background Art

[0002] With the continuous development of emerging science and technologies such as artificial intelligence and cloud computing, the industry's demand for information storage capabilities is increasing. In order to increase the density of memory, the size of semiconductor devices continues to shrink, and high-density memory technology has gradually become a research hotspot and the preferred solution for large-scale storage integration.

[0003] In traditional implementation schemes, new memory is usually used in combination with a selection device. The selection device is a component that provides switching capability and assists in the selection and access of new memory at a specific address in the circuit. A common combination is a new memory and a metal-oxide-semiconductor field-effect transistor (MOSFET), but due to the current density, voltage resistance and device size of MOSFET, this combination will bring greater performance and area constraints to the new memory in actual applications.

[0004] To solve this problem, two-terminal selectors have become an alternative to MOSFETs due to their high current density and small size. Among them, selectors based on the insulator-metal-transition effect (IMT) have the advantages of good material compatibility and high drive current. However, while IMT selectors have the advantage of high drive current, they also have the problem of high leakage current. Figure 3 As shown, common IMT selection devices provide milliampere-level on-state current driving capability, but their leakage current also reaches microampere level, which restricts the actual use of new memory.

[0005] In view of this, there is an urgent need to provide a selection device solution to alleviate the leakage current problem of the selection device, thereby providing a selection device with good selection characteristics to better adapt to the new memory. Summary of the invention

[0006] In order to at least solve one or more of the technical problems mentioned above, the present disclosure proposes a selection device solution based on the insulator-metal transition effect in multiple aspects.

[0007] In a first aspect, the present disclosure provides a selection device based on an insulator-metal transition effect, comprising: a bottom electrode, a selection layer and a top electrode stacked in sequence; wherein the selection layer comprises: a first region and a second region, and the first region is prepared by an annealing process in an oxygen environment.

[0008] In some embodiments, the selection device further includes: a barrier layer, which is disposed between the selection layer and the top electrode; the barrier layer includes: a third region and a fourth region, and the third region is formed by an annealing process in an oxygen environment.

[0009] In some embodiments, the first region is located outside the second region, and the first region located on a single side of the second region includes at least a first part, and the top surface of the first part at least partially overlaps with the top surface of the selection layer; if the minimum width of the top surface of the selection layer is greater than or equal to 40nm, the width d1 of the first part is between 3nm and 5nm; if the minimum width of the top surface of the selection layer is less than 40nm, the width d1 of the first part is between 2nm and (0.125×CD1)nm, wherein CD1 is the minimum width of the top surface of the selection layer.

[0010] In some embodiments, the third region is located outside the fourth region, and the third region located on a single side of the fourth region includes at least a second part, and the top surface of the second part at least partially overlaps with the top surface of the barrier layer; if the minimum width of the top surface of the barrier layer is greater than or equal to 40nm, the width d2 of the second part is between 3nm and 5nm; if the minimum width of the top surface of the barrier layer is less than 40nm, the width d2 of the second part is between 2nm and (0.125×CD2)nm, wherein CD2 is the minimum width of the top surface of the barrier layer.

[0011] In some embodiments, the barrier layer is made of a first metal oxide insulator, the selection layer is made of a second metal oxide, and the second metal in the second metal oxide includes a VB group element.

[0012] In some embodiments, in the annealing process, the annealing temperature is between 200° C. and 600° C., and the annealing time is between 1 min and 60 min.

[0013] In some embodiments, the band gap provided by the barrier layer is greater than 3 eV, and the contact resistivity between the first metal oxide insulator and the second metal oxide is greater than 10 mΩ·cm.

[0014] In some embodiments, the material of the top electrode is more difficult to oxidize than the material of the selection layer.

[0015] In some embodiments, the material used for the top electrode includes titanium nitride or tantalum nitride.

[0016] In some embodiments, the work function of the material used for the bottom electrode is greater than 4.5 eV, and the electrode potential is greater than 0.4V.

[0017] In some embodiments, the thickness of the selection layer is between 10 nm and 50 nm.

[0018] In a second aspect, the present disclosure provides a storage unit comprising: a selection device as in any one of the first aspects; and a memory connected in series to the selection device.

[0019] In some embodiments, the operating voltage of the memory is positively correlated with the thickness of the selection layer in the selection device.

[0020] In a third aspect, the present disclosure provides an integrated chip, comprising: a storage unit as in any one of the second aspect.

[0021] In a fourth aspect, the present disclosure provides a method for preparing a selection device, including: preparing a semi-finished device, the semi-finished device including a bottom electrode and a selection layer stacked in sequence; annealing the semi-finished device in an oxygen environment so that the selection layer forms a first region oxidized by the annealing process; and subsequently preparing the annealed semi-finished device to obtain a selection device.

[0022] In some embodiments, the semi-finished device also includes: a barrier layer stacked on the selection layer; after preparing the semi-finished device, the preparation method also includes: annealing the semi-finished device in an oxygen environment so that the barrier layer forms a third region oxidized by the annealing process; subsequent preparation of the annealed semi-finished device includes: preparing a top electrode on the barrier layer.

[0023] In some embodiments, the semi-finished device also includes a barrier layer and a top electrode, the barrier layer is stacked on the selection layer, and the top electrode is stacked on the barrier layer; after preparing the semi-finished device, the preparation method also includes: annealing the semi-finished device in an oxygen environment so that the barrier layer forms a third region oxidized by the annealing process; subsequent preparation of the annealed semi-finished device includes: insulating the annealed semi-finished device.

[0024] In some embodiments, annealing the semi-finished device in an oxygen environment includes: controlling the annealing temperature between 200°C and 600°C, and annealing the semi-finished device in the oxygen environment for a preset annealing time, wherein the preset annealing time is between 1 min and 60 min.

[0025] The disclosed embodiment provides a selection device based on the insulator-metal transition effect, which performs an annealing process on the selection layer in the selection device in an oxygen environment, so that the effective area and leakage current of the selection device are suppressed by the annealed oxidation part of the selection layer, and then a current suppression effect is formed under the joint action of the selection layer and the annealing process, thereby alleviating the problem of large leakage current of traditional IMT selection devices and improving the application range of IMT selection devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0027] Figure 1 A schematic diagram of the structure of an existing novel memory and MOSFET combination is shown;

[0028] Figure 2 A schematic diagram showing the structure of a combination of an existing novel memory and an IMT selection device is shown;

[0029] Figure 3 A current-voltage characteristic curve of an existing IMT selection device is shown;

[0030] Figure 4 An exemplary structural diagram of a selection device based on an insulator-metal transition effect according to an embodiment of the present disclosure is shown;

[0031] Figure 5 An exemplary structural diagram of a selection device based on an insulator-metal transition effect according to some embodiments of the present disclosure is shown;

[0032] Figure 6 A current-voltage characteristic curve of a selection device based on an insulator-metal transition effect according to an embodiment of the present disclosure is shown;

[0033] Figure 7 An exemplary structural diagram showing a selection device based on an insulator-metal transition effect according to some other embodiments of the present disclosure;

[0034] Figure 8 An exemplary structural diagram showing a selection device based on an insulator-metal transition effect according to some other embodiments of the present disclosure;

[0035] Fig. 9 An exemplary flow chart showing a method for preparing a selection device according to some embodiments of the present disclosure;

[0036] Fig.10An exemplary flow chart showing a method for preparing a selection device according to other embodiments of the present disclosure;

[0037] Fig.11 A schematic diagram showing the preparation process of the selection device of other embodiments of the present disclosure is shown;

[0038] Fig.12 A schematic diagram showing the preparation process of the selection device of some other embodiments of the present disclosure is shown;

[0039] Fig.13 An exemplary flow chart showing a method for preparing a selection device according to yet other embodiments of the present disclosure;

[0040] Fig.14 An exemplary structural block diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0042] It should be understood that the terms "include" and "comprising" used in the specification and claims of the present disclosure indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0043] It should also be understood that the terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the disclosure. As used in this disclosure and claims, the singular forms of "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in this disclosure and claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations.

[0044] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0045] The specific implementation of the present disclosure is described in detail below with reference to the accompanying drawings.

[0046] Exemplary application scenarios

[0047] High-density memory usually uses a combination of new memory and selection devices. The selection device is used to assist in the selection and access of new memory at a specific address in the circuit. The combination of common new memory and MOSFET is limited by the current density, voltage resistance and device size of MOSFET, which will limit the performance and area of ​​the new memory in actual use. Figure 1 FIG. 4 shows a schematic diagram of the structure of an existing novel memory and a MOSFET combination. Figure 1 As shown in the figure, the combination connects the resistive random access memory (ReRAM) to the drain in the MOSFET to form a 1T1R structure as the basic unit of storage. Since the MOSFET itself is large in size and has a limited current density under the same plane area, the use of MOSFET as a selection device has brought great constraints on the regulation of the overall chip area and ReRAM performance.

[0048] In order to improve the defects of the combination of the new memory and MOSFET, some existing solutions are to use an IMT selection device and a resistive memory in series to form a 1S1R structure as a basic unit of storage. Figure 2 FIG. 4 shows a schematic diagram of a structure of a combination of an existing novel memory and an IMT selection device. Figure 2 As shown in the figure, the lower electrode of ReRAM is connected to the top electrode of IMT selection device. Since IMT selection device can achieve a large on-state current in a small area, and under the premise of providing sufficient switching ratio, IMT selection device also has a high voltage resistance, thus solving the restriction of MOSFET on ReRAM performance. At the same time, since IMT selection device has a smaller area, it is more conducive to reducing chip area.

[0049] However, although IMT selection devices have the advantage of high drive current, they also have the problem of large leakage current. Figure 3 FIG. 4 shows a current-voltage characteristic curve of an existing IMT selection device, such as Figure 3 As shown, although the existing IMT selection devices can provide milliampere-level on-state current driving capability when the device size is very small, their leakage current also reaches microampere level, resulting in the performance of new memory still being restricted.

[0050] Exemplary Application Scenarios

[0051] In view of this, the disclosed embodiment provides a selection device solution, which uses an annealing process to process the barrier layer and the selection layer, so that the effective area and leakage current of the IMT selection device are suppressed by the annealed oxidation portion of the barrier layer and the selection layer, thereby alleviating the leakage current problem of the IMT selection device.

[0052] Figure 4 An exemplary structural diagram of a selection device based on the insulator-metal transition effect of an embodiment of the present disclosure is shown, as shown in FIG. Figure 4 As shown, the selection device shown in the embodiment of the present disclosure includes: a top electrode 11, a selection layer 13 and a bottom electrode 14, wherein the bottom electrode 14, the selection layer 13 and the top electrode 11 are stacked in sequence. Further, the selection device also includes: a barrier layer 12, which is arranged between the selection layer 13 and the top electrode 11.

[0053] In the IMT selection device, the top electrode 11 serves as the upper contact layer of the selection device, and its function is to connect to the external circuit to provide a path for current input or output. In some cases, the top electrode 11 also participates in the phase change process controlled by the electric field. For example, by changing the voltage applied to the top electrode, the material can be induced to undergo a phase change from an insulator to a metal, thereby achieving regulation of the conductivity state of the selection device. In some embodiments of the present disclosure, the top electrode 11 can be prepared using a material that is more difficult to oxidize than the selection layer 13. Specifically, the materials that can be used for the top electrode 11 include: titanium nitride or tantalum nitride.

[0054] In the IMT selection device, the bottom electrode 14 serves as the lower contact layer of the device and also serves to connect to the external circuit. In some cases, the bottom electrode 14 is also involved in the injection or extraction of charge, thereby affecting the conductivity state of the device. In the IMT selection device, the material and structural design of the bottom electrode 14 have a significant impact on the integrity of the device. Taking the ferroelectric film as an example, the bottom electrode has an important influence on the structure and electrical properties of the film. In some embodiments of the present disclosure, the bottom electrode 14 uses a material with a relatively high work function and is relatively inert. Specifically, the work function of the material used for the bottom electrode 14 is greater than 4.5 eV and the electrode potential is greater than 0.4V.

[0055] In the IMT selection device, the function of the selection layer 13 is to improve the selectivity of the device, which is usually used to control the current flow in a specific area, thereby improving the switching ratio of the device and reducing the leakage current. In some embodiments of the present disclosure, the selection layer 13 uses a second metal oxide and the second metal in the second metal oxide includes a VB group element.

[0056] It should be further explained that when the IMT selection device of the disclosed embodiment is used in combination with a memory, the thickness of the selection layer 13 can be flexibly configured according to the operating voltage range of the memory. As an example, the thickness of the selection layer 13 of the IMT selection device can be between 10nm and 50nm.

[0057] In the preparation process of the IMT selection device shown in the embodiment of the present disclosure, after the thin film structure of the selection layer 13 is formed by using the above materials, it is necessary to complete the annealing oxidation of the selection layer 13 through an annealing process in an oxygen environment to prepare the final selection layer 13.

[0058] For ease of understanding, Figure 5 An exemplary structural diagram of a selection device based on the insulator-metal transition effect according to some embodiments of the present disclosure is shown. Figure 5 The selection device shown may include, in addition to the bottom electrode 14, the selection layer 13 and the top electrode 11, a lower metal layer 15 and an insulating layer 16, wherein the insulating layer 16 is arranged on the lower metal layer 15, the lower metal layer 15 and the insulating layer 16 are arranged adjacent to each other, and the bottom electrode 14 is arranged in or on the insulating layer 16. Figure 5 CD1 represents the minimum width of the top surface of the selection layer 13. After the annealing process in an oxygen environment, the left sidewall and the right sidewall of the selection layer 13 can form a first region with a width of d, which can also be understood as an annealed oxide layer with a thickness of d1.

[0059] In the disclosed embodiment, the annealed and oxidized selection layer 13 includes: a first region 131 and a second region 132, wherein the first region 131 is a portion of the selection layer 13 that is annealed and oxidized by an annealing process in an oxygen environment. Specifically, the first region is distributed on the sidewall of the selection layer 13, that is, the first region 131 is located outside the second region 132, and from a cross-sectional perspective, the first region 131 is located on both sides of the second region 132.

[0060] It should be noted that the minimum thickness of the portion of the selection layer 13 formed by annealing and oxidation is related to the minimum width of the top surface of the selection layer 13. Figure 5 As shown, in some embodiments of the present disclosure, the selection layer 13, the barrier layer 12 and the top electrode 11 are arranged on the bottom electrode 14 and are etched into a columnar structure with inclined sidewalls. At this time, the bottom width and top width of the selection layer 13 are inconsistent, and the top width is smaller than the bottom width. After oxidation annealing, since the first region 131 is located outside the second region 132, the first region 131 also has an inclined sidewall, resulting in the top width and bottom width of the first region 131 being inconsistent. In order to facilitate the description of the annealing oxidation process of this embodiment, Figure 7 illustrative structural diagrams of selection devices based on the insulator-metal transition effect according to other embodiments of the present disclosure are shown, such as Figure 7 As shown, in this embodiment, a portion of the first region 131 having the same width as the top surface is regarded as a first portion 1311, the top surface of the first portion 1311 at least partially overlaps with the top surface of the selection layer 13, and the other portion is regarded as a third portion 1312. The first region 131 includes at least the first portion 1311, wherein the width of the first portion 1311 can be regarded as the minimum thickness of the portion formed by the annealing and oxidation of the selection layer 13, and the width d1 of the first portion 1311 is determined according to the minimum width of the top surface of the selection layer 13.

[0061] It should be further explained that, in some other embodiments, the selection layer 13, the barrier layer 12 and the top electrode 11 may also be etched into a columnar structure with vertical sidewalls, in which case the top surface width of the selection layer 13 may be considered to be consistent with the bottom surface width. In some other embodiments, the selection layer 13, the barrier layer 12 and the top electrode 11 may not be etched.

[0062] As an example, when the minimum width of the top surface of the selection layer 13 is greater than or equal to 40nm, from a cross-sectional perspective, the width d1 of the first portion on either side is between 3nm and 5nm. In the case of CD1≥40nm, if d1 is less than 3nm, the thickness of the annealed oxidized portion formed by the annealing process is relatively small, which results in fewer annealed portions with higher resistivity at this time, and the leakage current problem of the IMT selection device cannot be effectively suppressed; in the case of CD1≥40nm, if d1 is greater than 5nm, the annealing process is more difficult, and the process complexity increases accordingly, and if d1 is greater than 5nm, the annealed oxidized portion formed by the annealing process is too large, and the higher resistivity of the annealed oxidized portion will increase the overall working resistance of the selection device, resulting in increased power consumption of the selection device.

[0063] As another example, when the minimum width of the top surface of the selection layer 13 is less than 40nm, the minimum value of the width d1 of the first part on either side can reach 2nm, and the maximum value is (0.125×CD1)nm. In the case of CD1<40nm, if d1 is less than 2nm, the thickness of the annealed oxide portion formed by the annealing process is small, which results in less annealed portions with higher resistivity at this time, and the leakage current problem of the IMT selection device cannot be effectively suppressed; in the case of CD1<40nm, if d1 is greater than (0.125×CD1)nm, the annealed oxide portion formed by the annealing process is too large, and the higher resistivity of the annealed oxide portion will increase the overall working resistance of the selection device, resulting in increased power consumption of the selection device.

[0064] Based on this, the minimum thickness of the portion of the selection layer 13 formed by annealing and oxidation is determined according to the minimum width of the top surface of the selection layer 13, which can not only form an annealing portion with the effect of reducing leakage current in the selection layer, but also effectively avoid the disadvantage of worsening power consumption caused by the increase in the overall resistance of the selection device.

[0065] In the IMT selection device, the barrier layer 12 is usually composed of a material with a larger band gap, which is sandwiched between two more conductive material layers and forms an energy barrier, which controls the distribution of carriers in the quantum well by preventing the flow of electrons and holes between different layers. In some cases, the barrier layer 12 provides a certain barrier height for the gate Schottky contact, thereby affecting the electric field strength and current collapse characteristics of the device. In some embodiments of the present disclosure, the barrier layer 12 uses a first metal oxide insulator, that is, an insulating metal oxide material, which has a special electronic phase change characteristic between metal and semiconductor. In this phase change, the conductivity of the material will change from an insulator to a metal state due to external stimulation.

[0066] In order to improve the performance of the barrier layer 12 in the IMT selection device, in some embodiments, the barrier layer 12 of the IMT selection device in the disclosed embodiment can be selectively prepared using insulating metal oxides such as aluminum oxide and titanium oxide, so that the band gap provided by the barrier layer is greater than 3eV. In addition, in order to ensure the insulation of the material of the barrier layer 12, the contact resistivity of the first metal oxide insulator used in the barrier layer 12 and the second metal oxide of the selection layer is greater than 10mΩ·cm.

[0067] Similar to the selection layer 13 , the barrier layer 12 can also be annealed and oxidized by an annealing process in an oxygen environment, thereby preparing the final barrier layer 12 .

[0068] like Figure 5 As shown, in the disclosed embodiment, the barrier layer 12 after annealing and oxidation includes: a third region 121 and a fourth region 122, wherein the third region 121 is a portion of the barrier layer 12 that is annealed and oxidized by an annealing process in an oxygen environment. Specifically, the third region 121 is distributed on the sidewall of the barrier layer 12, that is, the third region 121 is located outside the fourth region 122, and from a cross-sectional perspective, the third region 121 is located on both sides of the fourth region 122.

[0069] Similar to the selection layer 13, the portion of the barrier layer 12 formed by annealing and oxidation can also be divided into two parts. In other words, the third region 121 at least includes a second portion 1211, which is similar to the first portion 1311 of the first region 131. The second portion 1211 is a portion of the third region 121 with the same width as the top surface. The top surface of the second portion 1211 at least partially overlaps with the top surface of the barrier layer 12. The third region 121 also includes a fourth portion 1212. In some embodiments, the fourth portion 1212 can be as follows: Figure 5 and Figure 7 The minimum thickness d2 of the third region 121 is related to the minimum width CD2 of the top surface of the barrier layer 12 . In other words, the width d2 of the second portion 1211 is determined according to the minimum width CD2 of the top surface of the barrier layer 12 .

[0070] As an example, when the minimum width of the top surface of the barrier layer 12 is greater than or equal to 40nm, the width d2 of the second portion 1211 on either side is between 3nm and 5nm. In the case of CD2≥40nm, if d2 is less than 3nm, the thickness of the annealed oxide portion formed by the annealing process is relatively small, which results in fewer annealed portions with higher resistivity at this time, and the leakage current problem of the IMT selection device cannot be effectively suppressed; in the case of CD2≥40nm, if d2 is greater than 5nm, the annealing process is more difficult, and the process complexity increases accordingly, and if d2 is greater than 5nm, the annealed oxide portion formed by the annealing process is too large, and the higher resistivity of the annealed oxide portion will increase the overall working resistance of the selection device, resulting in increased power consumption of the selection device.

[0071] As another example, when the minimum width of the top surface of the barrier layer 12 is less than 40nm, the minimum value of the width d2 of the second portion 1211 on either side can reach 2nm, and the maximum value is (0.125×CD2)nm. In the case of CD2<40nm, if d2 is less than 2nm, the thickness of the annealed oxide portion formed by the annealing process is small, which results in less annealed portions with higher resistivity at this time, and the leakage current problem of the IMT selection device cannot be effectively suppressed; in the case of CD2<40nm, if d2 is greater than (0.125×CD2)nm, the annealed oxide portion formed by the annealing process is too large, and the higher resistivity of the annealed oxide portion will increase the overall working resistance of the selection device, resulting in increased power consumption of the selection device.

[0072] Based on this, the minimum thickness of the barrier layer 12 formed by annealing and oxidation is determined according to the minimum width of the top surface of the barrier layer 12, which can not only form an annealing part with the effect of reducing leakage current in the barrier layer, but also effectively avoid the disadvantage of worsening power consumption caused by the increase in the overall resistance of the selection device.

[0073] In the IMT selection device, the saturated oxide formed by annealing can also provide a thin layer for current suppression, that is, the annealed and oxidized portion of the barrier layer 12 and the selection layer 13 can effectively suppress the leakage current of the IMT selection device. Figure 6 The current-voltage characteristic curve of the selection device based on the insulator-metal transition effect of the embodiment of the present disclosure is shown as follows: Figure 6 As shown, Figure 6 The larger dotted box in the middle selects the current-voltage characteristic curve of the existing IMT selection device, and the smaller dotted box selects the current-voltage characteristic curve of the IMT selection device shown in the embodiment of the present disclosure. Compared with the existing IMT selection device, the leakage current of the IMT selection device shown in the embodiment of the present disclosure is significantly reduced.

[0074] Further, in some embodiments, the annealing temperature used in the annealing process is between 200°C and 600°C. For example, in practical applications, annealing temperatures such as 300°C, 350°C, 400°C, 450°C or 500°C can be used, without excessive restrictions. Further, in some embodiments, the annealing temperature can be preferentially set in a numerical range of 350°C to 400°C. In addition, the annealing time used in the annealing process is between 1min and 60min. For example, in practical applications, the preset annealing time can be controlled to be set to 30min, 40min or 45min, without excessive restrictions. Further, in the annealing process, the oxygen flow in the oxygen environment can be regulated by control settings such as valves and controllers.

[0075] It should be noted that Figure 4 or Figure 5 The figure shows the basic structure of the IMT selection device providing the switching capability. In practical applications, the IMT selection device may also have other semiconductor structure layers. Figure 7 illustrative structural diagrams of selection devices based on the insulator-metal transition effect according to other embodiments of the present disclosure are shown, such as Figure 7 As shown, IMT selects devices except Figure 4 In addition to the structure shown, the structure also includes: a lower metal layer 15 , an insulating layer 16 , a sidewall protection layer 17 and an intermetallic dielectric layer 18 .

[0076] exist Figure 7 In the structure shown, the lower metal layer 15 and the insulating layer 16 are arranged adjacent to each other. The lower metal layer 15 is one of the conductive layers used for signal transmission and power distribution in the integrated circuit, and is isolated from other conductive layers by the insulating layer 16 to prevent current leakage. Furthermore, the insulating layer 16 can be made of materials such as silicon nitride, silicon dioxide, or nitride-doped silicon carbide.

[0077] In some embodiments, the bottom electrode 14 is disposed within the insulating layer 16. Figure 5 and Figure 7 As shown, the insulating layer 16 also has a hole structure, and the bottom electrode 14 of the IMT selection device is arranged in the hole structure and connected with the lower metal layer 15 to form a conductive channel. In other embodiments, Figure 8 illustrative structural diagrams of selection devices based on the insulator-metal transition effect according to some other embodiments of the present disclosure are shown, such as Figure 8 As shown, the bottom electrode 14 may also be directly disposed on the insulating layer 16, rather than inside the insulating layer 16. In order to achieve electrical connection between the bottom electrode and the underlying metal layer, a metal via for conduction may be provided inside the insulating layer. In other embodiments, the insulating layer 16 may also be simplified so that the bottom electrode is directly conductive with the underlying metal layer. In this case, the bottom electrode is directly disposed on the underlying metal layer.

[0078] In the selection device, the selection layer 13, the barrier layer 12 and the top electrode 11 are stacked in sequence on the bottom electrode 14 to form a columnar structure, and the sidewall protection layer 17 covers the surface of the columnar structure to protect the selection layer 13, the barrier layer 12 and the top electrode 11, including protecting the first region 131 formed by annealing and oxidation in the selection layer 13 and the third region 121 formed by annealing and oxidation in the barrier layer 12, so as to protect them from damage caused by ion implantation, prevent metal layer diffusion and migration, prevent current leakage, and reduce potential breakdown risks.

[0079] Furthermore, in some embodiments, Figure 7 or Figure 8 As shown, the edge portion of the semiconductor structure layer above the insulating layer 16 is etched, so that part of the insulating layer 16 is exposed. At this time, the sidewall protection layer 17 also covers the surface of the exposed insulating layer 16. The metal interlayer dielectric layer 18 covers the surface of the sidewall protection layer 17 to prevent mutual diffusion and migration between metal layers. In the metal interconnect structure, the metal interlayer dielectric layer 18 can also wrap the lower metal layer 15 to prevent metal ion diffusion and improve the reliability and electromigration characteristics of the IMT selection device.

[0080] Based on the IMT selection device described in any of the foregoing embodiments, some embodiments of the present disclosure may provide a storage unit, which includes a memory and the IMT selection device described in any of the foregoing embodiments. In the storage unit, the memory and the IMT selection device are connected in series. As an example, the memory includes an upper electrode and a lower electrode, and the upper electrode of the memory is connected in series with the bottom electrode of the IMT selection device. In other embodiments, the arrangement structure in the storage unit can be inverted upside down, that is, in the series structure of the memory and the IMT selection device, the lower electrode of the memory is connected in series with the top electrode of the selection device to form a storage unit.

[0081] In practical applications, the memory may be one or more of the following types: resistive memory, ferroelectric memory, magneto-variable memory, phase-change memory and other types of memory, without excessive limitation here.

[0082] Since the IMT selection device described in any of the foregoing embodiments completes the annealing and oxidation treatment of the selection layer in an oxygen environment through an annealing process, the saturated oxide formed by the annealing provides a thin layer for current suppression near the sidewall protection layer, and the effective area and leakage current of the selection device are suppressed by the annealing and oxidation portion of the selection layer. Therefore, the IMT selection device can provide a larger on-state current and a smaller leakage current in a smaller size, which is beneficial to the release of ReRAM performance in the storage unit and also beneficial to reducing the occupied area required for the storage unit.

[0083] In the memory cell described above, the operating voltage of the memory is positively correlated with the thickness of the selection layer in the IMT selection device, that is, the thicker the selection layer, the greater the operating voltage of the memory adapted by the IMT selection device.

[0084] With the growing demand for information storage capacity, high-density memory has become the preferred solution for large-scale storage integration. To a certain extent, the area of ​​an integrated chip that realizes large-scale storage function is limited by the area of ​​its storage unit. Therefore, based on the storage unit described in the above embodiments, some embodiments of the present disclosure may also provide an integrated chip, in which the storage unit may be a storage unit described in any of the above embodiments, and is composed of an IMT selection device and a memory in series. The IMT selection device partially suppresses leakage current by annealing and oxidizing the selection layer, thereby providing a larger on-state current and a smaller leakage current in a smaller size to adapt to the release of ReRAM performance, while reducing the occupied area required for the storage unit.

[0085] In order to prepare the IMT selection device described in the above embodiments, some embodiments of the present disclosure also provide a method for preparing the selection device. Fig. 9 An exemplary flow chart of a method 900 for preparing a selection device according to some embodiments of the present disclosure is shown.

[0086] like Fig. 9 As shown, in step S901, a semi-finished device is prepared. In step S901, the semi-finished device includes a selection layer and further includes a bottom electrode, and the selection layer is stacked on the bottom electrode.

[0087] Furthermore, in step S901, the bottom electrode may be made of an electrode material with a relatively high work function and relatively inert, such as tungsten. Furthermore, the work function of the material used for the bottom electrode is greater than 4.5 eV, and the electrode potential is greater than 0.4V.

[0088] It should be noted that the semi-finished device refers to the selection device that has not been completely processed. Among them, incomplete processing can refer to the structure of the selection device that has not been completed. In this case, compared with the completed selection device that has been formed, the semi-finished device lacks some structural layers. Incomplete processing can also refer to certain processes and procedures that are not completed, for example, the oxidation annealing process or the insulation protection process is not completed, etc. In this case, compared with the completed selection device that has been formed, the semi-finished device may lack some structural layers, or may not lack structural layers.

[0089] In step S902, the semi-finished device is annealed in an oxygen environment. When executing step S902, the annealing temperature is controlled between 200° C. and 600° C., and the semi-finished device is annealed in the oxygen environment for a preset annealing time, which is between 1 minute and 60 minutes.

[0090] After step S902, the selection layer will form a first region oxidized by the annealing process. In other words, the annealing process can form a saturated oxide, thereby providing a thin layer for current suppression, so that the effective area and leakage current of the selection device are suppressed by the annealing oxidation part of the barrier layer and the selection layer. Furthermore, step S902 can control the oxygen concentration in the oxygen environment by controlling the oxygen flow rate. In addition, the annealing temperature used in the annealing process can be between 200°C and 600°C, and the annealing time can be between 1min and 60min. The specific annealing temperature and annealing time can be flexibly adjusted according to actual conditions, and no excessive restrictions are made here.

[0091] It should be noted that in the preparation method shown in the embodiment of the present disclosure, the annealing process can be performed after the basic structure of the IMT selection device that provides switching capability is prepared. At this time, the semi-finished device includes, in addition to the bottom electrode and the selection layer, a barrier layer and a top electrode. The barrier layer is stacked on the selection layer, and the top electrode is stacked on the barrier layer. Step S902 will also cause the barrier layer to form a third region oxidized by the annealing process.

[0092] However, when the above preparation method is performed to prepare the selection device, the annealing treatment of the selection layer will inevitably bring annealing effects to the top electrode, which will cause the resistivity of the top electrode to increase, thereby causing the overall resistance of the selector unit to increase.

[0093] To address this problem, the disclosed embodiment also provides another preparation method, which performs an annealing process before preparing the top electrode to prevent the top electrode from being affected by the annealing process. At this time, the semi-finished device includes, in addition to the bottom electrode and the selection layer, a barrier layer stacked on the selection layer, and the semi-finished device does not include the top electrode. Step S902 also causes the barrier layer to form a third region oxidized by the annealing process.

[0094] In step S903, the annealed semi-finished device is subsequently prepared to obtain a selection device. If the annealing process is performed after the basic structure of the IMT selection device providing the switching capability is prepared, the subsequent preparation includes insulating the annealed semi-finished device. Specifically, in this embodiment, after the final barrier layer and the selection layer are prepared by annealing, step S903 needs to be performed for insulation protection to avoid current leakage and ion diffusion between the conductive layers, thereby ensuring the reliability of the obtained IMT selection device.

[0095] If an annealing process is performed before preparing the top electrode, the subsequent preparation includes: preparing the top electrode on the barrier layer. In some embodiments, the top electrode may be made of a material that is relatively difficult to oxidize, such as titanium nitride or tantalum nitride.

[0096] Fig. 9 The invention introduces the preparation method of the basic structure providing switching capability in the IMT selection device. In practical applications, the IMT selection device may also have other semiconductor structure layers, including: a lower metal layer, an insulating layer, a sidewall protection layer and a metal interlayer dielectric layer.

[0097] Based on this, Fig.10 An exemplary flow chart of a method 1000 for preparing a selection device according to some other embodiments of the present disclosure is shown. Fig.11 A schematic diagram of the preparation process of the selection device according to some other embodiments of the present disclosure is shown.

[0098] like Fig.10 and Fig.11 As shown, in step S1001, an insulating layer is deposited and grown on the lower metal layer. The lower metal layer is a conductive layer for transmitting electrical signals between storage units, and is used to connect various functional units to achieve logical operations and data processing. The insulating layer is a non-conductive material layer that isolates the conductive layers. In some embodiments, it can be made of materials such as silicon nitride, silicon dioxide, or nitride-doped silicon carbide and formed on the lower metal layer.

[0099] Furthermore, the insulating layer can be prepared by a variety of processes including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, sol-gel and molecular beam epitaxy. The specific preparation process can be selected according to actual needs and no excessive restrictions are made here.

[0100] In step S1002, a hole-shaped structure is etched on the insulating layer. In some embodiments, the insulating layer can be etched using gas and plasma to obtain Figure 5 or Figure 7 Furthermore, in order to improve the etching accuracy, a gas with a high selectivity ratio for the material of the insulating layer can be selected for etching, thereby reducing the damage to the underlying metal layer. In other embodiments, a liquid chemical solution with a high selectivity ratio for the material of the insulating layer can be selected to wet etch the insulating layer or an atomic layer etching process can be used to complete the preparation of the pore structure.

[0101] In step S1003, a bottom electrode is deposited and grown in the hole-like structure. When executing step S1003, the material of the bottom electrode can be grown by a PVD preparation process. Further, in some embodiments, the growth thickness can be controlled by a process so that the height of the grown bottom electrode is equal to the hole depth, so that the top surface of the bottom electrode is flush with the top of the hole. In other embodiments, the bottom electrode material beyond the hole-like structure can also be removed by a chemical mechanical polishing process (CMP) to flatten the surface.

[0102] During the growth process, the bottom electrode may be made of a relatively inert electrode material with a relatively high work function, such as tungsten. Furthermore, a material with a work function greater than 4.5 eV and an electrode potential greater than 0.4 V may be used as the preparation material for the bottom electrode.

[0103] In step S1004, a growth selection layer and a barrier layer are sequentially deposited on the bottom electrode. When performing step S1004, the selection layer and the barrier layer can be sequentially grown by an ALD preparation process, wherein the selection layer uses a second metal oxide and the second metal in the second metal oxide is a VB group element, and the barrier layer uses a first metal oxide insulator. Further, the contact resistivity between the first metal oxide insulator and the second metal oxide is greater than 10 mΩ·cm. As an example, the first metal oxide insulator can be aluminum oxide or titanium oxide.

[0104] Since the material thickness of the selection layer in the IMT selection device can be configured according to the operating voltage range of the memory with which it is matched, the growth thickness of the selection layer can be controlled to be between 10nm and 50nm when growing the selection layer.

[0105] In step S1005, a top electrode is deposited and grown on the barrier layer. When executing step S1005, the top electrode can be grown by a PVD preparation process, and the top electrode can be made of a material that is more difficult to oxidize than the selective layer, such as titanium nitride or tantalum nitride.

[0106] In step S1006, the selection layer, the barrier layer and the top electrode are etched into a columnar structure. When performing step S1006, a dry etching process can be used to remove part of the selection layer, part of the barrier layer and part of the top electrode to expose part of the insulating layer. The remaining part of the selection layer, part of the barrier layer and part of the top electrode are in a columnar structure covering the bottom electrode.

[0107] It should be noted that step S1006 can be performed or not performed according to actual needs. In other words, in actual application, step S1006 can also be not performed, and at this time, the insulating layer is completely covered by the selected layer.

[0108] It should be noted that after step S1005 or step S1006 is completed, a semi-finished device can be obtained, which includes a lower metal layer, an insulating layer, a bottom electrode, a selection layer, a barrier layer and a top electrode. The structure and arrangement of each layer can refer to the above combined with Figure 7 The described embodiments will not be described in detail here.

[0109] In step S1007, annealing is performed in an oxygen environment. In some embodiments, the oxygen flow rate can be controlled by control devices such as valves and controllers. In other embodiments, the annealing temperature used in the annealing process can be between 200° C. and 600° C., and the annealing time can be between 1 min and 60 min.

[0110] After the annealing treatment, the formed saturated oxide can provide a thin layer with a current suppression effect. Combined with the current suppression effect of the barrier layer, the current suppression effect of the IMT selection device can be further enhanced, thereby alleviating the problem of excessive leakage current of the IMT selection device.

[0111] It should be noted that step S1007 can be performed after step S1006, that is, the annealing process is performed after the top electrode is prepared. However, this preparation method will cause the top electrode to be affected by annealing, resulting in an increase in the resistivity of the top electrode, thereby causing the overall resistance of the selector unit to increase.

[0112] In some other embodiments, step S1007 may also be performed before step S1005, that is, the annealing process is performed after the barrier layer is prepared and before the top electrode is prepared, so as to prevent the top electrode from being affected by the annealing process.

[0113] In step S1008, a sidewall protection layer is deposited on the columnar structure. When executing step S1008, an ALD preparation process can be used to deposit a layer of aluminum oxide film as the sidewall protection layer. The ALD preparation process can achieve a good conformal coverage effect and evenly cover every part of the columnar structure, including corners and recesses. In addition, the ALD preparation process can also cause damage to the structure below the covered area.

[0114] It should be noted that the above description of the preparation process and preparation materials of the side wall protection layer is only an example. In practical applications, other preparation processes and other preparation materials can be selected, and no excessive restrictions are imposed here.

[0115] In step S1009, a dielectric layer between the growing metal layers is deposited on the sidewall protection layer. When executing step S1009, a dielectric material can be deposited by a CVD preparation process to prepare the dielectric layer between the growing metal layers, so as to effectively reduce the capacitance between the metal wires, increase the transmission speed of the signal, and reduce the power consumption and electromagnetic interference of the circuit. Furthermore, the dielectric material can be a dielectric material with a low dielectric constant such as an organic polymer, an organic silicon material, and a fluorinated carbon polymer.

[0116] It should be noted that the above description of the preparation process of the metal interlayer dielectric layer is only an example. In practical applications, other preparation processes such as PVD can be selected and no excessive restrictions are made here.

[0117] In step S1010, an upper metal connection hole is formed in the metal interlayer dielectric layer and the sidewall protection layer. In some embodiments, the upper metal connection hole can be formed by etching by a process such as dry etching. In this step, the upper metal connection hole penetrates the metal interlayer dielectric layer and the sidewall protection layer and is connected to the top electrode.

[0118] In step S1011 , a conductive material is filled in the upper metal connection hole to be connected to the top electrode.

[0119] pass Fig.10 The preparation method shown can prepare a selection device, which includes: a lower metal layer, an insulating layer, a bottom electrode, a selection layer, a barrier layer, a top electrode, a sidewall protection layer and a metal interlayer dielectric layer. The lower metal layer and the insulating layer are arranged adjacent to each other, the insulating layer has a hole structure, and the bottom electrode is arranged in the hole structure. The selection layer, the barrier layer and the top electrode are stacked on the bottom electrode in sequence to form a columnar structure, the sidewall protection layer covers the surface of the columnar structure, and the metal interlayer dielectric layer covers the surface of the sidewall protection layer.

[0120] pass Fig.10The selection device prepared by the preparation method shown in the figure can effectively suppress the effective area and leakage current of the selection device, and realize a selection device with a high drive current, a small leakage current and a small area, so as to be more suitable for the new memory. After being connected in series with the new memory, the constraints on the performance and area of ​​the new memory can be reduced, and the integration of the memory unit can be improved.

[0121] According to the previous Fig. 9 It can be seen from the contents of the described embodiments that in order to prevent the top electrode from being affected by the annealing process, an annealing process can be performed before preparing the top electrode. Fig.12 Schematic diagrams showing the preparation process of the selection device of some other embodiments of the present disclosure are shown. Fig.12 As shown, after the selection layer and the barrier layer are deposited and grown on the bottom electrode 2 and the etching of the selection layer and the barrier layer is completed, an annealing process is performed in an oxygen environment, so that the selection layer forms an annealed and oxidized part, and the barrier layer may form an oxidized part due to the influence of annealing. After the annealing process is completed, the top electrode is deposited and grown and the etching of the top electrode is completed.

[0122] use Figure 10-12 The bottom electrode of the selection device prepared by the preparation method provided is located inside the insulating layer. In other embodiments, the bottom electrode can be located above the insulating layer. The selection device of this structure can be Fig.13 The preparation method shown is prepared.

[0123] Fig.13 An exemplary flow chart of a method 1300 for preparing a selection device according to some other embodiments of the present disclosure is shown. Fig.13 As shown, in step S1301, a growth insulating layer is deposited on the lower metal layer. In this embodiment, the content of step S1301 is consistent with step S1001 in the above embodiment, and will not be repeated here.

[0124] In step S1302, a bottom electrode is deposited and grown on the insulating layer. In this embodiment, the difference between step S1302 and step S1002 and step S1003 in the previous embodiment is that: the previous embodiment needs to etch a hole-like structure for filling the bottom electrode material in the insulating layer so that the final bottom electrode is located inside the insulating layer. In this embodiment, the bottom electrode is directly deposited and grown on the surface of the insulating layer to form a stacked insulating layer and bottom electrode. It should be noted that the bottom electrode is electrically connected to the underlying metal layer. In some embodiments, a metal connecting hole for conducting the bottom electrode and the underlying metal layer is provided inside the insulating layer. In other words, before step S1302 is performed, a step can be added to complete the preparation of the metal connecting hole inside the insulating layer. Alternatively, in other embodiments, the bottom electrode and the underlying metal layer can be directly electrically connected. In other words, in steps S1301 and S1302, the insulating layer may not be prepared, but the bottom electrode may be deposited on the underlying metal layer to complete the electrical connection.

[0125] In step S1303, a growth selection layer and a barrier layer are sequentially deposited on the bottom electrode. In this embodiment, the content of step S1303 is consistent with step S1004 in the above embodiment, and will not be repeated here.

[0126] In step S1304, a top electrode is deposited and grown on the barrier layer. In this embodiment, the content of step S1304 is consistent with step S1005 in the above embodiment, and will not be repeated here.

[0127] In step S1305, the device is annealed in an oxygen environment. Fig.10 Similar to the embodiment described above, step S1305 can be performed after the top electrode is prepared, or before the top electrode is prepared. In other words, step S1305 can be performed after step S1304, or before step S1304.

[0128] In step S1306, the bottom electrode, the selection layer, the barrier layer and the top electrode are insulated and protected. In some embodiments, the insulation protection is performed by the sidewall protection layer and / or the metal interlayer dielectric layer. Further, the bottom electrode, the selection layer, the barrier layer and the top electrode can be etched into a columnar structure, and part of the insulation layer is exposed, such as Figure 8 As shown, the sidewall protection layer covers the entire surface of the columnar structure and covers the exposed insulating layer, and the metal interlayer dielectric layer covers the sidewall protection layer.

[0129] In step S1307 , an upper metal connection hole is formed above the top electrode.

[0130] In step S1308 , a conductive material is filled in the upper metal connection hole to be connected to the top electrode.

[0131] pass Fig.13 The selection device prepared by the preparation method shown in the figure can effectively suppress the effective area and leakage current of the selection device, and realize a selection device with a high drive current, a small leakage current and a small area, so as to be more suitable for the new memory. After being connected in series with the new memory, the constraints on the performance and area of ​​the new memory can be reduced, and the integration of the memory unit can be improved.

[0132] In summary, the disclosed embodiment provides an IMT selection device, which, through the selection layer and annealing process, allows the effective area and leakage current of the selection device to be suppressed by the annealed oxidation part of the selection layer, thereby forming a current suppression effect under the joint action of the selection layer and the annealing process, thereby alleviating the problem of large leakage current of traditional IMT selection devices and alleviating the constraints of IMT selection devices on new memories.

[0133] Based on the above-mentioned IMT selection device, some embodiments of the present disclosure further provide a storage unit, which achieves high-density storage performance by connecting the above-mentioned IMT selection device and ReRAM in series.

[0134] Based on the above-mentioned storage unit, some embodiments of the present disclosure further provide an integrated chip, which uses the above-mentioned storage unit as the minimum storage unit, provides a large amount of storage space in a smaller area, and greatly improves the storage performance of the integrated chip.

[0135] In addition, some embodiments of the present disclosure also provide a method for preparing a selection device, by which the above-mentioned IMT selection device can be prepared. The saturated oxide formed by annealing during the preparation process can provide a thin layer for current suppression near the side wall protection layer. Combined with the current suppression effect of the barrier layer, the leakage current of the selection device can be effectively reduced.

[0136] In order to implement the method steps described in the foregoing text of this disclosure in conjunction with the accompanying drawings at the software and hardware level, the present disclosure also provides the following Fig.14 The electronic device shown. Specifically, Fig.14 An exemplary structural block diagram of an electronic device 1400 according to an embodiment of the present disclosure is shown.

[0137] like Fig.14 As shown, the electronic device 1400 disclosed in the present invention may include a processor 1410 and a memory 1420. Specifically, executable program instructions are stored in the memory 1420. When the program instructions are executed by the processor 1410, the electronic device implements the above-mentioned Fig. 9 , Fig.10 or Fig.12 As an example of the method steps, the electronic device 1400 may be a machine for fabricating semiconductor products.

[0138] It is understood that in order to clearly illustrate the solution of the present disclosure and avoid confusion with the prior art, Fig.14 The electronic device 1400 of the present disclosure only shows the components related to the embodiment of the present disclosure, and omits the components that may be necessary for implementing the embodiment of the present disclosure but belong to the scope of the prior art. Therefore, based on the content disclosed in the present disclosure, a person skilled in the art can clearly understand that the electronic device 1400 of the present disclosure can also include components related to the embodiment of the present disclosure. Fig.14 The constituent elements shown in are different from the common constituent elements.

[0139] In an exemplary implementation scenario, the above-mentioned processor 1410 can control the overall operation of the electronic device 1400. For example, the processor 1410 can control the operation of the electronic device 1400 by executing the program stored in the memory 1420. In terms of implementation, the processor 1410 of the present disclosure can be implemented by a central processing unit (CPU), an application processor (AP), an artificial intelligence processor chip (IPU), etc. provided in the electronic device 1400. Further, the processor 1410 of the present disclosure can also be implemented in any appropriate manner. For example, the processor 1410 can take the form of a computer-readable medium, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, etc., such as a microprocessor or a processor and a computer-readable program code (such as software or firmware) that can be executed by the (micro) processor.

[0140] In terms of storage content, the memory 1420 can be used to store hardware of various data and instructions processed in the electronic device 1400. For example, the memory 1420 can store processed data and data to be processed in the electronic device 1400. The memory 1420 can store data sets that have been processed or to be processed by the processor 1410. In addition, the memory 1420 can store applications, drivers, etc. to be driven by the electronic device 1400. For example: the memory 1420 can store various programs to be executed by the processor 1410. The memory 1420 can be a DRAM, but the present disclosure is not limited to this. In terms of type, the memory 1420 may include at least one of a volatile memory or a non-volatile memory. The non-volatile memory may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), and the like. The volatile memory may include a dynamic RAM (DRAM), a static RAM (SRAM), a synchronous DRAM (SDRAM), a PRAM, an MRAM, an RRAM, a ferroelectric RAM (FeRAM), etc. In an embodiment, the memory 1420 may include at least one of a hard disk drive (HDD), a solid state drive (SSD), a high-density flash memory (CF), a secure digital (SD) card, a micro secure digital (Micro-SD) card, a mini secure digital (Mini-SD) card, an extreme digital (xD) card, caches, or a memory stick.

[0141] In summary, the specific functions implemented by the memory 1420 and the processor 1410 of the electronic device 1400 provided in the implementation manner of this specification can be explained in comparison with the aforementioned implementation manner in this specification, and can achieve the technical effects of the aforementioned implementation manner, and will not be repeated here.

[0142] Additionally or optionally, the present disclosure may also be implemented as a non-temporary machine-readable storage medium (or computer-readable storage medium, or machine-readable storage medium) on which computer program instructions (or computer program, or computer instruction code) are stored. When the computer program instructions (or computer program, or computer instruction code) are executed by a processor of an electronic device (or electronic device, server, etc.), the processor executes part or all of the steps of the above-mentioned method according to the present disclosure.

[0143] Although multiple embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art may think of many changes, modifications, and alternatives without departing from the thought and spirit of the present disclosure. It should be understood that in the process of practicing the present disclosure, various alternatives to the embodiments of the present disclosure described herein may be adopted. The attached claims are intended to define the scope of protection of the present disclosure, and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A selection device based on insulator-metal transition effect, characterized in that: include: A bottom electrode (14), a selection layer (13) and a top electrode (11) stacked in sequence; The selection layer (13) comprises: a first region (131) and a second region (132), and the first region (131) is formed by an annealing process in an oxygen environment.

2. The selection device according to claim 1, characterized in that: The selection device further comprises: a barrier layer (12), wherein the barrier layer (12) is arranged between the selection layer (13) and the top electrode (11); The barrier layer (12) comprises: a third region (121) and a fourth region (122); the third region (121) is formed by an annealing process in an oxygen environment.

3. The selection device according to claim 1, characterized in that: The first region (131) is located outside the second region (132), the first region (131) located on one side of the second region (132) at least includes a first portion (1311), and the top surface of the first portion (1311) at least partially overlaps with the top surface of the selection layer (13); If the minimum width of the top surface of the selective layer (13) is greater than or equal to 40 nm, the width d1 of the first portion is between 3 nm and 5 nm; If the minimum width of the top surface of the selection layer (13) is less than 40 nm, the width d1 of the first portion is between 2 nm and (0.125×CD1) nm, wherein CD1 is the minimum width of the top surface of the selection layer (13).

4. The selection device according to claim 2, characterized in that: The third region (121) is located outside the fourth region (122), the third region (121) located on one side of the fourth region (122) at least comprises a second portion (1211), and a top surface of the second portion (1211) at least partially overlaps with a top surface of the barrier layer (12); If the minimum width of the top surface of the barrier layer (12) is greater than or equal to 40 nm, the width d2 of the second portion is between 3 nm and 5 nm; If the minimum width of the top surface of the barrier layer (12) is less than 40 nm, the width d2 of the second portion is between 2 nm and (0.125×CD2) nm, wherein CD2 is the minimum width of the top surface of the barrier layer (12).

5. The selection device according to claim 2, characterized in that: The barrier layer (12) is made of a first metal oxide insulator, the selection layer (13) is made of a second metal oxide, and the second metal in the second metal oxide includes a VB group element.

6. The selection device according to any one of claims 1 to 5, characterized in that: In the annealing process, the annealing temperature is between 200° C. and 600° C., and the annealing time is between 1 min and 60 min.

7. The selection device according to claim 5, characterized in that: The band gap reference provided by the barrier layer (12) is greater than 3 eV, and the contact resistivity between the first metal oxide insulator and the second metal oxide is greater than 10 mΩ·cm.

8. The selection device according to claim 1, characterized in that: The material of the top electrode (11) is more difficult to oxidize than the material of the selection layer (13).

9. The selection device according to claim 8, characterized in that: The material used for the top electrode (11) includes titanium nitride or tantalum nitride.

10. The selection device according to claim 1, characterized in that: The work function of the material used for the bottom electrode (14) is greater than 4.5 eV, and the electrode potential is greater than 0.4V.

11. The selection device according to claim 1, characterized in that: The thickness of the selection layer (13) is between 10 nm and 50 nm.

12. A storage unit, characterized in that: include: The selection device according to any one of claims 1 to 11; as well as The memory is connected in series to the selection device.

13. The storage unit according to claim 12, characterized in that The operating voltage of the memory is positively correlated with the thickness of the selection layer in the selection device.

14. An integrated chip, characterized in that: The integrated chip comprises: a storage unit as claimed in claim 12 or 13.

15. A method for preparing a selection device, characterized in that: include: preparing a semi-finished device, wherein the semi-finished device comprises a bottom electrode and a selection layer stacked in sequence; Performing an annealing process on the semi-finished device in an oxygen environment so that the selection layer forms a first region oxidized by the annealing process; as well as The annealed semi-finished device is subsequently prepared to obtain a selected device.

16. The preparation method according to claim 15, characterized in that: The semi-finished device further comprises a barrier layer stacked on the selection layer; After preparing the semi-finished device, the preparation method further includes: annealing the semi-finished device in an oxygen environment so that the barrier layer forms a third region oxidized by the annealing process; subsequent preparation of the annealed semi-finished device includes: preparing a top electrode on the barrier layer.

17. The preparation method according to claim 15, characterized in that: The semi-finished device further comprises a barrier layer and a top electrode, wherein the barrier layer is stacked on the selection layer, and the top electrode is stacked on the barrier layer; After preparing the semi-finished device, the preparation method further comprises: annealing the semi-finished device in an oxygen environment so that the barrier layer forms a third region oxidized by the annealing process; The subsequent preparation of the annealed semi-finished device includes: insulating and protecting the annealed semi-finished device.

18. The preparation method according to claim 15, characterized in that: The annealing treatment of the semi-finished device in an oxygen environment comprises: The annealing temperature is controlled to be between 200° C. and 600° C., and the semi-finished device is annealed for a preset annealing time in an oxygen environment, wherein the preset annealing time is between 1 min and 60 min.

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