Semiconductor device and method for forming the same

Abstract

The present application provides a semiconductor device and a method for forming the same, wherein the semiconductor device includes a plurality of discrete storage units, a sidewall protection layer, a heat insulating layer, and a heat conducting structure. The sidewall protection layer is located on the sidewall of the storage unit; the heat insulating layer is located between adjacent storage units; the heat conducting structure is located between the sidewall protection layer and the heat insulating layer, and the thermal conductivity of the heat conducting structure is greater than the thermal conductivity of the heat insulating layer. The sidewall protection layer can maintain the heat required for the operation of the storage unit, and the heat conducting structure forms a heat conducting channel between the sidewall protection layer and the heat insulating layer, thereby reducing the diffusion of heat between laterally adjacent storage units and reducing thermal crosstalk between adjacent storage units. The heat insulating layer can further isolate the heat between adjacent storage units, thereby further reducing thermal crosstalk and improving the stability of the read and write process. Since the heat diffusion capacity is increased, the problem of thermal crosstalk caused by heat accumulation is effectively solved, so the plane size can be reduced to increase the storage density.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] Phase Change Memory (PCM) is based on 3D crosspoint (3D Xpoint) technology. With its higher capacity than DRAM and lower latency and addressing capability than NAND, it has become one of the most promising and promising candidates in the field of non-volatile memory.

[0003] However, thermal crosstalk is easily generated between adjacent memory cells during read and write operations, thereby affecting the read and write operations. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor device and a method for forming the same, which can reduce heat diffusion to reduce thermal crosstalk between adjacent storage cells, so as to at least partially solve the above-mentioned technical problems.

[0005] An embodiment of the present application provides a semiconductor device, comprising: a plurality of discrete storage units; a sidewall protection layer located on the sidewalls of the storage units; a thermal insulation layer located between adjacent storage units; and a thermally conductive structure located between the sidewall protection layer and the thermal insulation layer, wherein the thermal conductivity of the thermally conductive structure is greater than the thermal conductivity of the thermal insulation layer.

[0006] In some embodiments, the thermal conductivity of the heat-conducting structure is greater than the thermal conductivity of the sidewall protection layer.

[0007] In some embodiments, the thermal conductivity of the heat-conducting structure is greater than 1 W / (m·K), and the thermal conductivity of the heat-insulating layer is 0 W / (m·K) to 1 W / (m·K).

[0008] In some embodiments, the thermal conductivity of the thermally conductive structure is greater than or equal to 50 W / (m·K).

[0009] In some embodiments, the material of the thermal conductive structure includes at least one of aluminum nitride and beryllium oxide.

[0010] In some embodiments, the viscosity of the thermal insulation layer material is lower than the viscosity of the thermal conductive structure material.

[0011] In some embodiments, it also includes a first address line and a second address line, and the storage unit is located between the first address line and the second address line; the heat conductive structure includes a first end and a second end opposite to each other, the first end contacts the first address line, and the second end contacts the second address line.

[0012] In some embodiments, the thermal insulation layer includes a third end and a fourth end opposite to each other, the thermal conductive structure connects the third end and the first address line, and / or the thermal conductive structure connects the fourth end and the second address line.

[0013] In some embodiments, the storage units are arranged in an array along a first direction and a second direction, the sidewall protection layer includes a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, the first sidewall and the second sidewall are located on both sides of the storage unit along the first direction, and the third sidewall and the fourth sidewall are located on both sides of the storage unit along the second direction; the heat conductive structure covers at least one of the first sidewall, the second sidewall, the third sidewall and the fourth sidewall.

[0014] An embodiment of the present application also provides a method for forming a semiconductor device, comprising: forming a plurality of discrete storage units; forming a sidewall protection layer on the sidewalls of the storage units; forming a heat-conducting structure on the sidewalls of the sidewall protection layer; forming a heat-insulating layer between adjacent storage units, the heat-conducting structure being located between the sidewall protection layer and the heat-insulating layer, and the thermal conductivity of the heat-conducting structure being greater than the thermal conductivity of the heat-insulating layer.

[0015] In the semiconductor device of the embodiment of the present application, the sidewall protection layer can maintain the heat required for the operation of the storage unit, and the heat-conducting structure forms a heat-conducting channel between the sidewall protection layer and the heat-insulating layer, so that the heat diffused from the sidewall protection layer is conducted out through the heat-conducting structure, thereby reducing the diffusion of heat between laterally adjacent storage units, quickly reducing the temperature of the medium between adjacent storage units, and reducing the thermal crosstalk between adjacent storage units. In addition, the heat-insulating layer outside the heat-conducting structure can further isolate the heat between adjacent storage units, thereby further reducing thermal crosstalk and improving the stability of the reading and writing process.

[0016] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0018] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0019] Figure 1is a schematic diagram of a cross-sectional structure of a semiconductor device along the XZ direction provided by some embodiments of the present application;

[0020] Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor device along the YZ direction;

[0021] Figure 3 is a schematic diagram of a cross-sectional structure of a semiconductor device along the XZ direction provided by some embodiments of the present application;

[0022] Figure 4 is a schematic diagram of a top view of a semiconductor device along the XY direction provided by some embodiments of the present application;

[0023] Figure 5 is a schematic diagram of a top view of a semiconductor device along the XY direction provided by some embodiments of the present application;

[0024] Figure 6 is a schematic flow chart of a method for forming a semiconductor device provided in some embodiments of the present application;

[0025] Figure 7 to Figure 13 It is a schematic diagram of the structure of a semiconductor device during the formation process provided by some embodiments of the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0027] Taking the 3D cross-point memory including the phase change layer and the gating layer as an example, the material of the phase change layer mainly includes chalcogenide based on Ge-Sb-Te (GST), and the material of the gating layer mainly includes OTS material based on chalcogenide. By controlling the waveform of the voltage and current pulse of the write operation and the temperature curve of the GST material, the amorphous state (high threshold voltage) and the crystalline state (low threshold voltage) are matched to record data.

[0028] The storage density of existing 3D cross-point technology is improved mainly by increasing the number of stacks and reducing the plane size. However, the reduction of the plane size will reduce the distance between adjacent storage cells, making the impact of thermal crosstalk more serious, restricting the further improvement of the storage density of phase change memory. In addition, continuous high-speed writing or reading will also cause continuous accumulation of heat, making the thermal crosstalk of adjacent storage cells and operating storage cells more serious.

[0029] The phase change of the phase change layer material requires a high amount of heat to occur. In the traditional process, only low thermal conductivity materials are used between adjacent storage cells to reduce heat diffusion and prevent thermal crosstalk between adjacent storage cells. However, since the heat cannot be diffused, it accumulates, which aggravates the impact of thermal crosstalk.

[0030] Based on the above reasons, an embodiment of the present application provides a semiconductor device, comprising: a plurality of discrete storage units; a sidewall protection layer located on the sidewalls of the storage units; a thermal insulation layer located between adjacent storage units; and a thermally conductive structure located between the sidewall protection layer and the thermal insulation layer, wherein the thermal conductivity of the thermally conductive structure is greater than the thermal conductivity of the thermal insulation layer.

[0031] The side wall protection layer can maintain the heat required for the operation of the storage unit. The heat-conducting structure forms a heat-conducting channel between the side wall protection layer and the heat-insulating layer, so that the heat diffused from the side wall protection layer is conducted out through the heat-conducting structure. Therefore, the heat diffusion between the adjacent storage units can be reduced, and the temperature of the medium between the adjacent storage units can be quickly reduced, and the thermal crosstalk between the adjacent storage units can be reduced. In addition, the heat-insulating layer outside the heat-conducting structure can further isolate the heat between the adjacent storage units, thereby further reducing the thermal crosstalk and improving the stability of the reading and writing process. Since the heat diffusion capacity is increased, the thermal crosstalk problem caused by heat accumulation is effectively solved, so the plane size can be reduced to increase the storage density.

[0032] The semiconductor device provided in the embodiments of the present application is described below with reference to the accompanying drawings.

[0033] See also Figure 1 and Figure 2 , Figure 1 is a schematic diagram of a cross-sectional structure of a semiconductor device along the XZ direction provided by some embodiments of the present application, Figure 2 yes Figure 1 Schematic diagram of the cross-sectional structure of the semiconductor device along the YZ direction. X represents the first direction, Y represents the second direction, and Z represents the third direction. The first direction X and the second direction Y are both perpendicular to the third direction Z, and the first direction X and the second direction Y are different. The angle between the first direction X and the second direction Y can be 85° to 95°, for example, the angle between the first direction X and the second direction Y is 90°, that is, the first direction X, the second direction Y and the third direction Z are perpendicular to each other.

[0034] The semiconductor device 100 includes a plurality of mutually independent storage units 10, a sidewall protection layer 20, a heat insulating layer 30 and a heat conducting structure 40. The sidewall protection layer 20 is located on the sidewall of the storage unit 10, the heat insulating layer 30 is located between adjacent storage units 10, the heat conducting structure 40 is located between the sidewall protection layer 20 and the heat insulating layer 30, and the heat conductivity of the heat conducting structure 40 is greater than the heat conductivity of the heat insulating layer 30.

[0035] The semiconductor device 100 further includes a first address line 50 and a second address line 60 , and the memory cell 10 is located between the first address line 50 and the second address line 60 .

[0036] For example, the first address line 50 and the second address line 60 are respectively located on both sides of the memory cell 10 along the third direction, and one of the first address line 50 and the second address line 60 is a bit line and the other is a word line. The first address line 50 and the second address line 60 cross in different planes, for example, the first address line 50 extends along the second direction Y, and the second address line 60 extends along the first direction X.

[0037] like Figure 1 and Figure 2 As shown, the first address line 50 is located below the second address line 60, that is, the first address line 50 is located on the substrate, and the second address line 60 is located on the side of the first address line 50 away from the substrate. The first address line 50 can be a bit line, and the second address line 60 can be a word line.

[0038] The plurality of memory cells 10 are located between the first address line 50 and the second address line 60 . The plurality of memory cells 10 are arranged in an array along the first direction X and the second direction Y. One memory cell 10 is located at the intersection of one first address line 50 and one second address line 60 .

[0039] Taking the phase change memory as an example, a memory cell 10 may include a first electrode 11, a gating layer 12, a second electrode 13, a phase change memory layer 14, and a third electrode 15. The materials of the first electrode 11, the second electrode 13, and the third electrode 15 may be the same, and may include carbon, and the material of the gating layer 12 may include ZnxTey, GexTey, NbxOy, SixAsy, AsxTey, etc. The material of the phase change memory layer 14 may include materials such as chalcogenide-based materials, which include any one of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te) forming Group VIA of the periodic table.

[0040] Taking the select-only memory as an example, one memory cell 10 may include a first electrode 11 , a gate layer 12 and a second electrode 13 .

[0041] The sidewall protection layer 20 can be located on the sidewalls of the storage unit 10 opposite to each other along the first direction X and the sidewalls of the storage unit 10 opposite to each other along the second direction Y, that is, the sidewall protection layer 20 can be arranged around the sidewalls of the storage unit 10. The sidewall protection layer 20 can protect the sidewalls of the storage unit 10 in subsequent process steps to reduce damage.

[0042] For example, the sidewall protection layer 20 includes a first side wall 21, a second side wall 22, a third side wall 23 and a fourth side wall 24, the first side wall 21 and the second side wall 22 are located on both sides of the storage unit 10 along the first direction X, and the third side wall 23 and the fourth side wall 24 are located on both sides of the storage unit 10 along the second direction Y.

[0043] In some embodiments, the heat conducting structure 40 covers at least one of the first side wall 21 , the second side wall 22 , the third side wall 23 , and the fourth side wall 24 .

[0044] In some embodiments, the sidewall protection layer 20 may be a single layer or a multi-layer structure. The single layer structure includes a single insulating layer, such as an oxide layer or a nitride layer. The multi-layer structure includes multiple insulating layers stacked on the sidewall of the memory cell 10, such as two, three or four insulating layers, wherein the four insulating layers may be an oxide layer / nitride layer / oxide layer / nitride layer.

[0045] The heat insulating layer 30 is not only located between adjacent memory cells 10 , but also located between the first address line 50 and the second address line 60 .

[0046] For example, the thermal insulation layer 30 includes an opposite third end portion 31 (eg Figure 2 as shown) and the fourth end 32 (as shown Figure 1 As shown), the third end 31 is connected to the first address line 50, and the fourth end 32 is connected to the second address line 60.

[0047] The heat insulation layer 30 may include an insulating material, such as at least one of silicon oxide, silicon nitride, and aluminum oxide.

[0048] In some embodiments, the viscosity of the insulation layer 30 material is lower than the viscosity of the sidewall protection layer 20 material. For example, the insulation layer 30 material includes an organic insulating material of carbon, oxygen and silicon, so that the insulation layer 30 material has a lower viscosity before curing and is easy to fill.

[0049] The "viscosity" of a material refers to its ability to deform under stress and how quickly it returns to its original shape. Viscosity is a physical property of a material that describes its deformation behavior under stress. Materials with high viscosity will deform more when subjected to stress and will recover more slowly, while materials with low viscosity will deform less when subjected to stress and will recover quickly. Low-viscosity materials have good fluidity before solidification and are easy to fill.

[0050] In some embodiments, the viscosity of the heat insulation layer 30 material is lower than that of the heat conductive structure 40 material, so that the heat insulation layer 30 material is easy to fill before curing. For example, the heat insulation layer 30 material includes an organic insulating material of carbon, oxygen and silicon, and the heat conductive structure 40 material includes at least one of aluminum nitride and beryllium oxide.

[0051] The thermal conductivity of the heat-conducting structure 40 is not only greater than the thermal conductivity of the heat-insulating layer 30, but also greater than the thermal conductivity of the sidewall protection layer 20. Therefore, the sidewall protection layer 20 can store a certain amount of heat for the operation of the storage unit 10, so that the storage unit 10 reaches a certain temperature in the operating state. The thermal conductivity of the heat-conducting structure 40 is the largest, and a heat-conducting channel is formed between the sidewall protection layer 20 and the heat-insulating layer 30 to conduct the heat diffused from the sidewall protection layer 20 longitudinally. The heat-insulating layer 30 can further isolate the heat diffused by the heat-conducting structure 40 in the lateral direction, so that the heat diffusion between adjacent storage units 10 can be further reduced, and the thermal crosstalk between adjacent storage units 10 can be further reduced.

[0052] In some embodiments, the thermal conductivity of the heat-conducting structure 40 is greater than 1W / (m·K), and the thermal conductivity of the heat-insulating layer 30 is 0W / (m·K) to 1W / (m·K). The thermal conductivity greater than 1W / (m·K) enables the heat-conducting structure 40 to have good thermal conductivity, and the thermal conductivity of 0W / (m·K) to 1W / (m·K) enables the heat-insulating layer 30 to have good isolation capability, further reducing thermal crosstalk between adjacent storage units 10.

[0053] In some embodiments, the thermal conductivity of the thermal conductive structure 40 is greater than or equal to 50 W / (m·K). Such a thermal conductive structure 40 with high thermal conductivity can quickly reduce the temperature of the medium between adjacent storage units 10 and reduce thermal crosstalk between adjacent storage units 10 .

[0054] For example, the material of the heat-conducting structure 40 includes at least one of aluminum nitride and beryllium oxide. The thermal conductivity of aluminum nitride is 70W / (m·K) to 180W / (m·K), and the thermal conductivity of beryllium oxide is 250W / (m·K) to 300W / (m·K), for example, the thermal conductivity of beryllium oxide is 270W / (m·K). Therefore, aluminum nitride and beryllium oxide can both have a very good heat dissipation effect.

[0055] It is understandable that materials of the heat-conducting structure 40 having a thermal conductivity greater than that of the heat-insulating layer 30 are all within the protection scope of the present application, and a greater thermal conductivity indicates a better thermal conductivity of the heat-conducting structure 40 .

[0056] It should be noted that, in order to reduce leakage between adjacent memory cells 10, the sidewall protection layer 20, the heat conducting structure 40 and the heat insulating layer 30 are all made of insulating materials, wherein the resistivity of aluminum nitride and beryllium oxide is greater than 10^14 ohm·cm.

[0057] like Figure 1 As shown, the heat-conducting structure 40 is located on two opposite sides of the storage unit 10 along the first direction X, that is, the heat-conducting structure 40 is located on the first side wall 21 and the second side wall 22 of the side wall protection layer 20. Therefore, the heat of each storage unit 10 can be conducted away from the heat-conducting structure 40.

[0058] like Figure 2 As shown, the heat-conducting structure 40 is also located on two opposite sides of the storage unit 10 along the second direction Y, that is, the heat-conducting structure 40 is located on four side walls (including the first side wall 21, the second side wall 22, the third side wall 23 and the fourth side wall 24) of the side wall protection layer 20. Thus, the relative area between the heat-conducting structure 40 and the storage unit 10 can be increased, and the heat diffusion capacity can be improved.

[0059] In some embodiments, Figure 1 As shown, the dimension of the heat-conducting structure 40 along the third direction may be greater than or equal to the dimension of the storage unit 10 along the third direction, ensuring that the first side wall 21 and the second side wall 22 are completely covered by the heat-conducting structure 40 to improve the heat diffusion effect.

[0060] In some embodiments, the heat-conducting structure 40 includes a first end 41 and a second end 42 opposite to each other, the first end 41 contacts the first address line 50, and the second end 42 contacts the second address line 60. The material of the first address line 50 and the second address line 60 is generally metal, and the heat-conducting structure 40 can conduct heat to the first address line 50 and the second address line 60, and then conduct heat out through the first address line 50 and the second address line 60, that is, the first address line 50 and the second address line 60 are used to assist heat dissipation.

[0061] See also Figure 3 , Figure 3 1 is a schematic diagram of a cross-sectional structure of a semiconductor device along the XZ direction provided by some embodiments of the present application. For ease of understanding and brief description, the same reference numerals are used for the same structures as those in the above embodiments, and the same structures are not described in detail. Only the different structures are described in detail in this embodiment.

[0062] This embodiment and Figure 1 The difference between the embodiments is that the thermal conductive structure 40 is also present between at least one end of the thermal insulation layer 30 and the address line, that is, the thermal conductive structure 40 covers at least one end of the thermal insulation layer 30, which can increase the contact area between the thermal conductive structure 40 and the address line, thereby improving the heat diffusion capacity.

[0063] because Figure 3 It is a cross-sectional structure in the XZ direction, so the first address line 50 is not shown, and the third end 31 connected to the first address line 50 is not shown. The third end 31 can be referred to Fig.13 .

[0064] In some embodiments, the thermal conductive structure 40 connects the third end 31 and the first address line 50 , and / or the thermal conductive structure 40 connects the fourth end 32 and the second address line 60 .

[0065] In other words, the heat-conducting structure 40 is also located between the third end 31 and the first address line 50; or the heat-conducting structure 40 is also located between the fourth end 32 and the second address line 60 (eg Figure 3 or the thermal conductive structure 40 is also located between the third end 31 and the first address line 50, and between the fourth end 32 and the second address line 60.

[0066] like Figure 3 As shown, the heat-conducting structure 40 is not only located on both sides of the storage unit 10 along the first direction X, but also between the fourth end 32 and the second address line 60, so that the contact area between the heat-conducting structure 40 and the second address line 60 can be increased, thereby improving the heat diffusion capability.

[0067] In some embodiments, reference may be made to Fig.13 The heat-conducting structure 40 is not only located on both sides of the storage unit 10 along the second direction Y, but also between the third end 31 and the first address line 50, so that the contact area between the heat-conducting structure 40 and the first address line 50 can be increased, thereby improving the heat diffusion capability.

[0068] In some embodiments, the heat conducting structure 40 is not only located on the four sidewalls of the sidewall protection layer 20 , but also located between the third end 31 and the first address line 50 , and between the fourth end 32 and the second address line 60 .

[0069] See also Figure 4 , Figure 41 is a schematic diagram of a top view of a semiconductor device along the XY direction provided by some embodiments of the present application. For ease of understanding and brief description, the same reference numerals are used for the same structures as those in the above embodiments, and the same structures are not described in detail. Only the different structures are described in detail in this embodiment. It should be noted that in order to show the storage unit 10, the sidewall protection layer 20, the heat insulation layer 30 and the heat conducting structure 40, Figure 4 The top view of FIG. 1 omits the second address line 60 .

[0070] This embodiment and Figure 1 and Figure 2 The same as the embodiment is that the heat-conducting structure 40 is located on two opposite sides of the storage unit 10 along the first direction X, that is, the heat-conducting structure 40 is located on the first side wall 21 and the second side wall 22. Figure 1 and Figure 2 The difference between the embodiments is that two opposite sides of the storage unit 10 along the second direction Y (ie, the third side wall 23 and the fourth side wall 24 ) are covered with a side wall protection layer 20 and a heat insulation layer 30 , but without a heat conducting structure 40 .

[0071] See also Figure 5 , Figure 5 1 is a schematic diagram of a top view of a semiconductor device along the XY direction provided by some embodiments of the present application. For ease of understanding and brief description, the same reference numerals are used for the same structures as those in the above embodiments, and the same structures are not described in detail. Only the different structures are described in detail in this embodiment. It should be noted that in order to show the storage unit 10, the sidewall protection layer 20, the heat insulation layer 30 and the heat conducting structure 40, Figure 4 The top view of FIG. 1 omits the second address line 60 .

[0072] This embodiment and Figure 1 and Figure 2 The same as the embodiment is that the heat-conducting structure 40 is located on two opposite sides of the storage unit 10 along the second direction Y, that is, the heat-conducting structure 40 is located on the third side wall 23 and the fourth side wall 24. Figure 1 and Figure 2 The difference between the embodiments is that two opposite sides of the storage unit 10 along the first direction X (ie, the first side wall 21 and the second side wall 22 ) are covered with a side wall protection layer 20 and a heat insulation layer 30 , but without a heat conducting structure 40 .

[0073] In the semiconductor device 100 of the embodiment of the present application, the sidewall protection layer 20 can maintain the heat required for the operation of the storage unit 10, and the heat-conducting structure 40 forms a heat-conducting channel between the sidewall protection layer 20 and the heat-insulating layer 30, so that the heat diffused from the sidewall protection layer 20 is conducted out through the heat-conducting structure 40, thereby reducing the diffusion of heat between the laterally adjacent storage units 10, quickly reducing the temperature of the medium between the adjacent storage units 10, and reducing the thermal crosstalk between the adjacent storage units 10. In addition, the heat-insulating layer 30 outside the heat-conducting structure 40 can further isolate the heat between the adjacent storage units 10, thereby further reducing the thermal crosstalk and improving the stability of the reading and writing process.

[0074] Correspondingly, an embodiment of the present application also provides a method for forming a semiconductor device.

[0075] See 6, Figure 6 The present invention provides a flow chart of a method for forming a semiconductor device according to some embodiments of the present invention. The method for forming a semiconductor device includes the following steps S1 to S6.

[0076] Step S1: forming a first address line;

[0077] Step S2: forming a plurality of discrete storage units on the first address line;

[0078] Step S3: forming a sidewall protection layer on the sidewall of the storage unit;

[0079] Step S4: forming a heat-conducting structure on the side wall of the side wall protection layer;

[0080] Step S5: forming a heat insulating layer between adjacent storage units, wherein the heat conducting structure is located between the side wall protection layer and the heat insulating layer, and the thermal conductivity of the heat conducting structure is greater than the thermal conductivity of the heat insulating layer 30;

[0081] Step S6: forming a second address line on a side of the storage unit away from the first address line.

[0082] Please combine Figure 7 to Figure 13 , Figure 7 to Figure 13 1 is a schematic diagram of the structure of the semiconductor device provided in some embodiments of the present application during the formation process. In the semiconductor device formed in the embodiment of the present application, the heat conduction structure 40 is not only located on the four side walls of the side wall protection layer 20, but also between the third end 31 and the first address line 50, and between the fourth end 32 and the second address line 60.

[0083] Step S1: forming a first address line 50. Figure 7 .

[0084] The method for forming the first address lines 50 includes: providing a substrate 1, forming a first conductive layer on the substrate 1; and etching the first conductive layer to form a plurality of first address lines 50. The first address lines 50 extend along the second direction Y and are arranged at intervals along the first direction X.

[0085] Step S2: forming a plurality of separate storage units 10 on the first address line 50. Figure 7 , Figure 11-12 .

[0086] See also Figure 7 , forming an initial storage stack on the first conductive layer; etching the initial storage stack to form a storage stack 10, wherein the storage stack 10 extends along the second direction Y. The initial storage stack 10a includes, from bottom to top, a first electrode layer 11a, a gating material layer 12a, a second electrode layer 13a, a phase change material layer 14a and a third electrode layer 15a.

[0087] In some embodiments, the etching process of the initial memory stack 10 a and the etching process of the first conductive layer may be performed in one etching process.

[0088] See also Fig.11 and Fig.12 , the memory stack 10 is etched to form a plurality of memory cells 10 separated from each other. Wherein, one memory stack 10 is etched to form a plurality of memory cells 10 arranged at intervals along the second direction Y.

[0089] Step S3: forming a sidewall protection layer 20 on the sidewall of the memory cell 10. Figure 7 and Fig.12 .

[0090] See also Figure 7 A first sidewall protection layer 201 is formed on the sidewalls of the storage stack 10 opposite to each other along the first direction X.

[0091] See also Fig.12 A second sidewall protection layer 202 is formed on the sidewall of the storage unit 10 along the second direction Y. The first sidewall protection layer 201 and the second sidewall protection layer 202 form the sidewall protection layer 20 .

[0092] The process of forming the first sidewall protection layer 201 and the second sidewall protection layer 202 includes but is not limited to chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) such as thermal oxidation, evaporation, sputtering and other methods.

[0093] Step S4: forming a heat conducting structure 40 on the side wall of the side wall protection layer 20. Figure 8-Figure 9 and Fig.13 .

[0094] See also Figure 8 , a first heat conducting structure 401 is formed on the sidewall of the first sidewall protection layer 201 and the surface of the substrate 1 ; after the first heat insulating layer 301 is formed below, the first heat insulating layer 301 is etched back to form a first groove T1 .

[0095] See also Fig. 9 A second heat conducting structure 402 connected to the first heat conducting structure 401 is formed in the first groove T1.

[0096] See also Fig.13 A third heat-conducting structure 403 is formed on the side wall of the second sidewall protection layer 202 and the surface of the first address line 50; after the second heat-insulating layer 302 is formed below, the second heat-insulating layer 302 is back-etched to form a second groove; and a fourth heat-conducting structure 404 connected to the first heat-conducting structure 401 is formed in the second groove.

[0097] The first heat-conducting structure 401, the second heat-conducting structure 402, the third heat-conducting structure 403 and the fourth heat-conducting structure 404 together form a heat-conducting structure 40. The formation process of the first heat-conducting structure 401, the second heat-conducting structure 402, the third heat-conducting structure 403 and the fourth heat-conducting structure 404 includes but is not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition (Atom Layer Deposition, ALD), physical vapor deposition (Physical Vapor Deposition, PVD) such as thermal oxidation, evaporation, sputtering and other methods.

[0098] The sidewall protection layer 20 includes a first sidewall 21, a second sidewall 22, a third sidewall 23 and a fourth sidewall 24. The first sidewall 21 and the second sidewall 22 are located on both sides of the storage stack 10 along the first direction X (eg Fig.10 The third side wall 23 and the fourth side wall 24 are located on both sides of the storage unit 10 along the second direction Y (as shown in FIG. Fig.13 The heat insulation layer 30 includes a third end 31 and a fourth end 32 opposite to each other, and the third end 31 is indirectly connected to the first address line 50 (as shown in FIG. Fig.13 The fourth end 32 is indirectly connected to the second address line 60 (as shown in Fig.10 shown).

[0099] In some embodiments, Fig.10 As shown, the heat conducting structure 40 is located at the first side wall 21 and the second side wall 22 . The heat conducting structure 40 may also be located between the fourth end 32 and the second address line 60 .

[0100] In some embodiments, Fig.13 As shown, the heat conducting structure 40 is located on the third side wall 23 and the fourth side wall 24 . The heat conducting structure 40 may also be located between the third end 31 and the first address line 50 .

[0101] Step S5: forming a heat insulating layer 30 between adjacent storage units 10, wherein the heat conducting structure 40 is located between the side wall protection layer 20 and the heat insulating layer 30, and the heat conductivity of the heat conducting structure 40 is greater than the heat conductivity of the heat insulating layer 30. Figure 8 and Fig.13 .

[0102] See also Figure 8 , a first thermal insulation layer 301 is formed between adjacent storage stacks 10 .

[0103] See also Fig.13 , a second heat insulation layer 302 is formed between the memory cells 10 adjacent to each other along the second direction Y.

[0104] The first thermal insulation layer 301 and the second thermal insulation layer 302 form the thermal insulation layer 30 , and the process of forming the first thermal insulation layer 301 and the second thermal insulation layer 302 includes a spin coating process.

[0105] Step S6: forming a second address line 60 on a side of the memory cell 10 away from the first address line 50. Fig.10 and Fig.12 .in, Fig.11 Show Fig.10 Cross-sectional structure of the semiconductor device at A-A1.

[0106] See also Fig.10 and 11 , a second conductive layer 60 a is formed on a side of the memory stack 10 away from the first address line 50 .

[0107] See also Fig.12 , the second conductive layer 60a is etched to form a plurality of second address lines 60. The second address lines 60 extend along the first direction X and are arranged in a second direction Y at intervals.

[0108] In some embodiments, the etching process of the second conductive layer 60 a and the etching process of the memory stack 10 may be performed in one etching process.

[0109] The method for forming a semiconductor device provided in an embodiment of the present application can form a partial heat-conducting structure 40 between adjacent storage stacks 10 after forming and etching the initial storage stack 10a to form the storage stack 10, and / or form a partial heat-conducting structure 40 between adjacent storage cells 10 along the second direction Y after etching the storage stack 10 to form the storage unit 10, so that the heat-conducting structure 40 can be formed on at least part of the sidewall of the sidewall protection layer 20 of each storage unit 10, so that the heat-conducting structure 40 can conduct away the heat diffused from the sidewall protection layer 20 of all storage units 10, thereby reducing the diffusion of heat between laterally adjacent storage units 10, quickly reducing the temperature of the medium between adjacent storage units 10, and reducing the thermal crosstalk between adjacent storage units 10. In addition, the heat-insulating layer 30 outside the heat-conducting structure 40 can further isolate the heat between adjacent storage units 10, thereby further reducing the thermal crosstalk and improving the stability of the read and write process. Since the heat diffusion capacity is increased, the thermal crosstalk problem caused by heat accumulation is effectively solved, so the plane size can be reduced to improve the storage density.

[0110] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0111] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0112] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0113] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A semiconductor device, characterized in that: include: A plurality of discrete storage units; A side wall protection layer, located on the side wall of the storage unit; A heat-insulating layer, located between adjacent storage units; The heat-conducting structure is located between the side wall protection layer and the heat-insulating layer, and the thermal conductivity of the heat-conducting structure is greater than the thermal conductivity of the heat-insulating layer.

2. The semiconductor device according to claim 1, wherein: The thermal conductivity of the heat-conducting structure is greater than the thermal conductivity of the sidewall protection layer.

3. The semiconductor device according to claim 1, wherein: The thermal conductivity of the heat-conducting structure is greater than 1 W / (m·K), and the thermal conductivity of the heat-insulating layer is 0 W / (m·K) to 1 W / (m·K).

4. The semiconductor device according to claim 3, characterized in that The thermal conductivity of the heat-conducting structure is greater than or equal to 50 W / (m·K).

5. The semiconductor device according to claim 4, characterized in that The material of the heat-conducting structure includes at least one of aluminum nitride and beryllium oxide.

6. The semiconductor device according to claim 1, wherein: The viscosity of the heat insulation layer material is lower than the viscosity of the heat conductive structure material.

7. The semiconductor device according to claim 1, wherein: Also comprising a first address line and a second address line, wherein the storage unit is located between the first address line and the second address line; The thermally conductive structure includes a first end portion and a second end portion opposite to each other, the first end portion being in contact with the first address line, and the second end portion being in contact with the second address line.

8. The semiconductor device according to claim 7, characterized in that The heat insulating layer includes a third end and a fourth end opposite to each other, the heat conducting structure connects the third end and the first address line, and / or the heat conducting structure connects the fourth end and the second address line.

9. The semiconductor device according to claim 1, wherein: The storage units are arranged in an array along a first direction and a second direction, the side wall protection layer includes a first side wall, a second side wall, a third side wall and a fourth side wall, the first side wall and the second side wall are located on both sides of the storage unit along the first direction, and the third side wall and the fourth side wall are located on both sides of the storage unit along the second direction; the heat conductive structure covers at least one of the first side wall, the second side wall, the third side wall and the fourth side wall.

10. A method for forming a semiconductor device, characterized in that: include: Forming a plurality of mutually discrete storage units; forming a sidewall protection layer on the sidewall of the storage unit; forming a heat-conducting structure on the side wall of the side wall protection layer; A heat insulating layer is formed between adjacent storage units, the heat conducting structure is located between the side wall protection layer and the heat insulating layer, and the heat conductivity of the heat conducting structure is greater than the heat conductivity of the heat insulating layer.

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