Three-dimensional memory array, memory and electronic equipment

Abstract

A three-dimensional memory array (31), a memory (300), a method of forming a memory array, and an electronic device. Relates to the technical field of semiconductor memories. The method is mainly used for improving the integration density of the storage unit (400) and simplifying the preparation method. The memory (300) comprises a substrate (100) and a plurality of memory layers (501, 502, 503), each memory layer (501, 502, 503) comprises a first metal layer (50A1) and a second metal layer (50A2) which are stacked in the direction perpendicular to the substrate (100), and the first metal layer (50A1) and the second metal layer (50A2) are electrically isolated by a dielectric layer (51); one storage unit (400) in each storage layer (501, 502, 503) comprises a transistor (Tr) and a capacitor (C), that is, the transistor (Tr) and the capacitor (C) in the storage unit (400) are integrated in a first metal layer (50A1), a dielectric layer (51) and a second metal layer (50A2) which are stacked. The storage array (31) can reduce the area of each storage unit (400) on the basis of realizing three-dimensional integration so as to improve the integration density, and in addition, the process is not greatly challenged.

Description

Three-dimensional storage array, memory and electronic device Technical Field

[0001] The present application relates to the field of semiconductor memory technology, and in particular to a three-dimensional memory array, a memory including the three-dimensional memory array, a method for forming a three-dimensional memory array, and an electronic device including the memory. Background Art

[0002] With the continuous advancement of integrated circuit technology, the number of transistors per unit area on chips in electronic devices such as computers and mobile phones continues to increase, thereby continuously optimizing the performance of these devices. For example, dynamic random access memory (DRAM), a memory structure that temporarily stores computational data for the central processing unit (CPU), continues to improve. To keep pace with processor speeds, the read and write speeds of DRAM are constantly increasing, leading to a continuous increase in storage density to meet the data processing needs of the information age.

[0003] As memory develops towards higher density and larger bandwidth, many types of memory cells have been developed, such as 1T1C memory cells or 1TnC memory cells, where T stands for transistor and C stands for capacitor.

[0004] While memories are rapidly developing towards high density and high capacity, this has brought challenges and limitations to the process size reduction of memory cells. For example, see Figure 1, which shows the process structure of a planar 1T1C memory cell. The source and drain are formed by doping in the substrate, and the gate and capacitor, as well as the word line (WL), bit line (BL), and plate line (PL) electrode lines are formed on the substrate. The gate is electrically connected to the word line WL, the drain is electrically connected to the bit line BL, and the source is electrically connected to the plate line PL through a capacitor.

[0005] The planar memory cell shown in Figure 1 occupies a large area, limiting the increase in storage density. At the same time, as transistor size shrinks, the projected area of ​​the capacitor on the substrate becomes smaller and smaller. To ensure stable operation of the 1T1C memory, the capacitor needs to be taller (e.g., increasing in size along the P direction shown in Figure 1). As the capacitor height continues to increase and its projected area continues to shrink, the etching process becomes extremely challenging. Therefore, the 2D memory cell shown in Figure 1 will encounter physical size limitations when scaled below 10nm.

[0006] Summary of the Invention

[0007] This application provides a three-dimensional memory array, a memory device including the three-dimensional memory array, a method for forming the three-dimensional memory array, and an electronic device including the memory device. The primary purpose is to provide a three-dimensional memory array structure that not only improves storage density but also poses minimal process challenges.

[0008] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0009] In a first aspect, the present application provides a three-dimensional memory array. For example, the three-dimensional memory array can be used in a dynamic random access memory (DRAM).

[0010] The three-dimensional memory array includes a substrate and multiple memory layers formed on the substrate. The multiple memory layers are stacked in a direction perpendicular to the substrate to form a three-dimensional stacked memory structure. Each memory layer includes multiple memory cells, each memory cell including a transistor and a capacitor electrically connected to the transistor. For example, the memory cell can be a 1T1C memory cell. The transistor includes a first electrode, a second electrode, a gate, and a channel layer. The capacitor includes a first capacitor electrode, a capacitor layer, and a second capacitor electrode. The first electrode of the transistor is electrically connected to the first capacitor electrode. Each memory layer includes a first metal layer and a second metal layer stacked in a direction perpendicular to the substrate. The first metal layer and the second metal layer are electrically isolated by a dielectric layer. The first electrode of the transistor and the capacitor are formed in the first metal layer, and the second electrode of the transistor is formed in the second metal layer. At least a portion of the gate and at least a portion of the channel layer are formed in the dielectric layer, and the channel layer surrounds the periphery of the gate. The first capacitor electrode, the capacitor layer, and the second capacitor electrode are stacked in a direction parallel to the substrate. The capacitor layer surrounds the periphery of the first capacitor electrode, and the second capacitor electrode may surround the periphery of the capacitor layer.

[0011] The memory cell provided in the present application may be a 1T1C memory cell. In the memory cell, the first electrode and the second electrode electrically connected to the channel layer are stacked in the corresponding first metal layer and the second metal layer in a direction perpendicular to the substrate, and the channel layer surrounds the periphery of the gate, that is, the transistor is a field effect transistor with a ring channel structure. In addition, in the capacitor of the memory cell, the capacitor layer surrounds the periphery of the first capacitor electrode, that is, the capacitor is a ring capacitor structure. Compared with the planar 2D memory cell, the present application reduces the size of the memory cell. Therefore, more memory cells can be integrated on a unit area parallel to the substrate to make the integration density of the three-dimensional memory array higher.

[0012] In addition, the integration of transistors and capacitors is achieved by stacking the first metal layer, the dielectric layer, and the second metal layer. Compared with using more metal layers to integrate storage units, the present application can reduce the number of metal layers and achieve 3D stacking of more storage layers to improve the storage density of the memory.

[0013] In addition, in the present application, the capacitor is a ring capacitor structure. Compared with the columnar capacitor extending in a direction perpendicular to the substrate in the related art, the ring capacitor structure not only increases the storage capacity, but also does not pose a major challenge to the etching process, thereby making the storage array a high-density, large-storage, low-cost storage array.

[0014] In addition, when preparing the memory array provided by the present application, multiple dielectric layers can be stacked first, and then processing can be performed on these stacked dielectric layer structures to simultaneously process multiple memory layers. For example, when stacking seven dielectric layers, two memory layers can be produced simultaneously after completing one processing step. In other words, the multiple memory layers of the present application can be processed simultaneously, i.e., a multi-layer device can be formed at one time, without having to first produce the first memory layer and then use the same process to produce the second memory layer, the third memory layer, etc. layer by layer. In this way, from a process perspective, the process flow can be simplified and manufacturing costs can be reduced. In particular, for memory arrays with a large number of three-dimensional stacked layers, the process complexity and manufacturing costs will be significantly reduced. In addition, the phenomenon of poor memory cell alignment accuracy caused by producing the memory layers layer by layer can be avoided.

[0015] In one possible implementation, one end of the gate extends into the first metal layer, the first electrode surrounds the periphery of the gate, and is electrically isolated from the gate by the gate dielectric layer; the other end of the gate extends into the second metal layer, the second electrode surrounds the periphery of the gate, and is electrically isolated from the gate by the gate dielectric layer.

[0016] From a process perspective, it is easy to manufacture the gate structure. For example, a through hole can be penetrated in a multi-layer stacked dielectric layer, and a columnar gate structure can be formed in the through hole.

[0017] In a possible implementation, one end of the channel layer extends into the second metal layer, and the second electrode surrounds the periphery of the channel layer.

[0018] Since the channel layer surrounding the gate extends into the metal layer where the second electrode is located, so that the second electrode surrounds the channel, the contact area between the second electrode and the channel layer can be increased, thereby achieving a larger area of ​​electrical contact, suppressing the increase of leakage current, and lowering electron mobility.

[0019] In a possible implementation, the other end of the channel layer extends into the first metal layer; the first pole and the first capacitor electrode share the same electrode; and the first capacitor electrode surrounds the periphery of the channel layer.

[0020] Similar to the position of the channel layer and the second electrode described above, the channel layer can also extend into the metal layer where the first electrode of the transistor is located, so that the first electrode surrounds the outer periphery of the channel layer. Similarly, a larger area of ​​electrical contact between the channel and the electrode is achieved, which suppresses the increase of leakage current and reduces electron mobility.

[0021] In addition, the first electrode of the transistor and the first capacitance electrode of the capacitor share the same electrode, which can simplify the process structure of the memory cell.

[0022] In one possible implementation, the channel layer located in the dielectric layer includes a surrounding channel and a first planar channel connected to the surrounding channel, the first planar channel is parallel to the substrate; the surrounding channel surrounds the periphery of the gate; and the surface of the second pole facing the first pole contacts the first planar channel.

[0023] In this embodiment, the channel layer includes not only a surrounding channel surrounding the periphery of the gate, but also a planar channel parallel to the substrate, thereby increasing the contact area with the second electrode.

[0024] In a possible implementation, the channel layer in the dielectric layer further includes a second planar channel parallel to the substrate and opposite to the first planar channel, the first planar channel and the second planar channel are connected via a surrounding channel; the second planar channel contacts the first pole.

[0025] In addition to the first planar channel in ohmic contact with the second electrode, the channel layer also includes a second planar channel in ohmic contact with the first electrode, so as to increase the ohmic contact area between the channel layer and the first electrode of the transistor.

[0026] In one possible implementation, the first capacitor electrode includes a surrounding electrode surrounding the periphery of the gate, and a planar electrode connected to the surrounding electrode and arranged parallel to the substrate, so that the first capacitor electrode forms a horizontal contact surface parallel to the substrate and a vertical contact surface perpendicular to the substrate, and a capacitor layer is formed on both the horizontal contact surface and the vertical contact surface.

[0027] By designing the first capacitor electrode to include not only a vertical contact surface in contact with the capacitor layer but also a horizontal contact surface in contact with the capacitor layer, the capacitor area of ​​the capacitor layer can be increased to improve the capacitor capacity, thereby improving the storage performance of the storage unit.

[0028] In one possible implementation, the planar electrode includes a first planar electrode and a second planar electrode arranged opposite to each other, and the first planar electrode and the second planar electrode are connected by a surrounding electrode so that a groove with an opening is formed in the first capacitor electrode, and the opening of the groove faces away from the gate. The capacitor layer and the second capacitor electrode are sequentially arranged on the inner wall surface of the groove to form a capacitor layer having a first notch and the first notch facing away from the gate.

[0029] In this embodiment, the planar electrode is designed to include a first planar electrode and a second planar electrode, thereby increasing the capacitance area of ​​the capacitance layer.

[0030] In one possible implementation, each storage layer also includes a first electrode line, and the second capacitor electrode of the capacitor is electrically connected to the first electrode line; the first electrode line extends in a direction perpendicular to the substrate, and the first electrode line is arranged close to the first notch; in multiple storage layers, the second capacitor electrodes of multiple capacitors arranged perpendicular to the substrate are electrically connected to the same first electrode line.

[0031] When the first capacitor electrode includes a first planar electrode and a second planar electrode, the second capacitor electrode in the capacitor is far away from the gate of the transistor. Then, the first electrode line (such as a PL line) electrically connected to the second capacitor electrode of the capacitor can be extended in a direction perpendicular to the substrate to electrically connect the second capacitor electrodes of multiple capacitors arranged perpendicular to the substrate.

[0032] In one possible implementation, the planar electrode has a plate-like structure and is connected to the surrounding electrode to form a capacitor layer having a second notch facing the gate. The second capacitor electrode is arranged on a surface of the capacitor layer facing away from the first capacitor electrode.

[0033] In one possible implementation, each storage layer also includes a first electrode line, and the second capacitor electrode of the capacitor is electrically connected to the first electrode line; the first electrode line has a plate-like structure and is arranged parallel to the substrate, and the first electrode line is set away from the second gap; in each storage layer, the second capacitor electrodes of multiple capacitors are electrically connected to the same first electrode line.

[0034] The first electrode line (eg, PL line) may be designed in a plate shape to electrically connect the second capacitor electrodes of all capacitors in one storage layer.

[0035] In a possible implementation, each storage layer further includes a second electrode line and a third electrode line; the gate of the transistor is electrically connected to the second electrode line; and the second electrode of the transistor is electrically connected to the third electrode line.

[0036] For example, the second electrode line is a word line WL, and the third electrode line is a bit line BL.

[0037] In a possible implementation, the second electrode line extends in a direction perpendicular to the substrate; and in the multiple storage layers, gates of multiple transistors arranged perpendicular to the substrate are electrically connected to the same second electrode line.

[0038] In a possible implementation, the third electrode line extends in a direction parallel to the substrate; in each storage layer, the second electrodes of a plurality of transistors arranged in parallel to the substrate are electrically connected to the same third electrode line.

[0039] That is, the second electrode line and the third electrode line can both be strip structures and can be perpendicular to each other. The second electrode line is electrically connected to the gates of multiple transistors arranged perpendicular to the substrate, and the third electrode line is electrically connected to the second poles of multiple transistors arranged parallel to the substrate.

[0040] In a possible implementation, the first metal layer is disposed close to the substrate, and the second metal layer is disposed away from the substrate.

[0041] That is, the capacitor is arranged close to the substrate, and the transistor is arranged far away from the substrate.

[0042] In some other implementation structures, the first metal layer is disposed away from the substrate, and the second metal layer may be disposed close to the substrate, that is, the capacitor is disposed away from the substrate, and the transistor is disposed close to the substrate.

[0043] In some other implementation structures, the memory array is a DRAM memory array, or the memory array is a ferroelectric memory array.

[0044] In some implementation structures, the multiple storage layers are formed on the substrate using a back-end process.

[0045] The transistors and capacitors in the memory cell are all manufactured using a back-end process, while the controller can be manufactured using a front-end process. The controller may include one or more circuits such as a decoder, a driver, a timing controller, a buffer, or an input / output driver, and may also include other functional circuits. The controller can control the first electrode line, the second electrode line, and the third electrode line in the embodiment of the present application.

[0046] After completing the front-end (FEOL) process, interconnects and memory arrays are fabricated through the back-end (BEOL) process. This allows for higher circuit density per unit area, thereby improving storage performance per unit area.

[0047] In a second aspect, the present application further provides a memory comprising a controller and a storage array in any of the above implementations, wherein the controller is electrically connected to the storage array, and the controller is used to control the reading and writing of the storage array.

[0048] In the memory provided in the present application, since the memory array in the above-mentioned implementation is included, in the memory array, the transistors and capacitors are arranged in a direction parallel to the substrate. In this way, the memory cells of this structure can be stacked in a direction perpendicular to the substrate and in a direction parallel to the substrate to achieve three-dimensional stacking, realize high-density integration, and improve storage capacity.

[0049] In a possible implementation, the storage array and the controller are integrated into a same chip, and the chip is disposed on a substrate.

[0050] In a possible implementation, the storage array is integrated into a first chip, the controller is integrated into a second chip, and both the first chip and the second chip are disposed on a substrate via an electrical connection structure.

[0051] In a possible implementation, the storage array is integrated into a first chip, the controller is integrated into a second chip, and the first chip and the second chip are stacked and integrated on a substrate.

[0052] In a third aspect, the present application also provides an electronic device, comprising a processor and a memory in any of the above-mentioned implementation methods, wherein the processor is electrically connected to the memory, and the memory is used to store data generated by the processor.

[0053] The electronic device provided in the embodiment of the present application includes the memory in any of the above-mentioned implementation methods. Therefore, the electronic device provided in the embodiment of the present application and the memory of the above-mentioned technical solution can solve the same technical problems and achieve the same expected effects.

[0054] In a fourth aspect, the present application further provides a method for forming a memory array, the method comprising:

[0055] Stacking multiple dielectric layers on a substrate, the multiple dielectric layers comprising multiple groups of functional dielectric layers and an electrical isolation dielectric layer located between two adjacent groups of functional dielectric layers, each group of functional dielectric layers comprising a first functional dielectric layer, a second functional dielectric layer, and a third functional dielectric layer stacked in sequence;

[0056] Patterning the plurality of functional dielectric layers to form a plurality of stacked memory layers, each memory layer comprising a first metal layer obtained by patterning the first functional dielectric layer, a second metal layer obtained by patterning the third functional dielectric layer, and a second functional dielectric layer located between the first metal layer and the second metal layer, each memory layer comprising a plurality of memory cells, each memory cell comprising a transistor and a capacitor;

[0057] The transistor includes a first electrode, a second electrode, a gate and a channel layer; the capacitor includes a first capacitor electrode, a capacitor layer and a second capacitor electrode; the first electrode of the transistor and the capacitor are formed in a first metal layer, and the second electrode of the transistor is formed in a second metal layer; at least part of the gate and at least part of the channel layer are formed in a second functional dielectric layer, and the channel layer surrounds the gate; the first capacitor electrode, the capacitor layer and the second capacitor electrode are stacked in a direction parallel to the substrate, and the capacitor layer surrounds the first capacitor electrode.

[0058] In the method for forming a memory array provided in the present application, multiple dielectric layers are stacked on a substrate, some of which are patterned into memory layers, thereby forming multiple memory layers arranged perpendicular to the substrate. For example, when two memory layers need to be prepared, seven dielectric layers can be stacked first, and the dielectric layer located in the middle layer of the seven dielectric layers serves as an electrically isolated dielectric layer, and the three layers above and below it can form memory layers respectively. It can be understood that after stacking multiple dielectric layers on a substrate, multiple memory layers can be formed simultaneously, rather than stacking one memory layer and then another memory layer. In this way, not only can the preparation process be simplified, but also the problem of greater difficulty in the alignment process caused by multi-layer stacking can be avoided.

[0059] In addition, the memory cell of the memory array obtained by the formation method given in this application has a channel of the transistor having a ring channel structure and a capacitor having a ring capacitor structure, so that the area occupied by the memory cell of this structure is close to 4F. 2 , compared with planar 2D memory cells, the memory cell size is reduced.

[0060] In addition, since the capacitor is a ring capacitor structure, compared with the columnar capacitor extending in a direction perpendicular to the substrate in the related art, the ring capacitor structure not only increases the storage capacity, but also does not pose a major challenge to the etching process, thereby making the storage array a high-density, large-storage, low-cost storage array.

[0061] In a possible implementation, forming the gate includes: opening a first through hole penetrating the multi-layer dielectric layer in a direction perpendicular to the substrate, and filling the first through hole with a conductive material to form the gate of the transistor.

[0062] That is, the columnar gate perpendicular to the substrate can be manufactured using this forming method.

[0063] In one possible implementation, after opening a first through hole penetrating the multi-layer dielectric layer and before filling the first through hole with a conductive material, the formation method further includes: filling the first through hole with a semiconductor material to form a channel layer of the transistor on the inner wall surface of the first through hole.

[0064] Thus, a gate-all-around channel structure can be formed. In addition, the channel layer of this structure can also increase the contact area with the source and drain of the transistor to avoid the short channel effect.

[0065] In one possible implementation, forming a first capacitor electrode, a capacitor layer, and a second capacitor electrode of a capacitor includes: filling a conductive material in a first through-hole, and before forming a gate, opening a first groove in a first functional dielectric layer, with an opening of the first groove facing the first through-hole, forming the first capacitor electrode, the capacitor layer, and the second capacitor electrode in the first groove to form a capacitor layer having a notch and the notch facing the first through-hole.

[0066] In this way, the formed capacitor layer includes not only a portion perpendicular to the substrate, but also a portion parallel to the substrate, thereby increasing the capacitance of the capacitor.

[0067] In one possible implementation, forming a first capacitor electrode, a capacitor layer, and a second capacitor electrode of a capacitor includes:

[0068] After filling the first through hole with a conductive material to form a gate, a second through hole is opened in a direction perpendicular to the substrate and passes through the multi-layer dielectric layer;

[0069] A second groove is opened in the first functional dielectric layer, the opening of the second groove faces the second through hole, and the bottom surface of the second groove passes through the first through hole. A first capacitor electrode, a capacitor layer, and a second capacitor electrode are formed in the second groove to form a capacitor layer with a notch and the notch facing away from the first through hole.

[0070] The capacitor layer formed in this way includes not only a portion perpendicular to the substrate, but also a portion parallel to the substrate, so as to increase the capacitance of the capacitor.

[0071] In a possible implementation, after forming the second through hole penetrating the multi-layer dielectric layer, the forming method further includes:

[0072] A third groove is formed in the second functional dielectric layer, with an opening of the third groove facing the second through hole. Semiconductor material is filled in the third groove to form a channel layer of the transistor on an inner wall surface of the third groove.

[0073] The formed channel layer includes not only a surrounding portion surrounding the periphery of the gate, but also a planar portion parallel to the substrate, so as to increase the contact area with the source and drain of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] FIG1 is a process structure diagram of a 1T1C memory cell in the prior art;

[0075] FIG2 is a circuit diagram of an electronic device provided in an embodiment of the present application;

[0076] FIG3 is a circuit diagram of a memory provided in an embodiment of the present application;

[0077] FIG4a is a packaging structure diagram of a storage array and a controller provided in an embodiment of the present application;

[0078] FIG4 b is a packaging structure diagram of a storage array and a controller provided in an embodiment of the present application;

[0079] FIG4c is a packaging structure diagram of a storage array and a controller provided in an embodiment of the present application;

[0080] FIG5 is a schematic diagram of a three-dimensional structure of a memory provided in an embodiment of the present application;

[0081] FIG6 is a simplified circuit diagram of a memory provided in an embodiment of the present application;

[0082] FIG7 is a circuit diagram of a storage unit in a memory provided in an embodiment of the present application;

[0083] FIG8 is a circuit diagram of a memory array provided in an embodiment of the present application;

[0084] FIG9 is a simplified structural diagram of a storage array provided in an embodiment of the present application;

[0085] FIG10 is a three-dimensional process structure diagram of a memory array provided in an embodiment of the present application;

[0086] FIG11 is a three-dimensional process structure diagram of a memory array provided in an embodiment of the present application;

[0087] FIG12 is an enlarged view of point A in FIG11 ;

[0088] FIG13 is a projection structure diagram of multiple memory cells on a substrate provided by an embodiment of the present application;

[0089] FIG14 is a cross-sectional view of a memory cell provided in an embodiment of the present application;

[0090] FIG15 is a cross-sectional view of a device including two storage layers provided in an embodiment of the present application;

[0091] FIG16 is a cross-sectional view of a device including two storage layers provided in an embodiment of the present application;

[0092] FIG17 is a three-dimensional process structure diagram of a memory array provided in an embodiment of the present application;

[0093] 18a to 18e are cross-sectional views of corresponding process structures after completion of each step in a memory array manufacturing method provided by an embodiment of the present application;

[0094] FIG19 is a three-dimensional process structure diagram of a memory array provided in an embodiment of the present application;

[0095] FIG20 is a three-dimensional process structure diagram of a memory array provided in an embodiment of the present application;

[0096] FIG21 is a structural diagram of a storage unit provided in an embodiment of the present application;

[0097] FIG22 is a cross-sectional view of a memory cell provided in an embodiment of the present application;

[0098] FIG23 is a three-dimensional process structure diagram of a memory array provided in an embodiment of the present application;

[0099] 24a to 24h are cross-sectional views of corresponding process structures after completion of each step in a memory array manufacturing method provided by an embodiment of the present application;

[0100] FIG25 is a flowchart of a method for manufacturing a storage array according to an embodiment of the present application;

[0101] 26a to 26n are cross-sectional views of corresponding process structures after completion of each step in a memory manufacturing method provided by an embodiment of the present application;

[0102] 27a to 27h are cross-sectional views of corresponding process structures after completion of each step in a memory manufacturing method provided by an embodiment of the present application.

[0103] Reference numerals:

[0104] 100-substrate;

[0105] 200-electronic equipment;

[0106] 300-memory;

[0107] 31-Storage array;

[0108] 32-controller;

[0109] 33-Substrate;

[0110] 400-storage unit;

[0111] Tr-transistor;

[0112] 11 – first pole;

[0113] 12 – second pole;

[0114] 13 – gate;

[0115] 14 – channel layer; 141 – surrounding channel; 142a – first planar channel; 142b – second planar channel;

[0116] 15 – gate dielectric layer;

[0117] C-capacitor;

[0118] 21 – first capacitor electrode; 211 – surrounding electrode; 212 – plane electrode; 212a – first plane electrode; 212b – second plane electrode;

[0119] 22 – second capacitor electrode;

[0120] 23 – capacitor layer;

[0121] 500a1 – first functional dielectric layer, 500a2 – second functional dielectric layer, 500a3 – third functional dielectric layer; 500, 500a, 500b – dielectric layers;

[0122] 501, 502, 503 - storage layer;

[0123] 50A1 – first metal layer;

[0124] 50A2 – second metal layer;

[0125] 51 – dielectric layer;

[0126] 61 – through hole; 611 – first through hole; 612 – second through hole;

[0127] 71, 711, 712, 713 – grooves;

[0128] 8 – Metal layer. DETAILED DESCRIPTION

[0129] The following describes the embodiments of the present application in conjunction with the accompanying drawings.

[0130] An embodiment of the present application provides an electronic device. FIG2 is a circuit block diagram of an electronic device 200 provided in an embodiment of the present application. The electronic device 200 can be a terminal device such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc.

[0131] As shown in Figure 2, the electronic device 200 may include a bus 205 and a system on chip (SOC) 210 connected to the bus 205. The SOC 210 can be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the SOC 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and a first random access memory (RAM) 213 for caching high-speed data. The first RAM 213 may be a static random access memory (SRAM) or an embedded flash memory (EFlash), etc. The above-mentioned AP 211, GPU 212 and first RAM 213 may be integrated into a die, or may be separately provided in multiple dies.

[0132] As shown in FIG2 , the electronic device 200 may further include a second RAM 220 connected to the SOC 210 via a bus 205. The second RAM 220 may be a dynamic random access memory (DRAM). The second RAM 220 may be used to store volatile data, such as temporary data generated by the SOC 210. The storage capacity of the second RAM 220 is generally greater than that of the first RAM 213, but the read speed is generally slower than that of the first RAM 213.

[0133] In addition, the electronic device 200 may further include a communication chip 230 and a power management chip 240 connected to the SOC 210 via the bus 205. The communication chip 230 may be used for processing the protocol stack, or for amplifying and filtering analog radio frequency signals, or for performing the above functions simultaneously. The power management chip 240 may be used to power other chips. In one embodiment, the SOC 210 and the second RAM 220 may be packaged in a single package structure, such as a 2.5D (dimension) or 3D package, to achieve a faster inter-chip data transmission rate.

[0134] FIG3 is a circuit block diagram of a memory 300 that can be used in an electronic device, as provided in an embodiment of the present application. In one embodiment, the memory 300 can be a ferroelectric random access memory (FeRAM or FRAM), or a dynamic random access memory (DRAM). This application does not limit the application scenarios of the memory 300.

[0135] As shown in FIG. 3 , the memory 300 includes a memory array 31 and a controller 32 for accessing the memory array 31 , wherein the controller 32 is used to control read and write operations of the memory array 31 .

[0136] The storage array 31 and the controller 32 shown in FIG3 have a variety of achievable packaging structures. For example, several achievable packaging structures are given below.

[0137] FIG4 a shows one packaging structure of a memory array 31 and a controller 32 according to an embodiment of the present application. Specifically, the memory array 31 and the controller 32 are two independent chips, each integrated on a substrate 33. For example, the memory array 31 and the controller 32 can be electrically connected via metal traces arranged on the substrate 33. In this structure, since the memory array 31 and the controller 32 are two independent chips, the memory array 31 can be referred to as a stand-alone memory.

[0138] FIG4 b shows another packaging structure of the memory array 31 and the controller 32 according to an embodiment of the present application. In this structure, similar to FIG4 a above, the memory array 31 and the controller 32 are two independent chips, and thus the memory array 31 can also be referred to as an independent memory. Unlike FIG4 a above, in FIG4 b , the memory array 31 and the controller 32 are stacked. For example, the memory array 31 and the controller 32 can be interconnected via through silicon vias (TSVs) or redistribution layers (RDLs).

[0139] Figure 4c shows another packaging structure of a memory array 31 and a controller 32 according to an embodiment of the present application. In this exemplary structure, the memory array 31 and the controller 32 are integrated into the same chip 3, which is integrated on a substrate 33. Therefore, the memory array 31 can be called an embedded memory.

[0140] In the structure shown in FIG. 4c , as shown in FIG. 5 , the controller 32 can be integrated on the substrate through a front-end of line (FEOL) process, and the interconnects and memory array are integrated on the controller 32 through a back-end of line (BEOL) process. The controller can generate control signals, which can be read / write control signals for controlling the read and write operations of data in the memory array. The controller can also include analog circuitry, such as a sense amplifier.

[0141] 5 , the memory array 31 can be a single memory layer or multiple memory layers stacked in the Z direction perpendicular to the substrate. When two or more memory layers are included, such a memory structure can be referred to as a three-dimensional integrated memory structure, thereby increasing storage capacity.

[0142] In one embodiment, the memory array 31 in the memory may include a plurality of memory cells 400 arranged in an array as shown in FIG6 , wherein each memory cell 400 may be used to store 1 bit (bit) or multiple bits of data. The memory array 31 may also include electrode lines such as word lines (WL) and bit lines (BL). Each memory cell 400 is electrically connected to the corresponding word line WL and bit line BL. Different memory cells 400 can be electrically connected through WL and BL. One or more of the above-mentioned WL and BL are used to select the memory cell 400 to be read or written in the memory array by receiving the control level output by the control circuit, thereby realizing the read and write operations of the data.

[0143] The controller 32 in the memory may include one or more circuit structures of the decoder 320 , the driver 330 , the timing controller 340 , the buffer 350 , or the input / output driver 360 shown in FIG. 6 .

[0144] In the memory 300 structure shown in Figure 6, the decoder 320 is used to decode the received address to determine the memory cell 400 to be accessed. The driver 330 is used to control the level of the signal line based on the decoding result generated by the decoder 320, thereby achieving access to the specified memory cell 400. The buffer 350 is used to cache the read data, for example, it can be cached using a first-in first-out (FIFO) method. The timing controller 340 is used to control the timing of the buffer 350 and control the driver 330 to drive the signal lines in the memory array 310. The input and output driver 360 is used to drive the transmission signal, such as the received data signal and the data signal to be sent, so that the data signal can be transmitted over a long distance.

[0145] The memory array 31 , decoder 320 , driver 330 , timing controller 340 , buffer 350 and input / output driver 360 may be integrated into one chip or integrated into multiple chips.

[0146] The memory 300 involved in the embodiment of the present application may be a dynamic random access memory (DRAM), for example, a DRAM including 1T1C memory cells.

[0147] In addition, the memory 300 involved in the embodiment of the present application may also be a ferroelectric random access memory (FeRAM), for example, it may also be a FeRAM including a 1T1C memory cell.

[0148] FIG7 is a circuit diagram of a memory cell 400 in a memory 300 according to an embodiment of the present application. As shown in FIG7 , the memory cell 400 has a 1T1C gain-cell structure, meaning that the memory cell 400 includes a transistor Tr and a capacitor C. For example, the transistor Tr may be a thin film transistor (TFT) structure.

[0149] Among them, the first electrode of transistor Tr is electrically connected to the first capacitor electrode of capacitor C, the second electrode of transistor Tr is electrically connected to the bit line (BL), the gate of transistor Tr is electrically connected to the word line (WL); and the second capacitor electrode of capacitor C is electrically connected to the plate line (PL).

[0150] In the memory cell shown in FIG. 7 , a plate line (PL) may be referred to as a first electrode line, a word line (WL) may be referred to as a second electrode line, and a bit line (BL) may be referred to as a third electrode line.

[0151] For example, when the memory cell shown in FIG7 is a FeRAM memory cell, that is, the capacitor layer formed between the first capacitor electrode and the second capacitor electrode is a ferroelectric material layer, the memory cell shown in FIG7 may also be a DRAM memory cell.

[0152] For example, when the memory cell shown in FIG7 is a FeRAM memory cell, during the write phase, the word line WL is used to receive a word line control signal, turning on the transistor Tr, the bit line BL is used to receive a bit line control signal, and the plate line PL electrically connected to the ferroelectric capacitor is used to receive a plate line control signal. The voltage difference between the bit line control signal and the plate line control signal causes the ferroelectric layer of the selected ferroelectric capacitor to be positively polarized or negatively polarized, thereby writing different logical information into the selected ferroelectric capacitor. For example, when the ferroelectric layer is positively polarized, a logic signal "0" is written, and when the ferroelectric layer is negatively polarized, a logic signal "1" is written.

[0153] In the embodiments of the present application, for example, the transistor Tr shown in FIG. 7 may be an NMOS (N-channel metal oxide semiconductor) tube, or a PMOS (P-channel metal oxide semiconductor) tube.

[0154] In addition, in the embodiments of the present application, one of the drain and source of the transistor Tr is referred to as the first electrode, the other is referred to as the second electrode, and the control terminal of the transistor is referred to as the gate. The drain and source of the transistor can be determined according to the direction of current flow.

[0155] FIG8 illustrates a circuit diagram of the memory cells 400 shown in FIG7 arranged in an array. Referring to FIG8 , the gates of the transistors Tr of the multiple memory cells arranged in the same direction can be electrically connected to the same word line WL; the second electrodes of the transistors Tr of the multiple memory cells arranged in the same direction can be electrically connected to the same bit line BL; and the second capacitor electrodes of the multiple capacitors C can be electrically connected to the same plate line PL, which can be grounded, for example.

[0156] In a DRAM memory cell or FeRAM memory cell such as that shown in FIG7 above, embodiments of the present application provide some memory cell process structures that can improve storage density, as detailed below.

[0157] The memory array provided in an embodiment of the present application, as shown in FIG9 , includes multiple memory layers, and these multiple memory layers are stacked in a direction perpendicular to the substrate 100. Adjacent memory layers are electrically isolated by an electrically isolating dielectric layer. Each memory layer may include multiple stacked metal layers, and adjacent metal layers are electrically isolated by a dielectric layer. Memory cells may be formed in these metal layers.

[0158] 10 and 11 are three-dimensional process structure diagrams of a memory array according to an embodiment of the present application. Specifically, the memory array 31 can be stacked on the substrate 100 through a front-end process, or integrated on the substrate 100 through a back-end process.

[0159] 11 , a memory array 31 is shown as comprising three memory layers, namely, memory layer 501, memory layer 502, and memory layer 503. Memory layer 501 and memory layer 502, as well as memory layer 502 and memory layer 503, are electrically isolated by dielectric layer 500.

[0160] Continuing to refer to FIG. 11 , each memory layer includes a first metal layer 50A1 , a second metal layer 50A2 , and a dielectric layer 51 located between the first metal layer 50A1 and the second metal layer 50A2 .

[0161] The memory cell shown in FIG. 7 may be formed in a first metal layer 50A1 , a second metal layer 50A2 , and a dielectric layer 51 . The specific process structure that can be implemented may be described below.

[0162] Referring again to Figures 11 and 12, Figure 12 is an enlarged view of point A in Figure 11. In conjunction with Figures 11 and 12, transistor Tr and capacitor C are integrated within a first metal layer 50A1, a second metal layer 50A2, and a dielectric layer 51. For example, a first electrode 11 of transistor Tr is formed within the first metal layer 50A1, a second electrode 12 of transistor Tr is formed within the second metal layer 50A2, at least a portion of the gate 13 of transistor Tr and at least a portion of the channel layer 14 extend through the dielectric layer 51; and a first capacitor electrode 21, a capacitor layer 23, and a second capacitor electrode 22 of capacitor C are all formed within the first metal layer 50A1.

[0163] That is, a layer of memory cell array is integrated by using the stacked first metal layer 50A1 , the second metal layer 50A2 and the dielectric layer 51 .

[0164] As shown in FIG11 and FIG12 , at least a portion of the gate 13 and at least a portion of the channel layer 14 of the transistor Tr penetrate the dielectric layer 51 . It can be understood that at least a portion of the gate 13 and at least a portion of the channel layer 14 penetrate the dielectric layer 51 in a direction perpendicular to the substrate.

[0165] Compared to some related technologies that use three, four, or even more metal layers to integrate a single memory cell array, the memory array provided by this application can significantly reduce the number of stacked metal layers. Thus, in a memory array with the same number of metal layers, this application can integrate more memory layers and more memory cells, thereby increasing the storage capacity of the memory.

[0166] 11 and 12 , in the transistor Tr of the memory cell of this embodiment, the gate 13 is a columnar structure penetrating the dielectric layer 51, and the channel layer 14 surrounds the gate 13. That is, the channel of the transistor Tr is a ring channel structure.

[0167] Furthermore, as shown in Figures 11 and 12, in the capacitor C of the memory cell of this embodiment, the first capacitor electrode 21, the capacitor layer 23, and the second capacitor electrode 22 are stacked in the first metal layer 50A1 in a direction parallel to the substrate 100. Furthermore, the capacitor layer 23 surrounds the periphery of the first capacitor electrode 21, and the second capacitor electrode 22 surrounds the periphery of the capacitor layer 23. In other words, the capacitor has a ring capacitor structure. The ring capacitor structure can increase the capacitor area, thereby increasing the capacitance and improving the storage performance of the memory.

[0168] The memory cell structure shown in Figures 11 and 12 in the embodiments of the present application can not only realize three-dimensional stacking, but also the area occupied by each memory cell is small, thereby correspondingly improving the storage density. For example, Figure 13 shows the area of ​​the positive projection of multiple memory cells 400 in a memory layer in Figure 11 on the substrate 100. Among them, the area occupied by each memory cell 400 is basically 2F×2F=4F. 2 , occupies a small area, and thus, more storage units 400 can be integrated per unit area.

[0169] In addition, compared to columnar capacitor structures, ring capacitor structures require a higher depth-to-width ratio to achieve high capacitance, which poses a process challenge for creating the through-holes that form the columnar capacitors. However, in the embodiments of the present application, ring capacitors can be implemented using a deposition process without significantly increasing the process difficulty.

[0170] Furthermore, during the preparation process of the memory array shown in Figures 11 and 12, multiple dielectric layers can be stacked in a direction perpendicular to the substrate. For example, when two memory layers need to be prepared, seven dielectric layers can be stacked, and then these dielectric layers can be patterned to simultaneously prepare two memory layers. That is, three dielectric layers are patterned into one memory layer, and another three dielectric layers are patterned into another memory layer. The two memory layers are then separated by a dielectric layer, rather than preparing one memory layer and then another memory layer. Therefore, when preparing the memory array provided in the embodiment of the present application, the preparation process flow can be simplified and the process complexity can be reduced. The specific process methods that can be implemented will be described later, and how to use a single process to prepare multiple memory layers simultaneously will be described in conjunction with the process methods. These will not be described here.

[0171] Continuing to refer to FIG. 12 , one end of the gate electrode 13 penetrating the dielectric layer 51 may extend into the first metal layer 50A1 and be electrically isolated from the first electrode 11 by the gate dielectric layer 15 .

[0172] The other end of the gate 13 may also extend into the second metal layer 50A2 and be electrically isolated from the second electrode 12 by the gate dielectric layer 15 .

[0173] As shown in FIG12 , since the first electrode 11 of the transistor Tr and the capacitor C are both formed in the first metal layer 50A1, in some optional embodiments, such as FIG12 , the first electrode 11 of the transistor Tr and the first capacitor electrode 21 of the capacitor C can share the same electrode to simplify the process structure. In other words, the formed metal layer can serve not only as the first electrode 11 of the transistor Tr, but also as the first capacitor electrode 21 of the capacitor C.

[0174] Figures 11 and 12 also illustrate a possible structure for the channel layer 14. As shown in Figures 11 and 12, the channel layer 14, which extends through the dielectric layer 51 and surrounds the gate 13, can extend into the first metal layer 50A1 and form an ohmic contact with the first electrode 11 in the first metal layer 50A1, with the first electrode 11 surrounding the periphery of the channel layer 14. This increases the contact area between the channel layer 14 and the first electrode 11, thereby preventing short-channel effects such as increased leakage current and reduced electron mobility.

[0175] Similarly, the channel layer 14 that extends through the dielectric layer 51 and surrounds the gate 13 can also extend into the second metal layer 50A2 and make ohmic contact with the second electrode 12 in the second metal layer 50A2, with the second electrode 12 surrounding the periphery of the channel layer 14. Similar to the first electrode 11 described above, the contact area between the second electrode 12 and the channel layer 14 can also be increased to improve electron mobility in the channel layer 14.

[0176] 11 and 12 introduce some process structures that can be realized for the first electrode 11, the second electrode 12, the gate 13 and the channel layer 14 of the transistor Tr. The following describes the process structure that can be realized for the capacitor C with reference to the accompanying drawings.

[0177] Figure 14 shows a cross-sectional view taken along the XZ line of a memory cell shown in Figures 11 and 12. The first capacitor electrode 21 includes not only a surrounding electrode 211 surrounding the periphery of the channel layer 14, but also a planar electrode 212 connected to the surrounding electrode 211 and arranged parallel to the substrate. The planar electrode 212 has an annular structure and surrounds the periphery of the surrounding electrode 211.

[0178] In the case of the extended planar electrode 212 as shown in FIG14 , the first capacitor electrode 21 of this structure has not only a horizontal contact surface N2 in contact with the capacitor layer 23, but also a vertical direct contact surface N1 in contact with the capacitor layer 23. The horizontal contact surface N2 is parallel to the substrate, and the vertical direct contact surface N1 is perpendicular to the substrate.

[0179] Compared with only having a surrounding electrode 211, the first capacitor electrode 21 provided in the embodiment of the present application can increase the contact area with the capacitor layer 23, that is, it can increase the capacitance area of ​​the capacitor layer 23, thereby improving the capacitance of the capacitor C.

[0180] 14 , the capacitor layer 23 is formed on the horizontal contact surface N2 and the vertical contact surface N1 of the first capacitor electrode 21 . The second capacitor electrode 22 is formed on the capacitor layer 23 so that the capacitor layer 23 is sandwiched between the first capacitor electrode 21 and the second capacitor electrode 22 .

[0181] Figures 15 and 16 respectively show cross-sectional views of a memory array including a memory layer 501 and a memory layer 502, taken along an XZ plane. In Figure 15 , a dielectric layer 500 is located between the memory layer 501 and the memory layer 502, electrically isolating the memory layer 501 and the memory layer 502. The channel layer 14 in the memory layer 501 is separated from the channel layer 14 in the memory layer 502 at the dielectric layer 500. In contrast, in Figure 16 , two dielectric layers, dielectric layer 500a and dielectric layer 500b, are located between the memory layer 501 and the memory layer 502. The channel layer 14 in the memory layer 501 can extend into the dielectric layer 500a that is closer to the memory layer 501. Furthermore, the channel layer 14 in the memory layer 501 is separated from the channel layer 14 in the memory layer 502 at the dielectric layer 500b.

[0182] In the memory array shown in Figures 10 and 11, not only the memory cells in each memory layer (including transistors Tr and capacitors C) are shown, but also the achievable process structures of the word lines WL, bit lines BL and plate lines PL that control the reading and writing of the memory cells are shown.

[0183] FIG17 illustrates the layout of the word lines WL, bit lines BL, and plate lines PL in the embodiments of FIG10 and FIG11. Specifically, as shown in FIG17, the word line WL extends in a direction perpendicular to the substrate 100 and electrically connects the gates 13 of multiple transistors Tr arranged in a direction perpendicular to the substrate in multiple storage layers. That is, the gates 13 of multiple transistors Tr arranged in a direction perpendicular to the substrate are electrically connected to the same word line WL. For example, the word line WL extends in the Z direction, and the gates 13 of multiple transistors Tr arranged in the Z direction in the storage layers 501, 502, and 503 are electrically connected to the same word line WL.

[0184] That is, the word line WL runs through multiple storage layers and the dielectric layer between each two adjacent storage layers. Of course, in this memory array, a word line WL layer is formed above the multiple storage layers to interconnect the multiple word lines WL shown in Figure 10.

[0185] In the embodiment shown in FIG17 , the bit line BL extends parallel to the substrate and electrically connects the second electrodes 12 of multiple transistors Tr arranged parallel to the substrate in each storage layer. That is, the second electrodes 12 of multiple transistors Tr arranged parallel to the substrate are electrically connected to the same bit line BL. For example, the bit line BL extends along the Y direction. In the storage layer 501, the second electrodes 12 of multiple transistors Tr arranged along the Y direction are electrically connected to the same bit line BL. Adjacent bit lines BL are electrically isolated by a dielectric layer.

[0186] Regarding the layout of the plate line PL, there are various possible structures. As shown in FIG17 , the plate line PL has a plate-like structure. The plate line PL is located in the first metal layer 50A1, and the second capacitor electrodes 22 of the capacitors C located in the first metal layer 50A1 are all electrically connected to the plate-like plate line PL. For example, in the storage layer 501, the plate line PL located in the first metal layer 50A1 is electrically connected to the second capacitor electrodes 22 of all capacitors C in the storage layer 501. In one example, the plate line PL can be grounded.

[0187] In the process flow for manufacturing the memory cell structure involved in the above embodiment, the following process methods may be used:

[0188] As shown in FIG18 a , a through hole 61 penetrating through the stacked multiple dielectric layers can be opened. The through hole 61 can be used to fill the channel layer 14 and the gate 13 .

[0189] Some of these dielectric layers serve as functional dielectric layers, forming storage layers, while others serve as electrical isolation layers, electrically isolating two adjacent storage layers. For example, as shown in FIG18a , these functional dielectric layers include a first functional dielectric layer 500a1, a second functional dielectric layer 500a2, and a third functional dielectric layer 500a3 stacked in sequence. The first functional dielectric layer 500a1, the second functional dielectric layer 500a2, and the third functional dielectric layer 500a3 can be used to form a storage layer.

[0190] Furthermore, the through hole 61 passes through the functional dielectric layers and the electrically isolated dielectric layers.

[0191] As shown in FIG18b , a groove 71 connected to the through hole 61 can be opened in the first functional dielectric layer 500a1 , and then a metal layer is formed on the inner wall surface of the groove 71 , and then the metal layer near the edge of the groove 71 near the through hole 61 is etched back to form the second capacitor electrode 22 .

[0192] As shown in FIG18 c , a capacitor layer 23 is formed in the groove 71 , thereby forming a capacitor layer structure having a notch facing the through hole 61 as shown in FIG18 c .

[0193] As shown in FIG18 d , a metal layer is then filled in the groove 71 to form the first capacitor electrode 21 of the capacitor C, thereby manufacturing the capacitor C.

[0194] As shown in FIG18e , the remaining dielectric layer where the capacitor C is located is etched away, and then a metal layer is filled to form a plate-shaped plate line PL, so that the plate line PL is in contact and electrically connected to the second capacitor electrode 22 of the capacitor C.

[0195] As shown in FIG18b, the metal layer near the edge of the through hole of the groove is etched back to prevent the formed plate line PL and capacitor layer from contacting the channel layer 14, thereby preventing the memory cell of the circuit structure shown in FIG7 from being formed.

[0196] As shown in FIG. 18 a to FIG. 18 e , the capacitor layer 23 prepared includes not only a portion perpendicular to the substrate, but also a portion parallel to the substrate, thereby increasing the area of ​​the capacitor layer to improve the capacitance.

[0197] In the memory array mentioned above, the first metal layer 50A1 forming the capacitor C in each memory layer is disposed close to the substrate, and the second metal layer 50A2 is disposed away from the substrate, that is, the capacitor C is closer to the substrate than the transistor Tr.

[0198] Of course, in some other process structures, the first metal layer 50A1 forming the capacitor C may be arranged away from the substrate, while the second metal layer 50A2 is arranged close to the substrate.

[0199] The embodiment of the present application also provides another storage unit structure including 1T1C, as shown in FIG19 and FIG20 . FIG19 and FIG20 also show a storage array including multiple 1T1C storage units.

[0200] The 1T1C memory cell shown in FIG19 may be a 1T1C memory cell of FeRAM, or may be a 1T1C memory cell of DRAM.

[0201] The storage array process structure shown in Figure 20 is similar to the storage array process structure shown in Figure 11 above in that it also belongs to a three-dimensional stacked storage array, and the three-dimensional stacked storage array also includes multiple storage layers, for example, storage layer 501, storage layer 502 and storage layer 503 shown in Figure 20; and, in Figure 20, each storage layer also includes a first metal layer 50A1 and a second metal layer 50A2, and a dielectric layer 51 located between the first metal layer 50A1 and the second metal layer 50A2.

[0202] The similarities also include: as shown in Figure 21, Figure 21 shows an enlarged view of a storage unit in Figure 20, wherein the first electrode 11 of the transistor Tr is formed in the first metal layer 50A1, and the second electrode 12 of the transistor Tr is formed in the second metal layer 50A2; the first capacitor electrode 21, the capacitor layer 23 and the second capacitor electrode 22 of the capacitor C are all formed in the first metal layer 50A1.

[0203] The following describes the differences between the embodiment shown in FIG. 20 and the embodiment shown in FIG. 11 .

[0204] In the memory cell shown in FIG21 , the gate 13 of the transistor Tr extends into the first metal layer 50A1 and the second metal layer 50A2 . However, the channel layer 14 of the transistor Tr is only formed in the dielectric layer 51 and does not extend into the first metal layer 50A1 and the second metal layer 50A2 .

[0205] Figure 22 shows a cross-sectional view of the memory cell shown in Figure 20 along the XZ line. The channel layer 14 includes a surrounding channel 141 surrounding the gate 13, and a first planar channel 142a connected to the surrounding channel 141 and parallel to the substrate 100. The first planar channel 142a makes ohmic contact with the second electrode 12 of the transistor Tr to achieve electrical connection.

[0206] 22 , the channel layer 14 further includes a second planar channel 142 b connected to the surrounding channel 141 and parallel to the substrate 100 . The first planar channel 142 a and the second planar channel 142 b are arranged opposite to each other. The second planar channel 142 b is in ohmic contact with the first electrode 11 of the transistor Tr to achieve electrical connection.

[0207] The process structure of the first capacitor electrode 21 and the capacitor layer 23 in the capacitor C in the structure shown in FIG. 22 is also different from that of the structure shown in FIG. 10 .

[0208] As shown in Figure 22, the first capacitor electrode 21 includes a surrounding electrode 211, a first planar electrode 212a, and a second planar electrode 212b. The first planar electrode 212a and the second planar electrode 212b are both parallel to the substrate and connected by the surrounding electrode 211. This forms a cavity with an opening within the first capacitor electrode 21, with the opening of the cavity facing away from the columnar gate 13. The capacitor layer 23 is formed on the inner wall surface of the cavity, and the second capacitor electrode 22 is formed on the capacitor layer 23.

[0209] According to the process structure of FIG22 , the first electrode 11 of the transistor Tr and the first capacitor electrode 21 of the capacitor C also share the same electrode.

[0210] Furthermore, the first planar channel 142 a of the channel layer 14 is in ohmic contact with the second electrode 12 of the transistor Tr, and the second planar channel 142 b of the channel layer 14 is in ohmic contact with the first planar electrode 212 a of the capacitor C.

[0211] Comparing FIG14 and FIG22 , it can be understood that in FIG14 , the capacitor layer 23 formed is a capacitor structure with the notch facing the gate 13 , while in FIG22 , the capacitor layer 23 formed is a capacitor structure with the notch facing away from the gate 13 .

[0212] The capacitor layer 23 structure shown in Figure 14 and Figure 22 includes not only a vertical portion perpendicular to the substrate, but also a horizontal portion parallel to the substrate. By arranging the vertical and horizontal portions, the capacitor area can be increased to improve the capacitance.

[0213] FIG23 shows the layout of word lines WL, bit lines BL, and plate lines PL in the memory array of FIG20 . The specific achievable process structure is as follows.

[0214] In the word line WL structure shown in FIG23 , similar to the word line WL structure shown in FIG17 of the aforementioned embodiment, the word line WL extends perpendicular to the substrate 100 and electrically connects the gates 13 of multiple transistors Tr arranged perpendicular to the substrate in multiple memory layers. In other words, the gates 13 of multiple transistors Tr arranged perpendicular to the substrate are electrically connected to the same word line WL. For example, the word line WL extends in the Z direction, and the gates 13 of multiple transistors Tr arranged in the Z direction in multiple memory layers are electrically connected to the same word line WL.

[0215] In the bit line BL structure shown in FIG23 , similar to the bit line BL structure shown in FIG17 , the bit line BL extends parallel to the substrate and electrically connects the second electrodes 12 of multiple transistors Tr arranged parallel to the substrate in each memory layer. In other words, the second electrodes 12 of multiple transistors Tr arranged parallel to the substrate are electrically connected to the same bit line BL. For example, if the bit line BL extends in the Y direction, the second electrodes 12 of multiple transistors Tr arranged in the Y direction in each memory layer are electrically connected to the same bit line BL.

[0216] Regarding the layout of the plate line PL, in Figure 23 , the plate line PL extends perpendicular to the substrate and electrically connects the second electrodes 12 of multiple transistors Tr arranged perpendicular to the substrate in multiple storage layers. In other words, the second capacitor electrodes 22 of multiple capacitors C arranged perpendicular to the substrate are electrically connected to the same plate line PL. For example, if the plate line PL extends along the Z direction, the second electrodes 12 of multiple transistors Tr arranged along the Z direction in multiple storage layers are electrically connected to the same plate line PL.

[0217] 23 , in each storage layer, the second capacitor electrodes 22 of two adjacent capacitors C arranged in the same direction can be electrically connected to the same plate line PL. For example, the second capacitor electrodes 22 of two adjacent capacitors C arranged in the X direction can be electrically connected to the same plate line PL.

[0218] In the process flow for obtaining the structures shown in FIG. 21 and FIG. 22 , the following process methods may be used:

[0219] As shown in FIG. 24 a , a first through hole 611 penetrating through the stacked multiple dielectric layers may be opened in the stacked multiple dielectric layers. The first through hole 611 may be used to fill the gate 13 .

[0220] Similar to the process flow shown in FIG18a above, a portion of these dielectric layers serves as a functional dielectric layer for forming a storage layer, while another portion serves as an electrical isolation layer for electrically isolating two adjacent storage layers. For example, as shown in FIG24a, these functional dielectric layers include a first functional dielectric layer 500a1, a second functional dielectric layer 500a2, and a third functional dielectric layer 500a3 stacked in sequence. The first functional dielectric layer 500a1, the second functional dielectric layer 500a2, and the third functional dielectric layer 500a3 can be used to form a storage layer.

[0221] As shown in FIG24 b , a groove 711 communicating with the first through hole 611 is opened in the third functional dielectric layer 500 a 3 , and then a metal layer is filled in the groove 711 to form the second electrode 12 of the transistor Tr.

[0222] As shown in FIG24 c , a gate dielectric layer 15 and a gate electrode 13 are formed in the first through hole 611 .

[0223] As shown in FIG24 d , a second through hole 612 penetrating through the stacked dielectric layers is then opened in the dielectric layers, and the second through hole 612 is located between two adjacent first through holes 611 .

[0224] As shown in FIG24 e , a groove 712 parallel to the substrate and connected to the second through hole 612 is opened in the second functional dielectric layer 500 a 2 . The groove 712 passes through to the gate dielectric layer 15 .

[0225] As shown in FIG24 f , a semiconductor material is filled on the inner wall surface of the groove 712 prepared as shown in FIG24 e to form a channel layer 14 on the inner wall surface of the groove 712 , and the gap of the channel layer 14 is away from the formed gate 13 .

[0226] As shown in Figures 24g and 24h, a groove 713 parallel to the substrate and connected to the second through hole 612 is opened in the first functional medium layer 500a1, and the first capacitor electrode 21, capacitor layer 23 and second capacitor electrode 22 of the capacitor C are formed in sequence on the inner wall surface of the groove 713.

[0227] In this way, the manufactured channel layer 14 includes not only a surrounding channel but also a planar channel; and the manufactured capacitor layer 23 includes not only a portion perpendicular to the substrate but also a portion parallel to the substrate.

[0228] In the 1T1C memory cells provided in the above embodiments, various materials may be selected for the functional layers of the transistor Tr, the functional layers of the capacitor C, and the word line WL, the bit line BL, and the plate line PL. Some of the selectable materials are given below.

[0229] Among the selectable materials, the first electrode, second electrode, gate, word line WL, bit line BL, and plate line PL of the transistor Tr are all made of conductive materials, such as metal materials. In selectable embodiments, the materials may be one or more of TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), and the like.

[0230] Among the selectable materials, the channel layer 14 of the transistor Tr can be selected from one or more semiconductor materials such as Si (silicon), poly-Si (p-Si, polycrystalline silicon), amorphous-Si (a-Si, amorphous silicon), In-Ga-Zn-O (IGZO, indium gallium zinc oxide) multi-compound, ZnO (zinc oxide), ITO (indium tin oxide), TiO2 (titanium dioxide), MoS2 (molybdenum disulfide), WS2 (tungsten disulfide), graphene, black phosphorus, etc.

[0231] The material of the gate dielectric layer of the above-mentioned transistor Tr can be one or more insulating materials such as SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconium oxide), TiO2 (titanium dioxide), Y2O3 (yttrium oxide) and Si3N4 (silicon nitride).

[0232] The first capacitor electrode 21 and the second capacitor electrode 22 in the capacitor C are both made of a conductive material. Among the selectable materials, one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver) can be used.

[0233] The capacitance layer 23 in the capacitor C can be selected from insulating materials such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4, HAO, etc., or ferroelectric materials such as ZrO2, HfO2, Al-doped HfO2, Si-doped HfO2, Zr-doped HfO2, La-doped HfO2, Y-doped HfO2, or materials doped with other elements based on these materials and any combination thereof.

[0234] The above description, combined with the accompanying drawings, introduces a three-dimensional memory array including 1T1C memory cells that can be implemented according to the embodiments of the present application. The following description, combined with the accompanying drawings, details the preparation method provided in the embodiments of the present application to prepare a three-dimensional memory array including 1T1C memory cells, as described below.

[0235] FIG25 exemplarily shows a flow chart of preparing a storage array.

[0236] Step S1: stacking multiple dielectric layers on a substrate, the multiple dielectric layers including multiple groups of functional dielectric layers and an isolation dielectric layer located between two adjacent groups of functional dielectric layers, each group of functional dielectric layers including a first functional dielectric layer, a second functional dielectric layer and a third functional dielectric layer stacked in sequence.

[0237] Adjacent dielectric layers in these multi-layer dielectric layers can be made of different materials. For example, if one of the two adjacent dielectric layers is made of one insulating material selected from SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconium oxide), TiO2 (titanium dioxide), Y2O3 (yttrium trioxide), and Si3N4 (silicon nitride), the other dielectric layer can be made of another insulating material selected from SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconium oxide), TiO2 (titanium dioxide), Y2O3 (yttrium trioxide), and Si3N4 (silicon nitride).

[0238] For example, when three storage layers need to be manufactured, eleven dielectric layers can be stacked on the substrate, with three dielectric layers each being used to manufacture one storage layer, and a dielectric layer between each three dielectric layers serving as an electrical isolation layer between two adjacent storage layers.

[0239] According to this design, when N storage layers need to be manufactured, 3N+(N-1) dielectric layers need to be stacked in sequence.

[0240] Step S2: Patterning the multiple functional dielectric layers to form a plurality of stacked storage layers, each storage layer comprising a first metal layer formed by patterning the first functional dielectric layer, a second metal layer formed by patterning the third functional dielectric layer, and a second functional dielectric layer located between the first metal layer and the second metal layer, each storage layer comprising a plurality of storage cells, each storage cell comprising a transistor and a capacitor;

[0241] The transistor includes a first electrode, a second electrode, a gate and a channel layer; the capacitor includes a first capacitor electrode, a capacitor layer and a second capacitor electrode; the first electrode of the transistor and the capacitor are formed in a first metal layer, and the second electrode of the transistor is formed in a second metal layer; at least part of the gate and at least part of the channel layer are formed in a second dielectric layer, and the channel layer surrounds the gate; the first capacitor electrode, the capacitor layer and the second capacitor electrode are stacked in a direction parallel to the substrate, and the capacitor layer surrounds the first capacitor electrode.

[0242] When manufacturing a three-dimensional memory array using the fabrication method described in the embodiments of this application, multiple dielectric layers are first stacked on a substrate, and then patterned on these multiple dielectric layers to simultaneously fabricate multiple memory layers, rather than fabricating one memory layer first and then another. This simplifies the fabrication process, reduces manufacturing costs, and avoids the gradual decrease in alignment accuracy that occurs when stacking multiple memory layers.

[0243] The specific process flow involved in the above-mentioned step S1 and step S2 is introduced below with reference to the accompanying drawings.

[0244] 26a to 26n illustrate the process structure after each step is completed in the process of manufacturing a memory array according to an embodiment of the present application.

[0245] As shown in FIG26a, multiple dielectric layers are stacked on a substrate. The multiple dielectric layers include multiple groups of functional dielectric layers and an electrically isolating dielectric layer 500b located between two adjacent groups of functional dielectric layers. Each group of functional dielectric layers includes a first functional dielectric layer 500a1, a second functional dielectric layer 500a2, and a third functional dielectric layer 500a3 stacked in sequence.

[0246] For example, FIG. 26 a shows two sets of functional dielectric layers, thereby making two stacked storage layers.

[0247] In addition, two adjacent dielectric layers may be made of different dielectric materials. The above describes a variety of dielectric materials that can be selected, which will not be described in detail here.

[0248] In addition, the example shown in FIG. 26 a shows two groups of functional dielectric layers with two electrically isolating dielectric layers 500 b between them.

[0249] As shown in FIG26 b , a plurality of openings K1 are provided, and each opening K1 passes through multiple dielectric layers.

[0250] For example, the plurality of openings K may be arranged at intervals along the X direction parallel to the substrate.

[0251] As shown in FIG. 26 c , dielectric material is filled into each opening K1 to completely fill the opening K1 .

[0252] As shown in FIG26 d , a plurality of through holes 61 arranged at intervals are provided between every two adjacent openings K1 , and the plurality of through holes 61 between every two adjacent openings K1 may also be arranged along the Y direction perpendicular to the X direction.

[0253] Furthermore, each through hole 61 penetrates through the multiple dielectric layers and is used to be filled with a conductive material to form a word line WL.

[0254] As shown in FIG26e, the third functional dielectric layer 500a3 is selectively etched to form a plurality of grooves 711 on the third dielectric layer 500a3. The plurality of grooves 711 are formed at intervals in the third functional dielectric layer 500a3. Two adjacent grooves 711 are separated by the dielectric layer.

[0255] Furthermore, the groove 711 surrounds the periphery of the through hole 61 made in FIG. 26 d , because the groove 711 is for forming the second electrode 12 of the transistor Tr.

[0256] As shown in FIG26 f , the groove 711 opened in FIG26 e is filled with metal to obtain the second electrode 12 of the transistor Tr.

[0257] In addition, when the second electrode 12 of FIG. 26 f is manufactured by a deposition process, metal may also be deposited in the through hole 61 . Therefore, the metal in the through hole 61 needs to be etched back.

[0258] As shown in FIG. 26 g , the first functional dielectric layer 500 a 1 is selectively etched to form a plurality of grooves 712 on the first functional dielectric layer 500 a 1 , and positions of the plurality of grooves 712 correspond to positions of the grooves 711 opened as shown in FIG. 26 e .

[0259] As shown in Figure 26h, a metal layer 8 is formed on the wall surface of the groove 712. In order to clearly show the partial diagram, Figure 26h shows a partial structural diagram of Figure 26g.

[0260] As shown in FIG26i , the metal layer at the edge of the groove 712 close to the through hole 61 is etched back.

[0261] As shown in FIG26 j , a capacitor material is filled to form a capacitor layer 23 on the metal layer produced in FIG26 i and at the edge of the groove 712 near the through hole 61 .

[0262] Since the capacitor material will be formed in the through hole 61 , the capacitor material in the through hole 61 needs to be etched away.

[0263] As shown in FIG26 k , the remaining space of the groove 712 is filled with metal material to form the first capacitor electrode 21 of the capacitor C.

[0264] Similarly, the metal material in the filled through-hole 61 needs to be etched away.

[0265] As shown in FIG261 , a gate dielectric layer 15 , a channel layer 14 and a metal layer are sequentially stacked on the inner wall surface of the through hole 61 , and the metal layer forms the word line WL of the memory array.

[0266] The dielectric layer between two adjacent second electrodes 12 on each third functional dielectric layer 500a3 is etched away along the Y direction parallel to the substrate, so that multiple second electrodes 12 along the Y direction parallel to the substrate are electrically connected to form a bit line BL.

[0267] In addition, the electrical isolation dielectric layer 500b is etched away so that the channel layer formed in FIG. 26l and located in the electrical isolation dielectric layer 500b perpendicular to the substrate is isolated, forming the structure shown in FIG. 26m.

[0268] As shown in FIG. 26 n , the second functional dielectric layer 500 a 2 is selectively etched, and metal PL is filled so that the second capacitor electrodes of the capacitor layer on the same layer are interconnected through the plate lines PL, thereby forming the final 3D 1T1C memory array.

[0269] In order to clearly show the local diagram, Figures 26h to 26n show partial structural diagrams during the formation process of the memory array.

[0270] Based on the above-mentioned 3D 1T1C memory array fabrication method, it can be seen that after stacking multiple dielectric layers, multiple memory layers can be fabricated simultaneously using processes such as etching openings, selective etching, and deposition, rather than fabricating one memory layer first and then another.

[0271] When manufacturing a memory device by stacking one memory array layer and then another, as the storage density continues to increase, the number of stacked layers also increases, and the requirements for photolithographic alignment accuracy become increasingly higher. If the alignment accuracy of the lower memory array structure with the upper memory array structure is low, the read and write performance may be affected. However, the memory array manufacturing method provided by the embodiment of the present application has lower requirements for photolithographic alignment accuracy and does not pose a high challenge to the process. In this way, it can not only simplify the process and reduce the process difficulty, but also improve the product quality rate and the read and write performance of the memory device. In addition, it can also reduce the manufacturing cost of the memory device.

[0272] 27a to 27h illustrate the process structure after each step is completed in the process of manufacturing a memory array according to an embodiment of the present application.

[0273] As shown in Figure 27a, multiple dielectric layers are stacked on the substrate 100. The multiple dielectric layers include multiple groups of functional dielectric layers and an electrically isolating dielectric layer 500 located between two adjacent groups of functional dielectric layers. Each group of functional dielectric layers includes a first functional dielectric layer 500a1, a second functional dielectric layer 500a2 and a third functional dielectric layer 500a3 stacked in sequence.

[0274] For example, FIG. 27 a shows two sets of functional dielectric layers, thereby making two stacked storage layers.

[0275] Two adjacent dielectric layers may be made of different dielectric materials. The above describes a variety of dielectric materials that can be selected and will not be repeated here.

[0276] 27a, a plurality of first through holes 611 are formed at intervals, and each first through hole 611 penetrates through the multiple dielectric layers. The first through holes 611 are used to be filled with conductive material to form word lines WL.

[0277] As shown in FIG27b, the third functional dielectric layer 500a3 is selectively etched to form a plurality of grooves on the third dielectric layer 500a3. The plurality of grooves are formed at intervals in the third functional dielectric layer 500a3. Two adjacent grooves are separated by the dielectric layer.

[0278] Furthermore, the groove surrounds the periphery of the first through hole 611 made in FIG27b, because the groove is for forming the second electrode 12 of the transistor Tr.

[0279] The formed groove is filled with metal to form the second electrode 12 of the transistor Tr.

[0280] In addition, when the second electrode 12 of FIG. 27 b is manufactured by a deposition process, metal may also be deposited in the first through hole 611 . Therefore, the metal in the first through hole 611 needs to be etched back.

[0281] As shown in FIG27 c , a gate dielectric layer and a metal layer are sequentially formed on the inner wall surface of the first through hole 611 , and the metal layer forms the word line WL of the memory array.

[0282] Furthermore, a plurality of second through holes 612 are provided, each of which is arranged at intervals and is located between two adjacent first through holes 611. Each second through hole 612 passes through the dielectric layers.

[0283] As shown in FIG27 d , the second functional dielectric layer 500 a 2 is selectively etched to form a plurality of grooves 712 on the second functional dielectric layer 500 a 2 . The grooves 712 surround the periphery of the second through hole 612 , and the grooves 712 remain in the gate dielectric layer 15 within the first through hole 611 .

[0284] As shown in FIG27e, semiconductor material is deposited on the inner wall surface of the groove 712, and the semiconductor material at the outer edge of the groove 712 near the second through hole 612 is etched back to form a channel layer 14, and then the dielectric material is continuously filled to fill the groove 712.

[0285] As shown in FIG27 f ​​, the first functional dielectric layer 500 a 1 is selectively etched to form a plurality of grooves 713 on the first functional dielectric layer 500 a 1 . The grooves 713 surround the periphery of the second through hole 612 , and the grooves 712 remain in the gate dielectric layer 15 within the first through hole 611 .

[0286] As shown in FIG27g , a metal layer is formed on the inner wall surface of the groove 713 , and the metal layer located at the outer edge of the groove 713 near the second through hole 612 is etched back to obtain the first capacitor electrode of the capacitor C.

[0287] The capacitor material is filled to form a capacitor layer 23 on the metal layer produced in FIG. 27 g at the edge of the groove 713 close to the second through hole 612 .

[0288] Since the capacitor material will be formed in the second through hole 612 , the capacitor material in the second through hole 612 needs to be etched away.

[0289] As shown in FIG27h , the remaining space of the groove 713 is filled with metal material to form the first capacitor electrode 21 of the capacitor C. The second through hole 612 is filled with metal material to form a strip-shaped plate line PL. The final 3D 1T1C memory array is thus formed.

[0290] Based on the above description of the memory array process structure and formation method, it can be seen that a memory layer can be produced by patterning three adjacent dielectric layers, wherein one dielectric layer is patterned into a first metal layer, another dielectric layer is patterned into a second metal layer, and another dielectric layer is disposed between the two metal layers. Furthermore, the first electrodes of the capacitors and transistors in the memory cells are formed in the first metal layer, and the second electrodes of the transistors are formed in the second metal layer.

[0291] The “first electrodes of the capacitor and the transistor are formed in the first metal layer” involved in the embodiments of the present application can be understood as: in the process, patterning is performed in a film layer (for example, a dielectric layer) structure parallel to the substrate to form the first electrodes of the capacitor and the transistor, so that the first electrodes of the capacitor and the transistor are in the first metal layer parallel to the substrate, rather than the two capacitor electrodes in the capacitor, the capacitor layer and the first electrode of the transistor being stacked in a direction perpendicular to the substrate.

[0292] Similarly, the “second electrode of the transistor is formed in the second metal layer” involved in the embodiments of the present application can be understood as: in the process, patterning is performed in a film layer (for example, a dielectric layer) structure parallel to the substrate to form the second electrode of the transistor, so that the second electrode of the transistor is in the second metal layer parallel to the substrate.

[0293] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0294] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A storage array, characterized in that: include: substrate; A plurality of storage layers are formed on the substrate, wherein the plurality of storage layers are stacked along a direction perpendicular to the substrate; Each of the memory layers includes a plurality of memory cells, and each of the memory cells includes a transistor and a capacitor electrically connected to the transistor; The transistor includes a first electrode, a second electrode, a gate and a channel layer; The capacitor comprises a first capacitor electrode, a capacitor layer and a second capacitor electrode; The first electrode is electrically connected to the first capacitor electrode; Each of the storage layers includes a first metal layer and a second metal layer stacked in a direction perpendicular to the substrate, wherein the first metal layer and the second metal layer are electrically isolated by a dielectric layer; The first electrode of the transistor and the capacitor are formed in the first metal layer, and the second electrode of the transistor is formed in the second metal layer; At least a portion of the gate and at least a portion of the channel layer penetrate the dielectric layer, and the channel layer surrounds the periphery of the gate; The first capacitor electrode, the capacitor layer and the second capacitor electrode are stacked in a direction parallel to the substrate, and the capacitor layer surrounds the periphery of the first capacitor electrode.

2. The storage array according to claim 1, wherein: One end of the gate extends into the first metal layer, the first electrode surrounds the periphery of the gate and is electrically isolated from the gate by a gate dielectric layer; The other end of the gate extends into the second metal layer. The second electrode surrounds the periphery of the gate and is electrically isolated from the gate by a gate dielectric layer.

3. The storage array according to claim 1 or 2, wherein: One end of the channel layer extends into the second metal layer, and the second electrode surrounds the outer periphery of the channel layer.

4. The storage array according to any one of claims 1 to 3, wherein: The other end of the channel layer extends into the first metal layer; The first electrode and the first capacitor electrode share the same electrode; The first capacitor electrode surrounds the periphery of the channel layer.

5. The storage array according to claim 1 or 2, wherein: The channel layer located in the dielectric layer includes a surrounding channel and a first planar channel connected to the surrounding channel, wherein the first planar channel is parallel to the substrate; The surrounding channel surrounds the periphery of the gate; A surface of the second pole facing the first pole contacts the first planar channel.

6. The storage array according to claim 5, wherein: The channel layer located in the dielectric layer further includes a second planar channel parallel to the substrate and opposite to the first planar channel, and the first planar channel and the second planar channel are connected through the surrounding channel; The second planar channel contacts the first pole.

7. The storage array according to any one of claims 1 to 6, wherein: The first capacitor electrode includes a surrounding electrode surrounding the periphery of the gate, and a planar electrode connected to the surrounding electrode and arranged parallel to the substrate, so that the first capacitor electrode forms a horizontal contact surface parallel to the substrate and a vertical contact surface perpendicular to the substrate, and the capacitor layer is formed on both the horizontal contact surface and the vertical contact surface.

8. The storage array according to claim 7, wherein: The planar electrode includes a first planar electrode and a second planar electrode arranged opposite to each other. The first planar electrode and the second planar electrode are connected by the surrounding electrode so that a groove with an opening is formed in the first capacitor electrode, and the opening of the groove faces away from the gate. The capacitor layer and the second capacitor electrode are sequentially arranged on the inner wall surface of the groove to form the capacitor layer having a first notch, and the first notch faces away from the gate.

9. The storage array according to claim 8, wherein: Each of the storage layers further includes a first electrode line, and the second capacitor electrode of the capacitor is electrically connected to the first electrode line; The first electrode line extends in a direction perpendicular to the substrate, and the first electrode line is arranged close to the first notch; In the multiple storage layers, the second capacitor electrodes of the multiple capacitors arranged perpendicular to the substrate are electrically connected to the same first electrode line.

10. The storage array according to claim 7, wherein: The planar electrode is in a plate-like structure and is connected to the surrounding electrode to form the capacitor layer having a second notch facing the gate. The second capacitor electrode is arranged on a surface of the capacitor layer away from the first capacitor electrode.

11. The storage array according to claim 10, wherein: Each of the storage layers further includes a first electrode line, and the second capacitor electrode of the capacitor is electrically connected to the first electrode line; The first electrode line is in a plate-like structure and is arranged parallel to the substrate, and the first electrode line is arranged away from the second notch; In each of the storage layers, the second capacitor electrodes of a plurality of the capacitors are electrically connected to the same first electrode line.

12. The storage array according to any one of claims 1 to 11, wherein: Each of the storage layers further includes a second electrode line and a third electrode line; The gate of the transistor is electrically connected to the second electrode line; The second electrode of the transistor is electrically connected to the third electrode line.

13. The storage array according to claim 12, wherein: The second electrode line extends in a direction perpendicular to the substrate; In the multiple storage layers, the gates of the multiple transistors arranged vertically to the substrate are electrically connected to the same second electrode line.

14. The storage array according to claim 12 or 13, wherein: The third electrode line extends in a direction parallel to the substrate; In each of the storage layers, the second electrodes of a plurality of the transistors arranged parallel to the substrate are electrically connected to the same third electrode line.

15. The storage array according to any one of claims 1 to 14, wherein: The first metal layer is disposed close to the substrate, and the second metal layer is disposed far from the substrate.

16. The storage array according to any one of claims 1 to 15, wherein: The memory array is a DRAM memory array, or the memory array is a ferroelectric memory array.

17. The storage array according to any one of claims 1 to 16, wherein: The plurality of storage layers are formed on the substrate by adopting a back-end process.

18. A memory, characterized in that: include: The storage array according to any one of claims 1 to 17; A controller is electrically connected to the storage array and is used to control the reading and writing of the storage array.

19. An electronic device, characterized in that: include: processor; The memory according to claim 18, wherein the processor is electrically connected to the memory, and the memory is used to store data generated by the processor.

20. A method for forming a memory array, characterized in that: The forming method comprises: stacking a plurality of dielectric layers on a substrate, the plurality of dielectric layers comprising a plurality of groups of functional dielectric layers and an electrical isolation dielectric layer located between two adjacent groups of the functional dielectric layers, wherein each group of the functional dielectric layers comprises a first functional dielectric layer, a second functional dielectric layer, and a third functional dielectric layer stacked in sequence; Patterning the multiple groups of functional dielectric layers to form a plurality of stacked storage layers, each storage layer comprising a first metal layer obtained by patterning the first functional dielectric layer, a second metal layer obtained by patterning the third functional dielectric layer, and a second functional dielectric layer located between the first metal layer and the second metal layer, each storage layer comprising a plurality of storage cells, each of the storage cells comprising a transistor and a capacitor; Wherein, the transistor includes a first electrode, a second electrode, a gate and a channel layer; The capacitor comprises a first capacitor electrode, a capacitor layer and a second capacitor electrode; The first electrode of the transistor and the capacitor are formed in the first metal layer, and the second electrode of the transistor is formed in the second metal layer; At least a portion of the gate and at least a portion of the channel layer are formed in the second functional dielectric layer, and the channel layer surrounds the periphery of the gate; The first capacitor electrode, the capacitor layer and the second capacitor electrode are stacked in a direction parallel to the substrate, and the capacitor layer surrounds the periphery of the first capacitor electrode.

21. The method for forming a memory array according to claim 20, wherein: Forming the gate includes: A first through hole is opened along a direction perpendicular to the substrate and passes through the multi-layer dielectric layer, and a conductive material is filled in the first through hole to form the gate of the transistor.

22. The method for forming a memory array according to claim 21, wherein: After forming the first through hole penetrating the multi-layer dielectric layer and before filling the first through hole with a conductive material, the forming method further includes: The first through hole is filled with a semiconductor material to form the channel layer of the transistor on the inner wall surface of the first through hole.

23. The method for forming a memory array according to claim 21, wherein: The first capacitor electrode, the capacitor layer, and the second capacitor electrode of the capacitor are formed, including: Before the first through hole is filled with the conductive material and the gate is formed, a first groove is opened in the first functional dielectric layer, with the opening of the first groove facing the first through hole, and the first capacitor electrode, the capacitor layer and the second capacitor electrode are formed in the first groove to form the capacitor layer with a notch and the notch facing the first through hole.

24. The method for forming a memory array according to claim 21, wherein: The first capacitor electrode, the capacitor layer, and the second capacitor electrode of the capacitor are formed, including: After filling the first through hole with the conductive material to form the gate, a second through hole is opened in a direction perpendicular to the substrate and passes through the multi-layer dielectric layer; A second groove is opened in the first functional medium layer, the opening of the second groove faces the second through hole, and the bottom surface of the second groove passes through the first through hole. The first capacitor electrode, the capacitor layer and the second capacitor electrode are formed in the second groove to form the capacitor layer with a notch and the notch facing away from the first through hole.

25. The method for forming a memory array according to claim 24, wherein: After the second through hole is formed through the multi-layer dielectric layer, the forming method further includes: A third groove is formed in the second functional dielectric layer, with an opening of the third groove facing the second through hole. Semiconductor material is filled in the third groove to form the channel layer of the transistor on an inner wall surface of the third groove.

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