Light emitting diode chip structure

Abstract

The application discloses a light emitting diode (LED), and more specifically, discloses an LED chip structure. The LED chip structure includes one or more arrangements of contacts, interconnects, contact structures, and / or reflective layers that effectively rout conductive paths while reducing instances of charged metals that are opposite in polarity and too close in pitch. Certain LED chip structures include electrically isolated metal-containing layers at various locations of the chip that allow for vertical placement of n-type contact interconnects below or near p-type contacts. Certain contact structures include various arrangements, including segmented contact structures that extend laterally to electrically couple n-type contact interconnect sets across various portions of the LED chip.

Description

Technical Field

[0001] The present disclosure relates to light emitting diodes (LEDs), and more particularly, to LED chip structures. Background Art

[0002] Solid-state lighting devices, such as light-emitting diodes (LEDs), are increasingly used in consumer and commercial applications. Advances in LED technology have resulted in light sources that are efficient, rugged, and have a long lifespan. As a result, modern LEDs have enabled a variety of new display applications and are increasingly used in general lighting, often replacing incandescent and fluorescent sources.

[0003] An LED is a solid-state device that converts electrical energy into light and typically includes one or more active layers (or active regions) of semiconductor material arranged between n-type and p-type layers of opposite doping types. When a bias voltage is applied between the doped layers, holes and electrons are injected into the one or more active layers where they recombine to produce radiation such as visible light or ultraviolet light. The active region can be made of, for example, silicon carbide, gallium nitride, gallium phosphide, aluminum nitride, and / or gallium arsenide-based materials and / or organic semiconductor materials. Photons generated by the active region are emitted in all directions.

[0004] Generally, it is desirable for an LED to operate at maximum luminous efficiency, which can be measured by emission intensity related to output power (e.g., in lumens per watt). A practical goal of improving luminous efficiency is to maximize the amount of light extracted from the active region in the desired transmission direction. The light extraction efficiency and external quantum efficiency of an LED may be limited by a variety of factors, including internal reflections and current injection. In order to enhance current diffusion within an LED chip (particularly for large-area LED chips), it has been found useful to add a high conductivity layer to one or more epitaxial layers of the LED. In addition, the electrodes of the LED may have a larger surface area and may include various electrode arrangements that are configured to conduct current and distribute it more evenly across the LED.

[0005] As modern LED technology advances, the art continues to seek improved LEDs and solid-state lighting devices with desirable lighting characteristics that overcome the challenges associated with traditional lighting devices. Summary of the invention

[0006] The present disclosure relates to light emitting diodes (LEDs), and more particularly, to LED chip structures. The LED chip structures include arrangements of one or more contacts, interconnects, contact structures, and / or reflective layers that effectively lay out conductive paths while reducing instances of charged metals of opposite polarity and spaced too closely together. Certain LED chip structures include electrically isolated metal-containing layers at various locations on the chip that allow for the presence of n-type contact interconnects that are vertically arranged below or near p-type contacts. Certain contact structures include various arrangements, including segmented contact structures that extend laterally to electrically couple groups of n-type contact interconnects across portions of the LED chip.

[0007] In one aspect, an LED chip includes: an active LED structure including an n-type layer, a p-type layer, and an active layer arranged between the n-type layer and the p-type layer; an n-type contact electrically coupled to the n-type layer; a p-type contact electrically coupled to the p-type layer; and a plurality of n-type contact interconnects electrically coupled between the n-type layer and the n-type contact, wherein one or more of the plurality of n-type contact interconnects are vertically arranged between the p-type contact and the n-type layer. In some embodiments, one or more of the plurality of n-type contact interconnects are electrically coupled to an n-type contact structure, which is electrically coupled to the n-type contact. In some embodiments, the n-type contact structure is arranged to extend laterally from a position vertically aligned with the n-type contact to a position vertically aligned with the p-type contact, such that the n-type contact structure is electrically coupled to one or more of the plurality of n-type contact interconnects vertically arranged between the p-type contact and the n-type layer.

[0008] The LED chip may further include: a peripheral n-type contact interconnect electrically coupled to a portion of the n-type layer outside the mesa sidewall of the active LED structure, the mesa sidewall including the sidewalls of the p-type layer, the active layer, and a portion of the n-type layer; wherein the n-type contact structure is arranged to extend laterally from a position vertically aligned with the n-type contact to the mesa sidewall, so that the n-type contact structure is electrically coupled to the peripheral n-type contact interconnect. In some embodiments, the peripheral n-type contact interconnect is electrically coupled to one or more n-type contact interconnects vertically arranged between the p-type contact and the n-type layer among the plurality of n-type contact interconnects. In some embodiments, the peripheral n-type contact interconnect is electrically coupled to a portion of the n-type layer outside the mesa sidewall in a continuous manner near two or more peripheral edges of the active LED structure. In some embodiments, the peripheral n-type contact interconnect is electrically coupled to a portion of the n-type layer outside the mesa sidewall in a discontinuous manner, so that a portion of the peripheral n-type contact interconnect is in contact with the n-type layer, and other portions of the peripheral n-type contact interconnect are separated from the n-type layer by a passivation layer.

[0009] In some embodiments, the LED chip further includes a reflective structure on the active LED structure, wherein the reflective structure includes an electrically insulating first reflective layer, a conductive second reflective layer, and a plurality of reflective layer interconnects extending through the first reflective layer to electrically couple a first portion of the second reflective layer to the p-type layer. In some embodiments, the second portion of the second reflective layer is electrically isolated from the active LED structure. In some embodiments, the second portion of the second reflective layer is vertically arranged between the n-type contact structure and the active LED structure. In some embodiments, the second portion of the second reflective layer is completely separated from the p-type layer by a passivation layer, and the second portion of the second reflective layer is electrically coupled to the n-type contact.

[0010] The LED chip may further include: a passivation layer on the active LED structure, wherein a plurality of n-type contact interconnects extend through a portion of the passivation layer; and a first metal-containing intermediate layer, a second metal-containing intermediate layer, and a third metal-containing intermediate layer arranged within the passivation layer, wherein each of the first metal-containing intermediate layer, the second metal-containing intermediate layer, and the third metal-containing intermediate layer is electrically isolated from the n-type contact and the p-type contact.

[0011] In some embodiments, the n-type contact and the p-type contact are contact pads that are used to receive external electrical connections when the LED chip is mounted in a flip-chip manner.

[0012] On the other hand, the LED chip includes: an active LED structure including an n-type layer, a p-type layer, and an active layer arranged between the n-type layer and the p-type layer; a passivation layer on the active LED structure; and a first metal-containing intermediate layer, a second metal-containing intermediate layer, and a third metal-containing intermediate layer at least partially within the passivation layer, wherein each of the first metal-containing intermediate layer, the second metal-containing intermediate layer, and the third metal-containing intermediate layer is electrically isolated from the active LED structure. The LED chip may further include: a reflective structure on the active LED structure, wherein the reflective structure includes an electrically insulating first reflective layer, a conductive second reflective layer, and a plurality of reflective layer interconnects extending through the first reflective layer to electrically couple a first portion of the second reflective layer to the p-type layer; wherein the second metal-containing intermediate layer includes a second portion of the second reflective layer that is electrically isolated from the active LED structure. The LED chip may further include: an n-type contact electrically coupled to the n-type layer; a p-type contact electrically coupled to the p-type layer; a plurality of n-type contact interconnects electrically coupled between the n-type layer and the n-type contact; and an n-type contact structure electrically coupled to one or more of the plurality of n-type contact interconnects, wherein the n-type contact structure is arranged to extend laterally within the passivation layer. In some embodiments, the third metal-containing intermediate layer comprises the same material as the n-type contact structure. In some embodiments, the second metal-containing intermediate layer is vertically arranged between the n-type contact structure and the active LED structure. The LED chip may further include: a reflective structure on the active LED structure, wherein the reflective structure comprises an electrically insulating first reflective layer, a conductive second reflective layer, and wherein the first reflective layer is between the second reflective layer and the p-type layer; wherein the second metal-containing intermediate layer comprises a portion of the second reflective layer that is electrically isolated from the active LED structure. In some embodiments, the portion of the second reflective layer that is electrically isolated from the active LED structure is vertically arranged between the n-type contact structure and the active LED structure. In certain embodiments, the first metal-containing intermediate layer, the second metal-containing intermediate layer, and the third metal-containing intermediate layer are vertically arranged within the passivation layer.

[0013] On the other hand, the LED chip includes: an active LED structure including an n-type layer, a p-type layer, and an active layer arranged between the n-type layer and the p-type layer; a plurality of n-type contact interconnects electrically coupled to the n-type layer; and an n-type contact structure electrically coupled to the plurality of n-type contact interconnects, the n-type contact structure including: a first segment connected to a first group of n-type contact interconnects among the plurality of n-type contact interconnects, and a second segment connected to a second group of n-type contact interconnects among the plurality of n-type contact interconnects. In some embodiments, the first segment of the n-type contact structure is discontinuous with the second segment of the n-type contact structure. In some embodiments, the first segment of the n-type contact structure is arranged to extend continuously from one edge of the active LED structure to the opposite edge of the active LED structure. In some embodiments, the second segment of the n-type contact structure is arranged to extend continuously, but not to at least one edge of the active LED structure. The LED chip may further include: an n-type contact electrically coupled to the n-type contact structure; and a p-type contact electrically coupled to the p-type layer; wherein the plurality of n-type contact interconnects are arranged vertically outside the peripheral edge of the p-type contact. In some embodiments, the p-type contact includes: a first portion vertically arranged between a boundary of a first segment of the n-type contact structure and a periphery of the active LED structure; and a second portion vertically arranged between another boundary of the first segment of the n-type contact structure and a boundary of the second segment of the n-type contact structure, wherein the first portion of the p-type contact is discontinuous with the second portion of the p-type contact.

[0014] On the other hand, the various aspects described above can be used alone or in combination, and / or the various independent aspects and features described herein can be combined to achieve additional advantages. Unless otherwise specified herein, any of the various features and elements disclosed herein can be combined with other one or more disclosed features and elements.

[0015] Those skilled in the art will appreciate the scope of the present disclosure and implement additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and together with the description serve to explain the principles of the disclosure.

[0017] 1A is a top view of a typical light emitting diode (LED) chip having a flip chip structure including an active LED structure and an n-type contact interconnect disposed along or within certain portions of the active LED structure.

[0018] 1B is a bottom view of the LED chip of FIG. 1A , showing the locations of the p-type and n-type contacts.

[0019] Figure 2A is a top view of an LED chip in a flip-chip configuration according to the principles of the present disclosure, wherein an n-type contact interconnect is arranged across an increased area of ​​the active LED structure.

[0020] Figure 2B yes Figure 2A Bottom view of an LED chip, showing the locations of the p-contact and n-contact pads.

[0021] Figure 3 is with Figure 2A and 2B An LED chip in FIG. 1 is a schematic cross-sectional view of a portion of an LED chip similar to FIG.

[0022] Figure 4A The cross-sectional view is a manufacturing step in which an active LED structure is formed on a substrate with a portion of an LED chip, and a plurality of first openings are defined through a p-type layer, an active layer, and a portion of an n-type layer of the active LED structure.

[0023] Figure 4B yes Figure 4A An exemplary top view of an LED chip in FIG. 1 shows how the first openings are arranged in an array on the LED chip.

[0024] Figure 5A yes Figure 4A A cross-sectional view of a portion of an LED chip in a manufacturing step after a current diffusion layer is formed on the p-type layer.

[0025] Figure 5B yes Figure 5A An exemplary top view of an LED chip in FIG. 1 shows how the current spreading layer is arranged relative to each first opening.

[0026] Fig. 6A yes Figure 5A A cross-sectional view of a portion of an LED chip in a manufacturing step after a first reflective layer is formed and a plurality of second openings and a third opening are formed through the first reflective layer.

[0027] Figure 6B yes Fig. 6A An exemplary top view of an LED chip in FIG. 1 shows how the second opening and the third opening may be arranged relative to the first opening.

[0028] Fig. 7A yes Fig. 6A A cross-sectional view of a portion of an LED chip in a manufacturing step after a second reflective layer is formed on the first reflective layer.

[0029] Figure 7B yes Fig. 7AAn exemplary top view of an LED chip in FIG. 1 shows how the second reflective layer is arranged relative to the first opening and the second opening.

[0030] Figure 8 yes Fig. 7A A cross-sectional view of a portion of an LED chip in a manufacturing step after a portion of a passivation layer is formed on the second reflective layer.

[0031] Fig. 9A yes Figure 8 A cross-sectional view of a portion of an LED chip in a manufacturing step after forming an n-type contact structure, an n-type contact interconnection, and a third intermediate layer.

[0032] Fig. 9B yes Fig. 9A An exemplary top view of an LED chip in FIG. 1 shows the layout pattern of the n-type contact structure, n-type contact interconnection and the third intermediate layer on the active LED structure.

[0033] Fig. 10A yes Fig. 9A A cross-sectional view of a portion of an LED chip in a manufacturing step after forming a passivation layer and an additional portion of a first intermediate layer.

[0034] Fig. 10B yes Fig. 10A An exemplary top view of an LED chip in FIG. 1 shows the layout pattern of the first intermediate layer.

[0035] Fig.11 yes Fig. 10A A cross-sectional view of a manufacturing step after forming an additional portion of the passivation layer on the first intermediate layer and forming an eighth opening and a ninth opening through the sixth opening and the seventh opening, respectively.

[0036] Fig.12 yes Fig.11 A cross-sectional view of a portion of an LED chip in a manufacturing step after forming a p-type contact, a p-type contact via, an n-type contact, and an n-type contact via.

[0037] Fig.13A is a cross-sectional view of a portion of an LED chip. Fig.12 The LED chip in A is similar, and in this figure, the n-contact structure also includes a peripheral n-contact interconnect running along the peripheral edge of the LED chip.

[0038] Fig. 13B yes Fig.13A An exemplary top view of an LED chip in FIG. 1 shows the layout pattern of n-type contact interconnects, peripheral n-type contact interconnects, and n-type contacts relative to p-type contacts.

[0039] Fig.14Ais an exemplary top view of an LED chip with Fig.13A and 13B The LED chip in FIG. 1 is similar to that in FIG. 1 , and the figure further presents an implementation in which the electrical connection between the peripheral n-type contact interconnect and the n-type layer is segmented along the periphery of the LED chip.

[0040] Fig. 14B yes Fig.14A The LED chips in Fig.14A A cross-sectional view taken along section line 14B-14B.

[0041] Fig. 14C yes Fig.14A The LED chips in Fig.14A A cross-sectional view taken along section line 14C-14C.

[0042] Fig.15 is an exemplary top view of an LED chip with Fig.13A and 13B The LED chip in FIG. 1 is similar to that in FIG. 1 and includes an alternative arrangement in which the n-contact interconnect is not vertically aligned below the p-contact.

[0043] Fig.16 is an exemplary top view of an LED chip with Fig.15 The LED chip in FIG. 1 is similar to FIG. 1 , and this figure includes an arrangement in which the p-type contact covers a larger area of ​​the LED chip.

[0044] Fig.17A is a top view of an LED chip that will have a segmented p-type contact in a manufacturing step after other elements such as reflective layer interconnect, n-type contact interconnect, n-type contact structure, peripheral n-type contact interconnect, and openings have been formed.

[0045] Fig. 17B yes Fig.17A A top view of an LED chip in a subsequent manufacturing step after other elements such as segmented p-contacts, p-contact vias, and n-contacts have been formed.

[0046] Fig.18 is a top view of an LED chip with a pattern of n-type contact interconnects and reflective layer interconnects according to the principles disclosed herein.

[0047] Fig.19 is a top view of an LED chip. Fig.18 The LED chip in is similar to that in FIG and includes a higher density of n-type contact interconnects and reflective layer interconnects.

[0048] Fig. 20 is a top view of an LED chip. Fig.18The LED chip in FIG. 1 is similar to that in FIG. 1 , except that the n-type contact interconnect is not aligned between the boundary of the p-type contact and the active LED structure.

[0049] Fig.21 is a cross-sectional view of a portion of an LED chip, for an embodiment in which some portion of the second reflective layer is electrically coupled to the n-type contact, the LED chip is electrically coupled to the n-type contact. Fig.13A The LED chips in are similar. DETAILED DESCRIPTION

[0050] The embodiments described below present the necessary information to enable those skilled in the art to practice these embodiments and illustrate the best way to practice these embodiments. After reading the following description in conjunction with the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will be able to recognize the applications of these concepts not specifically mentioned in the present disclosure. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0051] It will be understood that although the terms first, second, etc. may be used in this article to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used in this article, the term "and / or" includes any and all combinations of one or more related listed items.

[0052] It should be understood that when an element such as a layer, region or substrate is referred to as "on another element" or "extending onto another element", the element may be directly located on another element or directly extend onto another element, or there may also be an intermediate element. On the contrary, when an element is referred to as "directly on another element" or "directly extending onto another element", there is no intermediate element. Similarly, it should be understood that when an element such as a layer, region or substrate is referred to as "above another element" or "extending above another element", the element may be directly above another element or directly extend above another element, or there may also be an intermediate element. On the contrary, when an element is referred to as "directly above another element" or "extending directly above another element", there is no intermediate element. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to another element, or there may be an intermediate element. On the contrary, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0053] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region as shown in the figures. It should be understood that these terms and those above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0054] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms as well. It should be further understood that when used herein, the terms "comprises", "comprising", "includes" and / or "including" specify the presence of features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups.

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should be further understood that the terms used herein should be interpreted as having the same meaning as they have in the context of this specification and the relevant art, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined in this article.

[0056] The embodiments described below are described with reference to the schematic diagrams of the embodiments of the present disclosure. Therefore, the actual sizes of the layers and elements may vary, and due to factors such as manufacturing processes and / or tolerances, it is expected that there will be deviations from the illustrated shapes. For example, an area illustrated or described as a square or rectangle may have circular or arc-shaped features, and an area shown as a straight line may have some irregularities. Therefore, the areas shown in the drawings are schematic, and their shapes are not intended to represent the precise shapes of the areas in the device, nor are they intended to limit the scope of the present disclosure. In addition, for ease of explanation, the size of a structure or area may be enlarged relative to other structures or areas, and therefore, these illustrations are intended to show the general structure of the subject matter, and may or may not be drawn to scale. The same elements between the drawings may be represented by the same element numbers herein, and may not be re-described later.

[0057] The present disclosure relates to light emitting diodes (LEDs), and more particularly, to LED chip structures. The LED chip structures include arrangements of one or more contacts, interconnects, contact structures, and / or reflective layers that effectively lay out conductive paths while reducing instances of charged metals of opposite polarity and spaced too closely together. Certain LED chip structures include electrically isolated metal-containing layers at various locations on the chip that allow for the presence of n-type contact interconnects that are vertically arranged below or near p-type contacts. Certain contact structures include various arrangements, including segmented contact structures that extend laterally to electrically couple groups of n-type contact interconnects across portions of the LED chip.

[0058] The LED chip typically includes an active LED structure or region, which may have a variety of different semiconductor layers arranged in different ways. The manufacture and operation of LEDs and their active structures are generally known in the art and are only briefly discussed here. The layers of the active LED structure can be manufactured using known processes, one suitable process of which is to use metal organic chemical vapor deposition for manufacturing. The layers of the active LED structure can include a variety of different layers, and typically include an active layer sandwiched between n-type and p-type epitaxial layers of opposite doping types, all of which are formed sequentially on a growth substrate. It is understood that other layers and elements may also be included in the active LED structure, including but not limited to buffer layers, nucleation layers, superlattice structures, undoped layers, cladding layers, contact layers, current diffusion layers, and light extraction layers and elements. The active layer may include a single quantum well, a multiple quantum well, a double heterostructure, or a superlattice structure.

[0059] Active LED structures can be made from different material systems, some of which are based on Group III nitrides. Group III nitrides refer to those semiconductor compounds formed between nitrogen (N) and elements in Group III of the periodic table, typically aluminum (Al), gallium (Ga), and indium (In). Gallium nitride (GaN) is a common binary compound. Group III nitrides also refer to ternary and quaternary compounds, such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). For Group III nitrides, silicon (Si) is a common n-type dopant and magnesium (Mg) is a common p-type dopant. Therefore, for Group III nitride-based material systems, the active layer, n-type layer, and p-type layer may include one or more layers of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN), which can be undoped or doped with silicon (Si) or magnesium (Mg). Other material systems include silicon carbide (SiC), organic semiconductor materials, and other III-V systems such as gallium phosphide (GaP), gallium arsenide (GaAs), and related compounds.

[0060] The active LED structure can be grown on a growth substrate that can contain many materials such as sapphire, SiC, aluminum nitride (AlN), GaN, with a suitable substrate being 4H-type SiC, although other SiC types such as 3C, 6H, and 15R can also be used. SiC has certain advantages, such as a closer lattice match to III-nitrides than other substrates, enabling high-quality III-nitride films to be obtained. SiC also has very high thermal conductivity, so that the total output power of III-nitride devices on SiC is not limited by the heat dissipation of the substrate. Sapphire is another common substrate for III-nitrides and also has certain advantages, including lower cost, mature manufacturing process, and good light transmission optical properties.

[0061] Different embodiments of the active LED structure may emit light of different wavelengths depending on the composition of the active layer and the n-type and p-type layers. In some embodiments, the active LED structure may emit blue light with a peak wavelength range of approximately 430 nanometers (nm) to 480 nm. In other embodiments, the active LED structure may emit green light with a peak wavelength range of 500 nm to 570 nm. In other embodiments, the active LED structure may emit red light with a peak wavelength range of 600 nm to 650 nm. In some embodiments, the active LED structure may be configured to emit light beyond the visible spectrum, including one or more ultraviolet (UV) spectrum portions, as well as infrared (IR) or near infrared spectrum. The UV spectrum is generally divided into three wavelength range categories represented by the letters A, B, and C. In this way, UV-A light is generally defined as having a peak wavelength range of 315 nm to 400 nm, UV-B is generally defined as having a peak wavelength range of 280 nm to 315 nm, and UV-C is generally defined as having a peak wavelength range of 100 nm to 280 nm. The near-IR and / or IR wavelengths of the LED structures of the present disclosure may have wavelengths above 700 nm, such as in the range of 750 nm to 1100 nm, or even longer.

[0062] The LED chip may also be covered with one or more luminescent materials or other conversion materials, such as phosphors, so that at least part of the light from the LED chip is absorbed by the one or more phosphors and emits a spectrum converted to one or more different wavelengths according to the characteristics of the one or more phosphors. In some embodiments, the combination of the LED chip and the one or more phosphors emits a light combination that is generally white. One or more phosphors may include phosphors that emit yellow (e.g., YAG:Ce), green (e.g., LuAg:Ce) and red (e.g., Cai-x-ySrxEuyAlSiN3), and combinations thereof. The luminescent materials described herein may be or may include one or more of the following: phosphors, scintillators, luminescent inks, quantum dot materials, fluorescent strips, etc. The luminescent material may be provided in any suitable manner, for example, directly coated on one or more surfaces of the LED, dispersed in a packaging material used to cover one or more LEDs, and / or coated on one or more surfaces of an optical element or a supporting element (e.g., by powder coating, inkjet printing, etc.). In certain embodiments, the luminescent material may be a down-conversion or up-conversion material, and a combination of both down-conversion and up-conversion materials may be provided. In some embodiments, a plurality of different (e.g., different compositions) luminescent materials (or fluorescent materials) are arranged to produce different peak wavelengths and can be configured to receive emitted light from one or more LED chips. In some embodiments, one or more phosphors may include yellow phosphors (e.g., YAG:Ce), green phosphors (e.g., LuAg:Ce), and red phosphors (e.g., Cai-x-ySrxEuyAlSiN3) and combinations thereof. One or more luminescent materials may be provided in various configurations on one or more portions and / or pads of an LED chip.

[0063] Light emitted by the active layer or region of an LED chip can typically propagate in a variety of directions. For targeted directional applications, internal reflectors or external reflective surfaces can be used to redirect as much light as possible to the desired emission direction. The internal reflector can include a single layer or a multilayer structure. Some multilayer reflectors include a metal reflective layer and a dielectric reflective layer, wherein the dielectric reflective layer is arranged between the metal reflective layer and a plurality of semiconductor layers. A passivation layer is arranged between the metal reflective layer and the first and second electrical contacts, wherein the first electrical contact is arranged to form a conductive electrical connection with the first semiconductor layer, and the second electrical contact is arranged to form a conductive electrical connection with the second semiconductor layer. For single or multilayer reflectors including a surface exhibiting a reflectivity of less than 100%, some light may be absorbed by the reflector. In addition, light redirected by the active LED structure may be absorbed by other layers or elements within the LED chip.

[0064] As used herein, a layer or region of a light emitting device may be considered "transparent" when at least 80% of the emitted radiation incident on a layer or region of the light emitting device is able to pass through the layer or region. In addition, as used herein, a layer or region is considered to be "reflective" or embodied as a "reflector" or "reflector" when at least 80% of the emitted radiation incident on a layer or region of the LED is reflected. In some embodiments, the emitted radiation includes visible light, such as blue and / or green LEDs with or without luminescent materials. In other embodiments, the emitted radiation may include invisible light. For example, in the context of GaN-based blue and / or green LEDs, silver (Ag) can be considered a reflective material (e.g., at least 80% reflective). In the case of UV LEDs, suitable materials can be selected to achieve the desired reflectivity (high reflectivity in some embodiments) and / or the desired absorptivity (low absorptivity in some embodiments). In some embodiments, a "light-transmitting" material can be configured to transmit at least 50% of the emitted radiation of the desired wavelength.

[0065] The present disclosure can be used for LED chips having various geometries, including flip chip geometries. The flip chip structure of the LED chip typically includes anode and cathode connections made from the same side or face of the LED chip. The anode and cathode sides are typically configured as mounting surfaces for the LED chip so that the LED chip can be mounted to another surface, such as a printed circuit board, in a flip chip manner. In this regard, the anode and cathode connections on the mounting surface are used to mechanically engage and electrically couple the LED chip to the other surface. When mounted in a flip chip manner, the other side or face of the LED chip corresponds to the light emitting surface, which faces the intended light emitting direction. In some embodiments, when mounted in a flip chip manner, the growth substrate of the LED chip can form the light emitting surface and / or be adjacent to the light emitting surface. During the chip manufacturing process, the active LED structure can be epitaxially grown on the growth substrate. When electrically activated, light from the active LED structure can pass through the growth substrate in the desired light emitting direction. In some embodiments, the flip chip LED may not have a growth substrate.

[0066] In operation, the quantum efficiency of an LED chip may be a function of various factors, such as current injection efficiency and thermal management. These factors may be particularly important for larger sized LED chips (e.g., those having lateral dimensions of 500 micrometers (μm) and above), where current must spread over a larger surface area and the LED chip may generate more heat, although the principles disclosed herein are readily applicable to smaller LED chips having lateral dimensions below 500 μm. Current injection across the active LED structure may be achieved by providing an electrical connection structure for anode and cathode connections of the active LED structure. The anode and cathode connections may include LED chip bonding pads arranged to receive external electrical connections to the LED chip, and the conductive path between the LED chip bonding pads and the active LED structure may be arranged through various conductive layers and through-hole structures.

[0067] In an exemplary flip-chip LED structure, the anode and cathode bonding pads are typically arranged on the mounting surface of the LED chip and have independent internal electrical connections, such as metal layers and through-hole structures, which provide electrical coupling between the active LED structure and each anode and cathode bonding pad, respectively. If the internal electrical connections of opposite polarity are arranged too close, strong electromotive forces may cause metal migration between them. For example, a sufficiently strong electromotive force may cause breakdown of the dielectric material that should provide electrical isolation between the electrical connections of opposite polarity. In addition, metal may migrate through defects present in the dielectric material, thereby increasing the possibility of an electrical short circuit. For these reasons, flip-chip LED structures typically avoid arranging any electrical connection to the n-type layer between the anode bonding pad and the active LED structure.

[0068] According to aspects of the present disclosure, an arrangement of a flip chip LED is disclosed that takes into account the above-mentioned electromotive force and allows electrical connection to the n-type layer between the anode bonding pad and the active LED structure. By providing such an arrangement that can achieve n-type electrical connection on a large area LED chip, improved current spreading and / or current injection can be achieved. In addition, the anode contact pad can be provided with a larger surface area so that the relative sizes of the anode and cathode contact pads can be similar. In this regard, providing a more uniform surface area for mounting the anode and cathode contact pads can improve the mounting stability to the external electrical connection (such as the line on the circuit board to which the LED chip is mounted in a flip chip manner).

[0069] FIG. 1A is a top view of a typical LED chip having a flip chip structure including an active LED structure 12 and an n-type contact interconnect 14 disposed along or within portions of the active LED structure 12. FIG. 1B is a bottom view of the LED chip 10 in FIG. 1A showing the locations of the p-type contact 16 (or p-type contact pad) and the n-type contact 18 (or n-type contact pad). The top view of FIG. 1A presents the light emitting side of the LED chip 10, while the bottom view of FIG. 1B presents the mounting side of the LED chip 10. As shown in FIG. 1B, the p-type contact 16 occupies a relatively small area compared to the n-type contact 18. Returning to FIG. 1A, the area on the left side of the LED chip 10 corresponds to the area of ​​the p-type contact 16 in FIG. 1B, and there is no n-type contact interconnect 14 in this area to avoid the problems described above with respect to electromotive force between internal electrical connections of opposite polarity and too close spacing.

[0070] Figure 2A is a top view of an LED chip 20 in a flip-chip configuration with an n-type contact interconnect 14 arranged across an increased area of ​​an active LED structure 12 in accordance with the principles of the present disclosure. Figure 2B yes Figure 2A FIG. 2 is a bottom view of an LED chip 20, showing the locations of the p-type contact 16 and the n-type contact pad 18. Figure 2A As shown, the n-type contact interconnect 14 may be arranged along Figure 2B As will be described in more detail below, various electrical connection arrangements between the p-type contact 16 and the p-type layer of the active LED structure 12, and various electrical connection arrangements between the n-type contact 18 and the n-type layer of the active LED structure 12 are disclosed, which reduce the electromotive force generated between internal electrical connections with opposite polarities and too close spacing. In this way, one or more n-type contact interconnects 14 can be arranged between the p-type contact 16 and the n-type layer of the active LED structure 12.

[0071] Figure 3 is with Figure 2A and 2B The LED chip 22 is a schematic cross-sectional view of a portion of an LED chip 22 similar to the LED chip 20 in FIG. The active LED structure 12 is formed on a substrate 24, such as an epitaxial growth substrate. The LED chip 22 may be a flip chip structure such that Figure 3 The orientation shown in FIG. 2 can be reversed for installation. In this regard, the mounting surface 22 ′ of the LED chip 22 is arranged at Figure 3The top of the substrate 24 is shown, and the main light emitting surface 22″ of the LED chip 22 is formed by the surface of the substrate 24. The active LED structure 12 generally includes a p-type layer 25, an n-type layer 26, and an active layer 28 formed on the substrate 24. In some embodiments, the n-type layer 26 is arranged between the active layer 28 and the substrate 24. In other embodiments, the doping order can be reversed, so that the layer 26 is doped to be p-type and the layer 25 is doped to be n-type. The substrate 24 can include a variety of different materials, such as sapphire or SiC, and can have one or more shaped, textured or patterned surfaces to enhance light extraction. In some embodiments, the substrate 24 is transmissive (preferably transparent) to the wavelength of light generated by the active LED structure 12.

[0072] The LED chip 22 may include a first reflective layer 30 disposed on the p-type layer 25. In some embodiments, a current spreading layer 32, such as a thin layer of a transparent conductive oxide such as indium tin oxide (ITO) or a metal such as molybdenum (Pt), may be disposed between the p-type layer 25 and the first reflective layer 30. The first reflective layer 30 may include a variety of different materials, and preferably includes a material that has a refractive index step with the material comprising the active LED structure 12 to promote total internal reflection (TIR) ​​of light generated by the active LED structure 12. Light that undergoes TIR can be redirected without being absorbed or lost, and thus contributes to achieving useful or desired LED chip emission. In some embodiments, the first reflective layer 30 includes a material with a refractive index lower than the refractive index of the material of the active LED structure 12. The first reflective layer 30 may include a variety of different materials, some of which have a refractive index less than 2.3, while other materials may have a refractive index less than 2.15, less than 2.0, and less than 1.5. In some embodiments, the first reflective layer 30 comprises a dielectric material, and some embodiments comprise silicon dioxide (SiO2) and / or silicon nitride (SiN). It will be appreciated that a variety of dielectric materials may be used, such as SiN, SiNx, Si3N4, Si, germanium (Ge), SiO2, SiOx, titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), ITO, magnesium oxide (MgOx), zinc oxide (ZnO), and combinations thereof. By providing the first reflective layer 30 as a dielectric layer, the first reflective layer 30 may be advantageously positioned across the active LED structure 12 without concern for electrical shorting between the anode and cathode electrical connections. In some embodiments, the first reflective layer 30 may comprise a plurality of alternating layers of different dielectric materials, such as alternating layers of SiO2 and SiN that are symmetrically repeated or asymmetrically arranged.

[0073] The LED chip 22 may further include a second reflective layer 34 on the first reflective layer 30, so that the first reflective layer 30 is arranged between the active LED structure 12 and the second reflective layer 34. The second reflective layer 34 may include a metal layer configured to reflect any light from the active LED structure 12 that may pass through the first reflective layer 30. The second reflective layer 34 may include a variety of different materials, such as Ag, gold (Au), Al, or a combination thereof. As shown, the second reflective layer 34 may include one or more reflective layer interconnects 38 that provide a conductive path through the first reflective layer 30 to electrically couple the second reflective layer 34 to the p-type layer 25. In some embodiments, the reflective layer interconnect 38 includes a reflective layer through hole. Therefore, the first reflective layer 30, the second reflective layer 34, and the reflective layer interconnect 38 form a reflective structure of the LED chip 22. In some embodiments, the reflective layer interconnect 38 includes the same material as the second reflective layer 34 and is formed simultaneously with the second reflective layer 34. In other embodiments, the reflective layer interconnect 38 may include a different material from the second reflective layer 34. The LED chip 22 may optionally include a barrier layer on a portion of the second reflective layer 34 opposite to the reflective layer interconnect 38 to prevent the material of the second reflective layer 34 (such as Ag) from migrating to other layers. Such a barrier layer may include a conductive material, suitable materials including but not limited to sputtered Ti / Pt, followed by an evaporated Au bulk material, or sputtered Ti / Ni, followed by an evaporated Ti / Au bulk material. A passivation layer 40 is included on the second reflective layer 34. The passivation layer 40 is arranged to protect the LED chip 22 and provide electrical insulation therefor, and may include a variety of different materials, such as dielectric materials. In some embodiments, the passivation layer 40 is a single layer, while in other embodiments, the passivation layer 40 includes multiple layers. Suitable materials for the passivation layer 40 include but are not limited to silicon nitride, silicon dioxide, aluminum oxide, and silicon oxynitride. In some embodiments, the passivation layer 40 includes a first metal-containing intermediate layer 42 disposed therein, wherein the first metal-containing intermediate layer 42 may include Al or other suitable metals. It is worth noting that the first intermediate layer 42 is embedded in the passivation layer 40 and is electrically isolated from the active LED structure 12. In applications, the first intermediate layer 42 can act as a crack stopper to prevent cracks that may propagate through the passivation layer 40.

[0074] exist Figure 3, the p-type contact 16 and the n-type contact 18 are arranged on the passivation layer 40 and are configured to receive external electrical connections and provide a portion of a conductive path to the active LED structure 12. The p-type contact 16 (also referred to as the anode contact) may include one or more p-type contact vias 44 extending through the passivation layer 40 to provide a conductive path to the p-type layer 25 through the second reflective layer 34 and the reflective layer interconnect 38. In some embodiments, the one or more p-type contact vias 44 may be referred to as a p-type feed of the p-type contact 16. The n-type contact 18 (also referred to as the cathode contact) may include one or more n-type contact vias 46 extending through the passivation layer 40 and electrically coupled to the n-type contact interconnect 14 to provide an electrical path to the n-type layer 26.

[0075] The n-type contact interconnect 14 may be formed as part of an n-type contact structure 48 embedded within the passivation layer 40. The n-type contact structure 48 is arranged to be electrically coupled between the n-type contact 18 and the n-type layer 26. The n-type contact structure 48 may be embodied as a continuous metal structure that includes both the n-type contact interconnect 14 and a lateral extension extending around the p-type contact via 44. Figure 3 It is a cross-sectional view, so it can be understood that the n-type contact structure 48 is continuous through the portion extending around the p-type contact through hole 44, which is located Figure 3 The n-type contact structure 48 is arranged to extend laterally across the LED chip 22 so as to lay out conductive paths between the n-type contact 18 and many different regions of the n-type layer 26, thereby improving current spreading. In some locations where the n-type contact via 46 connects to the n-type contact structure 48, such locations may also be vertically aligned or aligned with the locations of some n-type contact interconnects 14. The lateral extension of the n-type contact structure 48 can extend from the n-type contact via 46 to a location outside the region of the n-type contact 18 in the LED chip 22 to electrically connect with other n-type contact interconnects 14. For example, a portion of the n-type contact structure 48 is arranged to extend from a location vertically aligned with a region of the n-type contact 18 to a region of the LED chip 22 that is vertically aligned with a region of the p-type contact 16. In this manner, one or more n-type contact interconnects 14 are vertically arranged between the p-type contact 16 and the n-type layer 26. Although a single n-type contact interconnect 14 is shown vertically arranged between the p-type contact 16 and the active LED structure 12, in practice, there may be an array of n-type contact interconnects 14 to effectively spread the current across a larger area of ​​the LED chip 22 below the p-type contact 16.

[0076] As described above, if internal electrical connections of opposite polarity (i.e., from the n-type contact and the p-type contact) are arranged too close, the strong electromotive force may cause electromigration of the metal between them, thereby increasing the possibility of dielectric breakdown and / or electrical short circuit. In this way, some portions 34' or second portions of the second reflective layer 34 are formed to be electrically isolated or electrically decoupled from the p-type contact 16. Such portions 34' of the second reflective layer 34 can be located near the n-type contact interconnect 14 and the n-type contact structure 48 that are vertically aligned with one or both of the p-type contact 16 and the n-type contact 18. The portions 34' of the second reflective layer 34 can form an electrically isolated metal layer embedded in a dielectric material, such as a combination of the first reflective layer 30 and the passivation layer 40. In some embodiments, such electrical isolation can be achieved by patterning the portions 34' in a discontinuous manner so that these portions are discontinuous with the rest of the second reflective layer 34. The electrically isolated portions 34' of the second reflective layer 34 can be referred to as a second intermediate layer or a second metal-containing intermediate layer of the LED chip 22. In some embodiments, the electrically isolated portion 34′ of the second reflective layer 34 that is vertically aligned with the p-type contact 16 and the n-type contact structure 48 may be free of the reflective layer interconnect 38. In this way, any metal migration that occurs between the electrically activated n-type contact structure 48 and the electrically isolated portion 34′ of the second reflective layer 34 will not form a short circuit path to the p-type contact 16 via the current spreading layer 32.

[0077] In some embodiments, the third intermediate layer 50 can be formed by electrically isolating a portion of the n-type contact structure 48 from the active LED structure 12. In this manner, the third intermediate layer 50 can be formed simultaneously with the n-type contact structure 48 and using the same material as the n-type contact structure, and further, the third intermediate layer 50 is also electrically floating in the LED chip 22, similar to the first intermediate layer and the second intermediate layer (i.e., 42 and 34'). In some embodiments, the third intermediate layer 50 can be formed in a portion of the LED chip 22 that is vertically aligned with the n-type contact 18, and / or in a region of the LED chip 22 that extends between the p-type contact 16 and the n-type contact 18. In some regions, such as between the n-type contact 18 and the active LED structure 12, the first intermediate layer 42, the electrically isolated portion 34' of the second reflective layer 34 (or the second intermediate layer), and the third intermediate layer 50 can all be vertically aligned with each other within the passivation layer 40. Therefore, no intermediate layer can be charged, and a multi-layer structure for enhanced crack stopping is provided in the passivation layer 40. In some embodiments, the first intermediate layer 42, the electrically isolated portion 34' of the second reflective layer 34 (or the second intermediate layer), and the third intermediate layer 50 are all at least partially located within the passivation layer 40. In this manner, portions of the passivation layer 40 can be arranged to provide vertical spacing between the first intermediate layer 42, the electrically isolated portion 34' of the second reflective layer 34 (or the second intermediate layer), and the third intermediate layer 50.

[0078] FIG. 4A to FIG. 12 Shown with Figure 3 22 in FIG. 5 . For illustrative purposes, the cross-sectional views present a generalized schematic diagram showing how various features of LED chip 52 are arranged, while the corresponding top views are used to show example layouts of the features shown in the cross-sectional views. In this manner, the cross-sectional views are not necessarily cross-sections taken directly from the top views. Rather, the cross-sectional views provide detailed structures, while the top views provide an overall layout of how these structures are arranged across a larger area of ​​LED chip 52. Additionally, the order of the manufacturing steps may represent individual steps, and it should be understood that intermediate manufacturing steps may also be provided.

[0079] Figure 4A The cross-sectional view is a manufacturing step after a portion of the LED chip 52 forms an active LED structure 12 on the substrate 24, and a plurality of first openings 54 are defined through a portion of the p-type layer 25, the active layer 28, and the n-type layer 26. The first openings 54 can be formed by a patterned removal process, such as patterned etching of the active LED structure 12. Figure 4B yes Figure 4AFIG. 5 is an exemplary top view of an LED chip 52 in FIG. 5 , showing how the first openings 54 are arranged in an array across the LED chip 52. As will be described later, the first openings 54 define the n-type layer 26 where the n-type contact interconnect 14 (eg, Figure 3 shown).

[0080] Figure 5A yes Figure 4A FIG. 5 is a cross-sectional view of a portion of an LED chip 52 in a manufacturing step after a current diffusion layer 32 is formed on a p-type layer 25 . Figure 5B yes Figure 5A 54, showing how the current spreading layer 32 can be arranged relative to each first opening 54. The current spreading layer 32 can be selectively formed along the p-type layer 25 without having to extend completely to each first opening 54. In this way, a setback region is formed laterally between the edge of the current spreading layer 32 and the first opening 54 to prevent the conductive material in the current spreading layer 32 from inducing an electrical short circuit along the sidewalls of the p-type layer 25 and the n-type layer 26 within the first opening 54.

[0081] Fig. 6A yes Figure 5A FIG. 5 is a cross-sectional view of a portion of an LED chip 52 in a manufacturing step after forming a first reflective layer 30 and forming a plurality of second openings 56 and third openings 58 through the first reflective layer 30 . Figure 6B yes Fig. 6A , showing how the second opening 56 and the third opening 58 may be arranged relative to the first opening 54. As shown, the second opening 56 is arranged to be vertically aligned with the first opening 54, thereby providing a combined opening for exposing a portion of the n-type layer 26. In some embodiments, the second opening 56 may have a narrower diameter than the first opening 54 to reduce the occurrence of electrical shorts when subsequent components are formed. The third opening 58 may be formed across other portions of the first reflective layer 30 to expose portions of the current spreading layer 32. As will be described later, the third opening 58 defines Figure 3 The reflective layer interconnection 38 is to be formed in the region so as to establish electrical connection with the p-type layer 25 through the current diffusion layer 32. Figure 6B As shown, the first opening 54 and the second opening 56 can be formed in an array that is spaced apart on the LED chip 52, and the third opening 58 can be formed in another array on the LED chip 52. In this way, future n-type and p-type electrical connections can be arranged across the LED chip 52 to achieve effective current spreading.

[0082] Fig. 7A yes Fig. 6AFIG. 5 is a cross-sectional view of a portion of an LED chip 52 in a manufacturing step after a second reflective layer 34 is formed on the first reflective layer 30 . Figure 7B yes Fig. 7A , showing how the second reflective layer 34 is arranged relative to the first opening 54 and the second opening 56. As shown, the second reflective layer 34 can be formed on the portion of the active LED structure 12 located between the first openings 54. In this way, the second reflective layer 34 can be formed over a portion of the P-type layer 25. During the deposition process, the second reflective layer 34 can fill Fig. 6A The third opening 58 in the reflective layer is formed to form the reflective layer interconnect 38. In addition, the electrically isolated portion 34' of the second reflective layer 34 may be formed in the first reflective layer 30 without Fig. 6A On the portion of the third opening 58. Figure 7B As shown in the top view of FIG. 5 , the portion 34 ′ may be formed between adjacent first openings 54. As will be described in more detail below, such an area where the portion 34 ′ is located is Figure 3 The portion of the n-type contact structure 48 will extend laterally to electrically connect Figure 3 The region adjacent to the n-type contact interconnect 14. In this way, it is avoided to have a charged metal layer of opposite polarity in such a region.

[0083] Figure 8 yes Fig. 7A FIG. 5 is a cross-sectional view of a portion of an LED chip 52 in a manufacturing step after a portion of a passivation layer 40 is formed on the second reflective layer 34. The passivation layer 40 may be deposited all over, and the fourth opening 60 may be defined in an area vertically aligned with the center of the first opening 54. In this way, a conductive path to the n-type layer 26 is provided.

[0084] Fig. 9A yes Figure 8 FIG. 5 is a cross-sectional view of a portion of an LED chip 52 in a manufacturing step after forming an n-type contact structure 48 , an n-type contact interconnection 14 , and a third intermediate layer 50 . Fig. 9B yes Fig. 9A FIG. 5 is an exemplary top view of an LED chip 52 in FIG. 5 , showing the layout pattern of the n-type contact structure 48, the n-type contact interconnect 14 and the third intermediate layer 50 across the active LED structure 12. As shown in the figure, the n-type contact interconnect 14 can be formed at Figure 8 The n-type contact structure 48 may form a conductive path between adjacent pairs of n-type contact interconnects 14. The third intermediate layer 50 may be formed along other portions of the passivation layer 40 outside the n-type contact structure 48. The plurality of fifth openings 62 may be formed along the defined Figure 3The fifth opening 62 formed in the portion of the third intermediate layer 50 at the location of the p-type contact through hole 44 may be arranged to have a variety of different shapes, such as a circular shape. Fig. 9B In FIG. 1 , the fifth opening 62 is labeled with the letter P to indicate the location of the conductive path to the subsequently formed p-type contact 16 .

[0085] Fig. 10A yes Fig. 9A 5 is a cross-sectional view of a portion of an LED chip 52 in a manufacturing step after forming an additional portion of the passivation layer 40 and the first intermediate layer 42. Fig. 10B yes Fig. 10A FIG. 4 is an exemplary top view of an LED chip 52 in FIG. 4 , showing a layout pattern of the first intermediate layer 42. The first intermediate layer 42 can be deposited on the passivation layer 40 in its entirety, with a sixth opening 64 and a seventh opening 66 defined therein. The sixth opening 64 is aligned with the fifth opening 62 to define a conductive path for a subsequently formed p-type contact 16. The seventh opening 66 defines an area where a subsequently formed n-type contact via 46 will be formed. Fig. 10B As shown, the sixth opening 64 and the seventh opening 66 may be formed in arrays, respectively, which are spaced apart from each other along the LED chip 52 to define areas where the p-type contact 16 and the n-type contact 18 may be subsequently formed. For illustrative purposes, Fig. 10B , the exemplary areas of the p-type contact 16 and the n-type contact 18 are superimposed by the dashed boxes. In this way, the area of ​​the p-type contact 16 can be increased without being affected by the position of the n-type contact interconnect 14.

[0086] Fig.11 yes Fig. 10A FIG. 5 is a cross-sectional view of a portion of an LED chip 52 in a manufacturing step after an additional portion of the passivation layer 40 is formed on the first intermediate layer 42 and an eighth opening 68 and a ninth opening 70 are formed through the sixth opening 64 and the seventh opening 66, respectively. The eighth opening is formed through the central portion of the sixth opening 64 and through the passivation layer 40 to define the location of the subsequently formed p-type contact via 44. In a similar manner, the ninth opening 70 is formed through the central portion of the seventh opening 66 and through the passivation layer 40 to define the location of the subsequently formed n-type contact via 46.

[0087] Fig.12 yes Fig.11 FIG. 2 is a cross-sectional view of a portion of an LED chip 52 in a manufacturing step after forming a p-type contact 16, a p-type contact through hole 44, an n-type contact 18, and an n-type contact through hole 46. The LED chip 52 is accordingly arranged to be mounted with another surface in a flip chip manner. In this way, the p-type contact 16 and the n-type contact 18 are arranged at the mounting surface 52' of the LED chip 52, and the surface of the substrate 24 can form the main light emitting surface 52" of the LED chip 52 to be mounted with the substrate 24. Figure 3 In a manner similar to the LED chip 22 in FIG. 1 , the electrically isolated portion 34′ (or second intermediate layer) of the second reflective layer 34 can be disposed between the electrically active portion of the n-type contact structure 48 and the active LED structure 12. The third intermediate layer 50 or the electrically inactive portion of the n-type contact structure 48 can be disposed in the LED chip 52 at a position above the electrically active portion of the second reflective layer 34. In this manner, the LED chip 52 can have a structure that is capable of reducing the electromotive force and corresponding metal electromigration associated when oppositely charged metal layers are in close proximity to each other.

[0088] Fig.13A is a cross-sectional view of a portion of an LED chip 72. Fig.12 A is similar to the LED chip 52, and in this figure, the n-type contact structure 48 also includes a peripheral n-type contact interconnect 74 extending along the peripheral edge of the LED chip 72. Fig.12 In a similar manner to the LED chip 52 in FIG. 7 , the electrically isolated portion 34′ of the second reflective layer 34 can be arranged between the electrically active portion of the n-type contact structure 48 and the active LED structure 12, and the third intermediate layer 50 can be arranged in the LED chip 72 at the location of the electrically active portion of the second reflective layer 34. Depending on the layout of the n-type contact interconnects 14 of the LED chip 72, one or more peripheral n-type contact interconnects 74 can be arranged near the peripheral mesa sidewall 12′ of the active LED structure 12. The peripheral n-type contact interconnects 74 can be formed through the passivation layer 40 and portions of the first reflective layer 30 in a similar manner to the n-type contact interconnects 14. The peripheral n-type contact interconnects 74 can be electrically coupled to portions of the n-type layer 26 outside the peripheral mesa sidewall 12′, thereby providing additional conductive paths for the active LED structure 12 to enhance current spreading and injection. Portions of the passivation layer 40 and / or the first reflective layer 30 can be arranged between the peripheral mesa sidewall 12′ and the peripheral n-type contact interconnects 74 to avoid short circuits. In some embodiments, portions of n-type contact structure 48 can be arranged to electrically couple peripheral n-type contact interconnect 74 to one or more n-type contact interconnects 14 located within peripheral mesa sidewall 12'. In some embodiments, peripheral n-type contact interconnect 74 can be electrically coupled to n-type layer 26 in a continuous manner near two or more peripheral edges of active LED structure 12, or even near all peripheral edges.

[0089] Fig. 13B yes Fig.13A, showing an exemplary top view of an LED chip 72 in FIG. 4 , showing a layout pattern of n-type contact interconnect 14, peripheral n-type contact interconnect 74, and n-type contact 18 relative to p-type contact 16. In some embodiments, peripheral n-type contact interconnect 74 is a single continuous structure that extends around the periphery of LED chip 72. Peripheral n-type contact interconnect 74 and portions of n-type contact structure 48 can effectively conduct current between n-type contact 18 and n-type contact interconnect 14, which is located between n-type contact 18 and p-type contact 16, and / or is vertically aligned with p-type contact 16. For example, first n-type contact interconnect 14-1 is vertically aligned with n-type contact 18 and electrically coupled with the n-type contact. First portion 48-1 of n-type contact structure 48 is arranged to extend laterally and electrically couples first n-type contact interconnect 14-1 with second n-type contact interconnect 14-2 vertically arranged between n-type contact 18 and p-type contact 16. The second portion 48-2 of the n-type contact structure 48 is arranged to electrically couple the first n-type contact interconnect 14-1 with the peripheral n-type contact interconnect 74, and the third portion 48-3 of the n-type contact structure 48 electrically couples the third n-type contact interconnect 14-3 with the peripheral n-type contact interconnect 74. In another embodiment, the fourth n-type contact interconnect 14-4 is vertically aligned with and electrically coupled to the n-type contact 18, and the fourth portion 48-4 of the n-type contact structure 48 electrically couples the fourth n-type contact interconnect 14-4 to a fifth n-type contact interconnect 14-5 vertically aligned with the p-type contact 16. In this manner, a conductive path is provided between the n-type contact 18 and the plurality of n-type contact interconnects 14-1 to 14-5 regardless of the position of the plurality of n-type contact interconnects 14-1 to 14-5 relative to the n-type contact 18 and the p-type contact 16.

[0090] Fig.14A is an exemplary top view of an LED chip 76, which is connected to Fig.13A and 13B 72, and the figure further presents an embodiment in which the electrical connection between the peripheral n-type contact interconnect 74 and the n-type layer 26 is segmented along the periphery of the LED chip 76. Portions of the passivation layer 40 may remain between the peripheral n-type contact interconnect 74 and the n-type layer 26 along the periphery of the LED chip 76, thereby forming a pattern of localized areas without direct contact, rather than continuously contacting the n-type layer 26 outside the mesa sidewall 12'. For illustrative purposes, the localized areas of the passivation layer 40 are shown as rectangular boxes along the periphery of the LED chip 76. Fig. 14B yes Fig.14A The cross-sectional view of the LED chip 76 in FIG. 14A is taken along the cross-sectional line 14B-14B in FIG. 14A, which cross-sectional line does not intersect a portion of the passivation layer 40 that is retained along the periphery. As shown, the peripheral n-type contact interconnect 74 extends to the n-type layer 26 and is in electrical contact with the n-type layer. In contrast, Fig. 14C yes Fig.14A The LED chip 76 is along Fig.14A The cross-sectional view taken along the section line 14C-14C of FIG. 1 does not intersect a portion of the passivation layer 40 that remains along the periphery. Therefore, in such an area, the passivation layer 40 remains between the peripheral n-type contact interconnect 74 and the n-type layer 26. Such a structure can be used to control the amount of direct contact formed between the edge n-type contact interconnect 74 and the n-type layer 26 along the periphery of the LED chip, and the associated amount of current injection. By reducing the amount of direct contact, the local current spreading and the corresponding light emission effect can be adjusted along the peripheral portion of the LED chip 76.

[0091] Fig.15 is an exemplary top view of an LED chip 78, which is Fig.13A and 13B 72 in FIG. 1 , and the figure includes an alternative arrangement in which the n-contact interconnect is not vertically aligned below the p-contact. Thus, the principles described above for the peripheral n-contact interconnect 74 may not be limited to embodiments in which the n-contact interconnect 14 is vertically aligned with the p-contact 16. In this way, the peripheral n-contact interconnect 74 may lay out a conductive path between the n-contact 18 and the n-contact interconnect 14 that is adjacent to or even surrounds the p-contact 16, without having to lay it directly between the p-contact 16 and the rest of the LED chip 78. This arrangement may be beneficial in increasing the number of electrically active paths between the p-contact 16 and the portion of the LED chip 78 that is vertically aligned with the p-contact 16.

[0092] Fig.16 is an exemplary top view of an LED chip 80, which is Fig.15 78 in FIG. 1 , and this figure includes an arrangement where the p-type contact 16 covers a larger area of ​​the LED chip 80. For embodiments where the n-type contact interconnect 14 is not vertically aligned below the p-type contact 16, an arrangement of the n-type contact interconnect 14 and the n-type contact structure 48 can be provided to allow for a larger area of ​​the p-type contact 16 while still providing efficient current spreading. For example, the p-type contact 16 can include a lateral protrusion 16' extending toward the n-type contact 18. Fig.16 A particular arrangement of n-contact structures 48 and peripheral n-contact interconnects 74 is shown that routes conductive paths between n-contact 18 and various n-contact interconnects 14 that laterally surround p-contact 16 .

[0093] Fig.17A to 17C shows the Fig.15 and Fig.1678 and 80 in FIG. 8 , and also includes an arrangement in which the p-type contact 16 is segmented in a discontinuous manner across the LED chip 82. The sequence of manufacturing steps may represent individual steps, and it should be understood that intermediate manufacturing steps may also be provided.

[0094] Fig.17A 8 is a top view of an LED chip 82 during a manufacturing step after other components such as a reflective layer interconnect 38, an n-type contact interconnect 14, an n-type contact structure 48, a peripheral n-type contact interconnect 74, and an opening 62 have been formed. As shown, the n-type contact structure 48 can electrically couple a linear arrangement of n-type contact interconnects 14 (e.g., columns or rows depending on the orientation). In this regard, the n-type contact structure 48 can form a plurality of discontinuous segments, each of which is coupled to a separate grouping of n-type contact interconnects 14. Certain segments or first segments of the n-type contact structure 48 can extend continuously from one edge of the active LED structure 12 to the opposite edge to electrically couple between portions of the peripheral n-type contact interconnect 74 on the opposite edge. As used herein, the opposite edge of the active LED structure 12 can be embodied as a mesa sidewall 12', for example, as Fig.13A As shown. The other segments or second segments of the n-type contact structure 48 may extend continuously in the region of the LED chip 82 that does not extend to one or more opposite edges. Fig.17A , two such sections of the n-type contact structure 48 are shown, which are located near the center of the LED chip 82. In this way, one or more continuous portions of the active LED structure 12 can extend between certain sections of the n-type contact structure 48. Fig. 9A The opening 62 corresponds to the fifth opening 62 described and illustrated in FIG. Therefore, the opening 62 defines a region where the subsequently formed p-type contact via 44 will be formed.

[0095] Fig. 17B yes Fig.17A FIG. 8 is a top view of an LED chip 82 in a subsequent manufacturing step after other components such as the p-type contact 16, the p-type contact via 44, and the n-type contact 18 have been formed. The p-type contact via 44 effectively fills Fig.17AThe LED chip 82 includes an opening 62 in the p-type contact 16, thereby providing a conductive path between the p-type contact 16 and the active LED structure 12 (i.e., the p-type layer) below. The p-type contact 16 can be arranged in a discontinuous portion or segmented form relative to the n-type contact structure 48 and the n-type contact interconnect 14 to avoid the metal layers of opposite polarities being too close to each other when powered on. For example, the LED chip 82 includes outer segments (or first discontinuous portions) of the p-type contact 16, which are arranged circumferentially between the vertical boundaries of the segments of the n-type contact structure 48 and extend continuously between the opposite edges of the active LED structure 12 and other edges of the active LED structure 12. The LED chip 82 further includes a central segment (or second discontinuous portion) of the p-type contact 16, which is continuously distributed around the centrally located and mutually offset segments of the n-type contact structure 48. In this way, the LED chip 82 can be arranged without an n-type contact interconnect 14 vertically aligned with the p-type contact 16, while also providing a conductive path from the n-type contact 18 that extends throughout the area of ​​each of the segments in the active LED structure 12 that laterally surround the p-type contact 16.

[0096] As described herein, the principles of the present disclosure allow for various configurations that effectively lay out the electrical connections of n-type contacts and p-type contacts on an LED chip while reducing the situation where electrical connections of opposite polarity are placed too close to each other. The arrangement of the contact structures and interconnect structures provides flexibility and controllability for customizing current spreading and / or injection for various LED chip structures and sizes. Figures 18 to 20 Various arrangements of n-type contact interconnects and reflective layer interconnects are shown, and the arrangements can be applied to any of the embodiments described above, including at least one of the embodiments described above. Figures 3 to 17B The LED chip shown in .

[0097] Fig.18 8 is a top view of an LED chip 84 having a pattern of n-type contact interconnects 14 and reflective layer interconnects 38 that may be implemented according to an embodiment of the present disclosure. As shown, the reflective layer interconnects 38 and n-type contact interconnects 14 are disposed at a higher density near the peripheral edge of the LED chip 84 relative to the central region of the LED chip 84. This arrangement may be advantageous for large area LED chips (such as, edges greater than 0.5 μm), where current injection may be more challenging along the peripheral edge. By providing this higher density of reflective layer interconnects 38 and n-type contact interconnects 14, an increase in brightness along the peripheral edge and / or an increase in brightness uniformity across the LED chip 84 may be achieved.

[0098] Fig.19 is a top view of LED chip 86, which is connected to Fig.18The LED chip 84 in FIG. 8 is similar to the LED chip 84 in FIG. 86 , including a higher density of n-type contact interconnection 14 and reflective layer interconnection 38. As shown in the figure, the density of n-type contact interconnection 14 and reflective layer interconnection 38 at the peripheral edge of LED chip 86 is higher than that of n-type contact interconnection 14 and reflective layer interconnection 38. Fig.18 In addition, the density of the n-type contact interconnect 14 and the reflective layer interconnect 38 along the central region is also higher than that of Fig.18 LED chip 84. In this way, for larger chip areas with LED structures where current spreading is more challenging, Fig.19 The LED chip 86 in may have advantages in enhancing current spreading.

[0099] Fig. 20 is a top view of LED chip 88, which is Fig.18 16 is similar to the LED chip 84 in FIG. 1 , except that the n-contact interconnects are not aligned between the boundaries of the p-contact 16 and the active LED structure 12. As shown, various ones of the n-contact interconnects 14 are arranged between the edge of the p-contact 16 and the edge of the active LED structure 12 closest to the p-contact 16. In this way, the electrical path from the n-contact 18 can effectively cover a larger area of ​​the LED chip 88 while also avoiding the situation where electrical connections of opposite polarity begin to be arranged too close to each other.

[0100] Fig.21 is a cross-sectional view of a portion of an LED chip 90, for an embodiment in which some portions 34' of the second reflective layer 34 are electrically coupled to the n-type contact 18, the chip is electrically coupled to the n-type contact 18. Fig.13A 7. For example, a portion 34' of the second reflective layer 34 between the n-type contact 18 and the active LED structure 12 may be electrically coupled to the n-type contact 18 via another n-type contact via 92. One or more portions 34' of the second reflective layer 34 may be decoupled or completely separated from the current spreading layer 32, the p-type layer 25, and the remainder of the second reflective layer 34 via the passivation layer 40. As shown, the n-type contact via 92 may extend through the opening in the passivation layer 40 and the first intermediate layer 42. By electrically connecting such a portion 34' to the n-type contact 18, additional conductive material may be coupled to the electrical connection between the n-type contact 18 and the n-type layer 26, which may effectively reduce the associated resistance.

[0101] It is contemplated that any of the above aspects, and / or the various aspects and features described herein, can be combined with each other to obtain more benefits. Unless otherwise specified herein, any of the various embodiments disclosed herein can be combined with one or more other disclosed embodiments.

[0102] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. A light emitting diode (LED) chip, comprising: An active LED structure comprising an n-type layer, a p-type layer, and an active layer disposed between the n-type layer and the p-type layer; an n-type contact electrically coupled to the n-type layer; a p-type contact electrically coupled to the p-type layer; as well as A plurality of n-type contact interconnects are electrically coupled between the n-type layer and the n-type contacts, wherein one or more of the plurality of n-type contact interconnects are vertically arranged between the p-type contacts and the n-type layer.

2. The LED chip of claim 1, wherein: The one or more n-type contact interconnects of the plurality of n-type contact interconnects are electrically coupled to an n-type contact structure, which is electrically coupled to the n-type contact.

3. The LED chip of claim 2, wherein: The n-type contact structure is arranged to extend laterally from a position vertically aligned with the n-type contact to a position vertically aligned with the p-type contact, so that the n-type contact structure is electrically coupled to one or more n-type contact interconnects of the plurality of n-type contact interconnects vertically arranged between the p-type contact and the n-type layer.

4. The LED chip according to claim 2, further comprising: a peripheral n-type contact interconnect electrically coupled to a portion of the n-type layer outside a mesa sidewall of the active LED structure, the mesa sidewall comprising sidewalls of the p-type layer, the active layer, and a portion of the n-type layer; Wherein, the n-type contact structure is arranged to extend laterally from a position vertically aligned with the n-type contact to the mesa sidewall so that the n-type contact structure is electrically coupled to the peripheral n-type contact interconnect.

5. The LED chip according to claim 4, wherein: The peripheral n-type contact interconnect is electrically coupled to the one or more n-type contact interconnects of the plurality of n-type contact interconnects that are vertically arranged between the p-type contact and the n-type layer.

6. The LED chip according to claim 4, wherein: The peripheral n-type contact interconnect is electrically coupled to a portion of the n-type layer outside the mesa sidewalls in a continuous manner near two or more peripheral edges of the active LED structure.

7. The LED chip according to claim 4, wherein: The peripheral n-type contact interconnect is electrically coupled to a portion of the n-type layer outside the mesa sidewall in a discontinuous manner such that a portion of the peripheral n-type contact interconnect contacts the n-type layer and other portions of the peripheral n-type contact interconnect are separated from the n-type layer by a passivation layer.

8. The LED chip according to claim 1, further comprising a reflective structure on the active LED structure, wherein: The reflective structure includes an electrically insulating first reflective layer, a conductive second reflective layer, and a plurality of reflective layer interconnects extending through the first reflective layer to electrically couple a first portion of the second reflective layer to the p-type layer.

9. The LED chip according to claim 8, wherein: A second portion of the second reflective layer is electrically isolated from the active LED structure.

10. The LED chip according to claim 9, wherein: The second portion of the second reflective layer is vertically disposed between the n-type contact structure and the active LED structure.

11. The LED chip according to claim 8, wherein: A second portion of the second reflective layer is completely separated from the p-type layer by a passivation layer, and a second portion of the second reflective layer is electrically coupled to the n-type contact.

12. The LED chip according to claim 1, further comprising: a passivation layer over the active LED structure, wherein the plurality of n-type contact interconnects extend through portions of the passivation layer; and A first metal-containing intermediate layer, a second metal-containing intermediate layer, and a third metal-containing intermediate layer are disposed within the passivation layer, wherein each of the first metal-containing intermediate layer, the second metal-containing intermediate layer, and the third metal-containing intermediate layer is electrically isolated from the n-type contact and the p-type contact.

13. The LED chip according to claim 1, wherein: The n-type contact and the p-type contact are contact pads arranged to receive external electrical connections when the LED chip is mounted in a flip-chip manner.

14. A light emitting diode (LED) chip, comprising: An active LED structure comprising an n-type layer, a p-type layer, and an active layer disposed between the n-type layer and the p-type layer; a passivation layer on the active LED structure; as well as A first metal-containing intermediate layer, a second metal-containing intermediate layer, and a third metal-containing intermediate layer are at least partially disposed within the passivation layer, wherein each of the first metal-containing intermediate layer, the second metal-containing intermediate layer, and the third metal-containing intermediate layer is electrically isolated from the active LED structure.

15. The LED chip according to claim 14, further comprising: a reflective structure on the active LED structure, wherein the reflective structure includes an electrically insulating first reflective layer, an electrically conductive second reflective layer, and a plurality of reflective layer interconnects extending through the first reflective layer to electrically couple a first portion of the second reflective layer to the p-type layer; The second metal-containing intermediate layer includes a second portion of the second reflective layer that is electrically isolated from the active LED structure.

16. The LED chip according to claim 14, further comprising: an n-type contact electrically coupled to the n-type layer; a p-type contact electrically coupled to the p-type layer; a plurality of n-type contact interconnects electrically coupled between the n-type layer and the n-type contacts; as well as An n-type contact structure is electrically coupled to one or more of the plurality of n-type contact interconnects, wherein the n-type contact structure is arranged to extend laterally within the passivation layer.

17. The LED chip according to claim 16, wherein: The third metal-containing intermediate layer includes the same material as the n-type contact structure.

18. The LED chip according to claim 16, wherein: The second metal-containing intermediate layer is vertically disposed between the n-type contact structure and the active LED structure.

19. The LED chip according to claim 16, further comprising: a reflective structure on the active LED structure, wherein the reflective structure comprises an electrically insulating first reflective layer, an electrically conductive second reflective layer, and wherein the first reflective layer is between the second reflective layer and the p-type layer; The second metal-containing intermediate layer includes a portion of the second reflective layer that is electrically isolated from the active LED structure.

20. The LED chip according to claim 19, wherein: A portion of the second reflective layer that is electrically isolated from the active LED structure is vertically disposed between the n-type contact structure and the active LED structure.

21. The LED chip according to claim 14, wherein: The first metal-containing intermediate layer, the second metal-containing intermediate layer, and the third metal-containing intermediate layer are vertically arranged within the passivation layer.

22. A light emitting diode (LED) chip, comprising: An active LED structure comprising an n-type layer, a p-type layer, and an active layer disposed between the n-type layer and the p-type layer; a plurality of n-type contact interconnects electrically coupled to the n-type layer; as well as An n-type contact structure is electrically coupled to the plurality of n-type contact interconnects, the n-type contact structure comprising: a first section connected to a first group of n-type contact interconnects among the plurality of n-type contact interconnects, and a second section connected to a second group of n-type contact interconnects among the plurality of n-type contact interconnects.

23. The LED chip according to claim 22, wherein: The first section of the n-type contact structure is discontinuous with the second section of the n-type contact structure.

24. The LED chip according to claim 22, wherein: The first section of the n-type contact structure is arranged to continuously extend from one edge of the active LED structure to an opposite edge of the active LED structure.

25. The LED chip according to claim 22, wherein: The second section of the n-type contact structure is arranged to extend continuously but not to at least one edge of the active LED structure.

26. The LED chip according to claim 22, further comprising: an n-type contact electrically coupled to the n-type contact structure; as well as a p-type contact electrically coupled to the p-type layer; The plurality of n-type contact interconnects are vertically arranged outside the peripheral edge of the p-type contact.

27. The LED chip according to claim 26, wherein: The p-type contact comprises: a first portion disposed vertically between a boundary of the first section of the n-type contact structure and a periphery of the active LED structure; and a second portion disposed vertically between another boundary of the first section of the n-type contact structure and a boundary of the second section of the n-type contact structure; The first portion of the p-type contact is discontinuous with the second portion of the p-type contact.

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