Three-layer silicon-based accelerometer and method of manufacturing the same

Abstract

The application provides a manufacturing method of a three-layer silicon-based accelerometer, comprising first to fourth steps, the first step comprises the following steps: forming a silicon dioxide bonding layer on the surface of a fixed support layer of a first substrate, and performing patterning and etching treatment to form a first bonding anchor point, the second step comprises the following steps: based on the first bonding anchor point, bonding a functional layer of a second substrate and the silicon dioxide bonding layer of the first substrate to form a double-layer structure, and performing thinning, patterning and etching treatment to obtain a double-layer accelerometer comb structure, the third step comprises the following steps: forming a second bonding anchor point by etching the surface of a third substrate, and performing patterning and metal deposition treatment on the surface of the third substrate to obtain a surface-patterned electrode layer, and the fourth step comprises the following steps: based on the second bonding anchor point, bonding the double-layer accelerometer comb structure and the surface-patterned electrode layer to obtain a three-layer structure, wherein the first to third substrates are silicon wafers, and the fixed support layer and the functional layer are silicon layers.

Description

Technical Field

[0001] This invention relates to the field of sensors, and more specifically, to a three-layer silicon-based accelerometer and its manufacturing method. Background Technology

[0002] Silicon accelerometers are sensors fabricated using MEMS (Mechanical, Electron, and Microsystems) technology that proportionally convert input acceleration into output (usually electrical parameters). The basic structure of a capacitive MEMS accelerometer consists of a mass and fixed electrodes forming a capacitor. When acceleration causes displacement of the mass, the area or spacing of the capacitor plates changes, and acceleration is measured by measuring the capacitance. Capacitive MEMS accelerometers are widely used in instrumentation, wireless communication, energy and environment, biomedicine, military defense, aerospace, automotive electronics, and consumer electronics, among other fields.

[0003] Silicon accelerometers have different structures and processes depending on the application scenarios and needs, but most of them have problems such as poor full-temperature performance and complex processing procedures, which seriously affect the product performance and processing cycle of silicon accelerometers. Summary of the Invention

[0004] To address the above problems, this invention provides a three-layer silicon-based accelerometer and its manufacturing method.

[0005] According to one aspect of the present invention, a method for manufacturing a three-layer silicon-based accelerometer is provided, comprising a first step, a second step, a third step, and a fourth step. The first step includes: forming a silicon dioxide bonding layer on the surface of a fixed layer of a first substrate; patterning the silicon dioxide bonding layer; and etching the pattern formed by the silicon dioxide bonding layer to form a first bonding anchor point. The second step includes: bonding a functional layer of a second substrate to the silicon dioxide bonding layer of the first substrate based on the first bonding anchor point to form a bilayer structure; thinning the functional layer; and patterning and etching the thinned functional layer to obtain a bilayer accelerometer comb structure. The third step includes: forming a second bonding anchor point by etching the surface of a third substrate; forming a first insulating layer on the surface and patterning the first insulating layer; and patterning the first insulating layer. A first metal layer is formed on the surface of the first insulating layer after chemical treatment, and the first metal layer is patterned; a second insulating layer is formed on the surface of the patterned first metal layer, and the second insulating layer is patterned; a second metal layer is formed on the surface of the patterned second insulating layer, and the second metal layer is patterned to obtain a surface-patterned electrode layer. The fourth step includes: based on the second bonding anchor point, bonding the double-layer accelerometer comb structure obtained in the second step to the surface-patterned electrode layer obtained in the third step to obtain a three-layer structure; forming a third metal layer on the surface of the three-layer structure on the side of the first substrate away from the second substrate, and patterning the third metal layer to obtain a three-layer silicon-based accelerometer, wherein the first substrate, the second substrate, and the third substrate are silicon wafers, and the fixed layer and the functional layer are silicon layers.

[0006] Furthermore, the second step further includes: after thinning the functional layer, performing surface treatment on the functional layer to form a metal bonding layer.

[0007] Furthermore, in the first step, a silicon dioxide bonding layer is formed on the surface of the fixed layer by thermal oxidation or PECVD process.

[0008] Furthermore, in the first step, the pattern formed by the silicon dioxide bonding layer is etched using a dry etching or wet etching process.

[0009] Furthermore, in the second step located on the side of the first substrate away from the second substrate, the thinning process includes CMP.

[0010] According to another aspect of the present invention, a method for manufacturing a three-layer silicon-based accelerometer is provided, comprising a first step, a second step, a third step, a fourth step, and a fifth step. The first step includes: forming a silicon dioxide bonding layer on the surface of a support layer of a first substrate; patterning the silicon dioxide bonding layer; and etching the pattern formed by the silicon dioxide bonding layer to form first bonding anchors. The second step includes: etching the functional layer of a second substrate to obtain an accelerometer comb structure. The third step includes: bonding the functional layer of the second substrate to the silicon dioxide bonding layer of the first substrate based on the first bonding anchors to form a bilayer structure; and removing the bottom silicon and silicon dioxide buried oxide layers of the second substrate to obtain a bilayer accelerometer comb structure. The fourth step includes: forming second bonding anchors by etching the surface of a third substrate; and forming a first insulating layer on the surface. The first insulating layer is patterned; a first metal layer is formed on the surface of the patterned first insulating layer, and the first metal layer is patterned; a second insulating layer is formed on the surface of the patterned first metal layer, and the second insulating layer is patterned; a second metal layer is formed on the surface of the patterned second insulating layer, and the second metal layer is patterned to obtain a surface-patterned electrode layer. The fifth step includes: based on the second bonding anchor point, bonding the double-layer accelerometer comb structure obtained in the third step to the surface-patterned electrode layer obtained in the fourth step to obtain a three-layer structure; forming a third metal layer on the surface of the three-layer structure, and patterning the third metal layer to obtain a three-layer silicon-based accelerometer, wherein the first substrate and the third substrate are silicon wafers, the second substrate is an SOI wafer, and the fixed layer and the functional layer are silicon layers.

[0011] Furthermore, in the first step, a silicon dioxide bonding layer is formed on the surface of the fixed layer by thermal oxidation or PECVD process.

[0012] Furthermore, in the first step, the pattern formed by the silicon dioxide bonding layer is etched using a dry etching or wet etching process.

[0013] Furthermore, in the second step, the thinning process includes CMP.

[0014] According to another aspect of the present invention, a three-layer silicon-based accelerometer manufactured according to the above-described method for manufacturing a three-layer silicon-based accelerometer is provided.

[0015] This invention improves the full-temperature performance, sealing performance, and impact resistance of the accelerometer by adopting a three-layer all-silicon-based scheme and through key processes such as silicon-silicon bonding, polishing, and deep silicon etching of the cavity. Attached Figure Description

[0016] Figure 1This is a schematic diagram illustrating the structure of a three-layer silicon-based accelerometer according to an embodiment of the present invention.

[0017] Figure 2 This is a flowchart illustrating a method for manufacturing a three-layer silicon-based accelerometer according to an embodiment of the present invention.

[0018] Figure 3 This is a flowchart illustrating a method for manufacturing a three-layer silicon-based accelerometer according to another embodiment of the present invention.

[0019] Figure 4 This is a schematic diagram illustrating the structure of a three-layer silicon-based accelerometer according to another embodiment of the present invention.

[0020] Figure 5 This is a flowchart illustrating a method for manufacturing a three-layer silicon-based accelerometer according to another embodiment of the present invention. Detailed Implementation

[0021] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0022] Figure 1 This is a schematic diagram illustrating the structure of a three-layer silicon-based accelerometer according to an embodiment of the present invention.

[0023] Reference Figure 1 The structure of the three-layer silicon-based accelerometer includes a fixed support layer 1 with cavity anchor points, a silicon dioxide bonding layer 3, a functional layer 5, an accelerometer comb structure 6, an electrode layer 7 with cavity anchor points, an anchor point 9, a first metal layer 11 for grounding and electrical connection, a first insulating layer 10 for isolating the first metal layer 11 and the electrode layer 7, a second metal layer 13 for gold-silicon bonding, grounding and electrical connection, a second insulating layer 12 for isolating the first metal layer 11 and the second metal layer 13, and a third metal layer 14 for grounding.

[0024] Although Figure 1 The scribe lines and alignment marks 2 and 8 are shown, but the scribe lines and alignment marks 2 and 8 are only used for alignment purposes and can be omitted.

[0025] Figure 2 This is a flowchart illustrating a method for manufacturing a three-layer silicon-based accelerometer according to an embodiment of the present invention.

[0026] Reference Figure 2 and combined Figure 1 The manufacturing method of the three-layer silicon-based accelerometer includes steps (a)-(p).

[0027] Although Figure 2 The diagram shows step (a), which indicates that scribe lines and alignment marks 2 are made on the back side of the support layer 1 of the first substrate. However, step (a) is only for alignment purposes and can therefore be omitted in the manufacturing process.

[0028] In this embodiment, the first substrate may be a silicon wafer, preferably a double-polished low-resistivity silicon wafer, but the present invention does not limit this. The support layer 1 may be a silicon layer.

[0029] In an embodiment, step (b) may include preparing a silicon dioxide bonding layer 3 on the surface of the fixed layer 1. The silicon dioxide bonding layer 3 may be prepared by using processes such as thermal oxidation or PECVD, and the present invention does not particularly limit this.

[0030] Thermal oxidation is a process that forms a thin film of silicon dioxide on the surface of a silicon substrate. When the silicon wafer is heated, silicon reacts with oxygen or water vapor to form a silicon dioxide film.

[0031] PECVD is a process for forming a silicon oxide thin film on the surface of a silicon substrate. By using precursors such as silane and silicon dioxide gas, silicon and oxygen in the precursor gas undergo a chemical reaction on the substrate surface under the action of plasma to form a silicon dioxide thin film.

[0032] In an embodiment, step (c) may include patterning the silicon dioxide bonding layer 3, wherein patterning may include processes such as exposure and development.

[0033] Exposure is a process of exposing photoresist (a photosensitive material) to a light source. In this stage, photoresist is coated onto the surface of a silicon wafer, and then a specific pattern is transferred onto the photoresist using a mask. The main steps of exposure include: Coating: uniformly coating the photoresist onto the surface of the silicon wafer; Alignment: aligning the surface of the photoresist using a mask to ensure correct pattern transfer; Irradiation: irradiating the photoresist with ultraviolet light or other suitable light sources.

[0034] Developing is the chemical treatment of exposed photoresist to remove unexposed or exposed areas, thus forming the final pattern. The developing process includes: immersion or spraying: immersing the silicon wafer in the developing solution or spraying the developing solution onto the surface of the silicon wafer; photoresist removal: the developing solution selectively removes the photoresist, typically removing unexposed areas (for positive photoresist) or exposed areas (for negative photoresist); cleaning and drying: after developing, cleaning and drying steps are required to remove residual developing solution and photoresist.

[0035] In an embodiment, step (d) may include preparing bonding anchors 4 according to the pattern of the silicon dioxide bonding layer 3, wherein the bonding anchors 4 may be prepared by dry etching or wet etching.

[0036] Dry etching is a process that uses gas-phase reactions to remove materials. It typically includes the following steps: Gas introduction: A specific gas (such as hydrogen fluoride, chloride, etc.) is introduced into the etching chamber; Plasma generation: The gas is excited by radio frequency (RF) or microwave to generate plasma. The active particles in the plasma can react with the material to be etched; Reaction and removal: The particles in the plasma react with the material surface to form volatile byproducts, which are then extracted to remove the material.

[0037] Wet etching is a process that uses liquid chemical solutions to remove materials. It typically includes the following steps: Solution selection: Choose a suitable etching solution (such as hydrofluoric acid, sulfuric acid, sodium hydroxide, etc.) based on the type of material to be removed; Immersion or spraying: Immerse the silicon wafer in the etching solution, or spray the etching solution onto the material surface; Reaction: The etching solution reacts chemically with the material surface, forming soluble byproducts, thus removing the material; Rinsing and drying: After etching, rinse the silicon wafer with deionized water to remove residual etching solution, and finally dry it.

[0038] Since the silicon dioxide bonding layer 3 is patterned and then etched, the resulting bonding anchor point 4 can be a cavity anchor point.

[0039] In an embodiment, step (e) may include bonding the functional layer 5 of the second substrate 15 to the fixed layer 1 with silicon based on the bonding anchor point 4, thereby forming a double-layer structure.

[0040] In this embodiment, the second substrate 15 may be a silicon wafer, preferably a double-polished low-resistivity silicon wafer, but the present invention does not limit this. The functional layer 5 may be a silicon layer.

[0041] In an embodiment, step (f) may include thinning and polishing the functional layer 5 included in the double-layer structure to obtain a predetermined thickness, wherein the thinning and polishing can be achieved by CMP process.

[0042] CMP is a process used to planarize the surface of a wafer. It mainly includes: applying a polishing slurry containing chemicals and abrasives to the wafer surface; applying pressure to the wafer through a polishing pad while rotating the wafer to ensure full contact between the polishing slurry and the wafer surface; the abrasives physically grinding the wafer surface, while the chemical components help remove material; after polishing, the wafer needs to be cleaned to remove residual polishing slurry and waste generated.

[0043] In an embodiment, step (g) may include patterning and etching the thinned functional layer 5 to obtain the accelerometer comb structure 6.

[0044] The above steps (c) and (d) describe the patterning and etching processes, and step (g) will not be repeated here.

[0045] Specifically, in step (g), a deep silicon etching process may be used.

[0046] Deep silicon etching typically employs dry etching techniques, among which reactive ion etching or deep reactive ion etching are the most commonly used.

[0047] Although Figure 2 Step (h) is shown and step (h) indicates that scribe lines and alignment marks 8 are made on the back side of the third substrate, but step (h) is only for alignment purposes and therefore can be omitted in the manufacturing process.

[0048] In the embodiments, the third substrate may be a silicon wafer, preferably a double-polished low-resistivity silicon wafer, but the present invention does not limit this.

[0049] In an embodiment, step (i) may include creating anchor points 9 on the front side of the third substrate using dry etching or wet etching.

[0050] In an embodiment, step (j) may include preparing and patterning a first insulating layer 10 on the surface of a third substrate using thermal oxidation or PECVD, wherein the first insulating layer 10 may be silicon dioxide or silicon nitride.

[0051] In an embodiment, step (k) may include preparing and patterning a first metal layer 11 by means of sputtering or evaporation, wherein the first metal layer 11 may be any one or more of gold, titanium, tungsten, etc.

[0052] In an embodiment, step (l) may include preparing and patterning a second insulating layer 12, wherein the second insulating layer 12 may be silicon dioxide (or silicon nitride).

[0053] In an embodiment, step (m) may include preparing and patterning a second metal layer 13 using methods such as sputtering or vapor deposition, wherein the second metal layer 13 may be gold, thereby obtaining an electrode layer 7.

[0054] In an embodiment, step (n) may include bonding the functional layer 5 with the accelerometer comb structure 6 obtained according to step (g) to the surface-patterned electrode layer 7 obtained according to step (m), for example, gold-silicon bonding.

[0055] In an embodiment, step (o) may include preparing and patterning a third metal layer 14 by means of sputtering or vapor deposition, thereby obtaining a three-layer accelerometer.

[0056] Optionally, the method may further include step (p): obtaining a single three-layer accelerometer by scribbling.

[0057] As referred above Figure 2 The present invention provides a method for manufacturing a three-layer silicon-based accelerometer. To address the difficulty of deep silicon etching in the cavity described above, the present invention provides a new method, which will be described below with reference to... Figure 3 Describe it.

[0058] Reference Figure 3 and combined Figure 1 The manufacturing method of the three-layer silicon-based accelerometer includes steps (a)-(q).

[0059] Although Figure 3 Step (a) is shown and step (a) indicates that scribe lines and alignment marks are made on the back side of the support layer 1 of the first substrate, but step (a) is only for alignment purposes and therefore can be omitted in the manufacturing process.

[0060] In this embodiment, the first substrate may be a silicon wafer, preferably a double-polished low-resistivity silicon wafer, but the present invention does not limit this. The support layer 1 may be a silicon layer.

[0061] In an embodiment, step (b) may include preparing a silicon dioxide bonding layer 3 on the surface of the fixed layer 1. The silicon dioxide bonding layer 3 may be prepared by using processes such as thermal oxidation or PECVD, and the present invention does not particularly limit this.

[0062] In an embodiment, step (c) may include patterning the silicon dioxide bonding layer 3, wherein patterning may include processes such as exposure and development.

[0063] In an embodiment, step (d) may include preparing bonding anchors 4 according to the pattern of the silicon dioxide bonding layer 3, wherein the bonding anchors 4 may be prepared by dry etching or wet etching.

[0064] Since the silicon dioxide bonding layer 3 is patterned and then etched, the resulting bonding anchor point 4 can be a cavity anchor point.

[0065] Although Figure 3 Step (e) is shown and step (e) indicates the creation of scribe lines and alignment marks on the back of the SOI film, but step (e) is only for alignment purposes and therefore can be omitted in the manufacturing process.

[0066] In an embodiment, step (f) may include fabricating an accelerometer comb structure 6 on a second substrate 15.

[0067] According to the present invention, the second substrate 15 can be an SOI wafer, but the present invention is not limited thereto. The method will be described below only with the second substrate 15 being an SOI wafer.

[0068] SOI wafers consist of a three-layer structure, from bottom to surface: a bottom substrate silicon layer, a middle silicon dioxide buried oxide layer, and a surface silicon layer (i.e., the functional layer).

[0069] In this embodiment, the accelerometer comb structure 6 can be obtained by etching the functional layer 5 of the SOI wafer.

[0070] In an embodiment, step (g) may include silicon-silicon bonding of the accelerometer comb structure 6 obtained in step (f) to the support layer 1 in which the bonding anchor point 4 is formed in step (d).

[0071] In an embodiment, step (h) may include removing the SOI substrate silicon and the buried oxide layer of silicon dioxide from the SOI wafer. Removing the SOI substrate silicon can be accomplished by polishing or deep silicon etching, and removing the buried oxide layer of silicon dioxide can be accomplished by wet etching or VHF etching.

[0072] In particular, polishing can include CMP processes.

[0073] Although Figure 3 Step (i) is shown and step (i) indicates that scribe lines and alignment marks 8 are made on the back side of the third substrate, but step (i) is only for alignment purposes and therefore can be omitted in the manufacturing process.

[0074] In the embodiments, the third substrate may be a silicon wafer, preferably a double-polished low-resistivity silicon wafer, but the present invention does not limit this.

[0075] In an embodiment, step (j) may include creating anchor points 9 on the front side of the third substrate using dry etching or wet etching.

[0076] In an embodiment, step (k) may include preparing and patterning a first insulating layer 10 on the surface of a third substrate using thermal oxidation or PECVD, wherein the first insulating layer 10 may be silicon dioxide or silicon nitride.

[0077] In an embodiment, step (l) may include preparing and patterning a first metal layer 11 by means of sputtering or vapor deposition, wherein the first metal layer 11 may be any one or more of gold, titanium, tungsten, etc.

[0078] In an embodiment, step (m) may include preparing and patterning a second insulating layer 12, wherein the second insulating layer 12 may be silicon dioxide (or silicon nitride).

[0079] In an embodiment, step (n) may include preparing and patterning a second metal layer 13 using methods such as sputtering or evaporation, wherein the second metal layer 13 may be gold, thereby obtaining an electrode layer 7.

[0080] In an embodiment, step (o) may include bonding the functional layer 5 with the accelerometer comb structure 6 obtained according to step (f) to the surface-patterned electrode layer 7 obtained according to step (m), for example, gold-silicon bonding.

[0081] In an embodiment, step (p) may include preparing and patterning a third metal layer 14 by means of sputtering or vapor deposition, thereby obtaining a three-layer accelerometer.

[0082] Optionally, the method may further include step (q): obtaining a single three-layer accelerometer by slicing.

[0083] Reference above Figure 2 and Figure 3 Described Figure 1 The fabrication method of the three-layer accelerometer with the structure shown is to prevent... Figure 1 The gold-silicon bonding structure shown in the invention is prone to overflow. This invention proposes a new structure (as follows) Figure 4 As shown), this structure is compared to Figure 1 The structure adds a metal bonding layer ( Figure 4 (Represented by reference numeral 18 in the figure), the metal bonding layer 18 is used for signal extraction or subsequent bonding (e.g., bonding with electrode layer 7).

[0084] Reference Figure 4 The structure of the three-layer silicon-based accelerometer includes, in addition to Figure 1 In addition to the shown support layer 1 with cavity anchor points, silicon dioxide bonding layer 3, functional layer 5, accelerometer comb structure 6, electrode layer 7 with cavity anchor points, anchor point 9, first metal layer 11 for grounding and electrical connection, first insulating layer 10 for isolating the first metal layer 11 and electrode layer 7, second metal layer 13 for gold-silicon bonding, grounding and electrical connection, second insulating layer 12 for isolating the first metal layer 11 and second metal layer 13, and third metal layer 14 for grounding, there is also a metal bonding layer 18.

[0085] Figure 5 It shows Figure 4 The manufacturing method of the structure shown. Because... Figure 4 The structure shown is Figure 1 The only difference between the structures shown is the metal bonding layer 18, therefore compared to the reference... Figure 2 Description of manufacturing Figure 1 The method of the structure shown, Figure 5 The method can be supplemented with the following step: after thinning and before deep silicon etching, a metal bonding layer 18 is prepared on the surface of functional layer 5 by means of evaporation or sputtering (e.g.) Figure 5 (as shown in step (g)). Due to Figure 5 The method, except for step (g), involves the same steps as... Figure 2 The steps described are the same, therefore, to avoid repetition, Figure 5 The process will not be described in detail.

[0086] This invention produces a three-layer accelerometer through silicon-silicon bonding, gold-silicon bonding, and other methods. This method offers excellent hermeticity, eliminates the need for subsequent shell encapsulation, and, due to the use of an all-silicon solution, provides good all-temperature performance. Furthermore, the cavity depth can be flexibly designed according to the application environment to improve impact resistance.

[0087] This specification includes many details of specific embodiments, but it should be understood that these details do not limit any inventive concept or the content claimed in the specification, but rather describe the features of some exemplary embodiments.

[0088] The features described in the specification within the context of various exemplary embodiments may be implemented as a combination of one or more individual exemplary embodiments. Conversely, the various features described in the specification within the context of a single exemplary embodiment may be implemented individually or in appropriate sub-combinations as multiple exemplary embodiments.

[0089] Furthermore, features can be operated in specific combinations and can initially be described as required in the combination, but in some cases, one or more features can be excluded from the required combination, and the required combination can be changed into a sub-combination or a modification of the sub-combination.

[0090] Similarly, although the operations are described in a specific order in the accompanying drawings, they should not be construed as requiring the operations to be performed in a specific order or sequence to obtain the desired result, nor should they be construed as requiring all operations to be performed.

[0091] While the concept of the invention has been described in conjunction with exemplary embodiments that are now considered practical, it should be understood that the concept of the invention is not limited to such exemplary embodiments. Rather, the concept of the invention is intended to cover various modifications and equivalent arrangements within the spirit and scope of the appended claims.

Claims

1. A method for manufacturing a three-layer silicon-based accelerometer, characterized in that, Including the first step, the second step, the third step, and the fourth step. The first step includes: A silicon dioxide bonding layer is formed on the surface of the fixed layer of the first substrate; The silicon dioxide bonding layer is patterned. The pattern formed by the silicon dioxide bonding layer is etched to form the first bonding anchor point. The second step includes: Based on the first bonding anchor point, the functional layer of the second substrate is bonded to the silicon dioxide bonding layer of the first substrate using silicon-silicon bonding to form a bilayer structure; The functional layer is thinned. The thinned functional layer is then patterned and etched to obtain a dual-layer accelerometer comb structure. The third step includes: The second bonding anchor point is formed by etching the surface of the third substrate; A first insulating layer is formed on the surface, and the first insulating layer is patterned. A first metal layer is formed on the surface of a first insulating layer that has undergone patterning, and the first metal layer is then patterned. A second insulating layer is formed on the surface of a first metal layer that has undergone patterning, and the second insulating layer is then patterned. A second metal layer is formed on the surface of a patterned second insulating layer, and the second metal layer is then patterned to obtain a surface-patterned electrode layer. The fourth step includes: Based on the second bonding anchor point, the dual-layer accelerometer comb structure obtained through the second step is bonded to the surface-patterned electrode layer obtained through the third step to obtain a three-layer structure. A third metal layer is formed on the surface of the three-layer structure located on the side of the first substrate away from the second substrate, and the third metal layer is patterned to obtain the three-layer silicon-based accelerometer. Wherein, the first substrate, the second substrate and the third substrate are silicon wafers, and the fixed support layer and the functional layer are silicon layers.

2. The method for manufacturing a three-layer silicon-based accelerometer according to claim 1, characterized in that, The second step further includes: after thinning the functional layer, performing surface treatment on the functional layer to form a metal bonding layer.

3. The method for manufacturing a three-layer silicon-based accelerometer according to claim 1, characterized in that, In the first step, the silicon dioxide bonding layer is formed on the surface of the fixed layer by thermal oxidation or PECVD process.

4. The method for manufacturing a three-layer silicon-based accelerometer according to claim 1, characterized in that, In the first step, the pattern formed by the silicon dioxide bonding layer is etched using a dry etching or wet etching process.

5. The method for manufacturing a three-layer silicon-based accelerometer according to claim 1, characterized in that, In the second step, the thinning process includes CMP.

6. A method for manufacturing a three-layer silicon-based accelerometer, characterized in that, Including the first step, the second step, the third step, the fourth step, and the fifth step. The first step includes: A silicon dioxide bonding layer is formed on the surface of the fixed layer of the first substrate; The silicon dioxide bonding layer is patterned. The pattern formed by the silicon dioxide bonding layer is etched to form the first bonding anchor point. The second step includes: The functional layer of the second substrate is etched to obtain the accelerometer comb structure. The third step includes: Based on the first bonding anchor point, the functional layer of the second substrate is bonded to the silicon dioxide bonding layer of the first substrate with silicon to form a double-layer structure. The bottom silicon and silicon dioxide buried oxide layers of the second substrate are removed to obtain a double-layer accelerometer comb structure. The fourth step includes: The second bonding anchor point is formed by etching the surface of the third substrate; A first insulating layer is formed on the surface, and the first insulating layer is patterned. A first metal layer is formed on the surface of a first insulating layer that has undergone patterning, and the first metal layer is then patterned. A second insulating layer is formed on the surface of a first metal layer that has undergone patterning, and the second insulating layer is then patterned. A second metal layer is formed on the surface of a patterned second insulating layer, and the second metal layer is then patterned to obtain a surface-patterned electrode layer. The fifth step includes: Based on the second bonding anchor point, the dual-layer accelerometer comb structure obtained through the third step is bonded to the surface-patterned electrode layer obtained through the fourth step to obtain a three-layer structure. A third metal layer is formed on the surface of the three-layer structure located on the side of the first substrate away from the second substrate, and the third metal layer is patterned to obtain the three-layer silicon-based accelerometer. Wherein, the first substrate and the third substrate are silicon wafers, the second substrate is an SOI wafer, and the fixed support layer and the functional layer are silicon layers.

7. The method for manufacturing a three-layer silicon-based accelerometer according to claim 6, characterized in that, In the first step, the silicon dioxide bonding layer is formed on the surface of the fixed layer by thermal oxidation or PECVD process.

8. The method for manufacturing a three-layer silicon-based accelerometer according to claim 6, characterized in that, In the first step, the pattern formed by the silicon dioxide bonding layer is etched using a dry etching or wet etching process.

9. A three-layer silicon-based accelerometer, characterized in that, The three-layer silicon-based accelerometer is manufactured according to the manufacturing method of the three-layer silicon-based accelerometer according to any one of claims 1 to 8.

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