Method, apparatus, cluster, medium and product for cache management

Abstract

Embodiments of the present disclosure relate to a cache management method, apparatus, cluster, medium and product. The cache management method according to embodiments of the present disclosure is characterized in that it is applied to a storage system comprising a host and a storage device, the host running an application program and comprising a host-side cache, and the storage device comprising a device-side cache and a storage medium. The method comprises mapping a virtual address space of data to the host-side cache, the device-side cache and the storage medium respectively based on access frequency of the data. The method further comprises obtaining a target virtual address space of target data in the data based on a byte-granularity I / O request from the application program. The method further comprises accessing the target data from the host-side cache, the device-side cache or the storage medium based on the target virtual address space in a byte-granularity. In this way, flexible mapping based on access frequency can be provided, and collaborative cache management and byte access between the host side and the device side can be supported.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to the field of storage, and more specifically to a method, apparatus, computing device cluster, computer-readable storage medium, and computer program product for cache management. Background Technology

[0002] Solid-state drives (SSDs), also known as solid-state drives, are high-bandwidth, low-latency storage devices that use non-volatile flash memory (NAND flash). Unlike traditional hard disk drives (HDDs) that use rotating platters and moving read / write heads for data access, SSDs use solid-state electronic storage chips to store and read / write data. An SSD typically consists of a control unit and storage units (Flash chips and DRAM chips).

[0003] With the continuous advancement of storage technology, SSDs have gradually become the mainstream storage device. Compared to traditional HDDs, SSDs offer numerous advantages. For example, SSDs achieve faster data access speeds because their mechanical parts-free design allows direct reading of data from the storage chip, significantly reducing boot time and file transfer time. Furthermore, since SSDs do not require moving mechanical parts (such as motors and other moving components), they are more resistant to vibration and shock and less susceptible to magnetic field interference, resulting in more reliable data storage performance and lower power consumption. These advantages have made SSDs increasingly popular and widely used in computers, servers, mobile devices, and other fields, providing users with faster, more efficient, and more reliable data storage solutions. However, current SSD-based data storage solutions still face technical challenges that need to be overcome. Summary of the Invention

[0004] The embodiments of this disclosure provide a cache management scheme. The cache management scheme according to the embodiments of this disclosure can provide a byte access granularity abstraction for collaboration between the host and device sides to achieve data access and cache management at different granularities.

[0005] In a first aspect of this disclosure, a cache management method is provided, characterized by being applied to a storage system including a host and storage devices. The host runs an application and includes a host-side cache, and the storage devices include a device-side cache and storage media. The method includes mapping the virtual address space of data to the host-side cache, device-side cache, and storage media respectively based on the data's access frequency. The method further includes retrieving the target virtual address space of target data from the data based on byte-level I / O requests from the application. The method also includes accessing the target data from the host-side cache, device-side cache, or storage media at the byte-level based on the target virtual address space. In this manner, flexible mapping based on access frequency can be provided, and collaborative cache management and byte access between the host and device sides can be supported.

[0006] In some embodiments, host-side cache, device-side cache, and storage media can be managed by the host. In this way, storage devices (device-side) can be exposed to the host (host-side), in other words, the host can be aware of the devices, enabling them to work together without causing, for example, the same data to be cached multiple times, resulting in wasted cache space.

[0007] In some embodiments, the method further includes dividing the data into multiple parts of a predetermined unit size, and determining the access frequency for each of the multiple parts of the data. In this way, the access frequency is determined for each part of the predetermined unit size, and then customized cache management is performed on each part based on the access frequency of each part.

[0008] In some embodiments, data is written to a storage device, and determining the access frequency may include determining the location where each of a plurality of portions of the data is to be written, based on I / O requests for the data, and determining the frequency at which the determined locations were accessed in the previous time step as the access frequency. In this way, even if the data is new data to be written to the storage device, the access frequency of each portion can be estimated based on the historical access frequency of the location where each portion is to be written to the storage device.

[0009] In some embodiments, data has been written to a storage device, and determining the access frequency may include determining the frequency at which each of a plurality of portions of the data was accessed in the previous time step as the access frequency. In this way, with data already written to the storage device, these portions can be redistributed according to the historical access frequency of each portion, enabling dynamic cache management in the storage system and thereby improving the access performance of the storage system.

[0010] In some embodiments, the device-side cache may include a cache portion and a swap portion, and mapping the virtual address space of data to the host-side cache, device-side cache, and storage medium based on the data access frequency may further include: mapping the virtual address space of data accessed more frequently than a first frequency threshold to the host-side cache; mapping the virtual address space of data accessed more frequently than the first frequency threshold but more frequently than a second frequency threshold to the cache portion of the device-side cache; and mapping the virtual address space of data accessed less frequently than the second frequency threshold to the storage medium via the swap portion of the device-side cache, wherein the first frequency threshold is greater than the second frequency threshold. In this way, flexible mapping of virtual memory is performed according to the access frequency of each portion; that is, the virtual address space of each portion is mapped to the host-side cache, device-side cache, and storage medium respectively according to the access frequency of each portion. This data hot / cold separation caching technology stores data with different levels of access frequency in different cache levels, achieving data separation in the cache medium.

[0011] In some embodiments, accessing target data from a host-side cache, device-side cache, or storage medium at a byte-granularity based on a target virtual address space may include, in response to the target virtual address space including a first virtual address space mapped to the host-side cache, accessing first data corresponding to the first virtual address space directly from the host-side cache at a first byte-granularity. In this manner, the most frequently accessed data can be accessed directly from the host-side cache at a byte-granularity without needing to access the storage device side via the PCIe protocol. As a result, data interaction between the host and device is reduced, while PCIe traffic is decreased.

[0012] In some embodiments, accessing target data from a host-side cache, device-side cache, or storage medium at a byte-granularity based on a target virtual address space may include accessing second data corresponding to the second virtual address space from the cache portion at a second byte-granularity via the PCIe protocol, in response to the target virtual address space including a second virtual address space mapped to the cache portion. In this manner, less frequently accessed data can be accessed from the device-side cache on the storage device side via the PCIe protocol at a smaller byte-granularity.

[0013] In some embodiments, accessing target data at the byte level from a host-side cache, device-side cache, or storage medium based on a target virtual address space may include, in response to the target virtual address space including a third virtual address space mapped to the storage medium, accessing third data corresponding to the third virtual address space from the storage medium at the third byte level via the PCIe protocol by utilizing a switching portion. In this manner, the coldest data can be accessed at the byte level via the PCIe protocol from the storage medium on the storage device side, wherein the device-side cache on the storage device side does not cache the coldest data, but instead transfers the coldest data from the storage medium for access. Since the coldest data does not require frequent access, the interaction with the storage medium does not introduce high latency.

[0014] In some embodiments, the second byte granularity can correspond to the granularity of CPU L3 cache swapping. In this way, less frequently accessed data can be accessed at a smaller byte granularity corresponding to the granularity of CPU L3 cache swapping, avoiding read-write amplification degradation.

[0015] In some embodiments, the caching component can be configured to merge multiple byte-level I / O requests from the application into a single page-level I / O request, and cache the corresponding data from the storage medium at the page level based on the single page-level I / O request. This reduces the number of read / write operations on the storage medium, avoiding latency caused by repeated read / write operations.

[0016] In some embodiments, the host-side cache can be configured to perform cache replacement based on a Least Recently Used (LRU) policy. The cache portion can be configured to perform cache replacement based on a write-back policy and multiplexed group associative management. Furthermore, the switching portion can be configured to perform cache replacement based on a write-through policy.

[0017] According to a second aspect of this disclosure, a cache management apparatus is provided, characterized in that it is applied to a storage system including a host and a storage device, wherein the host runs an application and includes a host-side cache, and the storage device includes a device-side cache and a storage medium. The apparatus includes a mapping module configured to map the virtual address space of data to the host-side cache, the device-side cache, and the storage medium respectively based on the data's access frequency. The apparatus also includes an acquisition module configured to acquire the target virtual address space of target data from the data based on byte-level I / O requests from the application. The apparatus further includes an access module configured to access the target data from the host-side cache, the device-side cache, or the storage medium at a byte-level based on the target virtual address space. In this manner, flexible mapping based on access frequency can be provided, and collaborative cache management and byte access between the host and device sides can be supported.

[0018] According to a third aspect of this disclosure, a computing device is provided. The computing device includes a processor and a memory storing instructions that, when executed by the processor, cause the computing device to perform the method described according to a first aspect of this disclosure.

[0019] According to a fourth aspect of this disclosure, a computing device cluster is provided. The computing device cluster includes at least one computing device, each computing device including a processor and memory. The processor of the at least one computing device is configured to execute instructions stored in the memory of the at least one computing device to cause the computing device cluster to perform the method described in the first aspect of this disclosure. In some embodiments, the computing device cluster includes a single computing device. In other embodiments, the computing device cluster includes multiple computing devices. In some embodiments, the computing device may be a server, such as a central server, an edge server, or a local server in a local data center. In some embodiments, the computing device may also be a terminal device such as a desktop computer, a laptop computer, or a smartphone.

[0020] According to a fifth aspect of this disclosure, a computer-readable storage medium is provided. The computer-readable storage medium stores computer program instructions that, when executed by a cluster of computing devices, perform the method described according to a first aspect of this disclosure.

[0021] According to a sixth aspect of this disclosure, a computer program product is provided. The computer program product includes instructions that, when executed by a cluster of computing devices, cause the cluster of computing devices to perform the method described according to a first aspect of this disclosure. In some embodiments, the program product may include one or more software installation packages that can be downloaded or copied and executed on the computing devices when the method provided by the first aspect or its possible variations is required.

[0022] Please note that the Summary of the Invention is provided to introduce a series of concepts in a simplified form, which will be further described below in the Detailed Description. The Summary of the Invention is not intended to identify key or essential features of this disclosure, nor is it intended to limit the scope of this disclosure. Attached Figure Description

[0023] The above and other objects, features, and advantages of this disclosure will become clearer through a more detailed description of the embodiments thereof in conjunction with the accompanying drawings, in which:

[0024] Figure 1 This is a schematic diagram illustrating an exemplary storage system in which methods and / or processes according to embodiments of the present disclosure may be implemented;

[0025] Figure 2 This is a schematic diagram of a flowchart illustrating a cache management method according to an embodiment of the present disclosure;

[0026] Figure 3 An exemplary diagram of a cache management process according to an embodiment of the present disclosure is schematically illustrated;

[0027] Figure 4 A flowchart illustrating a process for determining access frequency according to an embodiment of the present disclosure is shown schematically.

[0028] Figure 5 A flowchart illustrating another process for determining the access frequency according to an embodiment of the present disclosure is shown schematically.

[0029] Figure 6 A schematic diagram illustrating a cache management framework according to an embodiment of the present disclosure is provided.

[0030] Figure 7 The diagram illustrates the granularity configuration and protocol configuration in the cache management process according to an embodiment of the present disclosure.

[0031] Figure 8 A schematic diagram illustrating the policy configuration in the cache management process according to an embodiment of the present disclosure is provided.

[0032] Figure 9 A schematic block diagram of a cache management apparatus according to an embodiment of the present disclosure is shown;

[0033] Figure 10 A schematic block diagram of an example device is shown, which can be used to implement exemplary implementations of this disclosure.

[0034] Figure 11 A schematic block diagram illustrating an example device cluster that can be used to implement exemplary implementations of this disclosure is shown; and

[0035] Figure 12 A schematic block diagram of another example device that can be used to implement exemplary implementations of this disclosure is shown.

[0036] In all the accompanying drawings, the same or similar reference numerals usually indicate the same or similar elements. Detailed Implementation

[0037] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0038] In the description of embodiments of this disclosure, the term "comprising" and its variations should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects unless explicitly indicated otherwise.

[0039] As mentioned above, a solid-state drive (SSD) is a high-bandwidth, low-latency hard drive. SSDs use solid-state electronic storage chips to store and read / write data; currently, the mainstream SSD storage chips are non-volatile flash memory (NAND-Flash) chips. As a high-performance storage device, SSDs typically use flash memory (Flash) as the storage medium, such as NAND-Flash. Compared to previous storage technologies, SSDs have faster read / write speeds and lower latency, and due to the non-volatile nature of SSD storage chips, they can retain data even when power is off.

[0040] The NAND flash memory mentioned above boasts advantages such as high density, low power consumption, and durability, making it widely used in various storage devices. NAND flash SSDs perform read and write operations on a page-by-page basis (i.e., at the page granularity), with each page typically being 4KB or 8KB in size. However, due to the write-after-erase characteristic of flash media, performing small-granularity read and write operations on an SSD requires first reading the entire page containing the data before performing the small-granularity read and write operation. In other words, small-granularity read and write requests are not SSD-friendly, as such read and write operations consume additional or extra storage resources and time costs. Traditional SSDs typically have a minimum memory access granularity of 512B or 4KB.

[0041] With an increasing number of small-granularity (e.g., byte-level) access requests to SSDs, such as application accesses to storage device caches, it is necessary to provide byte-level access interfaces for read and write operations. Some storage devices provide such interfaces. In some existing storage devices, host-side improvements have enabled byte-level read and write operations. However, because existing SSD interfaces limit the granularity of read and write operations (e.g., 4KB), while the granularity of CPU read and write caches is typically small (usually exchanging data with the L3 cache at a 64B granularity), this difference can lead to significant read / write amplification issues.

[0042] In some existing storage devices, improvements on the storage device side enable read and write operations at the byte level. However, since direct host access to the SSD cache requires the PCIe protocol, access latency is higher and bandwidth is limited compared to host-side caching, directly impacting application performance. Furthermore, host-side caching and SSD caching do not work together; SSD devices do not expose cache management interfaces to the host, leaving the host unaware of the device's caching layer. Since the host typically also has read / write caches from the storage device, multiple cache copies of the same data may exist on both the host and storage device sides, resulting in wasted cache space. Additionally, the different granularity of host-side and storage device-side caching can also lead to read / write amplification issues.

[0043] To address at least some of the aforementioned problems and other potential issues, a cache management method according to embodiments of this disclosure is proposed. This method is characterized by being applied to a storage system comprising a host and storage devices, wherein the host runs an application and includes a host-side cache, and the storage devices include a device-side cache and storage media. The method includes mapping the virtual address space of data to the host-side cache, device-side cache, and storage media respectively based on the data's access frequency. The method also includes obtaining the target virtual address space of target data within the data based on byte-level I / O requests from the application. Furthermore, the method includes accessing the target data from the host-side cache, device-side cache, or storage media at a byte-level based on the target virtual address space. In this manner, flexible mapping based on access frequency can be provided, and collaborative cache management and byte access between the host and device sides can be supported.

[0044] The following is for reference. Figures 1 to 12 The present disclosure is provided to illustrate its basic principles and several exemplary implementations. It should be understood that these exemplary embodiments are given only to enable those skilled in the art to better understand and implement the embodiments of the present disclosure, and are not intended to limit the scope of the disclosure in any way.

[0045] Figure 1 This is a schematic diagram illustrating an exemplary storage system 100 in which methods and / or processes according to embodiments of the present disclosure may be implemented. Figure 1 As shown, the storage system 100 includes a host 110 and storage devices 120, 121, and 122. Between the host 110 and the storage devices 120, 121, and 122, in addition to page-level (i.e., page-granularity) read and write operations, byte-level (i.e., byte-granularity) read and write operations can also be performed. For example, in... Figure 1 Between host 110 and storage device 120, access can be performed at a 64-bit granularity or, for example, a 4KB granularity. Access between host 110 and storage devices 121 and 122 is the same or similar. It should be noted that... Figure 1 The 64B and 4KB shown are merely examples of byte granularity and page granularity, and the embodiments of this disclosure are not limited thereto. For example, byte granularity may also include 32B, page granularity may also include 8KB, and other values ​​determined according to specific needs are also possible.

[0046] According to embodiments of this disclosure, host 110 may be a processing device with computing capabilities, on which applications may run, such as applications for accessing or managing storage devices 120, 121, and 122, or applications running based on data on storage devices 120, 121, and 122, etc. Host 110 may send access requests to storage devices 120, 121, and 122 to perform read and write operations. For example, an application on host 110 may send a request to storage devices 120, 121, and 122 to retrieve target data as required for its operation.

[0047] By way of example and not limitation, host 110 may include a computer, server, mobile device, wearable device, console, player, reader, personal digital assistant, or a combination thereof. It should be noted that the examples of host 110 and applications described herein are illustrative for purposes of understanding only, and embodiments of this disclosure are not limited to these examples and may include other different types or versions of devices and applications.

[0048] According to embodiments of this disclosure, storage devices 120, 121, and 122 can be configured to store data, such as data from applications running on host 110. Storage devices 120, 121, and 122 can be or include SSDs. SSD-based storage devices 120, 121, and 122 may include storage media such as NAND flash to provide faster read / write speeds, lower latency, and data reliability. Storage devices 120, 121, and 122 can respond to requests from host 110 by writing new data or caching data. It should be noted that embodiments of this disclosure do not specifically limit the version, size, etc., of storage devices 120, 121, and 122.

[0049] In storage system 100, the host 110 and storage devices 120, 121, and 122 can be coupled together, for example, via a bus, network, or directly connected through physical interfaces such as USB or eSATA. The host 110 and storage devices 120, 121, and 122 can be deployed locally or in a distributed manner. For example, storage device 120 can be deployed locally while storage devices 121 and 122 can be deployed in the cloud. Figure 1 As shown in the diagram, with host 110 and storage devices 120, 121, and 122 located locally, data transmission distances are shorter, resulting in lower latency. This is highly advantageous for applications requiring rapid response, such as real-time audio and video streaming. Furthermore, since data is primarily processed and stored locally, user privacy and sensitive data are better protected.

[0050] With the host 110 and storage devices 120, 121, and 122 distributed in a distributed manner, a distributed storage system 100 is formed. This cloud-like deployment allows for the easy addition of more hosts or storage devices, and the load can be distributed across all of these hosts or storage devices, thereby improving the overall performance and throughput of the storage system 100. Furthermore, the host 110 and storage devices 120, 121, and 122 can all be located in a single region, or they can be located in multiple regions. This multi-regional deployment ensures that even if a device in one region fails, other regions can continue operating, improving the availability and stability of the storage system 100.

[0051] It should be understood that, for the purpose of ease of explanation and illustration, in Figure 1The diagram shows only one host (i.e., host 110) and three storage devices (i.e., storage devices 120, 121, and 122). However, this is merely an example; other numbers of hosts and storage devices can exist, and they can be customized as described above, depending on the specific use case and needs, as will be discussed below. The above, combined with... Figure 1 The following describes an example environment in which methods and / or processes according to embodiments of this disclosure may be implemented, in conjunction with... Figure 2 This describes a cache management method 200 according to embodiments of the present disclosure.

[0052] Figure 2 This is a schematic illustration of a flowchart of a cache management method 200 according to an embodiment of the present disclosure. According to the combination... Figure 2 The described method 200 provides a flexible mapping based on access frequency and supports collaborative cache management and byte access between the host and device sides. In the following description, for ease of illustration and explanation, it is illustrated using one host (i.e., host 110) and one storage device (i.e., storage device 120), and it should be understood that multiple hosts and multiple storage devices are also possible, and... Figure 2 The situation described herein is the same as or similar.

[0053] The cache management method 200 according to embodiments of this disclosure is applied to a storage system 100 including a host 110 and a storage device 120. The host 110 runs an application and includes a host-side cache, while the storage device 120 includes a device-side cache and a storage medium. In this storage architecture, both the host-side cache and the storage device 120-side cache are enabled. This combined use of host-side and device-side cache reduces the number of accesses to the storage medium, thereby improving overall I / O performance.

[0054] At address 210, the virtual address space of data is mapped to the host-side cache, device-side cache, and storage medium based on the data's access frequency. This operation allows for flexible mapping of data's virtual memory addresses to different locations on the host 110 and storage device 120 sides, enabling data to be differentiated within the system based on access frequency. Thus, frequently accessed data can be cached for fast read / write operations, while infrequently accessed data is mapped to the storage medium to save cache space.

[0055] At 220, the target virtual address space of the target data is retrieved based on byte-level I / O requests from the application. When the application runs on host 110, it generates I / O requests for reading and writing to the target data, where these I / O requests indicate the target virtual address space of the target data. These I / O requests are then sent to storage device 120. After receiving these I / O requests, storage device 120 parses them to determine the target virtual address space of the target data, thereby completing the addressing. Here, byte-level I / O requests indicate that the read / write operation is in bytes, or that the target data to be accessed is in bytes.

[0056] At address 230, target data is accessed at the byte level from host-side cache, device-side cache, or storage medium, based on the target virtual address space. By introducing the combined use of host-side cache and device-side cache, not only can byte-level access between the host 110 side and the storage device 120 side be realized, but also the data read / write speed and reliability can be improved, and unnecessary data transfers and accesses to storage medium can be reduced.

[0057] According to the cache management method 200 of the embodiments of this disclosure, in addition to the page-level access interface, a byte-level access interface can also be provided between the source unit (e.g., host 110) and the target unit (e.g., storage device 120). This enriches the memory access interfaces within the system, which is beneficial for application development. Simultaneously, since byte-level access between the source and target units is implemented, the granularity difference with CPU L3 cache exchange is ensured, avoiding read / write amplification problems. Furthermore, grouping data with different levels of hotness and coldness for caching, i.e., a customized cache management strategy, solves the problem of frequent cache replacement. The following will combine... Figure 3 The cache management according to embodiments of this disclosure is described in further detail.

[0058] Figure 3 An exemplary diagram of a cache management process 300 according to an embodiment of the present disclosure is schematically illustrated. Figure 3As shown, host 110 includes an application 310 running thereon, from which I / O requests for accessing target data can be sent, such as byte-granular I / O requests. A byte-granular I / O request means that the read / write operation is performed in one or more bytes, or that the size of the target data to be accessed is several bytes. According to embodiments of this disclosure, in addition to page-level data exchange (e.g., 4K granularity), host 110 and storage device 120 can also perform byte-level data exchange (e.g., 64B granularity) because a byte-granular access interface is provided through joint interaction between the two caches, which is important for simplifying application storage management and performance optimization.

[0059] According to embodiments of this disclosure, the host 110 side includes a host-side cache 320, which may be part of the host 110-side memory. By way of example, and not limitation, the host 110-side memory may include dynamic random access memory (DRAM), a type of semiconductor memory commonly used as main memory to store running programs and data. DRAM is characterized by its high access speed and large capacity, and is therefore widely used. It should be noted that DRAM is only one exemplary implementation of the host 110-side memory, and embodiments of this disclosure may also include other different or improved implementations.

[0060] The host-side cache 320 can be used to cache frequently accessed or used data so that it can be accessed by the host 110 more quickly. This caching strategy can improve data read and write speed, thereby improving the performance of the entire storage system 100. The size of the host-side cache 320 can be configured according to specific application scenarios and device resources. In some cases, a larger cache can improve the system's data read and write speed, but it also requires more memory resources. Conversely, a smaller cache can reduce memory resource consumption, but it leads to increased memory access latency, thus affecting the system's response speed and throughput. Therefore, to strike a balance, the size of the host-side cache 320 can be selected based on specific uses and requirements, as well as the overall performance and resource limitations of the host 110.

[0061] like Figure 3As shown, storage device 120 includes device-side cache 330 and storage medium 340. By way of example and not limitation, storage device 120 may be an SSD-based storage device and may typically include DRAM chips and Flash chips. Device-side cache 330 may be part of the memory on the storage device 120 side. By way of example and not limitation, the memory on the storage device 120 side may include dynamic random access memory (DRAM). Again, DRAM is only one exemplary implementation of the memory on the storage device 120 side, and embodiments of this disclosure may also include other different or improved implementations. Device-side cache 330 may be used to cache data that is accessed from time to time or used sometimes so that it can be accessed by host 110 more quickly. When setting the size of device-side cache 330, factors such as purpose and resource configuration of the storage device (e.g., overall performance and resource limitations of storage device 120) also need to be considered. In addition, data access patterns, cache update strategies, etc., will also affect the size configuration of device-side cache 330.

[0062] Storage medium 340 can store data that is not frequently accessed or used. Data with low access frequency or low usage may not be cached on either the host 110 side or the storage device 120 side, but instead be stored in storage medium 340 and transferred via a cache (e.g., device-side cache 330) when needed. The advantage of this approach is that it avoids excessive memory resource consumption caused by caching this data. By way of example and not limitation, storage medium 340 may include a Flash-based storage medium, and embodiments of this disclosure may of course include other different or improved implementations. It should be noted that the size of storage medium 340 can also be customized based on various factors, and this disclosure does not limit it.

[0063] Because application memory accesses are byte-level, a dual-sided caching mechanism using host-side cache 320 and device-side cache 330 enables fine-grained data exchange between host 110 and storage device 120, resolving the mismatch between media (e.g., Flash media) and byte-level memory access granularity. Simultaneously, this smaller-granularity read / write request reduces the data transmission bandwidth on the data transfer link and provides the system with richer memory access interfaces. Furthermore, dynamic mapping based on access frequency or popularity improves the complex cache management on both the host 110 and storage device 120 sides, providing a more efficient and flexible customized storage solution.

[0064] According to embodiments of this disclosure, the host-side cache 320, device-side cache 330, and storage medium 340 can be managed by the host 110. In this way, the storage device 120 (device-side) can be exposed to the host 110 (host-side); in other words, the host-side can be aware of the device-side, enabling them to operate collaboratively without causing, for example, the same data to be cached multiple times, resulting in wasted cache space. As mentioned above, the virtual address space or virtual memory address of data can be mapped to different locations in the system, i.e., the host-side cache 320, device-side cache 330, and storage medium 340, depending on its popularity. Management of these components by the host 110 ensures that the host-side and device-side caches do not duplicate.

[0065] As described above, the popularity of data (i.e., the frequency of access) determines which of the following three caches—host-side cache 320, device-side cache 330, and storage medium 340—the data's virtual address space is mapped to. To facilitate determining the data access frequency, according to embodiments of this disclosure, the data can be divided into multiple parts of a predetermined unit size, and the access frequency can be determined for each of these parts. Thus, by determining the access frequency for each part of the predetermined unit size, customized cache management can be performed on each part based on its access frequency. This flexible management approach can better meet the access needs of different parts, thereby improving the overall performance of the system. The following will combine... Figure 4 and Figure 5 The process for determining the access frequency according to embodiments of this disclosure is described in further detail.

[0066] Figure 4 A flowchart illustrating a process 400 for determining access frequency according to an embodiment of the present disclosure is shown schematically. As described above, data can be divided into multiple parts having a predetermined unit size, and the access frequency can be determined for each such part. Such division allows for more accurate results to be obtained by detecting and analyzing the access frequency of each part. Embodiments of the present disclosure will consider at least two cases: one where data is about to be written to storage device 120, and the other where data has already been written to storage device 120. It should be noted that, in addition to these two cases, other cases based on access history are also possible, and their determination process can be the same as or similar to that described below.

[0067] Figure 4 This schematically illustrates the situation where data is about to be written to storage device 120. For example... Figure 4As shown, at 410, based on I / O requests for data, the location where each of the multiple portions of the data is to be written can be determined. The I / O request for data can indicate the location in storage system 100 where the data will be written (hereinafter also referred to as the target location), that is, it contains location information related to the location or identifier of the data. In addition, the I / O request can also indicate the data read / write mode, size and type, start and end times of data transfer, consistency or backup requirements, etc.

[0068] At 420, the frequency with which the determined location was accessed in the previous time step is determined. These portions of data have not yet been written to storage device 120. For example, through statistical methods such as sampling by the host operating system, the frequency with which these portions of the target location in storage system 100 were accessed in the past (i.e., the historical access frequency of the target location) is determined and estimated as the access frequency of each of these portions. The previous time step at 420 may include past times such as the previous hour, yesterday, or last week, and can be predetermined as needed; embodiments of this disclosure do not limit this.

[0069] At 430, the determined frequency is used as the estimated access frequency for each part. Based on the combination... Figure 4 The described process for determining access frequency 400, even if the data is new data to be written to storage device 120, can estimate the access frequency of each part based on the historical access popularity of the target location where each part is to be written, so that the data can be segmented based on historical access patterns.

[0070] Figure 5 A flowchart illustrating another process 500 for determining the access frequency according to an embodiment of the present disclosure is shown schematically. Figure 5 This schematically illustrates a situation where data already exists in storage device 120. For example... Figure 5 As shown, at 510, the frequency with which each of the multiple portions of the data was accessed in the previous time step (i.e., historical access frequency) is determined. For example, the frequency of access to these portions within past time periods or intervals can be determined through statistical methods such as sampling by the host operating system. Similarly, the previous time step at 510 can include past times such as the previous hour, yesterday, or last week, and can be predetermined as needed; embodiments of this disclosure do not limit this.

[0071] At point 520, the determined frequency is used as the access frequency for each part. Based on the combination... Figure 5The described process 500 for determining access frequency, after data has been written to storage device 120, allows for the redistribution of data based on the historical access frequency of each part. This enables dynamic cache management in storage system 100, thereby improving the access performance of the storage system. For example, when the cache is full, we can determine which part should be replaced based on the access frequency of each part. If a part has a very high access frequency, it should be kept in the cache, while if a part has a very low access frequency, it should be replaced. The following will combine... Figure 6 A cache management framework according to embodiments of the present disclosure is described in further detail.

[0072] Figure 6 A schematic diagram illustrating a cache management framework 600 according to an embodiment of the present disclosure is provided. Figure 6 As shown, the cache management framework 600 includes a virtual memory space 620, in which the virtual address space or virtual memory address of data can be based on its access frequency (e.g., by combining...). Figure 4 and Figure 5 The process of determining the described access frequency is mapped to different cache or storage layers, i.e. Figure 6 The segmented memory mapping 621 is included. Furthermore, the device-side cache 330 may include a cache portion 640 and a swap portion 650 to further subdivide its functionality to meet different caching needs.

[0073] According to embodiments of this disclosure, the virtual address space of data accessed more frequently than a first frequency threshold can be mapped to the host cache 320, the virtual address space of data accessed less frequently than the first frequency threshold but more frequently than a second frequency threshold can be mapped to the cache portion 640 in the device cache 330, and the virtual address space of data accessed less frequently than the second frequency threshold can be mapped to the storage medium 340 via the switching portion 650 in the device cache 330, wherein the first frequency threshold is greater than the second frequency threshold.

[0074] The first frequency threshold can refer to high access frequency and popularity, and data exceeding the first frequency threshold indicates that this data is frequently accessed or used. Caching frequently accessed or used data in the host-side cache 320 allows the host 110 to access this data faster, improving the read / write speed of hot data and thus improving the overall performance of the storage system 100. The host 110 can directly access the host-side cache 320, and access between the host 110 and the host-side cache 320 supports byte-level data exchange. Compared to the storage device 120, this caching strategy achieves faster speeds while maintaining relatively low data transfer traffic. In other words, it reduces the number of accesses to the storage device 120, thus reducing latency caused by PCIe protocol and Flash media read / write during memory access, while also reducing the load on the storage device 120 and extending its lifespan.

[0075] The second frequency threshold can refer to low access frequency and popularity, and data that is below the first frequency threshold but above the second frequency threshold indicates that this data is accessed intermittently or used occasionally. Caching intermittently accessed or used data in cache portion 640 of device-side cache 330 allows host 110 to access this less frequently accessed data faster via the PCIe protocol, thereby improving access performance. Access from host 110 to this cache portion 640 can be byte-level. Simultaneously, this caching strategy also saves host 110's memory resources. Since host 110's memory resources are limited, storing all data in host-side cache 320 would lead to a waste of memory resources.

[0076] Data below the second frequency threshold indicates that this portion of data is infrequently accessed or rarely used. Infrequently accessed or rarely used data (i.e., cold data) is stored in storage medium 340 without caching and is only retrieved when needed via a switching section 650 in the device-side cache 330. This switching section 650 provides a fine-grained, byte-level access interface to the host 110. This caching strategy conserves valuable cache resources and reduces the overhead of cache expiration and replacement, while effectively optimizing the performance and efficiency of the storage system by mitigating problems caused by cache overflows or data loss.

[0077] By implementing cache management through the cache management framework 600 according to embodiments of this disclosure, the most frequently accessed data can be accessed without repeated data interactions with the storage device 120, significantly reducing PCIe traffic. Under this cache management framework 600, less frequently accessed data is cached in the cache portion 640 of the memory on the storage device side 120, avoiding latency caused by repeated read / write operations on the storage medium 340. Simultaneously, the cached less frequently accessed data supports smaller granularity access, ensuring consistency with the granularity of CPU L3 cache swapping and preventing read / write amplification issues. Furthermore, cold data is relayed through the swap portion 650 of the memory on the storage device 120 side as an indirect layer, providing a byte-level access interface. Since it is not frequently accessed, the interaction with the storage medium 340 does not introduce high latency. Overall, this mechanism provides a byte-level interface for SSD data access while also ensuring high efficiency.

[0078] Furthermore, this mechanism provides three different cache management modes, effectively offering different memory access strategies for data of varying hotness and granularity, thus improving the flexibility of cache management and SSD data access. Combined with statistical methods such as host operating system sampling (e.g., memory access and sampling techniques in the Linux kernel, used to determine access frequency), this data hot-cold separation caching technology stores data of different hotness levels in different cache levels, achieving data separation in the cache medium, where corresponding data across different cache levels are mutually exclusive. Grouping and caching data of different hotness levels effectively solves problems such as data read / write amplification and frequent cache replacement. It should be understood that the embodiments of this disclosure divide data into three types based on access frequency: hot, moderately hot, and cold. However, more detailed classifications can be made as needed, and other factors besides access frequency can also be considered during classification; the embodiments of this disclosure do not impose any limitations on this.

[0079] Figure 7 A schematic diagram illustrates the granularity and protocol configuration 700 in the cache management process according to an embodiment of the present disclosure. This is for ease of illustration and explanation. Figure 7 The diagram exemplifies how the virtual address space or virtual memory address of data is divided into three segments: segment 1 (701), segment 2 (702), and segment 3 (703). Using the virtual memory system, the address space of the data to be manipulated can be mapped to the host-side cache (320), the device-side cache (cache portion 640), and the storage medium (340), respectively, with the data corresponding to these portions being mutually exclusive. It should be understood that this is merely illustrative and not restrictive; more or fewer segments are possible.

[0080] According to embodiments of this disclosure, in response to a target virtual address space for data including a first virtual address space mapped to a host-side cache 320, first data corresponding to the first virtual address space can be accessed directly from the host-side cache 320 at a first byte granularity. One or more portions of the data have their virtual address spaces mapped to the host-side cache 320, for example... Figure 7 The mapping between segment 3 703 and host-side cache 320 shown here can indicate that the data in one or more segments is frequently accessed or used, with a high "hot" or "cold" status. This data can be cached in host-side cache 320, allowing host 110 to access it faster. As shown at 710, access to hot data in host-side cache 320 can be byte-level. Accesses falling into host-side cache 320 are treated the same as normal direct memory access, byte-level from the application perspective, and page-level eviction occurs only when data needs to be evicted. Furthermore, as... Figure 7 As shown at 740, data exchange between the host-side cache 320 and the storage medium 340 in the storage device can be via the PCIe protocol and can be at the page granularity.

[0081] According to embodiments of this disclosure, in response to a target virtual address space for data including a second virtual address space mapped to cache portion 640, second data corresponding to the second virtual address space can be accessed from cache portion 640 via the PCIe protocol at a second byte granularity. The virtual address space of one or more portions of the data is mapped to cache portion 640, for example, as... Figure 7 The mapping between segment 2 702 and cache portion 640 shown in the diagram can mean that the data in one or more of these segments is data that is accessed from time to time or used occasionally, and has a high degree of hotness / coldness. The data in one or more of these segments can be cached in cache portion 640 in the storage device, allowing host 110 to access this less frequently accessed data at a faster speed via the PCIe protocol.

[0082] In some embodiments, the granularity of accessing cache portion 640 can correspond to or be consistent with the granularity of interaction with the CPU L3 cache, such as a 64-byte access granularity. Since the CPU L3 cache line size is 64 bytes, this granularity does not cause read / write amplification issues when exchanging data with the SSD. As shown at 720, access to cache portion 640 can be byte-level, and more specifically, can be a granularity corresponding to, for example, 64 bytes, the granularity of interaction with the CPU L3 cache.

[0083] Additionally, in some embodiments, the cache portion 640 can be configured to merge multiple byte-level I / O requests from application 310 into a single page-level I / O request, and cache corresponding data from storage medium 340 at the page level based on this single page-level I / O request. This reduces the number of read / write operations on storage medium 340, avoiding latency caused by repeated read / write operations. Figure 7 As shown at 760, the data exchange between the cache portion 640 and the storage medium 340 can be page-granular.

[0084] According to embodiments of this disclosure, in response to the target virtual address space of data including a third virtual address space mapped to storage medium 340, third data corresponding to the third virtual address space can be accessed from storage medium 340 at a third-byte granularity via the PCIe protocol by utilizing the switching section 650 to transfer third data from storage medium 340. The virtual address space of one or more portions of the data is mapped to the storage medium rather than to caches on either side, for example... Figure 7 The mapping between segment 1 701 and storage medium 340 shown can imply that the data in one or more segments is infrequently accessed or rarely used, and has a low hot / cold status. This data in one or more segments can be stored in storage medium 340 within storage device 120 without caching on either side, and can only be read via swap section 650 when needed. Furthermore, as... Figure 7 As shown at point 750, the transfer between the swap section and the storage medium can be at the page granularity.

[0085] By way of example rather than limitation, at system startup, there is no distinction between hot and cold data. All data is exchanged with the SSD at the page level, with only the host-side cache 320. After the application 310 has been running for a period of time, the host-side cache 320 is exhausted, and the operating system also records the corresponding page access frequency. At this time, the relatively cold data is mapped to the cache portion 640 of the SSD, and this part of the data will also be evicted from the host-side cache 320.

[0086] Assuming the size of the host-side cache 320 used to cache SSD data on the host 110 is x, and the size of the SSD cache portion 640 is y, the data of size x with the highest access frequency is cached in the host-side cache 320, and the data of size y with the second highest access frequency is cached in the SSD cache portion 640. The remaining memory of the SSD can be used as the swap portion 650 to provide the host 110 with a byte-level memory access interface.

[0087] When the physical memory corresponding to the virtual memory address of the data is located in the host cache 320, the memory access is no different from a normal memory access. The host 110 uses a combination of page counting and the Least Recently Used (LRU) strategy for cache replacement. When the physical memory corresponding to the virtual memory address of the data is located in the SSD cache portion 640, the memory access can be swapped into the CPU cache in 64-byte granularity, and flushing only occurs when the data is evicted from the SSD cache portion 640. When the memory access misses either of these two memory segments, the SSD internally pulls the data to the swap portion 650 and then completes the data read / write operation.

[0088] Figure 8 A schematic diagram illustrates a policy configuration 800 in a cache management process according to an embodiment of the present disclosure. This is for ease of illustration and explanation. Figure 8 The example illustrates three segments: cold data, sub-hot data, and hot data. It should be understood that this is merely exemplary and not limiting; more or fewer segments of different numbers or types are possible, and the embodiments of this disclosure are not limited thereto.

[0089] like Figure 8 As shown, at 810, a Least Recently Used (LRU) policy can be configured between hot data and host-side cache 320. The LRU policy is a cache eviction strategy that determines data validity based on its most recent usage time, considering recently used data as useful and data that hasn't been used in a long time as useless. When the cache space is full and data needs to be evicted, the LRU policy selects the least recently accessed data for eviction.

[0090] At address 820, a write-back policy can be configured between the less frequently accessed data and the cache portion 640, and multi-way set-associative management can be implemented. A write-back policy is a cache replacement strategy that replaces infrequently accessed data in the cache instead of immediately writing it to disk (i.e., the storage medium). When the cache is full, some data is selected for replacement to free up space for new data. Write-back policies typically use algorithms such as FIFO to select which data to replace. Furthermore, multi-way set-associative management is a cache management strategy used to improve the performance and efficiency of the storage system. In this strategy, multiple cache blocks are organized into different groups, and each group has its own direct mapping table.

[0091] At address 830, a write-through policy can be configured between cold data and the switching section 650. When data in the cache is modified, the write-through policy writes the data to both the cache and the disk simultaneously. This ensures that even if the cache fails or crashes, the data remains accessible on the disk, guaranteeing no data loss. Furthermore, data access with the storage medium 340 can be configured with in-disk processing address mapping, as shown at address 840.

[0092] The cache management scheme according to embodiments of this disclosure can provide dynamic and customized memory access strategies for different data. Such flexible mapping and collaborative cache management can enrich the system's memory access interface, enabling byte-level access and thus simplifying data operations, such as those of applications. Furthermore, this storage management scheme can reduce the transmission pressure within the system, providing a more efficient and flexible customized storage solution.

[0093] Figure 9 An apparatus 900 for cache management according to some embodiments of the present disclosure is illustrated. The cache management apparatus 900 according to embodiments of the present disclosure is applied to a storage system including a host and a storage device, the host running an application and including a host-side cache, and the storage device including a device-side cache and a storage medium. Figure 9 As shown, the cache management device 900 includes a mapping module 910, an acquisition module 920, and an access module 930.

[0094] According to embodiments of this disclosure, mapping module 910 is configured to map the virtual address space of the data to the host-side cache, the device-side cache, and the storage medium, respectively, based on the data access frequency. Acquisition module 920 is configured to acquire the target virtual address space of target data within the data based on byte-level input / output I / O requests from the application. Furthermore, access module 930 is configured to access the target data from the host-side cache, the device-side cache, or the storage medium at the byte-level based on the target virtual address space. It should be understood that, for purposes of illustration and ease of explanation, Figure 9 The diagram only shows the apparatus 900 including the mapping module 910, the acquisition module 920, and the access module 930. However, the apparatus 900 may also include other different modules, such as a partitioning module, a determination module, a merging module, and a caching module. These modules will be described in further detail below.

[0095] In some embodiments, host-side cache, device-side cache, and storage media can be managed by the host. In this way, storage devices (device-side) can be exposed to the host (host-side), in other words, the host can be aware of the devices, enabling them to work together without causing, for example, the same data to be cached multiple times, resulting in wasted cache space.

[0096] In some embodiments, the cache management apparatus 900 may further include a partitioning module and a determination module. The partitioning module is configured to divide data into multiple parts of a predetermined unit size, and the determination module is configured to determine the access frequency for each of the multiple parts of the data. In this way, the access frequency is determined for each part of the predetermined unit size, and then customized cache management is performed on each part based on the access frequency of each part.

[0097] In some embodiments, data is written to a storage device, and the determining module can be configured to determine the location where each of a plurality of parts of the data is to be written based on I / O requests for the data, and to determine the frequency at which the determined location was accessed in the previous time step as the access frequency. In this way, even if the data is new data to be written to the storage device, the access frequency of each part can be estimated based on the historical access frequency of the location where each part is to be written to the storage device.

[0098] In some embodiments, data has been written to a storage device, and the determining module can be configured to determine the frequency at which each of the multiple portions of the data was accessed in the previous time step as the access frequency. In this way, with data already written to the storage device, these portions can be redistributed according to their historical access frequencies, enabling dynamic cache management in the storage system and thereby improving the access performance of the storage system.

[0099] In some embodiments, the device-side cache may include a cache portion and a swap portion, and the mapping module 910 may be configured to: map the virtual address space of data accessed more frequently than a first frequency threshold to the host-side cache; map the virtual address space of data accessed less frequently than the first frequency threshold but more frequently than a second frequency threshold to the cache portion of the device-side cache; and map the virtual address space of data accessed less frequently than the second frequency threshold to the storage medium via the swap portion of the device-side cache, wherein the first frequency threshold is greater than the second frequency threshold. In this way, flexible mapping of virtual memory is performed based on the access frequency of each portion; that is, based on the access frequency of each portion, its virtual address space is mapped to the host-side cache, device-side cache, and storage medium respectively. This data hot / cold separation caching technology stores data with different levels of access frequency in different cache levels, achieving data separation in the cache medium.

[0100] In some embodiments, the access module 930 can be configured to access first data corresponding to the first virtual address space directly from the host cache at a first byte granularity in response to the target virtual address space including a first virtual address space mapped to a host cache. In this manner, the most frequently accessed data can be accessed directly from the host cache at a byte granularity without needing to access the storage device side via the PCIe protocol. As a result, data interaction between the host and device is reduced, while PCIe traffic is decreased.

[0101] In some embodiments, the access module 930 can be configured to access second data corresponding to the second virtual address space from the cache portion via the PCIe protocol at a second byte granularity in response to the target virtual address space including a second virtual address space mapped to the cache portion. In this way, less frequently accessed data can be accessed from the device-side cache on the storage device side via the PCIe protocol at a smaller byte granularity.

[0102] In some embodiments, the access module 930 can be configured to, in response to a target virtual address space including a third virtual address space mapped to the storage medium, access third data corresponding to the third virtual address space from the storage medium at a third-byte granularity via the PCIe protocol by utilizing a switching portion. In this manner, the coldest data can be accessed from the storage medium on the storage device side at a byte-granularity via the PCIe protocol, wherein the device-side cache on the storage device side does not cache the coldest data, but instead transfers the coldest data from the storage medium for access. Since the coldest data does not require frequent access, the interaction with the storage medium does not introduce high latency.

[0103] In some embodiments, the second byte granularity can correspond to the granularity of CPU L3 cache swapping. In this way, less frequently accessed data can be accessed at a smaller byte granularity corresponding to the granularity of CPU L3 cache swapping, avoiding read-write amplification degradation.

[0104] In some embodiments, the cache management apparatus 900 may further include a merging module and a caching module. The merging module is configured to merge multiple byte-granular I / O requests from the application into a single page-granular I / O request, and the caching module is configured to cache corresponding data from the storage medium at a page-granularity based on the single page-granular I / O request. In this way, the number of read and write operations to the storage medium can be reduced, avoiding the latency caused by repeated read and write operations to the storage medium.

[0105] In some embodiments, the host-side cache can be configured to perform cache replacement based on a Least Recently Used (LRU) policy. The cache portion can be configured to perform cache replacement based on a write-back policy and multiplexed group associative management. Furthermore, the switching portion can be configured to perform cache replacement based on a write-through policy.

[0106] As an example of a software functional unit, the mapping module 910 may include code running on a computing instance. The computing instance may include at least one of a physical host (computing device), a virtual machine, or a container. Further, the aforementioned computing instance may be one or more. For example, the mapping module 910 may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code may be distributed within the same region or in different regions. Further, the multiple hosts / virtual machines / containers used to run the code may be distributed within the same availability zone (AZ) or in different AZs, each AZ including one or more geographically proximate data centers. Typically, a region may include multiple AZs.

[0107] Similarly, multiple hosts / virtual machines / containers used to run this code can be distributed within the same Virtual Private Cloud (VPC) or across multiple VPCs. Typically, a VPC is set up within a region. Communication between two VPCs within the same region, as well as between VPCs in different regions, requires a communication gateway to be set up within each VPC to enable interconnection between VPCs.

[0108] As an example of a hardware functional unit, the mapping module 910 may include at least one computing device, such as a server. Alternatively, the mapping module 910 may also be a device implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be implemented using a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0109] The multiple computing devices included in the mapping module 910 can be distributed in the same region or in different regions. Similarly, the multiple computing devices included in the mapping module 910 can be distributed in the same Availability Zone (AZ) or in different AZs. Likewise, the multiple computing devices included in the mapping module 910 can be distributed in the same Virtual Private Cloud (VPC) or in multiple VPCs. These multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0110] It should be noted that, in other embodiments, the mapping module 910 can be used to perform any step in the cache management method according to the embodiments of the present disclosure, the acquisition module 920 can be used to perform any step in the cache management method according to the embodiments of the present disclosure, and the access module 930 can be used to perform any step in the cache management method according to the embodiments of the present disclosure. Furthermore, the above-mentioned partitioning module, determining module, merging module, and caching module can also be used to perform any step in the cache management method according to the embodiments of the present disclosure.

[0111] The steps implemented by the mapping module 910, the acquisition module 920, the access module 930, the partitioning module, the determination module, the merging module, and the caching module can be specified as needed. The mapping module 910, the acquisition module 920, the access module 930, the partitioning module, the determination module, the merging module, and the caching module respectively implement different steps in the cache management method according to the embodiments of this disclosure to realize all the functions of the cache management apparatus 900.

[0112] This disclosure also provides a computing device 1000. Figure 10 A schematic block diagram of an example computing device 1000 that can be used to implement exemplary implementations of this disclosure is shown. Figure 10 As shown, the computing device 1000 includes a bus 1002, a processor 1004, a memory 1006, and a communication interface 1008. The processor 1004, the memory 1006, and the communication interface 1008 communicate with each other via the bus 1002. The computing device 1000 can be a server or a terminal device. It should be understood that this disclosure does not limit the number of processors and memories in the computing device 1000.

[0113] Bus 1002 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 10 The bus 1002 may be represented by a single line, but this does not mean that there is only one bus or one type of bus. The bus 1002 may include a path for transmitting information between various components of the computing device 1000 (e.g., memory 1006, processor 1004, communication interface 1008).

[0114] The processor 1004 may include any one or more processors such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0115] The memory 1006 may include volatile memory, such as random access memory (RAM). The processor 1004 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0116] The memory 1006 stores executable program code, and the processor 1004 executes the executable program code to implement the functions of the aforementioned mapping module 910, acquisition module 920, access module 930, etc., thereby realizing the cache management method according to the embodiments of this disclosure. That is, the memory 1006 stores instructions for executing the cache management method according to the embodiments of this disclosure.

[0117] Alternatively, the memory 1006 stores executable code, which the processor 1004 executes to implement the functions of the aforementioned cache management apparatus 900, thereby implementing the cache management method according to an embodiment of the present disclosure. That is, the memory 1006 stores instructions for executing the cache management method according to an embodiment of the present disclosure.

[0118] The communication interface 1008 uses transceiver modules such as, but not limited to, network interface cards and transceivers to enable communication between the computing device 1000 and other devices or communication networks.

[0119] This disclosure also provides a computing device cluster. Figure 11 A schematic block diagram of an example computing device cluster 1100 that can be used to implement exemplary implementations of the present disclosure is shown. The computing device cluster 1100 includes at least one computing device. The computing device may be a server, such as a central server, an edge server, or a local server in a local data center. In some embodiments, the computing device may also be a terminal device such as a desktop computer, a laptop computer, or a smartphone.

[0120] like Figure 11 As shown, the computing device cluster 1100 includes at least one computing device 1000. The memory 1006 of one or more computing devices 1000 in the computing device cluster 1100 may store the same instructions for performing a cache management method according to embodiments of this disclosure.

[0121] In some possible implementations, the memory 1006 of one or more computing devices 1000 in the computing device cluster 1100 may also store partial instructions for performing the cache management method according to embodiments of the present disclosure. In other words, a combination of one or more computing devices 1000 can jointly execute instructions for performing the cache management method according to embodiments of the present disclosure.

[0122] It should be noted that the memory 1006 in different computing devices 1000 within the computing device cluster 1100 can store different instructions, which are used to execute some functions of the cache management device 900. That is, the instructions stored in the memory 1006 of different computing devices 1000 can implement the functions of one or more modules such as the mapping module 910, the acquisition module 920, and the access module 930.

[0123] In some possible implementations, one or more computing devices in the computing device cluster 1100 can be connected via a network. This network can be a wide area network (WAN) or a local area network (LAN), etc. Figure 12One possible implementation is shown. For example... Figure 12 As shown, two computing devices 1000A and 1000B are connected via a network. Specifically, they are connected to the network through communication interfaces in each computing device. In this possible implementation, the memory 1006 in computing device 1000A stores instructions for executing the functions of the mapping module 910. Simultaneously, the memory 1006 in computing device 1000B stores instructions for executing the functions of the acquisition module 920 and the access module 930.

[0124] Figure 12 The connection method between the computing device cluster 1100 shown may be that, considering that the cache management method provided in this disclosure may be for distributed storage devices, the functions implemented by the acquisition module 920 and the access module 930 are delegated to the computing device 1000B for execution.

[0125] It should be understood that, Figure 12 The functions of computing device 1000A shown can also be performed by multiple computing devices 1000. Similarly, the functions of computing device 1000B can also be performed by multiple computing devices 1000.

[0126] This disclosure also provides another computing device cluster 1100. The connection relationships between the computing devices in this computing device cluster 1100 can be similarly referred to... Figure 12 and Figure 12 The connection method of the computing device cluster 1100. The difference is that the memory 1006 of one or more computing devices 1000 in the computing device cluster 1100 may store the same instructions for executing the cache management method according to the embodiments of this disclosure.

[0127] In some possible implementations, the memory 1006 of one or more computing devices 1000 in the computing device cluster 1100 may also store partial instructions for performing the cache management method according to embodiments of the present disclosure. In other words, a combination of one or more computing devices 1000 can jointly execute instructions for performing the cache management method according to embodiments of the present disclosure.

[0128] This disclosure also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium capable of being stored by a computing device, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct a computing device to perform a cache management method according to embodiments of this disclosure.

[0129] This disclosure also provides a computer program product containing instructions. The computer program product may be a software or program product containing instructions capable of running on a computing device or stored on any usable medium. When the computer program product is run on at least one computing device, it causes the at least one computing device to perform a cache management method according to embodiments of this disclosure.

[0130] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present invention.

Claims

1. A cache management method, characterized in that, The method, applied to a storage system comprising a host and a storage device, wherein the host runs an application and includes a host-side cache, and the storage device includes a device-side cache and a storage medium, comprises: Based on the data access frequency, the virtual address space of the data is mapped to the host-side cache, the device-side cache, and the storage medium, respectively. Based on byte-level input / output I / O requests from the application, obtain the target virtual address space of the target data in the data; and Based on the target virtual address space, the target data is accessed at the byte granularity from the host-side cache, the device-side cache, or the storage medium. The device-side cache includes a cache portion, and accessing the target data from the host-side cache, the device-side cache, or the storage medium at the byte granularity based on the target virtual address space includes: in response to the target virtual address space including a second virtual address space mapped to the cache portion, accessing second data corresponding to the second virtual address space from the cache portion at the second byte granularity via the External Component Interconnect Fast PCIe protocol.

2. The method according to claim 1, characterized in that, The host-side cache, the device-side cache, and the storage medium are managed by the host.

3. The method according to claim 1 or 2, characterized in that, Also includes: The data is divided into multiple parts using predetermined unit sizes; as well as For each of the plurality of portions of the data, the access frequency is determined.

4. The method according to claim 3, characterized in that, The data will be written to the storage device, and determining the access frequency includes: Based on the I / O requests for the data, determine the location where each of the plurality of portions of the data should be written; and The frequency at which the determined position is accessed in the previous time step is defined as the access frequency.

5. The method according to claim 3, characterized in that, The data has been written to the storage device, and determining the access frequency includes: The frequency at which each of the plurality of portions of the data is accessed in the previous time step is determined as the access frequency.

6. The method according to claim 3, characterized in that, The device-side cache further includes a switching component, and maps the virtual address space of the data to the host-side cache, the device-side cache, and the storage medium based on the access frequency of the data, and further includes: Map the portion of the virtual address space of the data that is accessed more frequently than a first frequency threshold to the host-side cache; Map the virtual address space of the data whose access frequency is below the first frequency threshold and above the second frequency threshold to the cached portion of the device-side cache; and The virtual address space of the data whose access frequency is below the second frequency threshold is mapped to the storage medium via the switching portion in the device-side cache. The first frequency threshold is greater than the second frequency threshold.

7. The method according to claim 6, characterized in that, Accessing the target data from the host-side cache, the device-side cache, or the storage medium at the byte granularity, based on the target virtual address space, includes: In response to the target virtual address space including a first virtual address space mapped to the host-side cache, the first data corresponding to the first virtual address space is accessed directly from the host-side cache at a first byte granularity.

8. The method according to claim 6, characterized in that, Accessing the target data from the host-side cache, the device-side cache, or the storage medium at the byte granularity, based on the target virtual address space, includes: In response to the target virtual address space including a third virtual address space mapped to the storage medium, the third data corresponding to the third virtual address space is transferred from the storage medium using the switching portion, and the third data is accessed from the storage medium at a third byte granularity via the PCIe protocol.

9. The method according to claim 1, characterized in that, The granularity of the second byte corresponds to the granularity of the L3 cache exchange in the central processing unit (CPU).

10. The method according to claim 6, characterized in that, The cache portion is configured as follows: Merge multiple byte-level I / O requests from the application into a single page-level I / O request; and Based on the I / O request at the individual page granularity, the corresponding data is cached from the storage medium at the page granularity.

11. The method according to claim 6, characterized in that: The host-side cache is configured to perform cache replacement based on a least recently used strategy; The cache portion is configured to perform cache replacement based on a write-back policy and multi-way set-associative management; and The switching section is configured to perform cache replacement based on a write-through policy.

12. An apparatus for cache management, characterized in that, An apparatus for use in a storage system comprising a host and a storage device, wherein the host runs an application and includes a host-side cache, and the storage device includes a device-side cache and a storage medium, the apparatus comprising: The mapping module is configured to map the virtual address space of the data to the host-side cache, the device-side cache, and the storage medium respectively based on the data access frequency; The acquisition module is configured to acquire the target virtual address space of the target data in the data based on byte-granular input / output I / O requests from the application; and The access module is configured to access the target data from the host-side cache, the device-side cache, or the storage medium at the byte granularity, based on the target virtual address space. The device-side cache includes a cache portion, and the access module is further configured to: in response to the target virtual address space including a second virtual address space mapped to the cache portion, access second data corresponding to the second virtual address space from the cache portion via the external component interconnect fast PCIe protocol at a second byte granularity.

13. A computing device cluster comprising at least one computing device, each computing device including a processor and a memory, wherein the processor of the at least one computing device is configured to execute instructions stored in the memory of the at least one computing device to cause the computing device cluster to perform the method according to any one of claims 1 to 11.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed by a computing device, cause the computing device to perform the method according to any one of claims 1 to 11.

15. A computer program product, characterized in that, The computer program product includes instructions that, when executed by a computing device, cause the computing device to perform the method according to any one of claims 1 to 11.

Images