Method and device for realizing one-line-through data receiving and sending, chip and electronic equipment

Abstract

The application provides a method for receiving and sending one-wire data by using SPI. The receiving method comprises the following steps: configuring an SPI_MOSI pin as a GPIO input or a high impedance state, configuring an SPI_MISO pin as a GPIO input, and detecting an edge interrupt; waiting for receiving the edge interrupt, configuring the SPI_MISO pin as an SPI function after receiving the edge interrupt; configuring a DMA module, comprising: configuring the DMA module to transmit data received by the SPI module to a memory, and starting DMA transmission; configuring the SPI module, comprising: configuring the SPI module as a receiving mode, and starting SPI transmission; waiting for receiving a receiving completion interrupt of the DMA module; and analyzing data received by the SPI module in the memory. The application can occupy less CPU resources, and improve data accuracy.

Description

Technical Field

[0001] This invention relates to the field of signal transmission technology, and in particular to a method, apparatus, chip, electronic device, communication system, and storage medium for implementing one-wire data reception and transmission using SPI. Background Technology

[0002] Single Interface Frame (SIF) is a widely used communication protocol in electric two-wheelers for communication between the controller, lithium battery, and charger. Physically, SIF requires only a single signal wire for data transmission. Transmitted data consists of communication frames, each composed of three parts: a synchronization signal, a main message signal, and a stop signal. The frame format definition can be found in the "Electric Bicycle Communication Protocol Group Standard T / JSEBA 002-2022".

[0003] Currently, the common implementation method for One-Line Communication is to use software timer interrupts combined with GPIO (General-purpose input / output) to receive or send One-Line Communication protocol data. This requires processing GPIO data during each timer interrupt. Taking a timer with a period Ttimer = 200µs as an example, the timing diagram corresponding to the timer interrupt and the signal is as follows: Figure 1 As shown.

[0004] Implementing one-wire communication using timer interrupts and GPIO has the following main problems: Because GPIO status needs to be sampled periodically, there will be a lot of timer interrupts during the transmission process, which will consume a lot of CPU and affect the operation of other tasks in the system.

[0005] Since GPIO state processing and signal conversion are completed in the interrupt function, the system has high real-time requirements. When the CPU load is heavy, if the interrupt cannot be responded to in time, the calculated signal duty cycle may be inaccurate, leading to misjudgment. Summary of the Invention

[0006] In view of this, the present invention provides a method, apparatus, chip, electronic device, communication system and storage medium for implementing one-wire data reception and transmission using SPI (Serial Peripheral Interface), which can reduce the CPU resource consumption and improve data accuracy.

[0007] In a first aspect, the present invention provides a method for receiving one-wire data using SPI, the method comprising: Configure the SPI_MOSI pin as a GPIO input or a high-impedance state, configure the SPI_MISO pin as a GPIO input, and detect edge interrupts; Wait for the edge interrupt generated by GPIO, and after receiving the edge interrupt, configure the SPI_MISO pin to SPI function; Configure the DMA module, including: configuring the DMA module to transfer the data received by the SPI module to memory, and starting the DMA transfer; Configure the SPI module, including: configuring the SPI module to receive mode and starting SPI transmission; Waiting to receive the receive completion interrupt generated by the DMA module; After receiving the received data completion interrupt, the data received by the SPI module in memory is parsed.

[0008] Optionally, configuring the SPI module may also include setting the SPI clock and receiving data on the rising edge of the SPI clock.

[0009] Secondly, the present invention provides a method for implementing one-wire data transmission using SPI, the method comprising: The data to be transmitted via the One-Line Communication Protocol is converted into data to be transmitted by the SPI module and stored in memory; Configure the SPI_MISO pin as a GPIO input and disable interrupts, or configure it to a high-impedance state, and configure the SPI_MOSI pin for SPI function; Configure the DMA module, including: configuring the DMA module to transfer data from memory to the SPI module, and initiating DMA transfer; Configure the SPI module, including: configuring the SPI module to transmit mode and starting SPI transmission; Waiting to receive the transmit completion interrupt generated by the DMA module.

[0010] Optionally, configuring the SPI module may also include setting the SPI clock and transmitting data on the falling edge of the SPI clock.

[0011] Thirdly, the present invention provides an apparatus for receiving one-wire data using SPI, the apparatus comprising: The first SPI pin configuration unit is used to configure the SPI_MOSI pin as a GPIO input or a high-impedance state, configure the SPI_MISO pin as a GPIO input, and detect edge interrupts. An edge interrupt handling unit is used to wait for edge interrupts generated by GPIO, and after receiving the edge interrupt, configure the SPI_MISO pin to SPI function; The first DMA configuration unit is used to configure the DMA module, including: configuring the DMA module to transfer the data received by the SPI module to memory, and starting DMA transfer; The first SPI configuration unit is used to configure the SPI module, including: configuring the SPI module to receive mode and starting SPI transmission; The first interrupt unit is used to wait for the receive completion interrupt generated by the DMA module; The first signal conversion unit is used to parse the data received by the SPI module in memory after receiving the received completion interrupt.

[0012] Fourthly, the present invention provides an apparatus for transmitting one-wire data using SPI, the apparatus comprising: The second signal conversion unit is used to convert the one-wire protocol data to be transmitted into the data to be transmitted by the SPI module and store it in memory; The second SPI pin configuration unit is used to configure the SPI_MISO pin as a GPIO input and disable interrupts, or configure it as a high-impedance state, and configure the SPI_MOSI pin as an SPI function; The second DMA configuration unit is used to configure the DMA module, including: configuring the DMA module to transfer data in memory to the SPI module, and starting DMA transfer; The second SPI configuration unit is used to configure the SPI module, including: configuring the SPI module to transmit mode and starting SPI transmission; The second interrupt unit is used to wait for the transmission completion interrupt generated by the DMA module.

[0013] Fifthly, the present invention provides a chip, the chip comprising: The SPI module has its SPI_MISO pin multiplexed as a GPIO function; DMA module; Memory; A memory and a processor, the memory for storing a computer program and the processor for executing the computer program to implement the method for receiving data using SPI as described in the first aspect, and / or the method for transmitting data using SPI as described in the second aspect.

[0014] In a sixth aspect, the present invention provides an electronic device comprising the chip described in the fifth aspect.

[0015] In a seventh aspect, the present invention provides a one-line communication system, including the electronic device described in the sixth aspect.

[0016] Eighthly, the present invention provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the method for receiving data using SPI as described in the first aspect, and / or the method for transmitting data using SPI as described in the second aspect.

[0017] This invention provides a method, apparatus, chip, electronic device, communication system, and storage medium for implementing one-wire communication data reception and transmission using SPI. The SPI module is responsible for receiving and transmitting one-wire communication protocol data, with the data reception and transmission handled by both the SPI and DMA modules, without consuming CPU resources. During this process, the CPU can be used for other tasks. The SPI module receives and transmits data at a fixed frequency, ensuring uninterrupted reception and transmission, accurate signal waveforms, and eliminating the problem of inaccurate duty cycle. Furthermore, SPI is a high-speed serial bus, and its operating frequency can be set according to accuracy requirements. Attached Figure Description

[0018] Figure 1 The signal timing diagram for implementing one-wire communication using timer schemes in existing technologies; Figure 2 This is a schematic flowchart of a method for receiving data using SPI in one embodiment of the present invention; Figure 3 This is a schematic flowchart of a method for transmitting data using SPI in one embodiment of the present invention; Figure 4 This is a signal timing diagram of a one-wire communication implementation using the SPI scheme in one embodiment of the present invention; Figure 5 This is a schematic diagram of a device for implementing one-wire data reception using SPI in one embodiment of the present invention; Figure 6 This is a schematic diagram of a device for implementing one-wire data transmission using SPI in one embodiment of the present invention; Figure 7 This is a schematic diagram of the chip structure in one embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a one-line communication system according to an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0022] First, this application carefully studies the signal characteristics of the One-Line Communication protocol, utilizes the GPIO level detection function, and combines it with the working principle of SPI (Serial Peripheral Interface) to design a scheme for receiving or transmitting One-Line Communication protocol data using an SPI module. Data is directly transferred via DMA (Direct Memory Access), reducing CPU usage. The scheme is based on chips (including but not limited to MCUs) with an SPI module and the SPI_MISO pin multiplexed as GPIO (General Purpose Input Output). On the hardware side, this scheme only uses two pins: SPI_MISO (data receive pin) and SPI_MOSI (data transmit pin). The two signal lines from these two pins are connected together to connect to the One-Line Communication device at the other end.

[0023] This invention proposes a method for receiving one-wire data using SPI, such as... Figure 2 As shown, the method includes the following steps: S201 configures the SPI_MOSI pin as a GPIO input or a high-impedance state, configures the SPI_MISO pin as a GPIO input, and detects edge interruption. The two signal lines from the SPI_MISO pin and the SPI_MOSI pin are connected together and connected to the one-wire communication device on the other end. S202, waits for an edge interrupt generated by GPIO, and after receiving the edge interrupt, configures the SPI_MISO pin to SPI function; S203, Configure the DMA module, including: configuring the DMA module to transfer the data received by the SPI module to memory, and starting the DMA transfer; S204, Configure the SPI module, including: Configure the SPI module to receive mode and start SPI transmission; S205, waiting for the receive completion interrupt generated by the DMA module; S206, after receiving the receive completion interrupt, parses the data received by the SPI module in memory.

[0024] In step S201, the SPI_MOSI pin is configured as either a GPIO input or a high-impedance state. The high-impedance state is a state in which both the input and output are turned off, which can meet the requirements.

[0025] Further, in step S203, configuring the DMA module includes: configuring the DMA module to transfer data from the SPI module's receive buffer to the software receive buffer (memory), setting the DMA transfer data length, and starting the DMA transfer.

[0026] In step S204, the SPI module is configured, including: configuring the SPI module to receive mode, setting the SPI clock, receiving data on the rising edge of the SPI clock, setting the received data length, and starting SPI transmission.

[0027] The data receiving process is as follows: the SPI module receives data sent by the peer's communication device and transfers it to memory via DMA. Once the SPI data reception is complete and the DMA data transfer is complete, the DMA module generates a reception completion interrupt and informs the CPU to prepare for data processing through a system event.

[0028] In step S206, the CPU parses the data received by the SPI module (also known as sampled data) using the following method: The parsing process includes: Step 1: Enter the synchronization signal analysis stage; Step 2: Read the sampled data and record the number of bits with a value of 0, denoted as a, until the bit value becomes 1. Combined with the SPI clock cycle Tclk, convert a to a low level time Ta. Step 3: Read the sampled data and record the number of bits with a value of 1, denoted as b, until the bit value becomes 0. Combined with the SPI clock period Tclk, convert b into a high level time Tb. Step 4: Remove the read bits from the sampled data; Step 5: Determine whether Ta and Tb satisfy the low and high level durations of the synchronization signal; Step 6: Enter the main message parsing stage; Step 7: Perform the same action as in Step 2, read the sampled data, record the number of bits with a value of 0, and denote it as a, until the bit value becomes 1. Combined with the SPI clock cycle Tclk, convert a to a low level time Ta. Step 8: Determine if Ta is less than the maximum duration of the low level of the data bit; Step 9: Perform the same action as in Step 3, read the sampled data, record the number of bits with a value of 1, denoted as b, until the bit value becomes 0, and convert b to a high level time Tb in combination with the SPI clock period Tclk; Step 10: Perform the same action as in Step 4, removing the read bits from the sampled data; Step 11: According to the duty cycle of the low and high levels of the main message signal data bits, convert Ta and Tb to data bits "0" or data bits "1"; Step 12: Return to step 7 and repeat steps 7-11 until step 8 detects that the Ta value is greater than the maximum low level time of the data bit, then jump to step 13; Step 13: Enter the stop signal analysis stage; Step 14: Read the sampled data and record the number of bits with a value of 0, denoted as a, until the bit value becomes 1. Combine this with the SPI clock period Tclk to convert a into a low-level time Ta; determine whether Ta satisfies the low-level time of the stop signal. Step 15: Read the sampled data and record the number of bits with a value of 1, denoted as b, until the bit value becomes 0. Combined with the SPI clock period Tclk, convert b to a high level time Tb and determine whether Tb satisfies the high level time of the stop signal. Step 16: Stop signal valid, parsing complete.

[0029] The above method is illustrated using the reception of one frame of data as an example. In order to maintain the continuity of the received data, after step S205 is executed, return to step S201, configure the SPI_MISO pin as a GPIO input again, and detect edge interrupts.

[0030] The method for receiving data using SPI provided in this invention utilizes GPIO and SPI to receive data according to the SPI protocol. The GPIO level detection reuses the SPI_MISO pin. Data reception is completed by the SPI module and the DMA module, without consuming CPU resources. During this process, the CPU can be used for other tasks. The SPI module receives data at a fixed frequency, ensuring uninterrupted reception and accurate signal waveforms without inaccurate duty cycles. Furthermore, SPI is a high-speed serial bus, and its operating frequency can be set according to accuracy requirements.

[0031] Another embodiment of the present invention provides a method for implementing one-wire data transmission using SPI, such as... Figure 3 As shown, the method includes the following steps: S301 converts the data to be sent using the One-Line Communication Protocol into data to be sent by the SPI module and stores it in memory; S302, configure the SPI_MISO pin as a GPIO input and disable interrupts, or configure it to a high impedance state, and configure the SPI_MOSI pin as an SPI function. The two signal lines from the SPI_MISO pin and the SPI_MOSI pin are connected together and connected to the one-wire communication device on the other end. S303, Configure the DMA module, including: Configure the DMA module to transfer data from memory to the SPI module, and start the DMA transfer; S304, Configure the SPI module, including: Configure the SPI module to transmit mode and start SPI transmission; S305, waiting for the transmit completion interrupt generated by the DMA module.

[0032] Further, in step S301, the synchronization signal, main message signal and stop signal to be sent are converted into data to be sent by the SPI module bit by bit and stored in memory.

[0033] The conversion process can be carried out in the following steps: Step 1: Enter the synchronization signal conversion stage; Step 2: Combine the SPI clock cycle to convert the low-level time of the signal into the number of bits with a value of 0, and set them into the SPI transmit buffer bit by bit; Step 3: Combine the SPI clock cycle to convert the high-level time of the signal into the number of bits with a value of 1, and set them into the SPI transmit buffer bit by bit; Step 4: After the synchronization signal conversion is completed, the main message signal conversion stage begins; Step 5: Read the data to be sent, and convert the main message signal according to the method in steps 2 and 3 based on whether the data bit is "0" or "1". Step 6: Repeat step 5 until all data to be sent has been converted; Step 7: Enter the stop signal conversion stage; Step 8: Convert the stop signal according to the methods in steps 2 and 3.

[0034] In step S303, the DMA module is configured, including: configuring the DMA module to transfer data from the software transmit buffer (memory) to the SPI module transmit buffer, setting the DMA transfer data length, and starting the DMA transfer.

[0035] In step S304, the SPI module is configured, including: configuring the SPI module to transmit mode, setting the SPI clock, transmitting data on the falling edge of the SPI clock, setting the transmission data length, and starting SPI transmission.

[0036] The data transmission process is as follows: the DMA module transfers the One-Wire Protocol data to be transmitted from memory to the SPI module, and the SPI module then sends the data to the peer One-Wire device. Once the DMA data transfer and SPI data transmission are complete, the DMA module generates a transmission completion interrupt, notifying the CPU of the data transmission completion via a system event.

[0037] The above method is illustrated using the sending of one frame of data as an example. One frame of data is sent at a time. After the data is sent, in order to facilitate the reception of the next frame of data, the SPI_MOSI pin is configured as a GPIO input or a high-impedance state, the SPI_MISO pin is configured as a GPIO input, and edge interruption is detected.

[0038] The method for transmitting one-wire communication data using SPI provided in this embodiment of the invention utilizes SPI to transmit one-wire communication protocol data. Data transmission is completed by the SPI module and the DMA module, without consuming CPU resources. During this process, the CPU can be used for other tasks. The SPI module transmits data at a fixed frequency, ensuring uninterrupted transmission and accurate signal waveforms without the problem of inaccurate duty cycle. Furthermore, SPI is a high-speed serial bus, and its operating frequency can be set according to accuracy requirements.

[0039] Taking an SPI clock set to 5kHz (Tclk=200us) as an example, the timing diagram of the clock waveform and corresponding signals is as follows: Figure 4 As shown, the SPI module receives data on the rising edge of the SPI clock and sends data on the falling edge of the SPI clock.

[0040] On the other hand, embodiments of the present invention provide a device for receiving one-wire data using SPI, such as... Figure 5 As shown, the device includes: The first SPI pin configuration unit 501 is used to configure the SPI_MOSI pin as a GPIO input or a high-impedance state, configure the SPI_MISO pin as a GPIO input, and detect edge interrupts. The edge interrupt handling unit 502 is used to wait for the edge interrupt generated by GPIO, and after receiving the edge interrupt, configure the SPI_MISO pin to SPI function. The first DMA configuration unit 503 is used to configure the DMA module, including: configuring the DMA module to transfer the data received by the SPI module to memory, and starting DMA transfer; The first SPI configuration unit 504 is used to configure the SPI module, including: configuring the SPI module to receive mode and starting SPI transmission; The first interrupt unit 505 is used to wait for the receive completion interrupt generated by the receive DMA module; The first signal conversion unit 506 is used to parse the data received by the SPI module in memory after receiving a receive completion interrupt.

[0041] It is understood that the apparatus for receiving data using SPI provided in the embodiments of the present invention is an embodiment of the method for receiving data using SPI.

[0042] On the other hand, embodiments of the present invention provide a device for transmitting one-wire data using SPI, such as... Figure 6 As shown, the device includes: The second signal conversion unit 601 is used to convert the one-wire protocol data to be transmitted into the data to be transmitted by the SPI module and store it in memory; The second SPI pin configuration unit 602 is used to configure the SPI_MISO pin as a GPIO input and disable interrupts, or configure it to a high impedance state, and configure the SPI_MOSI pin as an SPI function. The second DMA configuration unit 603 is used to configure the DMA module, including: configuring the DMA module to transfer data in memory to the SPI module, and starting DMA transfer; The second SPI configuration unit 604 is used to configure the SPI module, including: configuring the SPI module to transmit mode and starting SPI transmission; The second interrupt unit 605 is used to wait for the transmit completion interrupt generated by the receive DMA module.

[0043] It is understood that the apparatus for transmitting data using SPI provided in the embodiments of the present invention is an embodiment of the method for transmitting data using SPI.

[0044] On the other hand, embodiments of the present invention provide a chip, such as Figure 7 As shown, the chip includes: SPI module 704, the SPI_MISO pin of SPI module 704 can be multiplexed as GPIO function; DMA module 705; 706MB memory; The system includes a processor 701, a memory 702, and a communication bus 703. The processor 701 and the memory 702 communicate with each other via the communication bus 703. The processor 701 can execute computer programs stored in the memory 702 to implement the methods for receiving data using SPI and / or transmitting data using SPI provided in the above embodiments.

[0045] On the other hand, another embodiment of the present invention provides an electronic device including the chip described in the above embodiment.

[0046] On the other hand, another embodiment of the present invention provides a one-line communication system, which includes the electronic equipment described in the above embodiment. For example... Figure 8 As shown, in this one-line communication system, the one-line communication device at the other end can be a battery, charger, or controller. The two signal lines from the SPI_MISO and SPI_MOSI pins of the electronic device are connected together and then connected to the one-line communication device at the other end.

[0047] It should also be noted that the electronic device using the technical solution of this application can be used as the host of a one-line communication system or as a slave device of a one-line communication system, without any special limitations.

[0048] Of course, in a one-line communication system, multiple one-line communication devices are also allowed to adopt the technical solution of this application.

[0049] On the other hand, embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the methods for receiving data using SPI and / or transmitting data using SPI provided in the above embodiments.

[0050] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0051] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for receiving one-wire data using SPI, characterized in that, The method is based on a chip with an SPI module, where the SPI_MISO pin is multiplexed as a GPIO pin. It uses only the SPI_MISO and SPI_MOSI pins. The two signal lines from the SPI_MISO and SPI_MOSI pins are connected together and then connected to a single-line communication device on the other end. The method includes: Configure the SPI_MOSI pin as a GPIO input or a high-impedance state, configure the SPI_MISO pin as a GPIO input, and detect edge interrupts; Wait for the edge interrupt generated by GPIO, and after receiving the edge interrupt, configure the SPI_MISO pin to SPI function; Configure the DMA module, including: configuring the DMA module to transfer the data received by the SPI module to memory, and starting the DMA transfer; Configure the SPI module, including: configuring the SPI module to receive mode and starting SPI transmission; Waiting to receive the receive completion interrupt generated by the DMA module; After receiving the received data completion interrupt, the data received by the SPI module in memory is parsed. The parsing process includes: Step 1: Enter the synchronization signal analysis stage; Step 2: Read the data to be parsed, record the number of bits with a value of 0, until the bit value becomes 1, and combine the SPI clock cycle to convert the number of bits with a value of 0 into the first low level time; Step 3: Read the data to be parsed, record the number of bits with a value of 1 until the bit value becomes 0, and convert the number of bits with a value of 1 into the first high level time in combination with the SPI clock cycle; Step 4: Remove the read bits from the data to be parsed; Step 5: Determine whether the first low level time and the first high level time satisfy the low level and high level time of the synchronization signal. If they satisfy, proceed to step 6. Step 6: Enter the main message parsing stage; Step 7: Read the data to be parsed, record the number of bits with a value of 0, until the bit value becomes 1, and combine it with the SPI clock cycle to convert the number of bits with a value of 0 into the second low level time; Step 8: Determine whether the second low-level time is less than the maximum low-level time of the data bit. If so, proceed to step 9. Step 9: Read the data to be parsed, record the number of bits with a value of 1 until the bit value becomes 0, and convert the number of bits with a value of 1 into the second high level time in combination with the SPI clock cycle; Step 10: Remove the read bits from the data to be parsed; Step 11: According to the duty cycle of the low and high levels of the main message signal data bits, convert the second low level time and the second high level time into data bits "0" or "1"; Step 12: Return to step 7 and repeat steps 7-11 until step 8 detects that the second low-level time is greater than the maximum low-level time of the data bit, then jump to step 13; Step 13: Enter the stop signal analysis stage; Step 14: Read the data to be parsed, record the number of bits with a value of 0 until the bit value becomes 1, and convert the number of bits with a value of 0 into the third low level time in combination with the SPI clock cycle; determine whether the third low level time meets the low level time of the stop signal. If it does, proceed to step 15. Step 15: Read the data to be parsed, record the number of bits with a value of 1 until the bit value becomes 0, and convert the number of bits with a value of 1 into the third high level time in combination with the SPI clock cycle. Determine whether the third high level time meets the high level time of the stop signal. If it does, proceed to step 16. Step 16: Stop signal valid, parsing complete.

2. The method according to claim 1, characterized in that, Configuring the SPI module also includes setting the SPI clock and receiving data on the rising edge of the SPI clock.

3. A method for transmitting data over a single wire using SPI, characterized in that, The method is based on a chip with an SPI module, where the SPI_MISO pin is multiplexed as a GPIO pin. It uses only the SPI_MISO and SPI_MOSI pins. The two signal lines from the SPI_MISO and SPI_MOSI pins are connected together and then connected to a single-line communication device on the other end. The method includes: The data to be transmitted via the One-Line Communication Protocol is converted into data to be transmitted by the SPI module and stored in memory; Configure the SPI_MISO pin as a GPIO input and disable interrupts, or configure it to a high-impedance state, and configure the SPI_MOSI pin for SPI function; Configure the DMA module, including: configuring the DMA module to transfer data from memory to the SPI module, and initiating DMA transfer; Configure the SPI module, including: configuring the SPI module to transmit mode and starting SPI transmission; Waiting to receive the transmit completion interrupt generated by the DMA module; The conversion process of transforming the data to be transmitted using the One-Wire Protocol into the data to be transmitted by the SPI module includes: Step 1: Enter the synchronization signal conversion stage; Step 2: Combine the SPI clock cycle to convert the low-level time of the synchronization signal into the number of bits with a value of 0, and set them into the SPI transmit buffer bit by bit; Step 3: Combine the SPI clock cycle to convert the high-level time of the synchronization signal into the number of bits with a value of 1, and set them into the SPI transmit buffer bit by bit; Step 4: After the synchronization signal conversion is completed, the main message signal conversion stage begins; Step 5: Read the data to be sent. Based on whether the data bit is "0" or "1" and combined with the SPI clock cycle, convert the low-level time of the data bit into the number of bits with a value of 0, and set them into the SPI transmit buffer bit by bit. Also, convert the high-level time of the data bit into the number of bits with a value of 1, and set them into the SPI transmit buffer bit by bit. Step 6: Repeat step 5 until all data to be sent has been converted; Step 7: Enter the stop signal conversion stage; Step 8: Combine the SPI clock cycle to convert the low-level time of the stop signal into the number of bits with a value of 0, and set them into the SPI transmit buffer bit by bit; and convert the high-level time of the stop signal into the number of bits with a value of 1, and set them into the SPI transmit buffer bit by bit.

4. The method according to claim 3, characterized in that, Configuring the SPI module also includes setting the SPI clock and sending data on the falling edge of the SPI clock.

5. A device for receiving one-wire data using SPI, characterized in that, The device is based on a chip with an SPI module, and the SPI_MISO pin is multiplexed as a GPIO function. It only uses the SPI_MISO and SPI_MOSI pins. The two signal lines from the SPI_MISO and SPI_MOSI pins are connected together and then connected to a single-wire device on the other end. The device includes: The first SPI pin configuration unit is used to configure the SPI_MOSI pin as a GPIO input or a high-impedance state, configure the SPI_MISO pin as a GPIO input, and detect edge interrupts. An edge interrupt handling unit is used to wait for edge interrupts generated by GPIO, and after receiving the edge interrupt, configure the SPI_MISO pin to SPI function; The first DMA configuration unit is used to configure the DMA module, including: configuring the DMA module to transfer the data received by the SPI module to memory, and starting DMA transfer; The first SPI configuration unit is used to configure the SPI module, including: configuring the SPI module to receive mode and starting SPI transmission; The first interrupt unit is used to wait for the receive completion interrupt generated by the DMA module; The first signal conversion unit is used to parse the data received by the SPI module in memory after receiving the received completion interrupt. The parsing process includes: Step 1: Enter the synchronization signal analysis stage; Step 2: Read the data to be parsed, record the number of bits with a value of 0, until the bit value becomes 1, and combine the SPI clock cycle to convert the number of bits with a value of 0 into the first low level time; Step 3: Read the data to be parsed, record the number of bits with a value of 1 until the bit value becomes 0, and convert the number of bits with a value of 1 into the first high level time in combination with the SPI clock cycle; Step 4: Remove the read bits from the data to be parsed; Step 5: Determine whether the first low level time and the first high level time satisfy the low level and high level time of the synchronization signal. If they satisfy, proceed to step 6. Step 6: Enter the main message parsing stage; Step 7: Read the data to be parsed, record the number of bits with a value of 0, until the bit value becomes 1, and combine it with the SPI clock cycle to convert the number of bits with a value of 0 into the second low level time; Step 8: Determine whether the second low-level time is less than the maximum low-level time of the data bit. If so, proceed to step 9. Step 9: Read the data to be parsed, record the number of bits with a value of 1 until the bit value becomes 0, and convert the number of bits with a value of 1 into the second high level time in combination with the SPI clock cycle; Step 10: Remove the read bits from the data to be parsed; Step 11: According to the duty cycle of the low and high levels of the main message signal data bits, convert the second low level time and the second high level time into data bits "0" or "1"; Step 12: Return to step 7 and repeat steps 7-11 until step 8 detects that the second low-level time is greater than the maximum low-level time of the data bit, then jump to step 13; Step 13: Enter the stop signal analysis stage; Step 14: Read the data to be parsed, record the number of bits with a value of 0 until the bit value becomes 1, and convert the number of bits with a value of 0 into the third low level time in combination with the SPI clock cycle; determine whether the third low level time meets the low level time of the stop signal. If it does, proceed to step 15. Step 15: Read the data to be parsed, record the number of bits with a value of 1 until the bit value becomes 0, and convert the number of bits with a value of 1 into the third high level time in combination with the SPI clock cycle. Determine whether the third high level time meets the high level time of the stop signal. If it does, proceed to step 16. Step 16: Stop signal valid, parsing complete.

6. A device for transmitting one-wire data using SPI, characterized in that, The device is based on a chip with an SPI module, and the SPI_MISO pin is multiplexed as a GPIO function. It only uses the SPI_MISO and SPI_MOSI pins. The two signal lines from the SPI_MISO and SPI_MOSI pins are connected together and then connected to a single-wire device on the other end. The device includes: The second signal conversion unit is used to convert the one-wire protocol data to be transmitted into the data to be transmitted by the SPI module and store it in memory; The second SPI pin configuration unit is used to configure the SPI_MISO pin as a GPIO input and disable interrupts, or configure it to a high impedance state, and configure the SPI_MOSI pin as an SPI function. The second DMA configuration unit is used to configure the DMA module, including: configuring the DMA module to transfer data in memory to the SPI module, and starting DMA transfer; The second SPI configuration unit is used to configure the SPI module, including: configuring the SPI module to transmit mode and starting SPI transmission; The second interrupt unit is used to wait for the transmission completion interrupt generated by the DMA module; The second signal conversion unit converts the one-wire communication protocol data to be transmitted into the data to be transmitted by the SPI module through a conversion process that includes: Step 1: Enter the synchronization signal conversion stage; Step 2: Combine the SPI clock cycle to convert the low-level time of the synchronization signal into the number of bits with a value of 0, and set them into the SPI transmit buffer bit by bit; Step 3: Combine the SPI clock cycle to convert the high-level time of the synchronization signal into the number of bits with a value of 1, and set them into the SPI transmit buffer bit by bit; Step 4: After the synchronization signal conversion is completed, the main message signal conversion stage begins; Step 5: Read the data to be sent. Based on whether the data bit is "0" or "1" and combined with the SPI clock cycle, convert the low-level time of the data bit into the number of bits with a value of 0, and set them into the SPI transmit buffer bit by bit. Also, convert the high-level time of the data bit into the number of bits with a value of 1, and set them into the SPI transmit buffer bit by bit. Step 6: Repeat step 5 until all data to be sent has been converted; Step 7: Enter the stop signal conversion stage; Step 8: Combine the SPI clock cycle to convert the low-level time of the stop signal into the number of bits with a value of 0, and set them into the SPI transmit buffer bit by bit; and convert the high-level time of the stop signal into the number of bits with a value of 1, and set them into the SPI transmit buffer bit by bit.

7. A chip, characterized in that, The chip includes: The SPI module has its SPI_MISO pin multiplexed as a GPIO function; DMA module; Memory; A memory and a processor, the memory for storing a computer program and the processor for executing the computer program to implement the method for receiving data using SPI as described in claim 1 or 2, and / or the method for transmitting data using SPI as described in claim 3 or 4.

8. An electronic device, characterized in that, The electronic device includes the chip as described in claim 7.

9. A one-line communication system, characterized in that, Including the electronic device as described in claim 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method for receiving data using SPI as described in claim 1 or 2, and / or the method for transmitting data using SPI as described in claim 3 or 4.

Images