Liquid crystal display and picture clearing method thereof

Abstract

A liquid crystal display includes a display panel and a driving unit. The display panel includes a plurality of reset areas corresponding to a plurality of pictures, respectively. A first voltage difference between a column voltage and a row voltage corresponding to a reset area and a second voltage difference between another column voltage and another row voltage corresponding to another reset area are provided. The second voltage difference reaches a second maximum voltage difference value with a delay time compared to a time for the first voltage difference to reach a first maximum voltage difference value, so as to clear the pictures. Thus, the rush current is suppressed. The disclosure also relates to a related picture clearing method of the liquid crystal display.

Description

Technical Field

[0001] This invention relates to a liquid crystal display and a method for clearing the screen thereon, and more particularly to a cholesterol liquid crystal display and a method for clearing the screen thereon that can reduce surge current. Background Technology

[0002] Driven by the pursuit of convenience, diverse display technologies and devices have been developed, such as Cholesteric Liquid Crystal Displays (LCDs), commonly used in electronic paper and electronic signage. When an LCD clears its image, the power supply system outputs its maximum voltage. However, this output voltage may generate excessive inrush current due to a large load, causing power supply system malfunctions or preventing the LCD image from being completely cleared.

[0003] Therefore, how to develop a liquid crystal display and its screen clearing method that can suppress surge current or reduce the energy of surge current so that the power supply system and the liquid crystal display screen are not affected by surge current has become an important issue in the market today. Summary of the Invention

[0004] This invention provides a liquid crystal display and a method for clearing the screen thereon. The display panel includes multiple reset areas, each of which displays a multiple screen. A first voltage difference exists between a column voltage and a row voltage corresponding to one reset area, and a second voltage difference exists between another column voltage and another row voltage corresponding to another reset area. The time for the second voltage difference to reach a second maximum voltage difference value is delayed compared to the time for the first voltage difference to reach a first maximum voltage difference value, so as to suppress surge current while clearing the screen of the liquid crystal display.

[0005] According to one embodiment of the present invention, a liquid crystal display is provided, comprising a display panel and a driving unit. The display panel includes a plurality of reset areas, each corresponding to displaying a plurality of images. The driving unit is used to output a plurality of column voltages and a plurality of row voltages, the column voltages corresponding to the row voltages to drive the reset areas respectively. A first voltage difference exists between a column voltage and a row voltage corresponding to one reset area, and a second voltage difference exists between another column voltage and another row voltage corresponding to another reset area. The time for the second voltage difference to reach a second maximum voltage difference value is delayed compared to the time for the first voltage difference to reach a first maximum voltage difference value, thereby clearing the image.

[0006] In the embodiments of the liquid crystal display according to the foregoing implementation, at least one of the first maximum voltage difference value and the second maximum voltage difference value may be the vertical alignment voltage.

[0007] In the embodiment of the liquid crystal display according to the foregoing implementation, the number of reset areas can be at least four. The first voltage difference, second voltage difference, third voltage difference and fourth voltage difference between the four column voltages and four row voltages corresponding to the four reset areas are sequentially achieved with a delay time to reach the first maximum voltage difference value, the second maximum voltage difference value, the third maximum voltage difference value and the fourth maximum voltage difference value, so as to clear the screen.

[0008] In the embodiment of the liquid crystal display according to the foregoing implementation, the image corresponding to the reset area can be cleared by the first maximum pressure difference value before the second maximum pressure difference value is reached.

[0009] In the embodiment of the liquid crystal display according to the foregoing embodiments, the first maximum voltage difference value is the difference between the first maximum column voltage value and the first maximum row voltage value.

[0010] In the embodiment of the liquid crystal display according to the foregoing embodiments, the first pressure difference can reach a first maximum pressure difference value after passing through at least one first-step pressure difference value, and the second pressure difference can reach a second maximum pressure difference value after passing through at least one second-step pressure difference value.

[0011] According to another embodiment of the present invention, a screen clearing method for a liquid crystal display is provided, comprising: configuring the display panel of the liquid crystal display as a plurality of reset areas, wherein the reset areas respectively correspond to displaying a plurality of images, and a plurality of column voltages are respectively matched with a plurality of row voltages to drive the reset areas; forming a first voltage difference between a column voltage and a row voltage corresponding to a reset area, and the first voltage difference reaches a first maximum voltage difference value; forming a second voltage difference between another column voltage and another row voltage corresponding to another reset area, and the second voltage difference reaches a second maximum voltage difference value, wherein the time to reach the second maximum voltage difference value is delayed compared to the time to reach the first maximum voltage difference value; and clearing the image by the first maximum voltage difference value and the second maximum voltage difference value.

[0012] In an embodiment of the liquid crystal display screen clearing method according to the foregoing embodiments, it may further include: forming a third voltage difference between a column voltage and a row voltage corresponding to a reset area, and the time for the third voltage difference to reach a third maximum voltage difference value has another delay time compared to the time for reaching a second maximum voltage difference value.

[0013] In an embodiment of the liquid crystal display screen clearing method according to the foregoing embodiments, it may further include: clearing a screen corresponding to a reset area using a first maximum pressure difference value, before the second maximum pressure difference value is reached; and clearing another screen corresponding to another reset area.

[0014] In an embodiment of the liquid crystal display screen clearing method according to the foregoing embodiments, the first pressure difference reaching a first maximum pressure difference value can be periodically executed multiple times, and the second pressure difference reaching a second maximum pressure difference value can be periodically executed multiple times.

[0015] According to another embodiment of the present invention, a screen clearing method for a liquid crystal display is provided, comprising: configuring the display panel of the liquid crystal display as a plurality of reset areas, wherein each reset area corresponds to displaying a plurality of images, and a plurality of column voltages are correspondingly matched with a plurality of row voltages to drive the reset areas respectively; forming a first voltage difference between a column voltage and a row voltage corresponding to a reset area, and reaching at least one first-step voltage difference value before the first voltage difference reaches a first maximum voltage difference value; forming a second voltage difference between another column voltage and another row voltage corresponding to another reset area, and reaching a second maximum voltage difference value, wherein the time to reach the second maximum voltage difference value is delayed compared to the time to reach the first maximum voltage difference value, and reaching at least one second-step voltage difference value before the second voltage difference reaches the second maximum voltage difference value; and clearing the image using the first maximum voltage difference value and the second maximum voltage difference value.

[0016] In an embodiment of the liquid crystal display screen clearing method according to the foregoing embodiments, at least one first step voltage difference value is the difference between at least one first column step voltage value and at least one first row step voltage value, and the number of steps of at least one first column step voltage value and the number of steps of at least one first row step voltage value may be the same or different. Attached Figure Description

[0017] Figure 1A A schematic diagram illustrating a cholesterol liquid crystal display according to a first embodiment of the present invention;

[0018] Figure 1B A schematic diagram illustrating the column voltage and row voltage of a partial reset region of a cholesterol liquid crystal display according to the first embodiment;

[0019] Figure 1C A schematic diagram illustrating the column voltage of the cholesterol liquid crystal display of the first embodiment is shown;

[0020] Figure 1D A flowchart illustrating the screen clearing method of a cholesterol liquid crystal display according to the first embodiment is shown;

[0021] Figure 2A A schematic diagram illustrating the column voltage and row voltage of a partial reset region of a cholesterol liquid crystal display according to a second embodiment of the present invention;

[0022] Figure 2B A schematic diagram illustrating the column voltage of the cholesterol liquid crystal display according to the second embodiment is shown;

[0023] Figure 2C A flowchart illustrating the screen clearing method of a cholesterol liquid crystal display according to the second embodiment is shown;

[0024] Figure 3A A schematic diagram illustrating the column voltage and row voltage of a cholesterol liquid crystal display according to a third embodiment of the present invention is shown.

[0025] Figure 3B A schematic diagram illustrating another column voltage and row voltage of the cholesterol liquid crystal display according to the third embodiment;

[0026] Figure 3C A flowchart illustrating the screen clearing method of a cholesterol liquid crystal display according to the third embodiment is shown;

[0027] Figure 4A A schematic diagram illustrating the column voltage and row voltage of a partial reset region of a cholesterol liquid crystal display according to a fourth embodiment of the present invention;

[0028] Figure 4B A schematic diagram illustrating the column voltage of the cholesterol liquid crystal display according to the fourth embodiment; and

[0029] Figure 4C A flowchart illustrating the screen clearing method of a cholesterol liquid crystal display according to the fourth embodiment is shown.

[0030] The reference numerals in the attached figures are explained as follows:

[0031] 10: Cholesterol LCD Monitor

[0032] 11: First Reset Zone

[0033] 12: Second Reset Area

[0034] 13: Third Reset Area

[0035] 14: Fourth Reset Area

[0036] 15: Display panel

[0037] 17: Train drive circuit

[0038] 18: Line drive circuit

[0039] 19: Drive Unit

[0040] 100, 200, 300, 400: Screen Clearing Methods

[0041] 110, 141, 142, 143, 144, 180, 210, 241, 242, 243, 244, 261, 262, 263, 264, 280, 321, 341, 380, 410, 421, 422, 423, 424, 441, 442, 443, 444, 480: Steps

[0042] td: Delay time

[0043] tm: Duration of maximum differential pressure

[0044] Vc1, Vc2, Vc3, Vc4: Column voltages

[0045] Vmc1: First maximum column voltage value

[0046] Vmc2: Second maximum column voltage value

[0047] Vmc3: Third maximum column voltage value

[0048] Vmc4: Fourth maximum column voltage value

[0049] Vmr1: First maximum row voltage value

[0050] Vmr2: Second maximum row voltage value

[0051] Vr1, Vr2: Row voltage

[0052] Vref: Reference voltage value

[0053] Vsc1: First column step voltage value

[0054] Vsc2: Second column step voltage value

[0055] Vsc3: Third column step voltage value

[0056] Vsc4: Fourth column step voltage value

[0057] Vsr1: Step voltage value in the first row

[0058] Vsr2: Step voltage value in the second row Detailed Implementation

[0059] Several embodiments of the present invention will now be described with reference to the accompanying drawings. For clarity, many practical details will be set forth in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, these practical details are not essential in the embodiments of the present invention. Furthermore, for the sake of simplicity in the drawings, some conventional structures and elements will be illustrated in a simple schematic manner; and repeated elements may be denoted by the same reference numerals.

[0060] Furthermore, the terms "first" and "second" are used only to describe different components and do not restrict the components themselves. Therefore, the first component can also be referred to as the second component. Moreover, the combination of components in this article is not a combination that is generally known, conventional, or customary in this field. Whether the components themselves are customary cannot be used to determine whether their combination relationship is easily completed by someone with ordinary knowledge in the technical field.

[0061] Please refer to Figure 1AThe illustration shows a schematic diagram of a cholesteric liquid crystal display according to a first embodiment of the present invention. The liquid crystal display described in the present invention may be, for example but is not limited to, a cholesteric liquid crystal display 10, which includes a display panel 15 and a driving unit 19. The display panel 15 includes a plurality of reset areas, such as a first reset area 11 and a second reset area 12. Each of the first reset area 11 and the second reset area 12 includes a plurality of pixel matrices to respectively display a plurality of images.

[0062] Please refer to the following: Figure 1B The diagram illustrates the column voltage and row voltage of a partial reset area of ​​a cholesterol liquid crystal display according to the first embodiment. The driving unit 19 is used to output the column voltage (column driving voltage) Vc1, Vc2 and the row voltage (row driving voltage) Vr1, Vr2 of the first reset area 11 and the second reset area 12. The column voltage Vc1 drives the first reset area 11 through the column driving line 17 and the row voltage Vr1 drives the second reset area 12 through the column driving line 17 and the row voltage Vr2 drives the second reset area 12 through the row driving line 18. A first voltage difference (|Vc1-Vr1|) exists between the column voltage Vc1 and the row voltage Vr1 corresponding to the first reset area 11, and a second voltage difference (|Vc2-Vr2|) exists between the column voltage Vc2 and the row voltage Vr2 corresponding to the second reset area 12. The time for the second voltage difference to reach the second maximum voltage difference value is delayed by a time td compared to the time for the first voltage difference to reach the first maximum voltage difference value, and the maximum voltage difference durations tm of the first and second maximum voltage difference values ​​partially overlap, which are used to clear the images corresponding to the first reset area 11 and the second reset area 12, respectively. In this way, the image corresponding to the second reset area 12 is cleared within a very short time after the image corresponding to the first reset area 11 is cleared. Inrush current is suppressed through time-division and zone-based driving, which helps to smoothly clear the image, ensure normal image display, and enable the cholesteric liquid crystal display 10 to operate normally. Furthermore, since no additional components are required, the requirement for low cost can be met.

[0063] Specifically, at least one of the first and second maximum voltage difference values ​​can be a homeotropic voltage. This effectively clears the image corresponding to the reset area. In the first embodiment, both the first and second maximum voltage difference values ​​are homeotropic voltages. According to other embodiments of the invention, each maximum voltage difference value can be greater than, less than, or equal to the homeotropic voltage, and with an appropriate maximum voltage difference duration tm, the image corresponding to the reset area can be cleared.

[0064] The first maximum voltage difference is the difference between the first maximum column voltage value Vmc1 and the first maximum row voltage value Vmr1 at the same time point. The first maximum column voltage value Vmc1 and the first maximum row voltage value Vmr1 may have opposite signs relative to the reference voltage value Vref (e.g., 0 volt). The second maximum voltage difference is the difference between the second maximum column voltage value Vmc2 and the second maximum row voltage value Vmr2 at the same time point, and the second maximum column voltage value Vmc2 and the second maximum row voltage value Vmr2 may have opposite signs relative to the reference voltage value Vref. Furthermore, the reference voltage value Vref for column voltage Vc1 and the reference voltage value Vref for row voltage Vr1 may be the same (e.g., 0 volt) or different. Moreover, the absolute value of the difference between the first maximum column voltage value Vmc1 and the reference voltage value Vref may be the same or different from the absolute value of the difference between the first maximum row voltage value Vmr1 and the reference voltage value Vref. The absolute value of the difference between each of the first maximum column voltage value Vmc1, the first maximum row voltage value Vmr1, the second maximum column voltage value Vmc2, and the second maximum row voltage value Vmr2 and the reference voltage value Vref is half of the vertical alignment voltage. This facilitates the design of the drive voltage. In the first embodiment, the column voltage Vc1 and the row voltage Vr1 are opposite waveforms, the column voltage Vc2 and the row voltage Vr2 are opposite waveforms, the waveforms of the column voltages Vc1 and Vc2 are identical, and the waveform of the column voltage Vc2 has a delay time td relative to the waveform of the column voltage Vc1.

[0065] Please refer to the above as well. Figure 1C The schematic diagram illustrating the column voltage of the cholesteric liquid crystal display of the first embodiment shows that, specifically, the display panel 15 further includes a third reset area 13 and a fourth reset area 14, and the number and arrangement of the reset areas according to the present invention are not limited to those disclosed in the drawings. Each of the third reset area 13 and the fourth reset area 14 includes a plurality of pixel matrices and displays a plurality of images respectively. Thus, the display panel according to the present invention can include at least four reset areas, and the same or different (independent) delay time td can be set in the power timing of each reset area of ​​arbitrary size, which is the reset section delay time, to achieve an asynchronous time-sharing power-on mode, thereby distributing the power timing of driving the display panel 15, avoiding the generation of surge currents that the cholesteric liquid crystal display 10 cannot withstand due to driving too large a load, resulting in power supply errors in the control system or incomplete clearing and / or abnormal display of the display panel 15.

[0066] The drive unit 19 is further used to output column voltages Vc3 and Vc4 and two row voltages, wherein column voltage Vc3 and one row voltage drive the third reset area 13, and column voltage Vc4 and the other row voltage drive the fourth reset area 14. A third voltage difference exists between the column voltage Vc3 and the row voltage corresponding to the third reset area 13, and a fourth voltage difference exists between the column voltage Vc4 and the row voltage corresponding to the fourth reset area 14. The time for the third voltage difference to reach the third maximum voltage difference value is delayed by a time td compared to the time for the second voltage difference to reach the second maximum voltage difference value, and the time for the fourth voltage difference to reach the fourth maximum voltage difference value is delayed by a time td compared to the time for the third voltage difference to reach the third maximum voltage difference value. Furthermore, the first, second, third, and fourth pressure differentials sequentially reach the first, second, third, and fourth maximum pressure differential values ​​with the same or different delay times td, and each of these values ​​is maintained during an active reset phase of maximum pressure differential duration tm to clear the screen of the cholesterol liquid crystal display 10. Other details of the third reset area 13 and the fourth reset area 14 can be found in the descriptions of the first reset area 11 and the second reset area 12, and will not be elaborated further here.

[0067] Please refer to the following: Figure 1D The flowchart illustrates a screen clearing method for a cholesterol liquid crystal display according to a first embodiment. The screen clearing method 100 of the cholesterol liquid crystal display 10 specifically includes steps 110, 141, 142, 143, 144, and 180.

[0068] Step 110 includes configuring the display panel 15 of the cholesterol liquid crystal display 10 as a first reset area 11, a second reset area 12, a third reset area 13 and a fourth reset area 14.

[0069] Step 141 includes forming a first voltage difference between the column voltage Vc1 and the row voltage Vr1 corresponding to the first reset area 11, and causing the first voltage difference to reach a first maximum voltage difference value.

[0070] Step 142 includes forming a second voltage difference between the column voltage Vc2 and the row voltage Vr2 corresponding to the second reset region 12, and causing the second voltage difference to reach a second maximum voltage difference value, wherein the time to reach the first second maximum voltage difference value is delayed by a time td compared to the time to reach the first first maximum voltage difference value.

[0071] Step 143 includes forming a third voltage difference between the column voltage Vc3 and the row voltage corresponding to the third reset region 13, and causing the third voltage difference to reach a third maximum voltage difference value, wherein the time to reach the first third maximum voltage difference value is delayed by a time td compared to the time to reach the first second maximum voltage difference value.

[0072] Step 144 includes forming a fourth voltage difference between the column voltage Vc4 and the row voltage corresponding to the fourth reset region 14, and causing the fourth voltage difference to reach a fourth maximum voltage difference value, wherein the time to reach the first fourth maximum voltage difference value is delayed by a time td compared to the time to reach the first third maximum voltage difference value.

[0073] Furthermore, please refer to Figure 1B and Figure 1C The first pressure difference reaching a first maximum pressure difference value, the second pressure difference reaching a second maximum pressure difference value, the third pressure difference reaching a third maximum pressure difference value, and the fourth pressure difference reaching a fourth maximum pressure difference value can each be periodically performed multiple times. This helps to ensure complete screen clearing and reduce inrush current. In the first embodiment, the first occurrence of the fourth maximum pressure difference value is earlier than the second occurrence of the first maximum pressure difference value, and the invention is not limited thereto.

[0074] In the repeated achievement of the first, second, third, and fourth maximum voltage difference values, the first maximum column voltage value Vmc1, the first maximum row voltage value Vmr1, the second maximum column voltage value Vmc2, the second maximum row voltage value Vmr2, the third maximum column voltage value Vmc3, the third maximum row voltage value, the fourth maximum column voltage value Vmc4, and the fourth maximum row voltage value alternate between positive and negative signs relative to the reference voltage value Vref. This facilitates complete image clearing and reduces the complexity of circuit design.

[0075] Step 180 includes clearing the screen of the cholesterol liquid crystal display 10 through a first maximum pressure difference value, a second maximum pressure difference value, a third maximum pressure difference value, and a fourth maximum pressure difference value.

[0076] Figure 2A A schematic diagram illustrating the column voltage and row voltage of a partial reset region of a cholesterol liquid crystal display according to a second embodiment of the present invention is shown. Figure 2B A schematic diagram illustrating the column voltage of the cholesterol liquid crystal display according to the second embodiment is shown. Figure 2C A flowchart illustrating the screen clearing method for a cholesterol-based liquid crystal display according to the second embodiment is provided. Please refer to... Figures 2A to 2C The screen clearing method 200 for a cholesterol liquid crystal display in the second embodiment specifically includes steps 210, 241, 261, 242, 262, 243, 263, 244, 264, and 280.

[0077] Step 210 includes configuring the display panel of the cholesterol liquid crystal display as a first reset area, a second reset area, a third reset area, and a fourth reset area. Further details regarding the first reset area, second reset area, third reset area, and fourth reset area can be found in the aforementioned first embodiment and will not be elaborated upon here.

[0078] Step 241 involves forming a first voltage difference between the column voltage Vc1 and the row voltage Vr1 corresponding to the first reset area, causing the first voltage difference to reach a first maximum voltage difference value and being periodically executed multiple times. Step 261 involves clearing the screen corresponding to the first reset area.

[0079] Step 242 involves forming a second voltage difference between the column voltage Vc2 and the row voltage Vr2 corresponding to the second reset area, causing the second voltage difference to reach a second maximum voltage difference value. The time to reach the first maximum voltage difference value is delayed by a time td compared to the time to reach the first maximum voltage difference value, and the process of the second voltage difference reaching the second maximum voltage difference value is performed periodically multiple times. Step 262 involves clearing the screen corresponding to the second reset area.

[0080] In other words, in the second embodiment, the clearing of the screen corresponding to the first reset zone by the first maximum voltage difference value (step 261) occurs earlier than the second maximum voltage difference value is reached in the first step (step 242). This allows the drive display panel design to be divided into multiple reset zones or at least four reset zones, with small blocks for clearing. This enables the power supply to clear only one small block of the panel at a time, avoiding excessive surge current caused by driving an excessively large load at once, which could lead to power supply errors in the control system or incomplete clearing of the display panel and / or display abnormalities. Furthermore, the delay time td in screen clearing method 200 is greater than the delay time td in screen clearing method 100.

[0081] Step 243 involves forming a third voltage difference between the column voltage Vc3 and the row voltage corresponding to the third reset area, causing the third voltage difference to reach a third maximum voltage difference value. The time to reach the first third maximum voltage difference value is delayed by a time td compared to the time to reach the first second maximum voltage difference value, and the process of reaching the third maximum voltage difference value is performed periodically multiple times. Step 263 involves clearing the screen corresponding to the third reset area.

[0082] Step 244 involves forming a fourth voltage difference between the column voltage Vc4 and the row voltage corresponding to the fourth reset area, causing the fourth voltage difference to reach a fourth maximum voltage difference value. The time to reach the first fourth maximum voltage difference value is delayed by a time td compared to the time to reach the first third maximum voltage difference value, and the process of the fourth voltage difference reaching the fourth maximum voltage difference value is performed periodically multiple times. Step 264 involves clearing the screen corresponding to the fourth reset area.

[0083] Furthermore, among the multiple attainments of the first maximum differential voltage value, the second maximum differential voltage value, the third maximum differential voltage value, and the fourth maximum differential voltage value, the first maximum column voltage value Vmc1, the first maximum row voltage value Vmr1, the second maximum column voltage value Vmc2, the second maximum row voltage value Vmr2, the third maximum column voltage value Vmc3, the third maximum row voltage value, the fourth maximum column voltage value Vmc4, and the fourth maximum row voltage value alternate between positive and negative signs relative to the reference voltage value Vref.

[0084] Step 280 involves clearing the image of the cholesterol liquid crystal display (CLCD) using a first maximum pressure difference value, a second maximum pressure difference value, a third maximum pressure difference value, and a fourth maximum pressure difference value, following the sequential execution of steps 210 to 264. In other embodiments of the invention (not shown), the image of the Cholesterol Liquid Crystal Display (CLCD) can be cleared by combining the aforementioned image clearing methods 100 and 200.

[0085] Figure 3A A schematic diagram illustrating the column voltage and row voltage of a cholesterol liquid crystal display according to a third embodiment of the present invention is shown. Figure 3B A schematic diagram illustrating another column voltage and row voltage of the cholesterol liquid crystal display according to the third embodiment is shown. Figure 3C A flowchart illustrating the screen clearing method for a cholesterol-based liquid crystal display according to the third embodiment is provided. Please refer to... Figures 3A to 3C The screen clearing method 300 of the cholesterol liquid crystal display in the third embodiment specifically includes steps 321, 341, and 380, and the display panel of the cholesterol liquid crystal display in the third embodiment may not be configured as multiple reset areas or blocks.

[0086] Step 321 includes forming a first voltage difference between the column voltage Vc1 and the row voltage Vr1 of the display panel, and causing the first voltage difference to reach at least one first-order voltage difference value, specifically causing the first voltage difference to sequentially reach multiple first-order voltage difference values.

[0087] Furthermore, the first step voltage difference is the difference between the first column step voltage value Vsc1 and the first row step voltage value Vsr1 at the same time point, and the number of steps of the first column step voltage value Vsc1 and the number of steps of the first row step voltage value Vsr1 can be different or the same. This improves the flexibility of circuit design.

[0088] Step 341 includes causing the first differential pressure to reach a first maximum differential pressure value, and achieving a plurality of first-step differential pressure values ​​before the first differential pressure reaches the first maximum differential pressure value (step 321). Furthermore, step 341 may further include, after the first maximum differential pressure value continues for a maximum differential pressure duration tm, the first differential pressure reaches the plurality of first-step differential pressure values ​​in reverse timing before reaching the reference voltage value Vref. Step 380 includes clearing the image of the cholesteric liquid crystal display using the first maximum differential pressure value. Here, driving the column and row terminals of the electrodes at both ends of the display panel in a multi-stage stepping manner, so that the voltage difference reaches the vertical alignment drive voltage to perform the clearing operation, can reduce inrush current and effectively avoid stopping the clearing operation or incomplete image clearing.

[0089] Figure 4A A schematic diagram illustrating the column voltage and row voltage of a partial reset region of a cholesterol liquid crystal display according to a fourth embodiment of the present invention is shown. Figure 4B A schematic diagram illustrating the column voltage of the cholesterol liquid crystal display according to the fourth embodiment is shown. Figure 4C A flowchart illustrating the screen clearing method for a cholesterol-based liquid crystal display according to the fourth embodiment is provided. Please refer to... Figures 4A to 4C The screen clearing method 400 for a cholesterol liquid crystal display in the fourth embodiment specifically includes steps 410, 421, 422, 423, 424, 441, 442, 443, 444, and 480.

[0090] Step 410 includes configuring the display panel of the cholesterol liquid crystal display as a first reset area, a second reset area, a third reset area, and a fourth reset area. Further details regarding the first reset area, second reset area, third reset area, and fourth reset area can be found in the aforementioned first embodiment and will not be elaborated upon here.

[0091] Step 421 includes forming a first voltage difference between the column voltage Vc1 and the row voltage Vr1 corresponding to the first reset area, and causing the first voltage difference to reach at least one first-order voltage difference value, specifically causing the first voltage difference to sequentially reach multiple first-order voltage difference values.

[0092] Step 422 includes forming a second voltage difference between the column voltage Vc2 and the row voltage Vr2 corresponding to the second reset area, and causing the second voltage difference to sequentially reach a plurality of second-step voltage difference values.

[0093] Step 423 includes forming a third voltage difference between the column voltage Vc3 and the row voltage corresponding to the third reset zone, and causing the third voltage difference to sequentially reach multiple third-step voltage difference values.

[0094] Step 424 includes forming a fourth voltage difference between the column voltage Vc4 and the row voltage corresponding to the fourth reset region, and causing the fourth voltage difference to sequentially reach multiple fourth-step voltage difference values.

[0095] Step 441 includes causing the first pressure differential to reach a first maximum pressure differential value, and a plurality of first-step pressure differential values ​​are reached before the first pressure differential reaches the first maximum pressure differential value (step 421). In the fourth embodiment, the first fourth pressure differential reaching the first of a plurality of fourth-step pressure differential values ​​is earlier than the first first pressure differential reaching the first maximum pressure differential value, and the present invention is not limited thereto.

[0096] Step 442 includes causing the second pressure differential to reach a second maximum pressure differential value, wherein the time to reach the first second maximum pressure differential value is delayed by a time td compared to the time to reach the first first maximum pressure differential value, and multiple second-step pressure differential values ​​are reached before the second pressure differential reaches the second maximum pressure differential value (step 422).

[0097] Step 443 includes causing the third pressure differential to reach a third maximum pressure differential value, wherein the time to reach the first third maximum pressure differential value is delayed by a time td compared to the time to reach the first second maximum pressure differential value, and multiple third-step pressure differential values ​​are reached before the third pressure differential reaches the third maximum pressure differential value (step 423).

[0098] Step 444 includes causing the fourth pressure differential to reach the fourth maximum pressure differential value, wherein the time to reach the first fourth maximum pressure differential value is delayed by a time td compared to the time to reach the first third maximum pressure differential value, and multiple fourth-step pressure differential values ​​are reached before the fourth pressure differential reaches the fourth maximum pressure differential value (step 424).

[0099] Furthermore, the number of steps in the first column step voltage value Vsc1 can be different from or the same as the number of steps in the first row step voltage value Vsr1. The second column step voltage value Vsc2, the second row step voltage value Vsr2, the third column step voltage value Vsc3, the third row step voltage value, the fourth column step voltage value Vsc4, and the fourth row step voltage value can also be designed similarly. Each of the following—the first voltage difference reaching the first maximum voltage difference value, the second voltage difference reaching the second maximum voltage difference value, the third voltage difference reaching the third maximum voltage difference value, and the fourth voltage difference reaching the fourth maximum voltage difference value—can be periodically executed multiple times. In the fourth embodiment, the first occurrence of the fourth maximum voltage difference value is earlier than the second occurrence of the first maximum voltage difference value, and this invention is not limited thereto.

[0100] Among the multiple attainments of the first maximum differential voltage value, the second maximum differential voltage value, the third maximum differential voltage value, and the fourth maximum differential voltage value, the first maximum column voltage value Vmc1, the first maximum row voltage value Vmr1, the second maximum column voltage value Vmc2, the second maximum row voltage value Vmr2, the third maximum column voltage value Vmc3, the third maximum row voltage value, the fourth maximum column voltage value Vmc4, and the fourth maximum row voltage value are alternately positive and negative relative to the reference voltage value Vref.

[0101] Step 480 involves clearing the screen of the cholesteric liquid crystal display (LCD) using a first maximum differential pressure value, a second maximum differential pressure value, a third maximum differential pressure value, and a fourth maximum differential pressure value. This, combined with time-division / zone and multi-stage stepping drive methods, further suppresses inrush current and ensures the normal operation of the cholesteric LCD.

[0102] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A liquid crystal display, characterized by comprising: Include: A display panel comprising multiple reset areas, each reset area corresponding to displaying multiple screens; and A driving unit is used to output multiple column voltages and multiple row voltages, wherein the multiple column voltages are matched with the multiple row voltages to drive the multiple reset areas respectively; There is a first voltage difference between a column voltage and a row voltage corresponding to a reset area, and a second voltage difference between another column voltage and another row voltage corresponding to another reset area. The time when the second voltage difference reaches a second maximum voltage difference value is delayed compared to the time when the first voltage difference reaches a first maximum voltage difference value, so as to clear the multiple screens.

2. The liquid crystal display as described in claim 1, characterized in that, At least one of the first maximum differential pressure value and the second maximum differential pressure value is a vertical alignment voltage.

3. The liquid crystal display as described in claim 1, characterized in that, The number of the plurality of reset zones is at least four. The first voltage difference, the second voltage difference, the third voltage difference and the fourth voltage difference between the four column voltages and the four row voltages corresponding to the four reset zones are sequentially reached with the delay time to achieve the first maximum voltage difference value, the second maximum voltage difference value, the third maximum voltage difference value and the fourth maximum voltage difference value, so as to clear the plurality of screens.

4. The liquid crystal display as described in claim 1, characterized in that, The first maximum pressure difference value is used to clear the screen corresponding to the reset area, which is earlier than the second maximum pressure difference value.

5. The liquid crystal display as described in claim 1, characterized in that, The first maximum voltage difference is the difference between a first maximum column voltage value and a first maximum row voltage value.

6. The liquid crystal display as described in claim 1, characterized in that, The first pressure difference reaches the first maximum pressure difference value after passing through at least one first-step pressure difference value, and the second pressure difference reaches the second maximum pressure difference value after passing through at least one second-step pressure difference value.

7. A method for clearing the screen of a liquid crystal display, characterized in that, Include: A display panel of an LCD is configured as multiple reset areas, wherein the multiple reset areas are respectively configured to display multiple images, and multiple column voltages are respectively matched with multiple row voltages to drive the multiple reset areas. A first voltage difference is formed between a column voltage and a row voltage corresponding to the reset area, and the first voltage difference reaches a first maximum voltage difference value; A second voltage difference is formed between another column voltage and another row voltage corresponding to another reset region, and the second voltage difference reaches a second maximum voltage difference value, wherein the time to reach the second maximum voltage difference value is delayed compared to the time to reach the first maximum voltage difference value; and The multiple screens are cleared by the first maximum pressure difference value and the second maximum pressure difference value.

8. The method for clearing the screen of a liquid crystal display as described in claim 7, characterized in that, It also includes: A third voltage difference is formed between the column voltage and the row voltage of the corresponding reset area, and the time for the third voltage difference to reach a third maximum voltage difference value has another delay compared to the time for the second maximum voltage difference value to be reached.

9. The method for clearing the screen of a liquid crystal display as described in claim 7, characterized in that, It also includes: The first maximum pressure difference value is used to clear the screen corresponding to the reset area, which is achieved before the second maximum pressure difference value is reached; and Clear the corresponding screen in the other reset area.

10. The method for clearing the screen of a liquid crystal display as described in claim 7, characterized in that, The first pressure difference reaching the first maximum pressure difference value is periodically executed multiple times, and the second pressure difference reaching the second maximum pressure difference value is periodically executed multiple times.

11. A method for clearing the screen of a liquid crystal display, characterized in that, Include: A display panel of an LCD is configured as multiple reset areas, wherein the multiple reset areas are respectively configured to display multiple images, and multiple column voltages are respectively matched with multiple row voltages to drive the multiple reset areas. A first voltage difference is formed between a column voltage and a row voltage corresponding to the reset region, and at least a first-order voltage difference value is reached before the first voltage difference reaches a first maximum voltage difference value; A second voltage difference is formed between another column voltage and another row voltage in the corresponding reset area, and the second voltage difference reaches a second maximum voltage difference value, wherein the time to reach the second maximum voltage difference value is delayed compared to the time to reach the first maximum voltage difference value, and at least one second-step voltage difference value is reached before the second voltage difference reaches the second maximum voltage difference value; and The multiple screens are cleared by the first maximum pressure difference value and the second maximum pressure difference value.

12. The method for clearing the screen of a liquid crystal display as described in claim 11, characterized in that, The at least one first step voltage difference value is the difference between the at least one first column step voltage value and the at least one first row step voltage value, and the number of steps of the at least one first column step voltage value is the same as or different from the number of steps of the at least one first row step voltage value.

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