Display device

Abstract

The application provides a display device, comprising: a system chip configured to output first differential data signals; a data conversion bridge chip electrically connected to the system chip, the data conversion bridge chip being configured to convert the first differential data signals into second differential data signals; and a source driving chip electrically connected to the data conversion bridge chip, configured to receive and process the second differential data signals and then output the second differential data signals to a display panel; wherein the number of the second differential data signals is an integer multiple of the number of the first differential data signals. Through the above scheme, as the resolution and refresh rate of the display device are continuously improved, the source driving chip does not need to be redesigned, the production cost is reduced, and the quality of signal transmission is ensured.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display device. Background Technology

[0002] Liquid crystal display devices mainly consist of a backlight and a liquid crystal panel (open cell). The liquid crystal panel is connected to a source driver chip, which in turn is connected to a system-on-a-chip (SoC) via a pin connector (FFC pin map). (See reference...) Figure 1 As shown, in some high-resolution, high-refresh-rate display devices, since the system chips and circuit pin connectors are already standardized, the source driver chip needs to have a pair of differential signal inputs. However, to meet the requirements of display devices with even higher resolutions and refresh rates, the source driver chips in related technologies cannot meet this requirement, necessitating a redesign of the source driver chip to achieve a higher transmission rate for the differential signal lines. This continuous increase in the differential transmission rate of the source driver chip as the resolution and refresh rate of the display device increases leads to a continuous increase in production and design costs and time costs, and also makes it difficult to standardize the source driver chip. Summary of the Invention

[0003] Embodiments of this application provide a display device to solve the problem in the related art that the performance of the source driver chip cannot match the increasingly higher resolution and refresh rate requirements of the display device.

[0004] To solve the above problems, the technical solution provided in this application is as follows:

[0005] This application provides a display device, including:

[0006] The system chip is configured to output type 1 differential data signals;

[0007] A data conversion bridge chip, electrically connected to the system chip, is configured to convert the first type of differential data signal into a second type of differential data signal; and

[0008] The source driver chip is electrically connected to the data conversion bridge chip and is configured to receive and process the second type of differential data signal and then output it to the display panel.

[0009] The number of the second type of differential data signals is an integer multiple of the number of the first type of differential data signals.

[0010] In one embodiment, the data conversion bridge chip includes multiple data conversion bridge modules;

[0011] Each of the data conversion bridging modules is configured to convert a pair of first-type differential data signals into two pairs of second-type differential data signals.

[0012] In one embodiment, the source driver chip includes multiple source driver modules;

[0013] Each of the data conversion bridging modules is connected to one of the source drive modules to convert N pairs of the first type of differential data signals into 2N pairs of the second type of differential data signals;

[0014] Where N is an integer greater than 0.

[0015] In one embodiment, the source driver chip includes multiple source driver modules;

[0016] The data conversion bridge chip includes multiple data conversion bridge modules, and each data conversion bridge module is connected to one of the source driver modules;

[0017] Each of the data conversion bridging modules includes at least a portion of cascaded data conversion bridging modules to convert N pairs of the first type of differential data signals into M pairs of the second type of differential data signals;

[0018] N is an integer greater than 0 and M is an integer multiple of N.

[0019] In one embodiment, the differential transmission rate X of the source driver chip is less than the total data bandwidth Y required by the display panel;

[0020] Where Y = a × b × c × d, a is the resolution width of the display panel, b is the resolution height of the display panel, c is the refresh rate of the display panel, and d is the color depth of the display panel.

[0021] In one embodiment, the display panel has a resolution of 4K, a refresh rate of 165Hz, and a color depth of 24-bit;

[0022] The source driver chip includes 12 source driver modules, and there are 6 data conversion bridge modules. The differential transmission rate of each source driver module is greater than or equal to 2Gbps.

[0023] In one embodiment, a pair of first-type differential data signals includes a positive first-type differential data signal and a negative first-type differential data signal.

[0024] In one embodiment, a pair of second-type differential data signals includes a positive second-type differential data signal and a negative second-type differential data signal.

[0025] In one embodiment, the display panel has an RBG pixel structure;

[0026] The first type of differential data signal includes at least RBG pixel data, and the second type of differential data signal includes at least RBG pixel data and GRB pixel data.

[0027] In one embodiment, the data conversion bridging module includes any one of a differential signal distributor, a differential buffer, and an FPGA.

[0028] This application provides a display device comprising: a system-on-a-chip (SoC) configured to output a first type of differential data signal; a data conversion bridge chip electrically connected to the SoC, the data conversion bridge chip configured to convert the first type of differential data signal into a second type of differential data signal; and a source driver chip electrically connected to the data conversion bridge chip, configured to receive and process the second type of differential data signal and then output it to a display panel; wherein the number of the second type of differential data signals is an integer multiple of the number of the first type of differential data signals. With this solution, as the resolution and refresh rate of display devices continue to increase, there is no need to redesign the source driver chip, thus reducing production costs while ensuring the quality of signal transmission. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Appendix Figure 1 This is a schematic diagram of the source driver chip in related technologies;

[0031] Appendix Figure 2 This is a schematic diagram of the overall structure of the display device in the embodiments of this application;

[0032] Appendix Figure 3 This is a schematic diagram of some module structures of the display device in the embodiments of this application;

[0033] Appendix Figure 4 This is a schematic diagram of the circuit structure of the display device in the embodiments of this application;

[0034] Appendix Figure 5 This is a schematic diagram of pixel data received by the data conversion bridging module in an embodiment of this application;

[0035] Appendix Figure 6 This is a schematic diagram of the pixel data output by the data conversion bridging module in an embodiment of this application.

[0036] Explanation of the reference numerals in the figure:

[0037] 1. Display device; 10. Display panel; 20. System chip; 30. Data conversion bridge chip; 31. Data conversion bridge module; 40. Source driver chip; 41. Source driver module. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0039] It will be understood that although the terms “first,” “second,” etc., may be used in this document to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another.

[0040] As used in this article, the singular forms “a,” “one,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0041] It will also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the said feature or component, but do not exclude the presence or addition of one or more other features or components.

[0042] Reference Figures 2 to 4 As shown, this application provides a display device 1, including a display panel 10, a system chip 20, a data conversion bridge chip 30, and a source driver chip 40. The system chip 20 is configured to output a first type of differential data signal. The data conversion bridge chip 30 is electrically connected to the system chip 20 and configured to convert the first type of differential data signal into a second type of differential data signal. The source driver chip 40 is electrically connected to the data conversion bridge chip 30 and configured to receive and process the second type of differential data signal before outputting it to the display panel 10. It should be noted that the number of second type differential data signals is an integer multiple of the number of first type differential data signals.

[0043] Through the above solution, this application can convert the first type of differential data signal emitted by the system chip 20 into more second type differential data signals without redesigning the source driver chip 40, through the data conversion bridge chip 30, which can effectively reduce time and production costs and improve signal transmission efficiency.

[0044] Specifically, refer to Figure 3As shown, in some embodiments of this application, the data conversion bridge chip 30 includes a plurality of data conversion bridge modules 31, wherein each data conversion bridge module 31 is configured to convert a pair of first-type differential data signals into two pairs of second-type differential data signals. It should be noted that a pair of first-type differential data signals includes a positive first-type differential data signal and a negative first-type differential data signal, and a pair of second-type differential data signals includes a positive second-type differential data signal and a negative second-type differential data signal.

[0045] Specifically, in some embodiments of this application, the source driver chip 40 also includes multiple source driver modules 41. The number of source driver modules 41 required by the display device 1 varies depending on the output capability of the source driver modules 41. In actual use, the specific settings can be made according to the requirements, and this application does not limit it here.

[0046] Based on this, as one implementation of the data conversion bridging module 31, each data conversion bridging module 31 is connected to a source driver module 41, which can convert N pairs of first-type differential data signals into 2N pairs of second-type differential data signals; where N is an integer greater than 0. Through this scheme, the data conversion bridging chip 30 can output second-type differential data signals, which is twice the number of first-type differential data signals. In this case, without changing the source driver chip 40, the signal transmission capability can be improved, which helps to reduce the production cost of the display device 1.

[0047] In addition, as some other implementations of the data conversion bridging module 31, the data conversion bridging chip 30 may include multiple data conversion bridging modules, each connected to a source driver module 41; wherein each data conversion bridging module includes at least some cascaded data conversion bridging modules 31 to convert N pairs of first-type differential data signals into M pairs of second-type differential data signals; N is an integer greater than 0 and M is an integer multiple of N. It should be noted that the data conversion bridging module can be a virtual range division or an actual hardware circuit division, which is not limited here. In this embodiment, in one of the two output terminals of a data conversion bridging module 31, either output terminal is connected to the input terminal of another data conversion bridging module 31, and the other data terminal of the first data conversion bridging module 31 is directly connected to the source driver module 41, thereby realizing the conversion of N pairs of first-type differential data signals into 3N pairs of second-type differential data signals. At this time, one data conversion bridging module includes two data conversion bridging modules 31. Similarly, if both outputs of a data conversion bridge module 31 are connected to the inputs of two other data conversion modules, then N pairs of first-type differential data signals can be converted into 4N pairs of second-type differential data signals. In this case, one data conversion bridge module includes three data conversion bridge modules 31. And so on, depending on the cascading method of the data conversion modules, various numbers of second-type differential data signals can be output. It should be noted that in this embodiment, since the first-type differential data signals undergo multiple data conversions, some anti-interference circuit modules can be included in the data conversion bridge chip 30 to avoid deviations in the first-type differential data signals after multiple data conversions.

[0048] In some more specific embodiments, the data conversion bridging module 31 described above may also include any one of a differential signal distributor, a differential buffer, and an FPGA.

[0049] In the above embodiments, since the data is converted by the data conversion bridging chip 30, it is no longer necessary to continuously increase the differential transmission rate of the source driver chip 40. In some embodiments of this application, the differential transmission rate X of the source driver chip 40 is less than the total data bandwidth Y required by the display panel 10; where Y = a × b × c × d, a is the resolution width of the display panel 10, b is the resolution height of the display panel 10, c is the refresh rate of the display panel 10, and d is the color depth of the display panel 10.

[0050] More specifically, refer to Figure 4As shown, in some embodiments of this application, the display panel 10 has a resolution of 4K, a refresh rate of 165Hz, and a color depth of 24 bits; the source driver chip 40 includes 12 source driver modules 41, and the data conversion bridge module 31 has 6 modules, so the differential transmission rate of each source driver module 41 can be greater than or equal to 2Gbps.

[0051] Furthermore, it should be noted that in some embodiments of this application, the display panel 10 has an RBG pixel structure; see reference Figure 5 As shown, the first type of differential data signal includes at least RBG pixel data, then refer to... Figure 6 As shown, the second type of differential data signal includes at least RBG pixel data and GRB pixel data.

[0052] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.

Claims

1. A display device, characterized in that, include: The system chip is configured to output type 1 differential data signals; A data conversion bridge chip is electrically connected to the system chip, and the data conversion bridge chip is configured to convert the first type of differential data signal into a second type of differential data signal; as well as The source driver chip is electrically connected to the data conversion bridge chip and is configured to receive and process the second type of differential data signal and then output it to the display panel. The number of the second type of differential data signals is an integer multiple of the number of the first type of differential data signals; the first type of differential data signals include at least RBG pixel data, and the second type of differential data signals include at least RBG pixel data and GRB pixel data; The differential transmission rate X of the source driver chip is less than the total data bandwidth Y required by the display panel; Where Y = a × b × c × d, a is the resolution width of the display panel, b is the resolution height of the display panel, c is the refresh rate of the display panel, and d is the color depth of the display panel; The data conversion bridge chip includes multiple data conversion bridge modules; Each of the data conversion bridging modules is configured to convert a pair of first-type differential data signals into two pairs of second-type differential data signals.

2. The display device according to claim 1, characterized in that, The source driver chip includes multiple source driver modules; Each of the data conversion bridging modules is connected to one of the source drive modules to convert N pairs of the first type of differential data signals into 2N pairs of the second type of differential data signals; Where N is an integer greater than 0.

3. The display device according to claim 1, characterized in that, The source driver chip includes multiple source driver modules; The data conversion bridge chip includes multiple data conversion bridge modules, and each data conversion bridge module is connected to one of the source driver modules; Each of the data conversion bridging modules includes at least a portion of cascaded data conversion bridging modules to convert N pairs of the first type of differential data signals into M pairs of the second type of differential data signals; N is an integer greater than 0 and M is an integer multiple of N.

4. The display device according to claim 1, characterized in that, The display panel has a resolution of 4K, a refresh rate of 165Hz, and a color depth of 24-bit. The source driver chip includes 12 source driver modules, and there are 6 data conversion bridge modules. The differential transmission rate of each source driver module is greater than or equal to 2Gbps.

5. The display device according to claim 1, characterized in that, A pair of first-type differential data signals includes a positive first-type differential data signal and a negative first-type differential data signal.

6. The display device according to claim 1, characterized in that, A pair of second-type differential data signals includes a positive second-type differential data signal and a negative second-type differential data signal.

7. The display device according to claim 1, characterized in that, The display panel has an RGB pixel structure.

8. The display device according to claim 2, characterized in that, The data conversion bridging module includes any one of a differential signal distributor, a differential buffer, and an FPGA.

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