Array substrate, display panel and display device

Abstract

The application relates to an array substrate, a display panel and a display device. In the technical scheme, the array substrate comprises a non-display area and a display area, the non-display area is provided with a source driving chip, an integrated gate driving circuit and a gate driving chip, and the display area is provided with M rows of thin film transistors, and M is a positive integer. The gate driving chip is used for driving continuous P rows of thin film transistors in the M rows of thin film transistors according to a first control signal and a first clock signal output by the source driving chip, and P is a positive integer smaller than M; the integrated gate driving circuit is used for driving continuous Q rows of thin film transistors in the M rows of thin film transistors according to a second control signal and a second clock signal output by the source driving chip, and Q is the difference between M and P. The technical scheme can realize special resolution in a cascaded mode of the GIA and the gate driving chip, and the cost is relatively low.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology

[0002] With the development of amorphous silicon (A-Si) technology, screens have become widely available, and users' requirements for screen resolution have also increased accordingly. For example, in the use of in-vehicle screens, users have expressed a need for screens with irregular resolutions (such as 1920*1240, 1280*1280, 2560*1500, etc.).

[0003] However, current in-vehicle screens typically have resolutions of Full High Definition (FHD) and Quad High Definition (QHD). FHD resolution is 1920*1200, while QHD resolution can be 2560*1440. Therefore, how to achieve irregular resolutions for in-vehicle screens has become a technical challenge. Summary of the Invention

[0004] This application provides an array substrate, a display panel, and a display device.

[0005] In a first aspect, this application provides an array substrate, the array substrate including a non-display area and a display area, the non-display area being provided with a source driver chip, an integrated gate driver circuit, and a gate driver chip, the display area being provided with M rows of thin-film transistors, where M is a positive integer; the source driver chip is used to output a first control signal and a first clock signal to the gate driver chip, and to output a second control signal and a second clock signal to the integrated gate driver circuit; the gate driver chip is used to drive P consecutive rows of thin-film transistors in the M rows of thin-film transistors according to the first control signal and the first clock signal, where P is a positive integer less than M; the integrated gate driver circuit is used to drive Q consecutive rows of thin-film transistors in the M rows of thin-film transistors according to the second control signal and the second clock signal, where Q is the difference between M and P.

[0006] In conjunction with the first aspect, in one possible implementation, P is greater than Q.

[0007] In conjunction with the first aspect, in one possible implementation, the second control signal includes a start control signal and a stop control signal.

[0008] In conjunction with the first aspect, in one possible implementation, the second control signal is a shutdown control signal; the integrated gate drive circuit is further configured to obtain a startup control signal from the gate drive chip; the integrated gate drive circuit is configured to drive consecutive Q rows of thin-film transistors in the M rows of thin-film transistors according to the second control signal, the startup control signal, and the second clock signal.

[0009] In conjunction with the first aspect, in one possible implementation, the charging time of each row of thin-film transistors in the continuous P rows of thin-film transistors is less than the charging time of each row of thin-film transistors in the continuous Q rows of thin-film transistors.

[0010] In conjunction with the first aspect, in one possible implementation, the gate driver chip includes a chamfered circuit.

[0011] In conjunction with the first aspect, in one possible implementation, the gate driving chip and the integrated gate driving circuit are distributed on the same side or different sides of the array substrate.

[0012] In conjunction with the first aspect, in one possible implementation, there are multiple integrated gate driving circuits, which are distributed on the upper and lower sides of the gate driving chip.

[0013] In a second aspect, this application provides a display panel that includes an array substrate as described in the first aspect or any of its implementations.

[0014] Thirdly, this application provides a display device that includes a display panel as described in the second aspect.

[0015] The technical solution provided in this application achieves irregular resolution by cascading an integrated gate driver in array (GIA) circuit with a gate driver chip. Since the GIA mainly consists of thin-film transistors (TFTs) and capacitors, it can be directly placed on the array substrate during the array substrate manufacturing process, thereby improving the array substrate's production efficiency. Furthermore, because the implementation cost of the GIA is lower than the procurement cost of the gate driver chip, the technical solution provided in this application has a lower implementation cost compared to achieving irregular resolution through cascading gate driver chips. Compared to achieving irregular resolution entirely through GIA, the technical solution provided in this application has lower power consumption. For applications with high screen refresh rates, this application proposes an unequal charging time design scheme. By extending the charging time of each row of TFTs driven by the GIA, the transmission stability of the GIA signal is improved, thus enhancing the screen's display performance. Additionally, this application adds a chamfering circuit to the gate driver chip to reduce the gate high voltage (VGH) during shutdown, balancing the driving capabilities of the gate driver chip and GIA for the TFTs, improving the issue of split-screen display, and enhancing the screen's display performance. Attached Figure Description

[0016] Figures 1 to 4 This is a schematic diagram of the design architecture of the array substrate provided in this application; Figure 5 A schematic diagram illustrating the source driver chip provided in this application; Figure 6 A schematic diagram of the driving mechanism of an array substrate provided in this application; Figure 7 A schematic diagram of a drive signal provided in this application; Figure 8 A schematic diagram of another array substrate provided in this application; Figure 9 A schematic diagram of another driving signal provided in this application; Figure 10 A schematic diagram of another driving signal provided in this application; Figure 11 A schematic diagram illustrating the split-screen layout provided in this application; Figure 12 A schematic diagram of the chamfering circuit provided in this application; Figure 13 A schematic diagram illustrating the gate chamfering function provided in this application. Detailed Implementation

[0017] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] In the description of this invention, it should be noted that the terms "upper," "lower," "left," "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. Furthermore, the technical features involved in the different embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0020] To facilitate understanding of this application, the relevant concepts will be explained below.

[0021] 1. Resolution Resolution is the number of pixels per unit length. Common screen resolutions include High Definition (HD), Full High Definition (FHD), and Quad High Definition (QHD). FHD resolution can be 1920*1200 (16:10), and QHD resolution can be 2560*1440 (16:9). Taking FHD resolution as an example, 1920 represents the number of pixels horizontally on the screen or image, 1200 represents the number of pixels vertically, and the aspect ratio is 16:10.

[0022] 2. Thin-film transistor (TFT) TFT is a technology used in liquid crystal displays (LCDs). TFTs are used to control the alignment of liquid crystal molecules, thereby controlling the light transmission and blocking of each pixel to display images.

[0023] 3. Gate driver chip (gate integrated circuit, gate IC) A gate driver chip is used to drive the gate of a TFT. For example, a gate driver chip can output scan signals to the gate of a TFT according to a certain timing sequence to turn the TFT gate on or off line by line, thereby realizing line-by-line scanning and control of pixels. The scan signal can be a pulse signal; a high level of the pulse signal is used to turn on the TFT gate, and a low level is used to turn off the TFT gate. The gate driver chip is a physical IC.

[0024] It should be noted that gate driver chips are typically designed with 720 / 1080 / 1200 channels (ch), used to drive 720 / 1080 / 1200 rows of TFTs in the vertical direction, thereby enabling control of 720 / 1080 / 1200 rows of pixels in the vertical direction. Each row of TFTs (i.e., each row of pixels) in the vertical direction requires one channel for control. For example, for a resolution of 1920*1080, there are 1080 rows of pixels in the vertical direction, so a single 1080-channel gate driver chip can be used to drive them.

[0025] 4. Integrated gate driver in array (GIA) circuit GIA (Gateway Interface) can be used to control the gate of a TFT (Thin-Film Transistor). For example, GIA can output scan signals to the gate of a TFT through internal components such as TFTs and capacitors, thereby turning the gate of the TFT on or off line by line, thus realizing line-by-line scanning and control of pixels. GIA can be a circuit arrayed on an array substrate or an arrayed on the TFT glass.

[0026] 5. Source driver chip A source driver chip is used to drive the source of a TFT. For example, a source driver chip can output an analog voltage signal to the source of a TFT to control the brightness and color of pixels. A source driver chip is a physical IC.

[0027] It should be noted that source driver chips are typically designed with 1920 channels, meaning that a single source driver chip can realize 1920 columns of TFTs in the horizontal direction, thereby controlling 1920 columns of pixels in the horizontal direction. For example, for a resolution of 1920*1080, there are 1920 columns of pixels in the horizontal direction, so they can be driven by a single source driver chip.

[0028] In some implementations, the source driver chip can be a timing controller embedded driver IC (TED IC) formed by integrating a timing controller (TCON) and a source driver (Source IC). The TCON module in the source driver chip converts the data input from the system's main control chip via a flexible printed circuit (FPC) and inputs the converted data internally to the source driver. Simultaneously, it outputs gate control signals to the gate driver chip via glass traces. The source driver chip and the gate driver chip can each transmit signals to the display area via glass traces, or in other words, they can each transmit signals to the TFT via glass traces. The display area can be understood as the region containing the TFT.

[0029] In some implementations, the source driver chip can be a touch and display driver integration (TDDI) chip.

[0030] 6. Start Vertical Signal (STV) In the driving circuits of display devices such as liquid crystal displays (LCDs), the STV signal can be used to indicate whether to turn on or stop the operation of the vertically progressive scan TFT. The STV signal can also be used to indicate the starting position of the progressive scan TFT.

[0031] 7. Clock signal Clock signals are primarily used to control the scanning rhythm of progressive scan TFTs in the vertical direction. For example, in liquid crystal display devices, each pulse of the clock signal corresponds to a point in time or step of the scanning operation, ensuring that the image is displayed in the correct order and rhythm in the vertical direction. Clock signals can be, for example, vertical clock pulse (CPV) signals or CLK signals.

[0032] The technical problems that this application needs to solve are described below.

[0033] With the development of amorphous silicon (A-Si) technology, screens have become widely used in various devices such as vehicles, home appliances, and fitness equipment. Simultaneously, users' demands for screen resolution have increased accordingly. For example, in the use of in-vehicle screens, users have requested screens with irregular resolutions (such as 1920*1240 (3:2), 1280*1280 (1:1), 2560*1500, etc.), but currently, the resolutions of in-vehicle screens are typically FHD and QHD. It should be noted that irregular resolution refers to a resolution that expands the number of pixels vertically compared to existing resolution standards. For example, a resolution of 1920*1240 expands by 40 pixels vertically compared to FDH resolution; a resolution of 2560*1500 expands by 60 pixels vertically compared to TDH resolution. In some implementations, irregular resolution can also be understood as a resolution where the number of pixels in the vertical direction is not an integer multiple of the number of pixel rows that the gate driver chip can drive. For example, a resolution of 1280*1280 has 1280 pixels in the vertical direction, which is 80 pixels more than a 1200ch gate driver chip.

[0034] Therefore, how to achieve irregular resolution for in-vehicle screens has become a technical problem.

[0035] One possible implementation involves adding a cascaded gate driver chip to drive the vertically extending pixels. However, this method is costly to implement and the utilization rate of the added gate driver chip is low.

[0036] In view of this, this application proposes an array substrate, a display panel, and a display device. The technical solution provided in this application achieves irregular resolution on an automotive screen by cascading a gate interface (GIA) and a gate driver chip. In the proposed technical solution, the GIA drives pixels extending vertically without requiring an additional gate driver chip. Since the GIA mainly consists of TFTs and capacitors, it can be directly placed on the array substrate during the production process, improving production efficiency. Furthermore, the implementation cost of the GIA is lower than the procurement cost of the gate driver chip; therefore, compared to the implementation method of adding an additional gate driver chip through cascading, the implementation cost of the technical solution provided in this application is lower. It should be noted that the technical solution provided in this application can be applied to other fields besides automotive screens, such as home appliance screens, and is not limited thereto.

[0037] Figures 1 to 4 A schematic diagram of the design architecture of the array substrate provided in this application. Figures 1 to 4The array substrate 100 shown includes a non-display area and a display area. The non-display area is provided with a GIA 110 and a gate driver chip 120, and the display area is provided with M rows of TFTs, where M is a positive integer.

[0038] In one possible implementation, the GIA 110 and the gate driver chip 120 can be distributed on the same side or different sides of the array substrate 100. For example... Figure 1 and Figure 2 In the middle, both the GIA 110 and the gate driver chip 120 are distributed on the right side of the array substrate 100; Figure 3 and Figure 4 In the array substrate 100, GIA 110 is distributed on the left side, and gate driver chip 120 is distributed on the right side.

[0039] It should be noted that, Figures 1 to 4 The number and distribution of GIAs and gate driver chips are for illustrative purposes only and are not intended to limit the technical solution of this application. For example, the gate driver chip may also be located on the left side of the array substrate. Furthermore, when there are two GIAs and one gate driver chip, the GIAs may be distributed on the top and bottom sides of the gate driver chip.

[0040] The gate driver chip 120 can drive P consecutive rows of TFTs in M ​​rows of TFTs, where P is a positive integer less than M; the gate driver chip 110 can drive Q consecutive rows of TFTs in M ​​rows of TFTs, where Q is the difference between M and P. It should be understood that the gate driver chip 120 and the gate driver chip 110 can be used to drive the gates of the TFTs on the display area, as described above, and will not be repeated here. The TFTs driven by the gate driver chip 110 and the gate driver chip 120 do not overlap.

[0041] See Figure 1 and Figure 3 The GIA 110 can drive the TFTs in rows 1 to Q, and the gate driver chip 120 can drive the TFTs in rows Q+1 to M. See also... Figure 2 and Figure 4 The gate driver chip 120 can drive the TFTs in rows 1 to P, and the GIA110 can drive the TFTs in rows P+1 to M.

[0042] It should be noted that when driving the same number of TFTs, the power consumption of the GIA is much greater than that of the gate driver chip. Therefore, P can be greater than Q, so that the gate driver chip drives a larger number of TFTs and the GIA drives a smaller number of TFTs, thereby further saving power consumption.

[0043] In one possible implementation, a source driver chip 130 is also provided on the non-display area of ​​the array substrate 100.

[0044] The source driver chip 130 can be used to output control signals and clock signals to the GIA 110 and the gate driver chip 120 to control the GIA 110 and the gate driver chip 120 to drive the TFT; it can also be used to drive the source of the TFT provided on the display area to control the brightness and color of the pixels.

[0045] It should be noted that, Figures 1 to 4 The number and location of the source drive chips 130 are merely examples, and this application does not impose any limitations on them.

[0046] Figure 5 A schematic diagram illustrating the source driver chip provided in this application. Figure 5 As shown, the source driver chip includes 38 pins. Pins 2 to 31 are used to output control and clock signals to the GIA; pin 34 outputs an output enable (OE) signal to the gate driver chip; pin 36 outputs a clock signal CPV to the gate driver chip, which can determine the output time and frequency of the scan signal based on the OE and CPV signals; pin 37 outputs an enable control signal STV-U to the gate driver chip; and pin 38 receives an disable control signal STV-D from the gate driver chip. It should be noted that the number of pins on the source driver chip that can output signals to the GIA is greater than the number of signals. Therefore, the output pins can be randomly selected or predefined; this application does not impose any restrictions on this.

[0047] The following example uses a car screen with a resolution of 1920*1240 and a refresh rate of 60Hz. Figures 6 to 9 The working principle of the technical solution provided in this application is explained. Specifically, 40 rows of TFTs in the vertical direction within the display area are driven by a GIA, and 1200 rows of TFTs in the vertical direction within the display area are driven by a 1200ch gate driver chip.

[0048] Figure 6 This is a schematic diagram of the driving mechanism of an array substrate provided in this application. Figure 6 The display area shown has 1240 rows of TFTs. The GIA and gate driver chips are located on the right side of the array substrate, and two source driver chips (such as...) are also located below the array substrate. Figure 6 Source driver chip 1 and source driver chip 2 are connected to the GIA, the gate driver chip, and source driver chip 2, respectively.

[0049] In this application, for ease of distinction and understanding, the control signal output by the source driver chip to the gate driver chip can be referred to as the first control signal, and the control signal output to the GIA can be referred to as the second control signal; the clock signal output by the source driver chip to the gate driver chip can be referred to as the first clock signal, and the clock signal output to the GIA can be referred to as the second clock signal.

[0050] In this embodiment, the first control signal may include a first start control signal STV-U and an OE signal, and the first clock signal may be a CPV signal. The second control signal may include second start control signals STV1 and STV2, and second stop control signals STV3 and STV4, and the second clock signal may include CLK1 to CLK4.

[0051] Figure 7 This is a schematic diagram of a drive signal design provided in this application. Figure 7 The driving signals shown include STV1, STV2, CLK1 to CLK4, STV3, STV4, STV-U, STV-D, and scan signals G41 to G1240 output by the gate driver chip to the TFT. It should be understood that the driving signals may also include other... Figure 7 Signals not given in the text, such as CPV, OE, and the scan signals G1 to G40 output by GIA to the TFT.

[0052] See Figure 7 The driving signals can be designed as pulse signals. Specifically, the pulse width of the STV-U and STV-D signals can be designed as T, with a high level of 3.3 volts (V) and a low level of 0V; the pulse width of the STV1 to STV4 signals can be designed as 3T, with a high level of the TFT gate high voltage (VGH) and a low level of the TFT gate low voltage (VGL); the high level of the CLK1 to CLK4 signals can be designed as the TFT VGH, with a pulse width of 3T; the low level of the CLK1 to CLK4 signals can be designed as the TFT VGL, with a pulse width of 5T. Figure 7 The pulse widths of the CPV and OE signals, not specified in the code, can be designed as T, with a high level of 3.3V and a low level of 0V. Considering that the scan signal output from the GIA or gate driver chip is used to turn the TFT gate on or off, the pulse width of the scan signal can be designed as T, with the high level of the scan signal being the TFT's VGH and the low level being the TFT's VGL. It should be noted that T can be understood as the charging time for one TFT row, or the charging time for one line. T can be related to the screen's refresh rate and the number of TFT rows requiring charging.

[0053] In one possible implementation, T can satisfy the formula: T = 1 / f / M. f is the refresh rate of the screen or display area, and M is the number of rows of TFTs that need to be charged, or the number of rows of TFTs provided on the array substrate.

[0054] In one possible implementation, a buffer (blank) time can be set between the charging times of each row of TFTs to reduce interference between the scan signals of each row of TFTs. For example, the charging time of 60 rows of TFTs can be set as the buffer time. In this case, T can satisfy the formula: T=1 / f / (M+60). If the screen refresh rate is 60Hz, then T=1 / 60 / (1240+60)=12.8 microseconds (µs).

[0055] In this embodiment, the source driver chip 1 outputs STV1 and STV2 signals to the GIA to instruct the GIA to start the scanning operation, and outputs clock signals CLK1 to CLK4 to the GIA, with each clock signal including 10 cycles, so that the GIA can output 40 scanning signals, such as G1 to G40, to the TFTs in the display area according to a certain timing sequence, thereby driving the TFTs in the 1st to 40th rows in the vertical direction, and thus realizing the control of the pixels in the 1st to 40th rows in the vertical direction; the source driver chip 1 outputs STV3 and STV4 signals to the GIA to instruct the GIA to stop the scanning operation. Accordingly, to ensure the continuity of TFT scanning, before GIA is about to complete the scanning operation, source driver chip 1 can output an STV-U signal to the gate driver chip to instruct the gate driver chip to start the scanning operation, and output OE and CPV signals to GIA. The OE and CPV signals include 1200 cycles, so that the gate driver chip can output 1200 scanning signals, such as G41 to G1240, to the TFTs in the display area according to a certain timing sequence, thereby driving the TFTs in rows 41 to 1240 in the vertical direction, and thus realizing the control of the pixels in rows 41 to 1240 in the vertical direction. The gate driver chip can output an STV-D signal to source driver chip 1 to indicate that the scanning is complete. The Gx signal is used to drive the TFT in row x in the vertical direction, 1≤x≤1240, where x is an integer. It should be understood that the output time of G41 is later than the output time of G40. In this embodiment, source driver chip 2 can output signals to the source of the TFTs provided on the display area to control the brightness and color of the pixels in the horizontal direction.

[0056] It should be understood that Figure 7 The driving method shown can be applied to schemes where GIA drives the TFTs in the display area before the gate driver chip, and can also be applied to... Figure 3 The array substrate shown.

[0057] Figure 8This is a schematic diagram of another array substrate provided in this application. Figure 8 The display area shown has 1240 rows of TFTs. The gate actuators (GIAs) are distributed on the left side of the array substrate, and the gate actuator chips are distributed on the right side of the array substrate. Two source actuator chips (such as...) are also located below the array substrate. Figure 8 Source driver chip 1 and source driver chip 2 are connected to the gate driver chip and source driver chip 2, respectively, and GIA is connected to source driver chip 2.

[0058] In this embodiment, the first control signal may include a first start control signal STV-U and an OE signal, and the first clock signal may be a CPV signal. The second control signal may be a second stop control signal STV3 and STV4, and the second clock signal may include CLK1 to CLK4.

[0059] In this embodiment, the second start control signals STV1 and STV2 can be obtained from the gate driver chip. For example, the last two scan signals output by the gate driver chip to the display area can be used as the start control signals for the GIA. It should be noted that since the timing of the last two scan signals G1199 and G1200 output by the gate driver chip is before the GIA start scan operation, and the levels of G1199 and G1200 meet the level design conditions for the GIA start control signal, the last two scan signals output by the gate driver chip can be used as the start control signals for the GIA.

[0060] Figure 9 A schematic diagram of another driving signal provided in this application. Figure 9 The driving signals shown include STV-U, STV-D, CLK1 to CLK4, STV3, STV4, and scan signals G1 to G1200 output by the gate driver chip to the TFT. STV1 and STV2 can be determined by G1199 and G1200. It should be understood that the driving signals may also include other signals not shown in the figure, such as CPV, OE, and scan signals G1201 to G1240 output by GIA to the TFT.

[0061] See Figure 9 The drive signal can be designed as a pulse signal. (And...) Figure 7 Compared to the design of the drive signals shown, this embodiment uses the last two stages of scan signals output by the gate driver chip as the GIA start control signals. The design of the remaining drive signals can be referenced. Figure 7 The relevant descriptions in the document will not be repeated here.

[0062] In this embodiment, the source driver chip 1 outputs STV-U to the gate driver chip to instruct the gate driver chip to start the scanning operation, and outputs OE and CPV signals to the gate driver chip. The OE and CPV signals include 1200 cycles, so that the gate driver chip can output 1200 scanning signals, such as G1 to G1200, to the TFTs in the display area according to a certain timing sequence, thereby driving the TFTs in the 1st to 1200th rows in the vertical direction, and thus realizing the control of the pixels in the 1st to 1200th rows in the vertical direction. The gate driver chip outputs STV-D signal to the source driver chip to indicate that the scanning is complete. Correspondingly, the GIA can initiate a scanning operation based on STV1 and STV2 obtained from the gate driver chip or the display area, and output scan signals G1201 to G1240 to the TFTs in the display area according to a certain timing sequence using clock signals CLK1 to CLK4 obtained from the source driver chip 2, thereby driving the TFTs in rows 1201 to 1240 in the vertical direction, and thus controlling the pixels in rows 1201 to 1240 in the vertical direction. The source driver chip 2 instructs the GIA to stop the scanning operation by outputting STV3 and STV4 signals to the GIA.

[0063] It should be understood that Figure 9 The driving method shown can be applied to schemes where the gate driver chip drives the TFTs in the display area before the GIA, and can also be applied to... Figure 2 The array substrate shown.

[0064] The technical solution provided in this application achieves irregular resolution by cascading GIA (Gate Interface) and gate driver chips. Compared to the implementation method of cascading gate driver chips, the technical solution provided in this application can save the number of gate driver chips, thereby saving costs. Compared to the implementation method of using all GIAs, the technical solution provided in this application has lower power consumption. According to actual application, the power consumption of a 2880-level GIA is 362 milliwatts (mW), the power consumption of a 40-level GIA is approximately 5mW, and the power consumption of a 1080-level gate driver chip is 29mW. The power consumption of a 2880-level GIA can be understood as the power consumption consumed by the GIA driving 2880 rows of TFTs, or the power consumption of a 2880-level GIA. Correspondingly, the power consumption of a 1080-level gate driver chip can be understood as the power consumption consumed by the gate driver chip driving 1080 rows of TFTs, or the power consumption of a 1080-level gate driver chip. Compared to a resolution of 1920*1240 (3:2), the power consumption of cascading GIA with a gate driver chip is comparable to that of two gate driver chips.

[0065] In this embodiment, due to its own circuit design and component characteristics, the load-carrying capacity of the GIA is weaker than that of the gate driver chip. As the screen refresh rate increases, the charging time for each row of TFTs decreases accordingly. Due to the limited load-carrying capacity, the GIA may not be able to provide sufficient power to each row of TFTs within a short charging time, resulting in reduced screen display performance. Therefore, this application provides a design scheme with unequal charging time. In this design scheme, the charging time of each row of TFTs driven by the gate driver chip can be appropriately reduced, and the time saved in the charging time of the TFTs driven by the gate driver chip can be compensated to the TFTs driven by the GIA, thereby extending the charging time of each row of TFTs driven by the GIA. This improves the transmission stability of the GIA signal and enhances the screen display performance. It should be noted that, due to the strong load-carrying capacity of the gate driver chip, appropriately reducing the charging time of each row of TFTs driven by the gate driver chip has a small impact on screen display performance. However, since the gate driver chip drives a larger number of TFT rows compared to the GIA-driven TFT rows, compensating for the time saved in the charging time of the TFTs driven by the gate driver chip with the charging time of the TFTs driven by the GIA will significantly increase the charging time of each row of TFTs driven by the GIA. It should be understood that in this design, the charging time of each row of TFTs driven by the GIA is greater than the charging time of each row of TFTs driven by the gate driver chip.

[0066] Taking a car screen with a resolution of 1920*1240 (3:2) and a refresh rate of 120Hz as an example, if unequal charging time is not used, the charging time T for each row of TFTs satisfies the formula: T=1 / 120 / (1240+60)=6.4 us. This charging time is relatively short, which may cause GIA to be unable to provide sufficient power to each row of TFTs within a short charging time. Therefore, an unequal charging time design can be adopted to extend the charging time of each row of TFTs driven by GIA.

[0067] As an example, the charging time design of the GIA 40-level can be equivalent to the charging time of each row of TFTs at a screen refresh rate of 60Hz, thus extending the charging time of each row of TFTs driven by the GIA to 12.8 µs. Correspondingly, the charging time of each row of TFTs driven by the gate driver chip can be appropriately reduced, assuming it is reduced to 6.2 µs. At this point, the charging time design of the gate driver chip 1200-level can be deduced as equivalent to the charging time of each row of TFTs at a screen refresh rate of 124Hz, such as f = 1 / (6.2 * (1240 + 60)) = 124Hz. The GIA 40-level charging time can be understood as the charging time of each row of TFTs in the 40 rows of TFTs driven by the GIA, and the gate driver chip 1200-level charging time can be understood as the charging time of each row of TFTs in the 1200 rows of TFTs driven by the gate driver chip.

[0068] Figure 10 This is a schematic diagram of another driving signal provided in this application. Figure 10 As shown, the charging time for the GIA 40th stage is T1, which is 12.8 μs, and the charging time for the gate driver chip 1200th stage is T2, which is 6.2 μs.

[0069] In this embodiment, due to its own circuit design and component characteristics, the GIA's driving capability for the TFT is weaker than that of the gate driver chip, resulting in a split-screen display issue, such as... Figure 11 As shown. To solve this problem, a chamfering circuit can be added to the gate driver chip to enable the gate driver chip to have a gate chamfering function, thereby reducing the VGH during shutdown, balancing the driving capabilities of the gate driver chip and GIA to the TFT, improving the problem of split-screen display, and enhancing the display performance of the screen. In the embodiments of this application, the driving capability of the GIA or gate driver chip to the TFT can also be referred to as the thrust of the GIA or gate driver chip.

[0070] Figure 12 A schematic diagram of the beveled circuit provided in this application. Figure 12 G-1 shown is the gate signal generated by the gate driver chip. For example... Figure 12 As shown, when the CPV signal is high, the PNP (positive-negative-positive) transistor is off, and G-1 is directly connected to G1 for output. When the CPV signal is low, the PNP transistor is on, and there are two scenarios: Scenario 1: If the output of the PNP transistor is connected to contact 1 of the switch (SW in the diagram), G-1, in addition to being connected to G1, will also be connected to an external resistor (R in the diagram) through the on-state PNP transistor. This causes G-1 to slowly discharge, thus lowering the off-state VGH until the CPV signal returns to high, the PNP transistor is off, and the discharge process of G-1 ends. It should be noted that the discharge rate of G-1 depends on the resistance value of the external resistor. Scenario 2: If the output of the PNP transistor is connected to contact 2 of the switch, G-1 will be connected to VGH through the PNP transistor. In this case, regardless of whether the PNP transistor is on or off, the gate chamfering function is off.

[0071] Figure 13 A schematic diagram illustrating the gate chamfering function provided in this application. (See diagram for reference.) Figure 13As shown, the gate driver chip can turn off the TFT gate at time T3, meaning the VGH signal starts switching to a low level at time T3. It can be seen that with the addition of the chamfering circuit, the VGH signal will begin to decrease slowly earlier at time T4, thus reducing the amount of VGH that is turned off. Furthermore, the magnitude of the decrease in VGH due to different resistance values ​​in the chamfering circuit also varies. For example, with resistance R=R1, the turned-off VGH is VGH1; with resistance R=R2, the turned-off VGH is VGH2; and with resistance R=R3, the turned-off VGH is VGH3. Where VGH1 > VGH2 > VGH3.

[0072] The present application also provides a display panel, which may include the array substrate described in the foregoing embodiments.

[0073] The present application also provides a display device, such as a display, which may include the display panel described in the foregoing embodiments.

[0074] It should be emphasized that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention shall still fall within the scope of the technical solution of the present invention.

Claims

1. An array substrate, characterized in that, The array substrate includes a non-display area and a display area. The non-display area is provided with a source driver chip, an integrated gate driver circuit, and a gate driver chip. The display area is provided with M rows of thin-film transistors, where M is a positive integer. The source driver chip is used to output a first control signal and a first clock signal to the gate driver chip, and to output a second control signal and a second clock signal to the integrated gate driver circuit, wherein the second control signal is a shutdown control signal; The gate driving chip is used to drive P consecutive rows of thin-film transistors in the M rows of thin-film transistors according to the first control signal and the first clock signal, where P is a positive integer less than M and P is greater than Q. The integrated gate driving circuit is also used to obtain a start control signal from the gate driving chip, wherein the start control signal is the last two levels of scan signals output by the gate driving chip to the display area; The integrated gate driving circuit is further configured to drive a continuous Q-row of thin-film transistors in the M-row thin-film transistors according to the second control signal, the start control signal, and the second clock signal, where Q is the difference between M and P. The thin-film transistors driven by the integrated gate driving circuit and the gate driving chip do not overlap, and the charging time of each row of thin-film transistors in the continuous P-row thin-film transistors is less than the charging time of each row of thin-film transistors in the continuous Q-row thin-film transistors.

2. The array substrate according to claim 1, characterized in that, The gate driver chip includes a chamfering circuit.

3. The array substrate according to claim 2, characterized in that, The gate driver chip and the integrated gate driver circuit are distributed on the same side or different sides of the array substrate.

4. The array substrate according to claim 3, characterized in that, The integrated gate driving circuits are multiple, and the integrated gate driving circuits are distributed on the upper and lower sides of the gate driving chip.

5. A display panel, characterized in that, The display panel includes an array substrate as described in any one of claims 1 to 4.

6. A display device, characterized in that, The display device includes the display panel as described in claim 5.

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