Wafer bifurcation deformation prediction method and device, electronic equipment and storage medium

Abstract

The embodiment of the present disclosure discloses a wafer bifurcation deformation prediction method and device, electronic equipment and storage medium, which belong to the technical field of semiconductor manufacturing. The wafer bifurcation deformation prediction method comprises: acquiring multiple surface morphologies of the wafer under different loads applied to the wafer; and predicting the bifurcation deformation tendency of the wafer according to the symmetry of the wafer under the multiple surface morphologies. The bifurcation deformation of the wafer is evaluated at the wafer manufacturing stage, so that the subsequent processing flow can be guided according to the evaluation result, such as adjusting the processing parameters or adopting a specific processing technology, thereby reducing the possibility of bifurcation deformation of the wafer in subsequent production.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method, apparatus, electronic device, and storage medium for predicting wafer bifurcation deformation. Background Technology

[0002] With the increasing demand for integration and storage capacity, the semiconductor manufacturing process requires stacking multiple layers of different materials on the wafer (such as 3D memory, which has a stacked structure of 32, 64 or even 128 layers).

[0003] As the number of stacked layers increases, the thermal expansion coefficients of the different stacked materials deposited on the wafer become mismatched. As the temperature decreases, the thin film and the substrate shrink at different rates. The residual stress generated within the wafer causes a deformation phenomenon where the center of the wafer bulges upward or downward, while the edges bend downward or upward. This wafer exhibits bifurcation deformation, also known as saddle warp. If the bending or warping of the wafer is too large, or if the warping varies in different directions, it will limit wafer processing and may even prevent the wafer from being processed on the same machine, increasing device manufacturing costs.

[0004] However, wafer bifurcation deformation usually does not occur during wafer manufacturing, but rather during semiconductor manufacturing. Therefore, there is a lack of a method to effectively predict and assess the tendency of wafer bifurcation deformation during wafer manufacturing. Summary of the Invention

[0005] In view of this, the present disclosure aims to provide a method, apparatus, electronic device, and storage medium for predicting wafer bifurcation deformation; capable of evaluating wafer bifurcation deformation during the wafer manufacturing stage.

[0006] The technical solution of this disclosure embodiment is implemented as follows: In a first aspect, embodiments of this disclosure provide a method for predicting wafer bifurcation deformation, comprising: obtaining multiple surface morphologies of the wafer under different loads; and predicting the tendency of the wafer to bifurcate based on the symmetry of the wafer under the multiple surface morphologies.

[0007] Secondly, embodiments of this disclosure provide a wafer bifurcation deformation prediction device, comprising: an acquisition part and a prediction part; the acquisition part is configured to acquire multiple surface morphologies of the wafer under different loads; the prediction part is configured to predict the bifurcation deformation tendency of the wafer based on the symmetry of the wafer under multiple surface morphologies.

[0008] Thirdly, embodiments of this disclosure provide an electronic device, the electronic device comprising: a processor and a memory; the processor is configured to execute instructions stored in the memory to implement the wafer bifurcation deformation prediction method described in the first aspect.

[0009] Fourthly, embodiments of this disclosure provide a computer storage medium storing at least one instruction, which is executed by a processor to implement the wafer bifurcation deformation prediction method as described in the first aspect.

[0010] This disclosure provides a method for predicting wafer bifurcation deformation, including: obtaining various surface morphologies of the wafer under different loads; and predicting the tendency of the wafer to undergo bifurcation deformation based on the symmetry of the wafer under various surface morphologies. In this disclosure, by applying different loads to the wafer, the deformation of the wafer under different stress conditions is simulated, and then the tendency of the wafer to undergo bifurcation deformation is predicted based on the symmetry of the wafer's surface morphology under different loads. This enables the evaluation of wafer bifurcation deformation during the wafer manufacturing stage, thereby guiding subsequent processing flows based on the evaluation results, such as adjusting processing parameters or adopting specific processing techniques, thereby reducing the possibility of bifurcation deformation in subsequently produced wafers. Attached Figure Description

[0011] Figure 1 This is a schematic diagram illustrating the deformation trend of a three-dimensional memory wafer, provided as an embodiment of this disclosure.

[0012] Figure 2 This is one of the flowcharts illustrating a wafer bifurcation deformation prediction method provided in an embodiment of this disclosure.

[0013] Figure 3 This is a schematic diagram of a vacuum suction cup provided in an embodiment of the present disclosure.

[0014] Figure 4 This is a schematic diagram showing different diameter directions selected for embodiments of this disclosure.

[0015] Figure 5 This is a second schematic flowchart of a wafer bifurcation deformation prediction method provided in an embodiment of this disclosure.

[0016] Figure 6 This is a schematic diagram of the structure of a wafer bifurcation deformation prediction device provided in an embodiment of this disclosure.

[0017] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure.

[0018] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0019] The technical solutions in the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0020] In the semiconductor manufacturing field, wafers are the core material for integrated circuit manufacturing, and their quality and performance directly affect the performance of the final product. With the development of integrated circuit manufacturing technology, especially the advancement of stacking process technology, higher requirements have been placed on the flatness and deformation control of wafers.

[0021] As the stacking process becomes more advanced, wafer deformation becomes increasingly difficult to control, such as Figure 1 The diagram illustrates the deformation trend of a 3D memory wafer. When the number of stacked layers is 32 or 64, the wafer hardly deforms. When the number of stacked layers increases to 96, the wafer begins to warp slightly. When the number of stacked layers continues to increase (corresponding to "More" in the diagram), the wafer undergoes severe deformation, exhibiting a saddle shape, which is often referred to in engineering as bifurcation deformation or saddle warping.

[0022] As shown in the figure, the wafer deformation deviates from symmetrical deformation. For symmetrical deformation, high-temperature annealing can be used to redistribute the stress inside the wafer, reducing deformation caused by inconsistent thermal expansion coefficients or stress introduced during processing. Alternatively, chemical mechanical polishing (CMP) can be used to polish the wafer surface to achieve global planarization, reducing symmetrical deformation caused by surface unevenness. Adding stress-buffering layers, such as silicon nitride or silicon oxide layers, to the wafer can absorb and redistribute stress, reducing deformation. However, for bifurcation deformation that deviates from symmetrical deformation, thermal annealing, which typically involves heating the entire wafer, is unsuitable for asymmetrical bifurcation deformation along the X and Y directions. Adding stress-buffering layers to the wafer, by depositing films of different thicknesses along the X and Y directions to optimize bifurcation deformation, results in an uneven surface, hindering wafer transfer via chucks. When using CMP to handle bifurcation deformation, improper control of polishing pressure or time can lead to over-polishing in some areas while under-polishing in others, causing further wafer deformation. Therefore, the post-processing of bifurcation deformation is very difficult, and there is an urgent need for a method that can assess the tendency of wafer bifurcation deformation during wafer manufacturing in order to optimize it during the manufacturing process.

[0023] However, bifurcation deformation does not usually occur during wafer manufacturing. Bifurcation deformation generally occurs in semiconductor manufacturing. Therefore, the assessment of the deformation tendency of silicon wafers mainly relies on the feedback from the semiconductor manufacturing process. During wafer manufacturing, there is a lack of effective assessment methods to predict and control this bifurcation deformation.

[0024] If it is necessary to evaluate the bifurcation deformation of the wafer during the wafer manufacturing stage, it is necessary to simulate the entire process flow of semiconductor manufacturing, which is neither economical nor practical in the wafer manufacturing process because it requires complex equipment and process adjustments.

[0025] Based on this, this disclosure first provides a wafer bifurcation deformation prediction method that can effectively assess wafer bifurcation deformation during the wafer manufacturing stage. Figure 2 A flowchart of a wafer bifurcation deformation prediction method is shown, which may include steps S210 and S220.

[0026] In step S210, various surface morphologies of the wafer are obtained under different loads.

[0027] A load refers to an external force or influence acting on a structure, material, or component. Different loads include at least two of the following: no load, symmetrical load, and asymmetrical load. No load refers to the state where no external force or stress acts on the wafer; that is, the wafer is not affected by any thin-film stress or mechanical stress and is in a free state. A symmetrical load refers to a uniform and symmetrical distribution of force or stress acting on the wafer. Symmetrical loads can be achieved through uniform thin-film stress, and the deformation of the silicon wafer under this type of load is also symmetrical. An asymmetrical load refers to an uneven distribution of force or stress acting on the silicon wafer, resulting in asymmetrical deformation of the silicon wafer. Asymmetrical loads are achieved through asymmetrical thin-film stress.

[0028] The surface morphology of a wafer changes when different loads are applied. The surface morphology of the wafer under different loads is obtained by measuring with an interferometer. In some feasible ways, the initial surface morphology of the wafer is obtained when no load is applied; the first surface morphology of the wafer is obtained when a symmetrical load is applied; and the second surface morphology of the wafer is obtained when an asymmetrical load is applied.

[0029] No load is applied to the wafer; that is, for the processed wafer, no deposited layer is attached, and the surface morphology of the wafer is directly measured by an interferometer. Here, the deposited layer refers to a layer of material formed on the wafer surface by various chemical or physical methods, such as depositing an oxide film (such as silicon dioxide) by atmospheric pressure chemical vapor deposition (APCVD) technology.

[0030] In some embodiments, applying a symmetrical load to a wafer can be achieved by uniformly depositing a layer on the entire wafer to obtain a wafer under symmetrical load, and then measuring the first surface morphology of the wafer under symmetrical load using an interferometer.

[0031] The purpose of uniformly depositing a layer on a wafer is to simulate the uniform stress that the wafer may encounter in actual use. Therefore, it is necessary to ensure that the thickness of the deposited layer is the same in all areas of the wafer under symmetrical loading, so as to ensure that uniform thin film stress is generated on the wafer under symmetrical loading, and thus ensure that the deformation of the wafer under symmetrical loading is also symmetrical.

[0032] In some embodiments, an asymmetric load is applied to the wafer. The preset area (a part of the wafer) under the symmetric load can be etched to obtain the wafer under the asymmetric load. The second surface morphology of the wafer under the asymmetric load is then measured by an interferometer.

[0033] The purpose of etching a predetermined area of ​​the wafer under symmetrical loading is to simulate the asymmetric stress that the wafer may encounter in actual use. Therefore, etching the predetermined area of ​​the wafer under symmetrical loading releases some of the stress, so that different regions of the wafer under asymmetric loading have different stresses, thereby ensuring that the deformation of the wafer under symmetrical loading is also symmetrical.

[0034] For example, such as Figure 3 The image shows a vacuum chuck with 2mm gaps distributed in the upper part of the chuck. The portion outside the 2mm gaps is the adsorption area, which is used to adsorb wafers. An etching solution (such as hydrofluoric acid) flows from the 2mm gaps to the wafer and reacts with the attached deposited layer, thereby removing the deposited layer on the wafer corresponding to the 2mm gap (corresponding to a preset area). The wafer portion corresponding to the adsorption area is not etched, thus achieving the purpose of relieving some stress.

[0035] In some embodiments, an asymmetric load is applied to the wafer, and deposited layers of different thicknesses are attached to different regions of the wafer to obtain a wafer under asymmetric load; then, the second surface morphology of the wafer under asymmetric load is obtained by measuring with an interferometer.

[0036] Specifically, the wafer is divided into at least two regions, and a deposition layer of different thickness is uniformly deposited on each region. For example, the wafer is divided into two regions, the first region is blocked, and a deposition layer is attached to the unblocked region; the wafer is divided into three regions, the first region is blocked, and a first deposition layer is attached to the unblocked second and third regions, and then the first and second regions are blocked again, and a second deposition layer is attached to the unblocked third region.

[0037] Thus, in a wafer under asymmetric loading, due to the different thicknesses of the attached deposition layer, the stresses experienced by each region are also different, thereby simulating the non-uniform stress that the wafer may encounter in actual use.

[0038] It should be noted that, for the same wafer, if a second morphology is obtained through etching, a deposition layer needs to be uniformly attached to the wafer first, the first morphology measured, and then etching performed to obtain the second morphology. If a second morphology is obtained by attaching deposition layers of different thicknesses, deposition layers of different thicknesses need to be attached to different areas of the wafer according to the settings, the second morphology measured, and then additional deposition layers of different thicknesses are deposited to make the thickness of each area the same, and the first morphology measured.

[0039] In step S220, the tendency of the wafer to bifurcate is predicted based on the symmetry of the wafer under various surface morphologies.

[0040] The symmetry of a wafer under various morphologies can be determined based on the overall curvature of the wafer, specifically by measuring the height difference between the wafer center and the edge; it can also be assessed by measuring the local and global geometry of the wafer surface using equipment such as atomic force microscopes or interferometers; or it can be determined by measuring the stress distribution inside the wafer using techniques such as X-ray diffraction or Raman spectroscopy, where the uniformity of the stress distribution can indicate the symmetry of the wafer. This disclosure does not limit the specific method for determining symmetry.

[0041] In some embodiments, predicting the bifurcation deformation tendency of a wafer based on the symmetry of the wafer under various surface morphologies includes: determining the curvature on multiple preset diameters under each surface morphology based on the various surface morphologies of the wafer, obtaining multiple sets of curvatures, each set of curvatures including the curvature on multiple preset diameters of the wafer under a surface morphology; and predicting the bifurcation deformation tendency of the wafer based on the multiple sets of curvatures.

[0042] The curvature of a wafer describes the degree of bending at a point on the wafer. For each surface morphology, several diameters in different directions are first determined, and several points are determined on each diameter. The curvature at these points is then calculated. A set of curvatures includes the curvature at multiple points in each of the multiple diameter directions.

[0043] Based on multiple sets of curvatures, the tendency of a wafer to undergo bifurcation deformation can be predicted. Specifically, this can involve determining the maximum and minimum values ​​of a set of curvatures corresponding to each surface morphology, and predicting the tendency of the wafer to undergo bifurcation deformation based on the ratio of the minimum to the maximum value. A smaller ratio indicates a higher probability of bifurcation deformation in the corresponding wafer, while a larger ratio indicates a lower probability of bifurcation deformation.

[0044] For example, such as Figure 4As shown, four diameters were pre-set: one along the X-axis, one along the Y-axis, one at 45 degrees, and one at 135 degrees. The curvature at several pre-set points was measured on each diameter. For the initial surface morphology, a set of curvatures determined on the four diameters was denoted as: K1-X, K1-45, K1-Y, K1-135. For the first surface morphology, a set of curvatures determined on the four diameters was denoted as: K2-X, K2-45, K2-Y, K2-135. For the second surface morphology, a set of curvatures determined on the four diameters was denoted as: K3-X, K3-45, K3-Y, K3-135, K... n This represents the curvature under a certain topography, where X, Y, 45, and 135 represent the diameter in different directions, and each "K" represents the curvature. n The "-diameter direction" includes curvature at multiple points. The symmetry a1 representing the wafer itself is determined as: abs(min(K1-X, K1-45, K1-Y, K1-135) / max(K1-X, K1-45, K1-Y, K1-135)×100%); the symmetry a2 representing wafer deformation under symmetrical loading is: abs(min(K2-X, K2-45, K2-Y, K2-135) / max(K2-X, K2-45, K2-Y, K2-135)×100%); and the symmetry a3 representing wafer deformation under asymmetrical loading is: abs(min(K3-X, K3-45, K3-Y, K3-135) / max(K3-X, K3-45, K3-Y, K3-135)×100%), where abs represents the absolute value.

[0045] In this embodiment, different loads are applied to the wafer to simulate its deformation under different stress conditions. Furthermore, the symmetry of the wafer's surface morphology under different loads is used to predict the tendency for bifurcation deformation. This allows for the evaluation of wafer bifurcation deformation during the wafer manufacturing stage, enabling subsequent processing steps to be guided based on the evaluation results, such as adjusting processing parameters or employing specific processing techniques, thereby reducing the likelihood of bifurcation deformation in subsequently produced wafers.

[0046] For wafers subjected to different loads, in order to ensure more accurate measurement of the wafer's surface morphology, the wafer needs to be cleaned before each measurement. Specifically, in some embodiments, such as... Figure 5 As shown, step S210 above obtains various surface morphologies of the wafer under different loads, which can be specifically achieved through the following steps S210a to S210c.

[0047] In step S210a, the wafer is pre-cleaned without applying a load.

[0048] In step S210b, while a load is applied to the wafer, the loaded wafer is post-cleaned.

[0049] In step S210c, various surface morphologies of the cleaned wafer are obtained.

[0050] The pre-cleaning process typically includes the following steps in sequence: ozone (O3), hydrofluoric acid (HF), standard cleaning solution 1 (SC1), standard cleaning solution 2 (SC2), and O3. O3 is a strong oxidant used to remove organic contaminants and some metal ions from the wafer surface. During the cleaning process, ozone decomposes into oxygen and atomic oxygen, which are highly reactive and effectively oxidize and remove organic matter. HF is a strong acid primarily used to remove the natural oxide layer (such as silicon dioxide) from the wafer surface. SC1 is a commonly used wafer cleaning solution, typically containing potassium hydroxide (KOH), water, and isopropanol (IPA). SC1 is mainly used to remove particles and certain types of organic contaminants. SC2 is another commonly used wafer cleaning solution, typically containing ammonium hydroxide (NH4OH), water, and hydrogen peroxide (H2O2). SC2 is used to remove organic and certain types of metal contaminants, and to further clean the wafer surface. Ozone is used again at the end of the cleaning process to further oxidize and remove any organic matter that may not have been completely removed in the previous steps, ensuring the cleanliness of the wafer surface.

[0051] The post-cleaning process includes: ozone (O3), standard cleaning solution 1 (SC1), standard cleaning solution 2 (SC2), and O3. HF is not included in the post-cleaning process to prevent the attached deposited layer from being etched away. Other cleaning processes included in the post-cleaning process can be found in the description of the pre-cleaning process above, and will not be repeated here.

[0052] Thus, through pre-cleaning and post-cleaning, impurities, oxide layers, and organic residues generated on the wafer surface during processing can be removed, ensuring that the measured surface morphology of the wafer is more accurate.

[0053] Furthermore, based on the same concept as the aforementioned wafer bifurcation deformation prediction method, and referring to... Figure 6 As shown, this example embodiment also provides a wafer bifurcation deformation prediction device 60, including an acquisition part 610 and a prediction part 620.

[0054] The acquisition part 610 is configured to acquire multiple surface morphologies of the wafer under different loads; the prediction part 620 is configured to predict the bifurcation deformation tendency of the wafer based on the symmetry of the wafer under multiple surface morphologies.

[0055] In one example implementation, the acquisition portion 610 is specifically configured to acquire an initial surface morphology of the wafer without applying a load; acquire a first surface morphology of the wafer when a symmetrical load is applied; and acquire a second surface morphology of the wafer when an asymmetrical load is applied.

[0056] In one example implementation, the acquisition portion 610 is specifically configured to uniformly attach a deposition layer to the wafer to obtain a wafer under symmetrical loading; and to acquire a first surface morphology of the wafer under symmetrical loading.

[0057] In one example implementation, the acquisition portion 610 is specifically configured to etch a preset region in a wafer under symmetric loading to obtain a wafer under asymmetric loading; and to acquire a second surface morphology of the wafer under asymmetric loading.

[0058] In one example implementation, the acquisition portion 610 is specifically configured to attach deposition layers of different thicknesses to different regions of the wafer to obtain a wafer under asymmetric loading; and to acquire a second surface morphology of the wafer under asymmetric loading.

[0059] In one example implementation, the prediction section 620 is specifically configured to determine the curvature on multiple preset diameters for each surface morphology of the wafer, thereby obtaining multiple sets of curvatures, each set of curvatures including the curvature on multiple preset diameters of the wafer for a surface morphology; and predict the bifurcation deformation tendency of the wafer based on the multiple sets of curvatures.

[0060] In one example implementation, the acquisition portion 610 is specifically configured to perform pre-cleaning on the wafer without applying a load; perform post-cleaning on the wafer with a load applied; and acquire various surface morphologies of the cleaned wafer.

[0061] It should be understood that the above-described device embodiments are merely illustrative, and the device disclosed herein can be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units, modules, or components may be combined, integrated into another system, or some features may be ignored or not executed.

[0062] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this disclosure can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.

[0063] In this embodiment, each part can implement the wafer bifurcation deformation prediction method provided in the above method embodiment and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0064] Please refer to Figure 7 This diagram illustrates a structural block diagram of an electronic device 700 provided in an exemplary embodiment of this disclosure. In some examples, the electronic device 700 may be at least one of devices such as a smartphone, smartwatch, desktop computer, laptop, virtual reality terminal, augmented reality terminal, wireless terminal, and laptop computer. The electronic device 700 has communication functions and can access wired or wireless networks. The electronic device 700 may refer to one of multiple terminals, and those skilled in the art will understand that the number of such terminals may be more or less. It is understood that the electronic device 700 undertakes the calculation and processing work of the technical solution of this disclosure, and the embodiments of this disclosure do not limit this aspect.

[0065] like Figure 7 As shown, the electronic device 700 may include at least one processor 710, a memory 720, and a communication interface 730.

[0066] The memory 720 is used to store programs. Specifically, the program may include program code, which includes computer operation instructions.

[0067] The memory 720 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0068] The processor 710 is used to execute computer execution instructions stored in the memory 720 to implement the wafer bifurcation deformation prediction method described in the foregoing method embodiments. The processor 710 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this disclosure.

[0069] The electronic device 700 may also include a communication interface 730, through which it can communicate and interact with external devices. In specific implementations, if the communication interface 730, memory 720, and processor 710 are implemented independently, they can be interconnected via a bus to complete communication. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc., but this does not imply that there is only one bus or one type of bus.

[0070] Optionally, in a specific implementation, if the communication interface 730, memory 720 and processor 710 are integrated on a single chip, then the communication interface 730, memory 720 and processor 710 can communicate through an internal interface.

[0071] This disclosure also provides a computer-readable storage medium, which may include various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory, a random access memory, a disk, or an optical disk. Specifically, the computer-readable storage medium stores program instructions, which are used in the wafer bifurcation deformation prediction method in the above embodiments.

[0072] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of an electronic device 700 reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device 700 to perform the wafer bifurcation deformation prediction method of the various embodiments described above.

[0073] Those skilled in the art will recognize that the functions described in the embodiments of this disclosure in one or more of the foregoing examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0074] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0075] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention applied herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not claimed herein.

[0076] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A wafer bifurcation deformation prediction method characterized by, include: Various surface morphologies of wafers were obtained by applying different loads to the wafers; Based on the symmetry of the wafer under the various surface morphologies, the tendency of the wafer to bifurcate and deform is predicted; The method of obtaining various surface morphologies of a wafer under different loads includes: The initial surface morphology of the wafer is obtained without applying a load. A first surface morphology of the wafer is obtained by applying a symmetrical load to the wafer; A second surface morphology of the wafer is obtained by applying an asymmetric load to the wafer; The method of predicting the bifurcation deformation tendency of the wafer based on the symmetry of the wafer under the various surface morphologies includes: Based on the various surface morphologies of the wafer, the curvature on multiple preset diameters under each surface morphology is determined to obtain multiple sets of curvatures, each set of curvatures including the curvature on multiple preset diameters of the wafer under one surface morphology; Based on the multiple sets of curvatures, the tendency of the wafer to bifurcate is predicted.

2. The wafer bifurcation deformation prediction method according to claim 1, characterized by, The step of obtaining the first surface morphology of the wafer under a symmetrical load includes: A uniformly deposited layer is attached to the wafer to obtain a wafer under symmetrical loading. Obtain the first surface morphology of the wafer under the symmetrical load.

3. The wafer bifurcation deformation prediction method according to claim 2, characterized by, The step of obtaining the second surface morphology of the wafer under an asymmetric load includes: A preset region in the wafer under symmetrical loading is etched to obtain a wafer under asymmetric loading. The second surface morphology of the wafer under the asymmetric load is obtained.

4. The wafer bifurcation deformation prediction method of claim 1, wherein, The step of obtaining the second surface morphology of the wafer under an asymmetric load includes: By attaching deposition layers of different thicknesses to different regions of the wafer, a wafer under asymmetric loading is obtained. The second surface morphology of the wafer under the asymmetric load is obtained.

5. The wafer bifurcation deformation prediction method of claim 1, wherein The method of obtaining various surface morphologies of a wafer under different loads includes: The wafer is pre-cleaned without applying a load; When a load is applied to the wafer, the loaded wafer is then post-cleaned. Various surface morphologies of the cleaned wafer are obtained.

6. A wafer bifurcation deformation prediction device characterized by comprising: include: Acquisition and prediction components; The acquisition section is configured to acquire various surface morphologies of the wafer under different loads. The prediction component is configured to predict the bifurcation deformation tendency of the wafer based on the symmetry of the wafer under the various surface morphologies. The acquisition section is specifically configured to acquire the initial surface morphology of the wafer without applying a load to the wafer; as well as, A first surface morphology of the wafer is obtained by applying a symmetrical load to the wafer; as well as, A second surface morphology of the wafer is obtained by applying an asymmetric load to the wafer; The prediction portion is specifically configured to determine the curvature on multiple preset diameters for each surface morphology of the wafer, thereby obtaining multiple sets of curvatures, each set of curvatures including the curvature on multiple preset diameters of the wafer for one surface morphology; and, Based on the multiple sets of curvatures, the tendency of the wafer to bifurcate is predicted.

7. An electronic device, comprising: It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the wafer bifurcation deformation prediction method as described in any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the wafer bifurcation deformation prediction method as described in any one of claims 1 to 6.

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