Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device may include: a channel structure; a gate structure on the channel structure; and a gate contact structure on the gate structure, the gate contact structure configured to receive a gate input signal, where the gate contact structure is part of the gate structure itself and is formed from the part of the gate structure.

Description

Technical Field

[0001] Apparatus and methods consistent with the disclosure relate to three-dimensionally stacked (3D stacked) semiconductor devices (also referred to as multi-stacked semiconductor devices). Background Art

[0002] In response to the increasing demand for integrated circuits with high device density and performance, 3D stacked semiconductor devices have been introduced. The 3D stacked semiconductor device may include a first transistor disposed at a first height and a second transistor disposed at a second height above the first height, wherein each of the two transistors may be a fin field effect transistor (FinFET), a nanosheet transistor, a fork sheet transistor, or any other type of transistor.

[0003] FinFET has one or more vertical fin structures arranged horizontally as a channel structure, at least three surfaces of the channel structure are surrounded by a gate structure, and the nanosheet transistor is characterized by vertically stacking one or more nanosheet channel layers as a channel structure on a substrate and a gate structure surrounding all four surfaces of each of the nanosheet channel layers. Nanosheet transistors are called gate-all-around (GAA) transistors, or multi-bridge channel field effect transistors (MBCFETs). A forksheet transistor is a combination of two nanosheet transistors with an insulating backbone structure in between. The nanosheet channel layer of each nanosheet transistor is formed at each side of the insulating backbone structure and passes through the gate structure in parallel with the backbone structure.

[0004] For 3D stacked semiconductor devices, as device density increases, the aspect ratio (or "height-width ratio" or "depth-width ratio") of gate structures and gate contact structures allowed to be formed in the 3D stacked semiconductor devices increases. In addition, due to the increase in short circuit risk and capacitance between the gate contact structure and other circuit elements such as source / drain contact structures and the capacitance between the gate contact structure and other circuit elements such as source / drain contact structures, the reduced contact-poly-pitch (CPP) and cell height and the high aspect ratio pose greater challenges in improving the yield of 3D stacked semiconductor devices.

[0005] The information disclosed in this background technology section has been known or derived by the inventor before or during the process of implementing the embodiments of the present application, or is technical information obtained in the process of implementing the embodiments. Therefore, it may contain information that does not form prior art known to the public. Summary of the invention

[0006] Aspects of the disclosure provide a semiconductor device and a method of manufacturing the semiconductor device in which a gate structure is reduced in height and a portion of the gate structure is formed as a gate contact structure.

[0007] According to one aspect of the disclosure, a semiconductor device is provided, which may include: a channel structure; a gate structure on the channel structure; and a gate contact structure on the gate structure, the gate contact structure being configured to receive a gate input signal, wherein the gate contact structure is part of the gate structure itself, and no connecting surface, interface or boundary is formed between the gate contact structure and the gate structure.

[0008] According to one aspect of the disclosure, a gate structure is formed of a gate dielectric layer, a work function metal layer, and a gate electrode, and the gate contact structure is part of the gate electrode.

[0009] According to one aspect of the disclosure, a semiconductor device is provided, which may include: a channel structure; a gate structure on the channel structure; and a gate contact structure on the gate structure, the gate contact structure being configured to receive a gate input signal, wherein the gate contact structure is part of the gate structure itself, and the gate contact structure includes a protrusion or column on the top surface of the gate structure.

[0010] According to one aspect of the disclosure, the gate structure includes a gate dielectric layer, a work function metal layer, and a gate electrode, and the top surface on which the protrusion or pillar is formed is a surface of the gate electrode.

[0011] According to one aspect of the disclosure, a method for manufacturing a semiconductor device is provided, the method may include: forming a gate structure on a channel structure; patterning the gate structure except for a portion so that the portion forms a protrusion on the gate structure; and connecting the protrusion to a metal layer, wherein the protrusion is a gate contact structure configured to receive a gate input signal for the semiconductor device, wherein the step of patterning the gate structure is performed by partially patterning the gate structure from the top except for the portion at a predetermined depth from the top. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The disclosed example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figures 1A to 1C A 3D stacked semiconductor device according to one or more embodiments is shown, in which a gate contact structure is formed on a gate structure, and source / drain contact structures are formed on source / drain regions at different heights, respectively.

[0014] Figure 2A and Figure 2BA 3D stacked semiconductor device including a gate contact structure that is part of the gate structure itself is shown according to one or more embodiments.

[0015] Figure 3A and Figure 3B A 3D stacked semiconductor device including a gate contact structure that is part of the gate structure itself is shown according to one or more other embodiments.

[0016] Figure 4A and Figure 4B A 3D stacked semiconductor device including a gate contact structure that is part of the gate structure itself is shown according to one or more other embodiments.

[0017] FIG. 5A to FIG. 5B arrive FIG. 13A to FIG. 13B A semiconductor device structure is shown after respective steps of manufacturing a 3D stacked semiconductor device including a gate contact structure as part of the gate structure itself according to one or more embodiments.

[0018] Figure 5A and Figure 5B A semiconductor device structure is shown in which a hard mask pattern is formed on a gate structure.

[0019] Fig. 6A and Figure 6B A semiconductor device structure is shown in which a gate structure is patterned based on a hard mask pattern to form a gate protrusion.

[0020] Fig. 7A and Figure 7B A semiconductor device structure is shown in which a gate capping structure is filled in a recess obtained by patterning the gate structure in a previous step to surround a gate protrusion.

[0021] Fig. 8A and Figure 8B A semiconductor device structure is shown in which a gate protrusion is partially patterned.

[0022] Fig. 9A and Fig. 9B A semiconductor device structure is shown in which a recess obtained by partial patterning of a gate protrusion is filled with an additional gate capping structure.

[0023] Fig. 10A and Fig. 10B A semiconductor device structure is shown in which an isolation structure is extended to cover an extended gate covering structure and a top surface of each of two source / drain regions at two different heights is exposed by the extended isolation structure.

[0024] Fig.11A and Fig. 11BA semiconductor device structure is shown in which a metal structure is formed to fill a recess that exposes top surfaces of two source / drain regions.

[0025] Fig. 12A and Fig. 12B A semiconductor device structure is shown patterned to expose a top surface of a gate protrusion and to form a source / drain contact structure.

[0026] Fig.13A and Fig. 13B A semiconductor device structure is shown where metal lines are formed to connect to a gate protrusion and source / drain contact structures.

[0027] Fig.14 A flow chart is shown for fabricating a semiconductor device including a gate contact structure that is part of the gate structure itself, according to one or more embodiments.

[0028] Fig.15 is a schematic block diagram showing an electronic device according to one or more embodiments, the electronic device comprising the above reference FIG. 5A to FIG. 5B arrive FIG. 13A to FIG. 13B and Fig.14 The manufactured FIG. 2A to FIG. 2B arrive FIG. 4A to FIG. 4B At least one of the 3D stacked semiconductor devices 20 , 30 , and 40 shown in FIG. DETAILED DESCRIPTION

[0029] The disclosed embodiments described herein are example embodiments, and therefore, the disclosure is not limited to this, but can be implemented in various other forms. It is not excluded that each of the embodiments provided in the following description is associated with one or more features of another example or another embodiment that is also provided herein or is not provided herein but is consistent with the disclosure. For example, even if the matters described in a specific example or embodiment are not described in an example or embodiment different from it, the matters may also be understood to be related to or combined with the different examples or embodiments, unless otherwise mentioned in its description. In addition, it should be understood that all descriptions of the disclosed principles, aspects, examples, and embodiments are intended to cover equivalents of their structures and functions. In addition, these equivalents should be understood to include not only currently known equivalents, but also equivalents developed in the future, that is, all devices invented to perform the same function regardless of their structure. For example, the channel layer, sacrificial layer, and isolation layer described herein may take different types or forms, as long as the disclosure is applicable to them.

[0030] It will be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an "element") of a semiconductor device is referred to as being "on," "over," "up," "under," "below," "under," "connected to," or "bonded to" another element of the semiconductor device, the element may be directly on, over, over, under, under, under, connected to, or bonded to the other element, or there may be one or more intermediate elements. Conversely, when an element of a semiconductor device is referred to as being "directly on," "directly over," "directly on," "directly under," "directly under," "directly under," "directly connected to," or "directly bonded to" another element of the semiconductor device, there are no intermediate elements. Throughout this disclosure, the same reference numerals refer to the same elements.

[0031] For ease of description, spatially relative terms such as "above", "above", "on", "below", "below", "below", "below", "below", "below", "left", "right", "lower left", "lower right", "upper left", "upper right", "center", "middle", etc. may be used herein to describe the relationship of one element to another or other elements as shown in the figure. It will be understood that in addition to the orientation depicted in the figure, the spatially relative terms are also intended to cover different orientations of the semiconductor device in use or operation. For example, if the semiconductor device in the figure is turned over, the element described as "below" or "below" another element will then be oriented as "above" the other element. Therefore, the term "below" can cover both the above and below orientations. The semiconductor device may be oriented otherwise (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein are interpreted accordingly. As another example, when the elements referred to as "left" elements and "right" elements are oriented differently, they can be "right" elements and "left" elements when the device or structure including these elements is oriented differently. Therefore, in the following description, the "left" element and the "right" element may also be referred to as the "first" element or the "second" element, as long as their structural relationship is clearly understood in the context of the description. Similarly, the term "lower" element and the "upper" element may be referred to as the "first" element and the "second" element, respectively, and the necessary description is used to distinguish the two elements.

[0032] It will be understood that although the terms "first," "second," "third," "fourth," "fifth," "sixth," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the disclosed teachings.

[0033] As used herein, expressions such as "at least one of..." when appended to (preceded to) a list of elements modify the entire list of elements rather than modifying the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. Herein, when the term "same" is used to compare the size of two or more elements, the term can cover "substantially the same" size.

[0034] It will also be understood that even if a particular step or operation of manufacturing a device or structure is described later than another step or operation, the step or operation may be performed no later than the other step or operation unless the other step or operation is described as being performed after the step or operation.

[0035] Many embodiments are described herein with reference to cross-sectional views, which are schematic illustrations of the embodiments (and intermediate structures). As such, variations from the shapes illustrated are expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments should not be construed as limited to the particular shapes of the regions shown herein, but rather are to include deviations in shapes due to, for example, manufacturing. The various regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of a region of the device and are not intended to limit the scope of the disclosure. In addition, in the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0036] For the sake of brevity, conventional elements, structures or layers of semiconductor devices including nanosheet transistors and materials forming the conventional elements, structures or layers may or may not be described in detail herein. For example, when a certain isolation layer or structure of a semiconductor device is not relevant to the novel features of an embodiment, the layer or structure and the materials forming the layer or structure may be omitted herein. In addition, when the materials forming the known structural elements of the semiconductor device are not relevant to the novel features of an embodiment, the description of those materials may be omitted herein. Here, the term "isolation" pertains to electrical insulation or electrical separation between structures, layers, components or regions in a corresponding device or structure.

[0037] Figures 1A to 1CA 3D stacked semiconductor device according to one or more embodiments is shown, in which a gate contact structure is formed on a gate structure, and source / drain contact structures are formed on source / drain regions at different heights, respectively.

[0038] Figure 1B and Figure 1C The intercepts are taken along the lines I-I' and II-II' respectively. Figure 1A A cross-sectional view of a 3D stacked semiconductor device as shown in FIG. Figure 1A To show the positional relationship between the gate structure, the gate contact structure, the source / drain region and the source / drain contact structure, Figure 1A Not shown Figure 1B and Figure 1C Some structural elements shown in FIG. 5 , such as isolation layers and back-end-of-line (BEOL) structures (such as metal lines).

[0039] like Figure 1A As shown in , the D1 direction is the channel length direction along which the current flows between two source / drain regions connected to each other by the channel structure, the D2 direction is the channel width direction or the cell height direction intersecting the D1 direction, and the D3 direction is the channel thickness direction intersecting the D1 direction and the D2 direction.

[0040] Reference Figures 1A to 1C , the 3D stacked semiconductor device 10 may include a plurality of first channel layers 110 and a plurality of second channel layers 120 above the plurality of first channel layers 110. The first channel layer 110 may be formed at a first height on the substrate 101, and the second channel layer 120 may be formed at a second height above the first height. Therefore, the first channel layer 110 may be disposed at a first height, and the second channel layer 120 may be disposed at a second height. The intermediate isolation structure 130 may be formed between the uppermost channel layer among the first channel layers 110 and the lowermost channel layer among the second channel layers 120. These channel layers 110 and 120 may have been epitaxially grown from the substrate 101. The first channel layer 110 may connect the first source / drain regions 135 to each other so that current flows between the first source / drain regions 135 under the control of the gate structure 125 surrounding the first channel layer 110. Similarly, the second channel layer 120 may connect the second source / drain regions 145 to each other so that current flows between the second source / drain regions 145 under the control of the gate structure 125 surrounding the second channel layer 120. The first source / drain regions 135 may be epitaxially grown from the first channel layer 110, and the second source / drain regions 145 may be epitaxially grown from the second channel layer 120.

[0041] Therefore, in the 3D stacked semiconductor device 10, the first channel layer 110 together with the first source / drain region 135 and the gate structure 125 can form a first transistor 10L at a first height, and the first transistor 10L is a nanosheet transistor. In addition, the second channel layer 120 together with the second source / drain region 145 and the gate structure 125 can form a second transistor 10U at a second height, and the second transistor 10U is also a nanosheet transistor.

[0042] The substrate 101 may be a silicon (Si) substrate. Additionally or alternatively, the substrate 101 may include other materials, such as silicon germanium (SiGe), siliconized carbon (SiC), but is not limited thereto. The first channel layer 110 and the second channel layer 120 may each be formed of silicon (Si) or silicon germanium (SiGe). The first source / drain region 135 and the second source / drain region 145 may also be formed of Si or SiGe. However, when the first source / drain region 135 is formed of Si and doped with n-type impurities (such as phosphorus (P), arsenic (As), antimony (Sb), etc.), the first transistor 10L may be an n-type transistor. In contrast, when the second source / drain region 145 is formed of SiGe and doped with p-type impurities (such as boron (B), gallium (Ga), indium (In), etc.), the second transistor 10U may be a p-type transistor.

[0043] A shallow isolation trench (STI) structure 103 may be formed on the upper left corner and the upper right corner of the substrate 101, and an isolation structure 141 may be formed on the STI structure 103. The STI structure 103 and the isolation structure 141 may isolate the 3D stacked semiconductor device 10 from another 3D stacked semiconductor device or circuit element. The STI structure 103 and the isolation structure 141 may each be made of silicon oxide (SiO, SiO 2 The intermediate isolation structure 130 may be formed of silicon nitride (eg, SiN, SiBCN, SiCN, SiOCN, etc.).

[0044] The gate structure 125 may include a gate dielectric layer 125I, a first work function metal layer 125L, a second work function metal layer 125U, and a gate electrode 125E. The gate structure 125 may have a height H1 in the D3 direction, and the height H1 may be the height of the gate electrode 125E. The gate dielectric layer 125I may include an interface layer and a high-k dielectric layer formed on the interface layer. The interface layer may be formed on each of the channel layers 110 and 120 to protect the channel layers 110 and 120 and promote the growth of the high-k dielectric layer thereon, and the high-k dielectric layer may be formed on the interface layer to allow increased gate capacitance without associated current leakage from the gate structure 125. For these purposes, the interface layer may include an oxide material, such as silicon oxide (SiO or SiO 2) and / or silicon oxynitride (SiON), but not limited thereto, and the high-k dielectric layer may include a high-k material, which may include Hf, Al, Zr, La, Mg, Ba, Ti, Pb and / or a combination thereof, but not limited thereto.

[0045] The first work function metal layer 125L may be formed on the gate dielectric layer 125I surrounding the first channel layer 110 to control the gate threshold voltage of the first transistor 10L, and the second work function metal layer 125U may be formed on the gate dielectric layer 125I surrounding the second channel layer 120 to control the gate threshold voltage of the second transistor 10U. Each of the first work function metal layer 125L and the second work function metal layer 125U may be formed of a metal-containing material such as Ti, Ta, Al, W, TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, and / or a combination thereof, but is not limited thereto. However, the first work function metal layer 125L of the first transistor 10L and the second work function metal layer 125U of the second transistor 10U may be formed of different materials when the two transistors have different polarity types (i.e., n-type and p-type, respectively). When the first transistor 10L has an n-type and the second transistor 10U has a p-type, the first work function metal layer 125L may be formed of Al or TiC, and the second work function metal layer 125U may be formed of TiN.

[0046] Although the first transistor 10L and the second transistor 10U have different first and second work metal layers 125L and 125U, respectively, the two work metal layers 125L and 125U may be surrounded by the same gate electrode 125E to form the two transistors 10L and 10U as a CMOS device, such as an inverter circuit. The gate electrode 125E may be formed of Cu, W, Al, Ru, Mo, Co, and / or a combination thereof, but is not limited thereto.

[0047] The gate capping structure 126 may be formed on the gate structure 125 to protect the gate structure 125. The gate capping structure 126 may be formed of silicon nitride (eg, SiN, SiBCN, SiCN, SiOCN, etc.).

[0048] A gate contact structure CB1 having a height T1 may be formed on the gate structure 125 to pass through the gate cover structure 126 and be connected to a metal line M11 formed on the gate contact structure CB1. The gate structure 125 may receive a gate input signal from the metal line M11 through the gate contact structure CB1. Similarly, a first source / drain contact structure CA11 may be formed on the first source / drain region 135, and a second source / drain contact structure CA12 may be formed on the second source / drain region 145. The first source / drain contact structure CA11 and the second source / drain contact structure CA12 may connect the first source / drain region 135 and the second source / drain region 145 to one or more voltage sources or another circuit element for internal signal routing (routing) through metal lines M12 and M13, respectively. The gate contact structure CB1 and the source / drain contact structures CA11 and CA12 may be formed of a metal that is the same as or similar to the metal forming the gate electrode 125E. However, since the gate contact structure CB1 and the gate electrode 125E are two different, separate structures formed in different steps, a connection surface (or interface) may be formed between the two structures. In addition, a barrier metal layer may be formed at the connection surface (or interface) to enhance adhesion between the two structures and reduce contact resistance between the two structures. The barrier metal layer may be formed of TiN, TaN, etc.

[0049] Figures 1A to 1C It is shown that the second channel layer 120 is formed to have a width smaller than that of the first channel layer 110 in the D2 direction, and therefore, the second source / drain region 145 grown from the second channel layer 120 has a width smaller than that of the first source / drain region 135 grown from the first channel layer 110 in the D2 direction. This width difference is provided so that the first source / drain contact structure CA11 extending straight downward from the metal line M12 can be formed on the top surface of the first source / drain region 135. This is because, when the second source / drain region 145 has a larger or equal width than the first source / drain region 135 therebelow, there is no space for connecting the first source / drain contact structure CA11 to the top surface of the first source / drain region 135.

[0050] Meanwhile, since the 3D stacked semiconductor device 10 is configured to provide a high device density in a limited nanoscale area, the size of the gate structure 125 is minimized in the D2 direction to have a cell height CH in the D2 direction (shown in FIG. Figure 1A Therefore, if Figure 1AAs shown in FIG. 1 , the gate contact structure CB1 may inevitably be formed on the gate structure 125 within the cell height CH. In addition, since the 3D stacked semiconductor device 10 provides the first transistor 10L and the second transistor 10U, which can each be a nanosheet transistor, at two different heights, Figure 1B and Figure 1C As shown in , the entire device structure may have a high aspect ratio. Therefore, there is a high risk of etching / deposition misalignment between the gate contact structure CB1 and the gate structure 125, which may cause a short circuit between the gate contact structure CB1 and other circuit elements including at least one of the source / drain contact structures CA11 and CA12.

[0051] The following embodiments provide a 3D stacked semiconductor device that can solve the above-mentioned misalignment and short circuit risks.

[0052] Figure 2A and Figure 2B A 3D stacked semiconductor device including a gate contact structure that is part of the gate structure itself is shown according to one or more embodiments. Figure 2A and Figure 2B is with Figure 1B and Figure 1C A cross-sectional view of a corresponding 3D stacked semiconductor device.

[0053] Reference Figure 2A and Figure 2B In addition to the gate electrode 125F, the gate contact structure CB2, and the source / drain contact structures CA21 and CA22, the 3D stacked semiconductor device 20 may include Figures 1A to 1C The 3D stacked semiconductor device 10 includes the same structural elements as the structural elements included in the 3D stacked semiconductor device 10. Therefore, while omitting repeated descriptions of the same structural elements, different aspects of the 3D stacked semiconductor device 20 considering the 3D stacked semiconductor device 10 are described below.

[0054] In the 3D stacked semiconductor device 20, the gate contact structure CB2 is not a separate structure formed on the gate structure 125, but can be a protrusion or column (hereinafter referred to as "protrusion" or "gate protrusion") of the gate structure 125 that protrudes upward by a height T2 in the D3 direction. The gate protrusion can be a part of the gate structure 125 itself (that is, a part of the gate electrode 125F itself), and therefore, the gate protrusion and the gate electrode 125F can be a single continuous structure without any connection surface, interface, boundary, barrier or barrier metal layer between the gate contact structure CB2 and the gate electrode 125F. For example, the gate protrusion can be formed by a part of the gate structure 125 itself (for example, a part of the gate electrode 125F itself).

[0055] Since the gate protrusion adopts a protrusion, the top surface of the gate structure 125 (e.g., the gate electrode 125F) may not be flat, not flat, or substantially not flat or flat. In this case, the uppermost surface of the gate structure 125 may be or may correspond to the uppermost surface of the gate electrode 125F (e.g., the top surface or uppermost surface of the gate protrusion). The protrusion of the gate electrode 125F may be connected to the metal line M11 as a gate contact structure and is laterally surrounded by the gate cap structure 126. For example, the gate cap structure 126 may be disposed on the lateral side of the protrusion of the gate electrode 125F (i.e., the gate contact structure CB2).

[0056] As will be described later, the height T2 of the gate protrusion of the gate structure 125 may be smaller than the height T1 of the gate contact structure CB1 of the 3D stacked semiconductor device 10. In addition, the gate structure 125 of the 3D stacked semiconductor device 20 may have a height H2 that is smaller than the height H1 of the gate structure 125 of the 3D stacked semiconductor device 10. Therefore, due to the gate structure 125 shortened in height including the gate contact structure CB2, an area gain may be achieved, and in the process of manufacturing the 3D stacked semiconductor device 20, the risk of misalignment between the gate contact structure CB2 and the metal line M11 may be reduced.

[0057] As the height of the gate structure 125 decreases, the heights of the source / drain contact structures CA21 and CA22 in the 3D stacked semiconductor device 20 may also be shortened in the D3 direction compared to the heights of the source / drain contact structures CA11 and CA12 in the 3D stacked semiconductor device 10. Therefore, the height of the isolation structure 141 in the 3D stacked semiconductor device 20 may also be formed to be smaller than the height of the isolation structure 141 in the 3D stacked semiconductor device 10 in the D3 direction.

[0058] The above structural characteristics of the 3D stacked semiconductor device 20 can provide device density and area gain. In addition, due to the gate contact structure CB2 as part of the gate structure 125 itself, the 3D stacked semiconductor device 20 can omit a separate gate contact structure (such as the gate contact structure CB1 of the 3D stacked semiconductor device 10), thereby making the process of manufacturing the 3D stacked semiconductor device 20 simpler. In addition, the gate structure 125 and the source / drain contact structures CA21 and CA22 that are shortened in height can enable the 3D stacked semiconductor device 20 to have a smaller aspect ratio, which can reduce the risk of forming misaligned gate contact structures CB2 and source / drain contact structures CA21 and CA22, thereby also reducing the risk of short circuits between the gate contact structure CB2 and the source / drain contact structures CA21 and CA22. Due to the smaller size of the gate contact structure CB2 and the source / drain contact structures CA21 and CA22, the capacitance between the gate contact structure CB2 and the source / drain contact structures CA21 and CA22 can also be reduced. Furthermore, since a connection surface, an interface, a barrier, or a barrier metal layer may not be formed between the gate contact structure CB2 and the gate electrode 125F, the gate contact structure CB2 and the gate electrode 125F may have no or minimal contact resistance therebetween.

[0059] In the above embodiments, Figure 2A As shown in FIG. 1 , a gate protrusion (ie, a gate contact structure CB) of the gate structure 125 is formed in a central portion of the gate structure 125. However, the disclosure is not limited to the above embodiment, and the gate protrusion may be formed at a different portion of the gate structure 125 according to one or more embodiments.

[0060] At the same time, Figures 1A to 1C Similar to the gate electrode 125E of the 3D stacked semiconductor device 10 shown in , the gate electrode 125F of the 3D stacked semiconductor device 20 may also be a common gate electrode surrounding both the first work function metal layer 125L and the second work function metal layer 125U. However, the disclosure is not limited thereto, and the first work function metal layer 125L and the second work function metal layer 125U may be surrounded by respective gate electrodes isolated from each other, in which case the gate contact structure CB2 may be formed as a protrusion surrounding the gate electrode of the second work function metal layer 125U, and may be configured to receive a gate input signal for the second transistor 10U. In this case, a separate gate contact structure may be formed on the gate electrode surrounding the first work function metal layer 125L to receive a gate input signal for the first transistor 10L.

[0061] Figure 3A and Figure 3BA 3D stacked semiconductor device including a gate contact structure that is part of the gate structure itself is shown according to one or more other embodiments. Figure 3A and Figure 3B is with Figure 2A and Figure 2B The corresponding cross-sectional view.

[0062] Reference Figure 3A and Figure 3B , except that the gate electrode 125G has a protrusion at a different position, the 3D stacked semiconductor device 30 may have Figure 2A and Figure 2B The 3D stacked semiconductor device 20 has the same structural elements as the structural elements in the 3D stacked semiconductor device 20. That is, in the 3D stacked semiconductor device 30, the protrusion of the gate electrode 125G as the gate contact structure CB3 is not formed from the central portion of the gate electrode 125G, but is formed from the left portion of the gate electrode 125G.

[0063] However, the gate structure 125 and the source / drain contact structures CA21 and CA22 that are shortened in height may still help increase device density and area gain, reduce capacitance and resistance, lower the risk of misalignment and short circuits, and achieve a simple manufacturing process.

[0064] Meanwhile, as described below, the gate protrusion may be formed such that the overall height of the gate structure is further reduced.

[0065] Figure 4A and Figure 4B A 3D stacked semiconductor device including a gate contact structure that is part of the gate structure itself is shown according to one or more other embodiments. Figure 4A and Figure 4B is with Figure 2A and Figure 2B The corresponding cross-sectional view.

[0066] Reference Figure 4A and Figure 4B , except that the protrusion of the gate electrode 125H as the gate contact structure CB4 is connected to the work function metal layer (eg, the second work function metal layer 125U) of the gate structure 125, the 3D stacked semiconductor device 40 may have the same Figure 2A and Figure 2B The structural elements in the 3D stacked semiconductor device 20 are identical structural elements.

[0067] When the gate structure 125 is formed such that the gate protrusion starts from the height of the top surface of the second work function metal layer 125U, the overall height H3 of the gate structure 125 of the 3D stacked semiconductor device 40 may become smaller than the overall height H2 of the gate structure 125 of the 3D stacked semiconductor device 20. In addition, the source / drain contact structures CA21 and CA22 may also be further shortened.

[0068] However, the gate structure 125 and the source / drain contact structures CA21 and CA22 that are shortened in height may still help increase device density and area gain, reduce capacitance and resistance, lower the risk of misalignment and short circuits, and achieve a simple manufacturing process.

[0069] A method of manufacturing a 3D stacked semiconductor device corresponding to the 3D stacked semiconductor device 20 according to one or more embodiments is provided herein below.

[0070] FIG. 5A to FIG. 5B arrive FIG. 13A to FIG. 13B A semiconductor device structure is shown after respective steps of manufacturing a 3D stacked semiconductor device including a gate contact structure as part of the gate structure itself according to one or more embodiments.

[0071] Since the 3D stacked semiconductor device manufactured through the various steps shown below can be Figure 2A and Figure 2B The 3D stacked semiconductor device 20 shown in FIG. 1 is the same as, or may be the same as Figure 2A and Figure 2B The 3D stacked semiconductor device 20 shown in FIG. 1 corresponds to the 3D stacked semiconductor device 20 shown in FIG. 1 , and thus a repeated description thereof may be omitted, and the same reference numerals may be used in the following description.

[0072] Figure 5A and Figure 5B A semiconductor device structure is shown in which a hard mask pattern is formed on a gate structure.

[0073] Reference Figure 5A , the semiconductor device structure 20' may include a first channel layer 110, an intermediate isolation structure 130, and a second channel layer 120 stacked on a substrate 101 and surrounded by a gate structure 125. The gate structure 125 may be surrounded by an isolation structure 141. In addition, the semiconductor device structure 20' may include a first source / drain region 135 and a second source / drain region 145 respectively connected to the first channel layer 110 and the second channel layer 120 and isolated from each other by the isolation structure 141.

[0074] The gate structure 125 may include a gate dielectric layer 125I, a first work function metal layer 125L, a second work function metal layer 125U, and a gate electrode 126F. The gate dielectric layer 125I may surround each of the first channel layer 110 and the second channel layer 120. The first work function metal layer 125L may surround the gate dielectric layer 125I on the first channel layer 110, and the second work function metal layer 125U may surround the gate dielectric layer 125I on the second channel layer 120. The gate electrode 125F may receive a common gate input signal for a 3D stacked semiconductor device that will be completed based on the 3D stacked semiconductor device structure 20'.

[0075] As reference Figures 1A to 1C As described, the second channel layer 120 may have a channel width smaller than that of the first channel layer 110 , and therefore, the second source / drain region 145 may have a width smaller than that of the first source / drain region 135 to facilitate the first source / drain contact structure CA11 to be formed on the top surface of the first source / drain region 135 .

[0076] A hard mask pattern 151 may be formed on a top surface of the gate electrode 125F of the gate structure 125. The hard mask pattern 151 may be formed by, for example, photolithography and etching operations so that the hard mask pattern 151 is disposed on the top surface of the gate electrode 125F at a portion where a gate contact structure will be formed thereunder in a later step. The hard mask pattern 151 may include a dielectric material such as silicon nitride (SiN), titanium nitride (TiN), or silicon oxynitride (SiON), but is not limited thereto.

[0077] Fig. 6A and Figure 6B A semiconductor device structure is shown in which a gate structure is patterned based on a hard mask pattern to form a gate protrusion.

[0078] Reference Fig. 6A , the gate electrode 125F may be partially patterned with a depth DEP based on the hard mask pattern 151 to form two recesses R1 and R2. Therefore, the gate electrode 125F may have a protrusion P between the two recesses R1 and R2 under the hard mask pattern 151. The protrusion P may be so named because it protrudes relative to the top surface of the gate structure 125 where the gate electrode 125F above is partially removed.

[0079] The protrusion P of the gate electrode 125F may have a height equal to the depth DEP of the two recesses R1 and R2 .

[0080] The patterning operation in this step may be performed by, for example, dry etching or wet etching that selectively etches the gate electrode 125F with respect to the hard mask pattern 151 and the isolation structure 141 surrounding the gate structure 125 .

[0081] Fig. 7A and Figure 7B A semiconductor device structure is shown in which a gate capping structure is filled in a recess obtained by patterning the gate structure in a previous step to surround a gate protrusion.

[0082] Reference Fig. 7A and Figure 7B A gate capping structure 126 may be formed in each of the recesses R1 and R2 by depositing silicon nitride (e.g., SiN, SiBCN, SiCN, SiOCN, etc.) via, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or a combination thereof, followed by planarization such as chemical mechanical polishing (CMP), but is not limited thereto.

[0083] After forming the gate capping structure 126 in each of the recesses R1 and R2 , the protrusion P of the gate electrode 125F may be surrounded by the gate capping structure 126 , and a top surface of the protrusion P may be horizontally aligned or coplanar with a top surface of the gate capping structure 126 .

[0084] Fig. 8A and Figure 8B A semiconductor device structure is shown in which a gate protrusion is partially patterned.

[0085] Reference Fig. 8A and Figure 8B , the protrusion P of the gate electrode 125F may be partially etched back, so that a recess R3 may be formed between the gate capping structures 126 on the etched protrusion P. The partial etching in this step may be performed by photolithography, masking, and dry and / or wet etching (but not limited thereto), so that the etched protrusion P of the gate electrode 125F may have a height T2. The height of the protrusion P of the gate electrode 125F may define a gate contact structure of a 3D stacked semiconductor device to be formed based on the semiconductor device structure 20'.

[0086] Fig. 9A and Fig. 9B A semiconductor device structure is shown in which a recess obtained by partial patterning of a gate protrusion is filled with an additional gate capping structure.

[0087] Reference Fig. 9A and Fig. 9BThe recess R3 obtained by partial etching of the protrusion P of the gate electrode 125F in the previous step may be filled with an additional gate covering structure of silicon nitride (e.g., SiN, SiBCN, SiCN, SiOCN, etc.) by, for example, PVD, CVD, PECVD, or a combination thereof and subsequent planarization such as CMP, but is not limited thereto. Therefore, the protrusion P of the gate electrode 125F may be completely covered by the extended gate covering structure 126.

[0088] Fig. 10A and Fig. 10B A semiconductor device structure is shown in which an isolation structure is extended to cover an extended gate covering structure and a top surface of each of two source / drain regions at two different heights is exposed by the extended isolation structure.

[0089] Reference Fig. 10A and Fig. 10B , an additional isolation structure may be formed on the existing isolation structure 141 and the extended gate covering structure 126, so that the extended isolation structure may be formed to surround the first source / drain region 135 and the second source / drain region 145. The extended gate covering structure 126 may also be covered by the extended isolation structure 141. The formation of the additional isolation structure may be performed by, for example, PVD, CVD, PECVD, or a combination thereof and subsequent planarization such as CMP, but is not limited thereto.

[0090] Furthermore, the extended isolation structure 141 may be subjected to, for example, photolithography, masking, and dry and / or wet etching to form recesses R4 and R5 in the extended isolation structure 141 that expose top surfaces of the first and second source / drain regions 135 and 145 , respectively.

[0091] Fig.11A and Fig. 11B A semiconductor device structure is shown in which a metal structure is formed to fill a recess that exposes top surfaces of two source / drain regions.

[0092] Reference Fig.11A and Fig. 11B , a metal or a metal compound may be deposited on the semiconductor device structure 20′ obtained in the previous step so that the metal or the metal compound may be filled in the recesses R4 and R5 to contact the top surface of the first source / drain region 135 and the top surface of the second source / drain region 145. The deposition of the metal or the metal compound may be performed by, for example, PVD, CVD, PECVD, or a combination thereof and subsequent planarization such as CMP, but is not limited thereto.

[0093] Fig. 12A and Fig. 12B A semiconductor device structure is shown patterned to expose a top surface of a gate protrusion and to form a source / drain contact structure.

[0094] Reference Fig. 12A and Fig. 12B The metal or metal compound deposited in the previous step, the extended isolation structure 141, and the extended gate covering structure 126 can be etched back to expose the top surface of the protrusion P of the gate electrode 125F, and a first source / drain contact structure and a second source / drain contact structure CM are formed on the first source / drain region 135 and the second source / drain region 145, respectively.

[0095] The etch-back operation in this step may be performed by, for example, dry etching, wet etching, ashing, and / or stripping, but is not limited thereto.

[0096] Fig.13A and Fig. 13B A semiconductor device structure is shown in which metal lines are formed to connect to a gate protrusion and source / drain contact structures.

[0097] Reference Fig.13A and Fig. 13B , a BEOL layer including metal lines M11 to M13 may be formed on the semiconductor device structure 20' obtained in the previous step, such that the metal line M11 is connected to the protrusion P of the gate electrode 125F (now the gate contact structure CB2), and the metal lines M12 and M13 are respectively connected to the contact structure CM (now the first source / drain contact structure CA21 and the second source / drain contact structure CA22).

[0098] The formation of the BEOL layer including the metal lines M11 to M13 may be performed by, for example, one or more damascene operations, but is not limited thereto.

[0099] Therefore, it is possible to produce Figure 2A and Figure 2B The 3D stacked semiconductor device 20 shown in FIG. 1 is the same as or corresponds to the 3D stacked semiconductor device 20 shown in FIG. Here, as previously described, the gate contact structure CB2 is a portion of the gate electrode 125F of the gate structure 125 .

[0100] Although the manufacturing and Figure 2A and Figure 2B The 3D stacked semiconductor device 20 shown in FIG. 1 is a method for manufacturing a 3D stacked semiconductor device, but the method can also be applied to manufacturing FIG. 3A to FIG. 3B The 3D stacked semiconductor device 30 shown in FIG. FIG. 4A to FIG. 4B The 3D stacked semiconductor device 40 is shown in FIG.

[0101] Fig.14 A flow chart is shown for fabricating a semiconductor device including a gate contact structure that is part of the gate structure itself, according to one or more embodiments.

[0102] In step S10 , a semiconductor device structure is provided, in which a gate structure surrounds a channel structure on a substrate.

[0103] When the semiconductor device to be manufactured is a 3D stacked semiconductor device, the channel structure may include a first channel structure formed on a substrate and a second channel structure formed on the first channel structure. The gate structure may include a first work function metal layer and a second work function metal layer surrounding the first channel structure and the second channel structure, respectively. The gate structure may also include a gate electrode surrounding the first work function metal layer and the second work function metal layer. The gate electrode may be a common gate electrode configured to receive a common gate input signal for a 3D stacked semiconductor device.

[0104] In step S20 , the gate electrode may be partially removed from the top to form a protrusion or a pillar on the gate electrode.

[0105] The partial removal of the gate electrode can be performed by, for example, photolithography / masking / etching operations based on a hard mask pattern formed on the top surface of the gate electrode where the gate contact structure is to be formed. Therefore, the gate electrode can be removed to a predetermined depth except for a portion of the gate electrode under the hard mask pattern.

[0106] In step S30, a gate covering structure may be formed on the space provided by partially removing the gate electrode, and based on the gate covering structure, a portion of the protrusion may be removed from the top so that the protrusion is formed into a gate contact structure of the semiconductor device structure, which will receive a gate input signal for the semiconductor device to be completed from the semiconductor device structure.

[0107] In step S40 , a BEOL layer may be formed on the gate contact structure, and the gate contact structure may be connected to a metal line included in the BEOL layer.

[0108] Therefore, since a portion of the gate electrode is formed as a gate contact structure for the semiconductor device, the semiconductor device manufactured based on the above process can omit a separate gate contact structure.

[0109] Fig.15 is a schematic block diagram showing an electronic device according to one or more embodiments, the electronic device comprising FIG. 2A to FIG. 2B arrive FIG. 4A to FIG. 4B The 3D stacked semiconductor devices 20, 30 and 40 shown in FIG. FIG. 5A to FIG. 5B arrive FIG. 13A to FIG. 13B and Fig.14 At least one of the fabricated 3D stacked semiconductor devices.

[0110] Reference Fig.15, the electronic device 1000 may include at least one processor 1100, a communication module 1200, an input / output module 1300, a storage device 1400, and a buffer random access memory (RAM) module 1500. According to an embodiment, the electronic device 1000 may be a mobile device such as a smart phone or a tablet computer, but is not limited thereto.

[0111] The processor 1100 may include a central processing unit (CPU), a graphics processing unit (GPU), and / or any other processor that controls the operation of the electronic device 1000. The communication module 1200 may be implemented to perform wireless or wired communication with an external device. The input / output module 1300 may include at least one of a touch sensor, a touch panel, a keyboard, a mouse, a proximity sensor, a microphone, etc. for receiving input, and at least one of a display, a speaker, etc. for generating an output signal processed by the processor 1100. The storage device 1400 may be implemented to store user data, output signals, etc. input through the input / output module 1300. The storage device 1400 may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash memory (UFS) device, etc.

[0112] The buffer RAM module 1500 may temporarily store data used for processing operations of the electronic device 1000. For example, the buffer RAM module 1500 may include a volatile memory such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0113] Despite Fig.15 Although not shown in the figure, the electronic device 1000 may further include at least one sensor, such as an image sensor.

[0114] According to one or more embodiments, at least one component in the electronic device 1000 may be based on FIG. 2A to FIG. 2B arrive FIG. 4A to FIG. 4B The 3D stacked semiconductor devices 20, 30 and 40 shown in FIG. FIG. 5A to FIG. 5B arrive FIG. 13A to FIG. 13B and Fig.14 The fabricated 3D stacked semiconductor device is formed.

[0115] In the above embodiments, each of the gate contact structures as part of the gate structure itself is formed for a 3D stacked semiconductor device. However, according to one or more other embodiments, the gate contact structure may also be formed for a single stack or single level transistor.

[0116] In the above embodiments, each of the 3D stacked semiconductor devices includes a transistor at a second height having a channel structure with a shorter width and a source / drain region with a shorter width than the transistor at the first height. However, each of the gate contact structures according to the above embodiments may also be formed in a semiconductor device in which the transistor at the first height and the transistor at the second height have a channel structure with the same width and a source / drain region with the same width.

[0117] In the above embodiments, each of the 3D stacked semiconductor devices includes a common gate electrode for both the transistor at the first height and the transistor at the second height, although the transistor at the first height and the transistor at the second height may have different work function metal layers. However, each of the gate contact structures according to the above embodiments may also be formed in such a semiconductor device in which the transistor at the first height and the transistor at the second height have separate gate electrodes isolated from each other. In this case, the gate contact structure of the above embodiment can be used for the gate electrode of the transistor at the second height.

[0118] In the above embodiments, each of the 3D stacked semiconductor devices is described as including one or more nanosheet transistors. However, each of the gate contact structures according to the above embodiments may also be formed in such a semiconductor device including different types of transistors, such as FinFETs, fork-sheet transistors, etc.

[0119] The foregoing is a description of example embodiments and is not to be construed as limiting the disclosure. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the above embodiments without materially departing from the disclosure.

Claims

1. A semiconductor device comprising: Channel structure; Gate structure, on the channel structure; as well as a gate contact structure, on the gate structure, the gate contact structure being configured to receive a gate input signal, Therein, the gate contact structure is part of the gate structure itself and is formed by said part of the gate structure.

2. The semiconductor device according to claim 1, wherein The gate contact structure includes a protrusion protruding above a top surface of the gate structure.

3. The semiconductor device according to claim 2, wherein: The gate structure includes a gate dielectric layer, a work function metal layer and a gate electrode, and The surface from which the protrusion starts to protrude from the top surface of the gate structure is at a height above the top surface of the work function metal layer.

4. The semiconductor device according to claim 2, wherein: The gate structure includes a gate dielectric layer, a work function metal layer and a gate electrode, and The surface from which the protrusions start protruding is at a height of a top surface of the work function metal layer.

5. The semiconductor device according to claim 1, wherein The gate structure includes a gate dielectric layer, a work function metal layer and a gate electrode, and The gate contact structure is part of the gate electrode itself. 6 . The semiconductor device of claim 1 , further comprising a gate capping structure on a lateral side of the gate contact structure.

7. The semiconductor device according to claim 1, wherein The channel structure includes a first channel structure disposed at a first height and a second channel structure disposed at a second height above the first height, The gate structure includes a first work function metal layer on the first channel structure and a second work function metal layer on the second channel structure. Wherein, the gate structure further includes a gate electrode on the second work function metal layer, and The gate contact structure is part of the gate electrode itself, and no connection surface, interface or boundary is formed between the gate contact structure and the gate electrode.

8. The semiconductor device according to claim 7, wherein: The gate electrode covers at least a portion of the first channel structure and at least a portion of the second channel structure.

9. The semiconductor device according to claim 1, wherein: The top surface of the gate structure is not flat.

10. A semiconductor device comprising: Channel structure; Gate structure, on the channel structure; as well as a gate contact structure, on the gate structure, the gate contact structure being configured to receive a gate input signal, Wherein the gate contact structure is part of the gate structure itself, and The gate contact structure includes a protrusion on a top surface of the gate structure.

11. The semiconductor device according to claim 10, wherein The gate structure includes a gate dielectric layer, a work function metal layer and a gate electrode, and The uppermost surface of the gate structure is the uppermost surface of the gate electrode.

12. The semiconductor device according to claim 10, wherein: The gate structure includes a gate dielectric layer, a work function metal layer and a gate electrode, and The gate contact structure is a part of the gate electrode.

13. The semiconductor device according to claim 12, wherein: The surface from which the protrusions protrude is at a height above the top surface of the work function metal layer.

14. The semiconductor device according to claim 10, wherein: The channel structure includes a first channel structure disposed at a first height and a second channel structure disposed at a second height above the first height, The gate structure includes a first work function metal layer and a second work function metal layer respectively on the first channel structure and the second channel structure. The gate structure further includes a gate electrode at least on the second work function metal layer, and The gate contact structure is part of the gate electrode itself, and no connection surface, interface or boundary is formed between the gate contact structure and the gate electrode.

15. The semiconductor device according to claim 10, wherein The top surface of the gate structure is not flat.

16. A method for manufacturing a semiconductor device, the method comprising: forming a gate structure on the channel structure; patterning the gate structure so that a protrusion is formed on the gate structure; as well as Connect the protrusions to the metal layer, The protrusion is configured to receive a gate input signal for the semiconductor device.

17. The method according to claim 16, wherein: The steps of patterning the gate structure include: forming a hard mask pattern on a top surface of a portion of the gate structure; and Portions of the gate structure are removed.

18. The method according to claim 16, wherein: The step of patterning the gate structure includes partially patterning the gate structure at a predetermined depth from a top surface of the gate structure.

19. The method according to claim 16, wherein: The gate structure includes a gate dielectric layer, a work function metal layer and a gate electrode, and The step of patterning the gate structure is performed on the gate dielectric layer, the work function metal layer and the gate electrode.

20. The method according to claim 16, wherein: The gate structure includes a gate dielectric layer, a work function metal layer and a gate electrode, and The gate contact structure is a part of the gate electrode.

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