Clock signal generation system, generation method and audio conversion chip

Abstract

The application discloses a clock signal generation system, a generation method and an audio conversion chip. The system comprises a delay-locked loop, a clock edge acquisition module, a counter and at least one first clock generation module. The first clock generation module is connected with the delay-locked loop and the counter, and is used for screening pulse signals of a frequency multiplication clock signal and an inverse frequency multiplication clock signal based on a count value to generate a first target clock signal. The application screens the frequency multiplication clock signal and the inverse frequency multiplication clock signal by the first clock generation module to generate the first target clock signal, realizes the generation of multiple clock signals with different frequencies under the condition of low cost, meets the demand of a multiple input clock system, and adopts digital circuit logic processing to reduce the hardware circuit cost of the chip.

Description

Technical Field

[0001] This invention belongs to the field of audio conversion chip technology, specifically relating to a clock signal generation system, generation method, and audio conversion chip. Background Technology

[0002] Taking an audio ADC (Analog-to-digital converter) chip using Delta-Sigma technology as an example, the analog front end typically generates sampled audio data through oversampling and Delta-Sigma noise shaping technology, while the digital back end uses a decimation algorithm to convert the oversampled audio data into data at one time the audio sampling rate.

[0003] There are many types of decimation algorithms, each with different characteristics: some are simple to implement and consume few resources, but have poor bandwidth flatness and are not adjustable; others are complex to implement and consume many resources, but have adjustable bandwidth. To fully utilize the advantages of various types of decimation filters, audio ADC chips are typically composed of multiple cascaded decimation filters with different characteristics.

[0004] For example, audio ADC chips typically include comb-type CIC decimation filters and FIR decimation filters. In practice, the input clock requirements for CIC filters, FIR filters, and the ADC analog front-end modules differ. Most audio ADC chips internally use a PLL (Phase Lock Loop) as a frequency multiplier. Based on the clock requirements of each module within the audio ADC chip, the PLL generates an ideal multiplied clock using its frequency multiplication capability. This clock is then divided by appropriate clock logic and provided to the various modules of the audio ADC chip.

[0005] However, a PLL module typically has a relatively large area, accounting for a significant proportion of the total area of ​​the audio ADC chip. If we don't want to use a large PLL as a clock multiplier, and instead use a clock multiplier with insufficient multiplication capability but a very small hardware area, such as a DLL (Delay Lock Loop) clock multiplier, it's difficult to directly use the multiplier's output clock or a divided clock to meet the clock requirements of each module.

[0006] Therefore, in order to address the above-mentioned technical problems, it is necessary to provide a clock signal generation system, a generation method, and an audio conversion chip. Summary of the Invention

[0007] The purpose of this invention is to provide a clock signal generation system, generation method, and audio conversion chip, which can simultaneously generate multiple clock signals that meet different clock requirements, while reducing circuit area overhead.

[0008] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0009] A clock signal generation system, the system comprising:

[0010] A delay phase-locked loop is used to generate a frequency-multiplied clock signal and an inverted frequency-multiplied clock signal based on the input clock signal and frequency multiplication configuration parameters.

[0011] The clock edge acquisition module, connected to the delay phase-locked loop, is used to delay the input clock signal according to the period of the frequency multiplier clock signal to generate a delayed clock signal, and to generate a clock edge pulse signal based on the delayed clock signal and the input clock signal.

[0012] The counter, connected to the clock edge acquisition module, is used to generate a count value based on two adjacent pulses in the clock edge pulse signal.

[0013] At least one first clock generation module, connected to a delay phase-locked loop and a counter, is used to filter the pulse signals of the frequency-doubled clock signal and the inverted frequency-doubled clock signal based on the count value to generate a first target clock signal.

[0014] In one or more embodiments of the present invention, the system further includes a pre-division module connected to a delay phase-locked loop (PLL) for dividing the input clock signal and generating an input clock division signal. The delay PLL generates a multiplied clock signal based on the input clock division signal and multiplication configuration parameters.

[0015] In one or more embodiments of the present invention, the first clock generation module includes a first register, a first clock filtering unit, and a first logic unit; wherein...

[0016] The first register is connected to a counter and is used to generate a first control word and a second control word based on clock configuration parameters and the count value.

[0017] The first clock filtering unit is connected to the first register and the delay phase-locked loop, and is used to generate a first window signal based on the first control word and the frequency multiplier clock signal, and to generate a second window signal based on the second control word and the inverted frequency multiplier clock signal;

[0018] The first logic unit is connected to a counter and is used to filter the pulse signal of the frequency multiplier clock signal based on the first window signal to generate a first output signal, filter the pulse signal of the inverted frequency multiplier clock signal based on the second window signal to generate a second output signal, and generate a first target clock signal based on the first output signal and the second output signal.

[0019] In one or more embodiments of the present invention, when the control bit of the first control word is 0, the first window signal is at a low level between the falling edge of the clock signal period corresponding to the control bit and the next adjacent falling edge; when the control bit of the first control word is 1, the first window signal is at a high level between the falling edge of the clock signal period corresponding to the control bit and the next adjacent falling edge.

[0020] When the control bit of the second control word is 0, the second window signal is at a low level during the period of the inverted frequency multiplier clock signal corresponding to the control bit; when the control bit of the second control word is 1, the second window signal is at a high level during the period of the inverted frequency multiplier clock signal corresponding to the control bit.

[0021] In one or more embodiments of the present invention, the clock generation system further includes a second clock generation module, the second clock generation module including a second register, a second clock filtering unit, and a second logic unit; wherein,

[0022] The second register is connected to a counter and is used to generate a third control word based on clock configuration parameters and the count value;

[0023] The second clock filtering unit is connected to the second register and the delay phase-locked loop, and is used to generate a third window signal based on the third control word and the frequency multiplier clock signal;

[0024] The second logic unit is connected to a counter and is used to generate a second target clock signal based on the third window signal and the input clock signal.

[0025] Another specific embodiment of the present invention provides the following technical solution:

[0026] A method for generating a clock signal, the method comprising:

[0027] Obtain the input clock signal and frequency multiplication configuration parameters;

[0028] A delay phase-locked loop generates a frequency-multiplied clock signal and an inverted frequency-multiplied clock signal based on the input clock signal and frequency multiplication configuration parameters.

[0029] The clock edge acquisition module delays the input clock signal according to the period of the frequency multiplication clock signal to generate a delayed clock signal, and generates a clock edge pulse signal based on the delayed clock signal and the input clock signal.

[0030] A counter generates a count value based on two adjacent pulses in a clock edge pulse signal;

[0031] A first target clock signal is generated by filtering the pulse signals of the frequency-doubled clock signal and the inverted frequency-doubled clock signal based on the count value by at least one first clock generation module.

[0032] In one or more embodiments of the present invention, the method further includes:

[0033] The input clock signal is divided by the pre-division module to generate the input clock divided signal;

[0034] A frequency-multiplied clock signal is generated by a delay phase-locked loop based on the input clock division signal and the frequency multiplication configuration parameters.

[0035] In one or more embodiments of the present invention, the method further includes:

[0036] The first control word and the second control word are generated by the first register based on the clock configuration parameters and the count value.

[0037] The first window signal is generated by the first clock filtering unit based on the first control word and the frequency multiplier clock signal, and the second window signal is generated based on the second control word and the inverted frequency multiplier clock signal.

[0038] The first logic unit filters the pulse signal of the frequency multiplication clock signal based on the first window signal to generate a first output signal, filters the pulse signal of the inverted frequency multiplication clock signal based on the second window signal to generate a second output signal, and generates a first target clock signal based on the first output signal and the second output signal.

[0039] In one or more embodiments of the present invention, the clock generation method includes:

[0040] When the control bit of the first control word is 0, the first window signal is at a low level from the falling edge of the clock signal period corresponding to the control bit to the next adjacent falling edge. When the control bit of the first control word is 1, the first window signal is at a high level from the falling edge of the clock signal period corresponding to the control bit to the next adjacent falling edge.

[0041] When the control bit of the second control word is 0, the second window signal is at a low level during the period of the inverted frequency multiplier clock signal corresponding to the control bit; when the control bit of the second control word is 1, the second window signal is at a high level during the period of the inverted frequency multiplier clock signal corresponding to the control bit.

[0042] In one or more embodiments of the present invention, the method further includes:

[0043] The third control word is generated by the second register based on the clock configuration parameters and the count value;

[0044] The third window signal is generated by the second clock filtering unit based on the third control word and the frequency multiplier clock signal;

[0045] The second target clock signal is generated by the second logic unit based on the third window signal and the input clock signal.

[0046] Another specific embodiment of the present invention provides the following technical solution:

[0047] An audio conversion chip, the audio conversion chip comprising a clock signal generation system, an analog front end, and at least one first decimation filter as described in any embodiment; wherein,

[0048] The analog front end is connected to the clock signal generation system and is used to receive the analog audio signal and oversample the analog audio signal based on the first target clock signal to generate the first sampled signal.

[0049] The first decimation filter is connected to the clock signal generation system and the analog front end, and is used to generate a second sampling signal based on the first sampling signal and the first target clock signal.

[0050] In one or more embodiments of the present invention, the audio conversion chip further includes a second decimation filter, which is connected to the clock generation system and the first decimation filter, and is used to generate a digital audio signal based on a second sampling signal and a second target clock signal.

[0051] Compared with the prior art, the clock signal generation system, generation method and audio conversion chip of the present invention, through the first clock generation module, filters the frequency multiplication clock signal and the inverted frequency multiplication clock signal to generate the first target clock signal, thereby realizing the simultaneous generation of multiple clock signals of different frequencies under low cost conditions and meeting the requirements of multi-input clock systems.

[0052] Digital circuit logic processing is used, which reduces the overhead of chip hardware circuitry. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a structural diagram of the clock signal generation system in Embodiment 1 of the present invention;

[0055] Figure 2 This is a structural diagram of the first clock signal generation module in Embodiment 1 of the present invention;

[0056] Figure 3 This is a timing diagram of the clock signal in Embodiment 1 of the present invention;

[0057] Figure 4 This is a timing diagram of the clock signal in Embodiment 1 of the present invention;

[0058] Figure 5 This is a structural diagram of the clock signal generation system in Embodiment 2 of the present invention;

[0059] Figure 6 This is a structural diagram of the second clock signal generation module in Embodiment 2 of the present invention;

[0060] Figure 7 This is a timing diagram of the clock signal in Embodiment 2 of the present invention;

[0061] Figure 8 This is a structural diagram of the clock signal generation system in Embodiment 3 of the present invention;

[0062] Figure 9 This is a structural diagram of the audio conversion chip in Embodiment 4 of the present invention;

[0063] Figure 10 This is a flowchart of the clock signal generation method in Embodiment 5 of the present invention. Detailed Implementation

[0064] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0065] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0066] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in this invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0067] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0068] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0069] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0070] Various components and devices may be referred to or shown in the singular (e.g., “MOS transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0071] The description uses the phrases "in this embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous.

[0072] Example 1:

[0073] like Figure 1 As shown, this embodiment provides a clock signal generation system, which includes a delay phase-locked loop 10, a clock edge acquisition module 20, a counter 30, and at least one first clock generation module 40.

[0074] Delayed phase-locked loop 10 is used to generate a frequency-multiplied clock signal Nx_clk and an inverted frequency-multiplied clock signal inv_Nx_clk based on the input clock signal in_clk and the frequency multiplication configuration parameters;

[0075] The clock edge acquisition module 20 is connected to the delay phase-locked loop 10. It is used to delay the input clock signal in_clk according to the period of the frequency multiplication clock signal Nx_clk to generate the delayed clock signal dly_in_clk, and generate the clock edge pulse signal inclk_edge based on the delayed clock signal dly_in_clk and the input clock signal in_clk.

[0076] Counter 30 is connected to clock edge acquisition module 20 and is used to generate a count value Nxclk_count based on two adjacent pulses in the clock edge pulse signal inclk_edge.

[0077] At least one first clock generation module 40, connected to the delay phase-locked loop 10 and the counter 30, is used to filter the pulse signals of the frequency multiplier clock signal Nx_clk and the inverted frequency multiplier clock signal inv_Nx_clk based on the count value Nxclk_count to generate the first target clock signal out_clk.

[0078] like Figure 2 As shown, the first clock generation module 40 in this embodiment includes a first register 41, a first clock filtering unit 42, and a first logic unit 43.

[0079] Specifically, the first register 41 is connected to the counter 30 and is used to generate the first control word CW1 and the second control word CW2 based on the clock configuration parameters and the count value Nxclk_count.

[0080] The first clock filtering unit 42 is connected to the first register 41 and the delay phase-locked loop 10, and is used to generate a first window signal Nx_clk_m based on the first control word CW1 and the frequency multiplier clock signal Nx_clk, and to generate a second window signal inv_Nx_clk_m based on the second control word CW2 and the inverted frequency multiplier clock signal inv_Nx_clk.

[0081] The first logic unit 43 is connected to the counter 30 and is used to filter the pulse signal of the frequency multiplier clock signal Nx_clk based on the first window signal Nx_clk_m to generate a first output signal m_Nx_clk1, filter the pulse signal of the inverted frequency multiplier clock signal inv_Nx_clk based on the second window signal inv_Nx_clk_m to generate a second output signal m_inv_Nx_clk1, and generate a first target clock signal out_clk based on the first output signal m_Nx_clk1 and the second output signal m_inv_Nx_clk1.

[0082] When the control bit of the first control word CW1 is 0, the first window signal Nx_clk_m is at a low level from the falling edge of the clock signal Nx_clk corresponding to the control bit to the next adjacent falling edge. When the control bit of the first control word CW1 is 1, the first window signal Nx_clk_m is at a high level from the falling edge of the clock signal Nx_clk corresponding to the control bit to the next adjacent falling edge.

[0083] When the control bit of the second control word CW2 is 0, the second window signal inv_Nx_clk_m is at a low level during the period of the inverted frequency multiplier clock signal inv_Nx_clk corresponding to the control bit. When the control bit of the second control word CW2 is 1, the second window signal inv_Nx_clk_m is at a high level during the period of the inverted frequency multiplier clock signal inv_Nx_clk corresponding to the control bit.

[0084] like Figure 3 As shown, the requirements for generating the first target clock signal out_clk1 based on the clock configuration parameters are: the first target clock signal out_clk1 is four times the frequency of the input clock signal in_clk, and the low-level pulse width is twice the high-level pulse width within one clock cycle of the first target clock signal out_clk1.

[0085] Specifically, the input clock signal in_clk is a 1x clock signal with a 6x frequency multiplication parameter. Therefore, the delay phase-locked loop 10 generates a 6x clock signal Nx_clk based on the input clock signal in_clk, and inverts the 6x clock signal Nx_clk to obtain the inverted 6x clock signal inv_Nx_clk.

[0086] The clock edge acquisition module 20 delays the input clock signal in_clk according to the period of the frequency multiplier clock signal Nx_clk to generate a delayed clock signal dly_in_clk. The delayed clock signal dly_in_clk is delayed by one period of the frequency multiplier clock signal Nx_clk relative to the input clock signal in_clk. The clock edge pulse signal inclk_edge is generated based on the delayed clock signal dly_in_clk and the input clock signal in_clk. Specifically, when the input clock signal in_clk is high and the delayed clock signal dly_in_clk is low, the clock edge pulse signal inclk_edge is high. In other cases (i.e., when the input clock signal in_clk is low and the delayed clock signal dly_in_clk is low, or when the input clock signal in_clk is high and the delayed clock signal dly_in_clk is high, or when the input clock signal in_clk is high and the delayed clock signal dly_in_clk is high), the clock edge pulse signal inclk_edge is low.

[0087] It is understood that at the falling edge of the high-level pulse of the clock pulse signal inclk_edge, counter 30 starts counting forward from 0, and the count value generated by counter 30 is incremented by 1 in each cycle of the frequency multiplication clock signal Nx_clk. At the falling edge of the next adjacent high-level pulse of the clock pulse signal inclk_edge, the current counting round ends, and counter 30 restarts counting forward from 0. It is understood that the count value generated in each round corresponds to the preset frequency multiplication period. For example, in this embodiment, the frequency multiplication clock signal Nx_clk is 6 times the frequency, that is, relative to the input clock signal in_clk, the frequency multiplication clock signal Nx_clk appears for 6 cycles within one cycle of the input clock signal in_clk. Therefore, the counting period of counter 30 is 6, that is, counter 30 counts from 0 to 5, and starts counting forward from 0 again at the falling edge of the next high-level pulse of the clock pulse signal inclk_edge. It is understood that the count value generated by counter 30 corresponds to the frequency of the frequency multiplication clock signal Nx_clk.

[0088] The first register 41 generates a first control word CW1 and a second control word CW2 based on the clock configuration parameters and the count value Nxclk_count. The number of bits in the first control word CW1 and the second control word CW2 is equal to the count value Nxclk_count generated by the counter 30. For example, if the count value is 8 (i.e., 0 to 7), then the first register 41 generates an 8-bit first control word CW1 and a second control word CW2. In this embodiment, if the count value is 6 (i.e., 0 to 5), then both the first control word CW1 and the second control word CW2 are 6 bits.

[0089] When the control bit of the first control word CW1 is 0, the first window signal Nx_clk_m is at a low level from the falling edge of the clock signal Nx_clk corresponding to the control bit to the next adjacent falling edge. When the control bit of the first control word CW1 is 1, the first window signal Nx_clk_m is at a high level from the falling edge of the clock signal Nx_clk corresponding to the control bit to the next adjacent falling edge. This can also be understood as follows: In this embodiment, when the control bit of the first control word CW1 is 0, the first window signal Nx_clk_m is at a low level during the clock signal Nx_clk corresponding to the control bit; when the control bit of the first control word CW1 is 1, the first window signal Nx_clk_m is at a high level during the clock signal Nx_clk corresponding to the control bit, and the first window signal Nx_clk_m is delayed by half a clock signal Nx_clk cycle relative to the clock signal Nx_clk.

[0090] When the control bit of the second control word CW2 is 0, the second window signal inv_Nx_clk_m is at a low level during the period of the inverted frequency multiplier clock signal inv_Nx_clk corresponding to the control bit. When the control bit of the second control word CW2 is 1, the second window signal inv_Nx_clk_m is at a high level during the period of the inverted frequency multiplier clock signal inv_Nx_clk corresponding to the control bit.

[0091] like Figure 3 As shown, taking a 6-bit control word as an example: In this embodiment, the first control word CW1 is set to 010010 based on the clock configuration parameters, with the 0th, 2nd, 3rd and 5th control bits being 0, and the 1st and 4th control bits being 1. The 0th, 1st, 2nd, 3rd, 4th and 5th control bits of the first control word CW1 correspond to the count values ​​0, 1, 2, 3, 4 and 5, respectively.

[0092] The first window signal Nx_clk_m1 is low between the falling edge of the clock signal Nx_clk period T0 (when the count value Nxclk_count is 0) and the next adjacent falling edge (i.e., the falling edge within the clock signal Nx_clk period T1). The first window signal Nx_clk_m1 is high between the falling edge of the clock signal Nx_clk period T1 (when the count value Nxclk_count is 1) and the next adjacent falling edge (i.e., the falling edge within the clock signal Nx_clk period T2). The first window signal Nx_clk_m1 is low between the falling edge of the clock signal Nx_clk period T1 (when the count value Nxclk_count is 2) and the next adjacent falling edge (i.e., the falling edge within the clock signal Nx_clk period T2), and so on. Figure 3 The first window signal Nx_clk_m1 is shown.

[0093] It is understandable that, because the first window signal Nx_clk_m1 is delayed relative to the count value Nxclk_count, that is, when the control bit of the first control word CW1 is 0, the first window signal Nx_clk_m1 is low within the period of the frequency multiplier clock signal Nx_clk corresponding to that control bit; when the control bit of the first control word CW1 is 1, the first window signal Nx_clk_m1 is high within the period of the frequency multiplier clock signal Nx_clk corresponding to that control bit, and the first window signal Nx_clk_m1 is delayed by half a frequency multiplier clock signal Nx_clk relative to the frequency multiplier clock signal Nx_clk, the following is obtained: Figure 3 The first window signal Nx_clk_m1 is shown.

[0094] In this embodiment, the second control word CW2 is set to 001001 based on the clock configuration parameters, with the 1st, 2nd, 4th and 5th control bits being 0 and the 0th and 3rd control bits being 1. The 0th, 1st, 2nd, 3rd, 4th and 5th control bits of the second control word CW2 correspond to the count values ​​0, 1, 2, 3, 4 and 5, respectively.

[0095] The second window signal inv_Nx_clk_m1 is high during the period T0 of the frequency multiplier clock signal Nx_clk when the count value Nxclk_count is 0, and low during the period T1 of the frequency multiplier clock signal Nx_clk when the count value Nxclk_count is 1, and so on, to obtain... Figure 3 The second window signal inv_Nx_clk_m1 is shown.

[0096] The first logic unit 43 is connected to the counter 30 and is used to filter the pulse signal of the frequency multiplier clock signal Nx_clk based on the first window signal Nx_clk_m1 to generate the first output signal m_Nx_clk1, filter the pulse signal of the inverted frequency multiplier clock signal inv_Nx_clk based on the second window signal inv_Nx_clk_m1 to generate the second output signal m_inv_Nx_clk1, and generate the first target clock signal out_clk1 based on the first output signal m_Nx_clk1 and the second output signal m_inv_Nx_clk1.

[0097] Furthermore, in this embodiment, the first logic unit 43 performs an AND operation on the first window signal inv_Nx_clk_m1 and the frequency multiplier clock signal Nx_clk to obtain the first output signal m_Nx_clk1, performs an AND operation on the second window signal inv_Nx_clk_m1 and the inverted frequency multiplier clock signal inv_Nx_clk to obtain the second output signal m_inv_Nx_clk1, and performs an OR operation on the first output signal m_Nx_clk1 and the second output signal m_inv_Nx_clk1 to generate the first target clock signal out_clk1.

[0098] like Figure 4 As shown, a first target clock signal out_clk2 needs to be generated based on another clock configuration parameter. Therefore, in this embodiment, another first clock generation module 40 is connected to the delay phase-locked loop 10 and the counter 30. It is used to filter the pulse signals of the frequency multiplication clock signal Nx_clk and the inverted frequency multiplication clock signal inv_Nx_clk based on the count value to generate the corresponding other first target clock signal out_clk2.

[0099] Based on another clock configuration parameter, the first control word CW1 is set to 110110, control bits 0 and 3 are 0, and control bits 1, 2, 4, and 5 are 1. The first window signal Nx_clk_m2 is low between the falling edge of the frequency multiplier clock signal Nx_clk period T0 corresponding to a count value of 0 and the next adjacent falling edge (i.e., the falling edge of the frequency multiplier clock signal Nx_clk period T1). The first window signal Nx_clk_m2 is high between the falling edge of the frequency multiplier clock signal Nx_clk period T1 corresponding to a count value of 1 and the next adjacent falling edge (i.e., the falling edge of the frequency multiplier clock signal Nx_clk period T2), and so on, to obtain... Figure 4 The first window signal Nx_clk_m2 is shown. It can be understood that because the first window signal Nx_clk_m2 is delayed relative to the count value, that is, when the 0 control bit of the first control word CW1 is 0, the first window signal Nx_clk_m2 is low within the period of the frequency multiplier clock signal Nx_clk corresponding to that control bit; when the 1 control bit of the first control word CW1 is 1, the first window signal Nx_clk_m2 is high within the period of the frequency multiplier clock signal Nx_clk corresponding to that control bit. Furthermore, the first window signal Nx_clk_m2 is delayed by half a frequency multiplier clock signal Nx_clk relative to the frequency multiplier clock signal Nx_clk, thus obtaining... Figure 4 The first window signal Nx_clk_m2 is shown.

[0100] In this embodiment, the second control word CW2 is set to 000000 based on the clock configuration parameters, and all control bits are 0. The second window signal inv_Nx_clk_m2 is low during the period T0 of the frequency multiplication clock signal Nx_clk corresponding to a count value of 0. Therefore, the following is obtained: Figure 4 The second window signal shown is inv_Nx_clk_m2.

[0101] The first logic unit 43 is connected to the counter 30 and is used to filter the pulse signal of the frequency multiplier clock signal Nx_clk based on the first window signal Nx_clk_m2 to generate the corresponding first output signal m_Nx_clk2, filter the pulse signal of the inverted frequency multiplier clock signal inv_Nx_clk based on the second window signal inv_Nx_clk_m2 to generate the corresponding second output signal m_inv_Nx_clk2, and generate the corresponding first target clock signal out_clk2 based on the first output signal m_Nx_clk2 and the second output signal m_inv_Nx_clk2.

[0102] Furthermore, in this embodiment, the first logic unit 43 performs an AND operation on the first window signal Nx_clk_m2 and the frequency multiplier clock signal Nx_clk to obtain the corresponding first output signal m_Nx_clk2, performs an AND operation on the second window signal inv_Nx_clk_m2 and the inverted frequency multiplier clock signal inv_Nx_clk to obtain the corresponding second output signal m_inv_Nx_clk2, and performs an OR operation on the first output signal m_Nx_clk2 and the second output signal m_inv_Nx_clk2 to generate the corresponding first target clock signal out_clk2.

[0103] Understandable Figure 3 and Figure 4 These are merely two possible examples of this embodiment. In more alternative embodiments, those skilled in the art can generate a first target clock signal out_clk that meets different clock signal requirements by setting one or more first clock generation modules 40 and based on the corresponding first control word CW1 and second control word CW2. The clock generation system proposed in this embodiment occupies a small hardware area and can generate a first target clock signal out_clk that meets the requirements of different modules of the audio conversion chip. The number of first clock generation modules 40 can be freely adjusted based on the number of modules in this embodiment.

[0104] Example 2:

[0105] like Figure 5 As shown, the difference from Embodiment 1 is that the clock generation system in this embodiment further includes a second clock generation module 50. The second clock generation module 50 is connected to the counter 30 and the delay phase-locked loop 10.

[0106] like Figure 6 As shown, the second clock generation module 50 includes a second register 51, a second clock filtering unit 52, and a second logic unit 53.

[0107] The second register 51 is connected to the counter 30 and is used to generate the third control word CW3 based on the clock configuration parameters and the count value Nxclk_count.

[0108] The second clock filtering unit 52 is connected to the second register 51 and the delay phase-locked loop 10, and is used to generate the third window signal clk_d based on the third control word CW3 and the frequency multiplier clock signal Nx_clk.

[0109] like Figure 7 As shown, taking the generation of a second target clock signal OUT_clk that is twice the frequency of the input clock signal in_clk as an example:

[0110] Based on another clock configuration parameter, the third control word CW3 is set to 000111, control bits 3, 4, and 5 are 0, and control bits 0, 1, and 2 are 1. The third window signal clk_d is low between the falling edge of the clock signal Nx_clk period T0 (when the count value Nxclk_count is 0) and the next adjacent falling edge (i.e., the falling edge of the clock signal Nx_clk period T1). The third window signal clk_d is low between the falling edge of the clock signal Nx_clk period T1 (when the count value Nxclk_count is 1) and the next adjacent falling edge (i.e., the falling edge of the clock signal Nx_clk period T2), and so on, to obtain... Figure 7 The third window signal clk_d is shown. It can be understood that because the third window signal clk_d is delayed relative to the count value, that is, when the 0 control bit of the first control word CW1 is 1, the third window signal clk_d is high within the corresponding period of the frequency multiplier clock signal Nx_clk; when the 1 control bit of the first control word CW1 is 1, the third window signal clk_d is high within the corresponding period of the frequency multiplier clock signal Nx_clk (and so on), and the third window signal clk_d is delayed by half a period of the frequency multiplier clock signal Nx_clk, thus obtaining... Figure 7 The third window signal clk_d is shown.

[0111] The second logic unit 53 is connected to the counter 30 and is used to generate a second target clock signal OUT_clk based on the third window signal clk_d and the input clock signal in_clk. Specifically, the second logic unit 53 performs an XOR operation on the third window signal clk_d and the input clock signal in_clk to generate the second target clock signal OUT_clk.

[0112] In this embodiment, the second target clock signal OUT_clk is indirectly generated by the frequency multiplier clock signal Nx_clk, which effectively avoids clock jitter.

[0113] Example 3:

[0114] like Figure 8 As shown, the difference between this embodiment and embodiment 1 or embodiment 2 is that the clock signal generation system in this embodiment further includes a pre-division module 60, which is connected to the delay phase-locked loop 10 and is used to divide the input clock signal in_clk and generate an input clock division signal div_in_clk. The delay phase-locked loop 10 generates a multiplied clock signal Nx_clk based on the input clock division signal div_in_clk and the multiplied clock configuration parameters.

[0115] If the input clock signal in_clk is a multiple frequency (e.g., 13 times the frequency), it is difficult to perform frequency multiplication. This embodiment proposes to divide the input clock signal in_clk to obtain a single-frequency input clock division signal div_in_clk. Then, the delay phase-locked loop 10 generates a frequency multiplication clock signal Nx_clk based on the input clock division signal div_in_clk and the frequency multiplication configuration parameters.

[0116] Example 4:

[0117] like Figure 9 As shown, this embodiment provides an audio conversion chip, which includes a clock signal generation system, an analog front-end 70, a first decimation filter 80, and a second decimation filter 90 as described in embodiments 1, 2, or 3. In this embodiment, the first decimation filter 80 is exemplified as a CIC filter 80, and the second decimation filter 90 is exemplified as an FIR filter 90.

[0118] The analog front-end 70 is connected to the first clock signal generation module 40 in the clock signal generation system. It receives the analog audio signal and oversamples the analog audio signal based on the first target clock signal out_clk1 to generate the first sampled signal S1. In this embodiment, the first target clock signal out_clk1 is as follows: Figure 3 As shown.

[0119] The CIC filter 80 is connected to the first clock signal generation module 40 and the analog front end 70 of the clock signal generation system, and is used to generate a second sampling signal S2 based on the first sampling signal S1 and the first target clock signal out_clk2. In this embodiment, the first target clock signal out_clk2 is as follows: Figure 4 As shown.

[0120] The FIR filter 90 is connected to the second clock signal generation module 50 and the CIC filter 70 of the clock generation system, and is used to generate a digital audio signal based on the second sampled signal S2 and the second target clock signal OUT_clk. The second target clock signal OUT_clk is as follows: Figure 7 As shown.

[0121] It is understandable that the analog front-end 70, the first decimation filter 80 and the second decimation filter 90 in the audio conversion chip require different input clock signals in_clk. In this embodiment, the clock signal generation system simultaneously generates at least one first target clock signal out_clk and a second target clock signal OUT_clk to meet the clock requirements of the audio conversion chip and give full play to the advantages of various types of decimation filters.

[0122] Example 5:

[0123] like Figure 10 As shown, this embodiment provides a clock signal generation method, the method including:

[0124] S1. Obtain the input clock signal in_clk and the frequency multiplication configuration parameters;

[0125] S2. The delay phase-locked loop 10 generates a frequency-multiplied clock signal Nx_clk and an inverted frequency-multiplied clock signal inv_Nx_clk based on the input clock signal in_clk and the frequency multiplication configuration parameters.

[0126] S3. The clock edge acquisition module 20 delays the input clock signal in_clk according to the period of the frequency multiplication clock signal Nx_clk to generate a delayed clock signal dly_in_clk, and generates a clock edge pulse signal inclk_edge based on the delayed clock signal dly_in_clk and the input clock signal in_clk.

[0127] S4. The counter 30 generates a count value Nxclk_count based on two adjacent pulses in the clock edge pulse signal inclk_edge.

[0128] S5. The pulse signals of the frequency multiplication clock signal Nx_clk and the inverted frequency multiplication clock signal inv_Nx_clk are filtered based on the count value Nxclk_count by at least one first clock generation module 40 to generate the first target clock signal out_clk.

[0129] Furthermore, the clock signal generation method in this embodiment also includes:

[0130] The input clock signal in_clk is divided by the pre-division module 60 to generate the input clock divided signal div_in_clk.

[0131] The delay phase-locked loop 10 generates a frequency-multiplied clock signal Nx_clk based on the input clock divider signal div_in_clk and the frequency multiplication configuration parameters.

[0132] Furthermore, the clock signal generation method in this embodiment also includes:

[0133] The first control word CW1 and the second control word CW2 are generated by the first register 41 based on the clock configuration parameters and the count value Nxclk_count.

[0134] The first clock filtering unit 42 generates a first window signal Nx_clk_m based on the first control word CW1 and the frequency multiplier clock signal Nx_clk, and generates a second window signal inv_Nx_clk_m based on the second control word CW2 and the inverted frequency multiplier clock signal inv_Nx_clk.

[0135] The first logic unit 43 filters the pulse signal of the frequency multiplication clock signal Nx_clk based on the first window signal Nx_clk_m to generate a first output signal, filters the pulse signal of the inverted frequency multiplication clock signal inv_Nx_clk based on the second window signal inv_Nx_clk_m to generate a second output signal, and generates a first target clock signal out_clk based on the first output signal and the second output signal.

[0136] Furthermore, the clock signal generation method in this embodiment also includes:

[0137] When the control bit of the first control word CW1 is 0, the first window signal Nx_clk_m is at a low level from the falling edge of the clock signal Nx_clk corresponding to the control bit to the next adjacent falling edge. When the control bit of the first control word CW1 is 1, the first window signal Nx_clk_m is at a high level from the falling edge of the clock signal Nx_clk corresponding to the control bit to the next adjacent falling edge.

[0138] When the control bit of the second control word CW2 is 0, the second window signal inv_Nx_clk_m is at a low level during the period of the inverted frequency multiplier clock signal inv_Nx_clk corresponding to the control bit. When the control bit of the second control word CW2 is 1, the second window signal inv_Nx_clk_m is at a high level during the period of the inverted frequency multiplier clock signal inv_Nx_clk corresponding to the control bit.

[0139] Furthermore, the clock signal generation method in this embodiment also includes:

[0140] The third control word CW3 is generated by the second register 51 based on the clock configuration parameters and the count value Nxclk_count.

[0141] The second clock filtering unit 52 generates a third window signal clk_d based on the third control word CW3 and the frequency multiplier clock signal Nx_clk;

[0142] The second logic unit 53 generates the second target clock signal OUT_clk based on the third window signal clk_d and the input clock signal in_clk.

[0143] As can be seen from the above technical solutions, the present invention has the following beneficial effects:

[0144] This invention sets up a first clock generation module and generates a first target clock signal that meets the requirements of different clock signals based on the count value. It also achieves the simultaneous generation of multiple clock signals of different frequencies under low cost conditions, thus meeting the requirements of multi-input clock systems.

[0145] The clock generation system proposed in this invention occupies a small hardware area and uses digital circuits for logic processing, which reduces the circuit area and chip hardware circuit overhead compared to analog circuits.

[0146] This invention can generate a first target clock signal that meets the needs of different modules of an audio conversion chip, and the number of first clock generation modules can be freely adjusted based on the clock signal requirements.

[0147] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0148] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A clock signal generation system, characterized in that, The system includes: A delay phase-locked loop is used to generate a frequency-multiplied clock signal and an inverted frequency-multiplied clock signal based on the input clock signal and frequency multiplication configuration parameters. The clock edge acquisition module, connected to the delay phase-locked loop, is used to delay the input clock signal according to the period of the frequency multiplier clock signal to generate a delayed clock signal, and to generate a clock edge pulse signal based on the delayed clock signal and the input clock signal. The counter, connected to the clock edge acquisition module, is used to generate a count value based on two adjacent pulses in the clock edge pulse signal. At least one first clock generation module, connected to a delay phase-locked loop and a counter, is used to filter the pulse signals of a frequency-multiplied clock signal and an inverted frequency-multiplied clock signal based on the count value to generate a first target clock signal. The first clock generation module includes a first register, a first clock filtering unit, and a first logic unit. The first register is connected to the counter and is used to generate a first control word and a second control word based on clock configuration parameters and the count value. The first clock filtering unit is connected to the first register and the delay phase-locked loop and is used to generate a first window signal based on the first control word and the frequency-multiplied clock signal, and a second window signal based on the second control word and the inverted frequency-multiplied clock signal. The first logic unit is connected to the counter and is used to filter the pulse signals of the frequency-multiplied clock signal based on the first window signal to generate a first output signal, filter the pulse signals of the inverted frequency-multiplied clock signal based on the second window signal to generate a second output signal, and generate the first target clock signal based on the first output signal and the second output signal.

2. The clock signal generation system according to claim 1, characterized in that, The system also includes a pre-division module, which is connected to a delay phase-locked loop (PLL) and is used to divide the input clock signal and generate an input clock division signal. The delay PLL generates a multiplied clock signal based on the input clock division signal and the multiplication configuration parameters.

3. The clock signal generation system according to claim 1, characterized in that, When the control bit of the first control word is 0, the first window signal is at a low level from the falling edge of the clock signal period corresponding to the control bit to the next adjacent falling edge. When the control bit of the first control word is 1, the first window signal is at a high level from the falling edge of the clock signal period corresponding to the control bit to the next adjacent falling edge. When the control bit of the second control word is 0, the second window signal is at a low level during the period of the inverted frequency multiplier clock signal corresponding to the control bit; when the control bit of the second control word is 1, the second window signal is at a high level during the period of the inverted frequency multiplier clock signal corresponding to the control bit.

4. The clock signal generation system according to claim 1, characterized in that, The clock signal generation system further includes a second clock generation module, which comprises a second register, a second clock filtering unit, and a second logic unit; wherein... The second register is connected to a counter and is used to generate a third control word based on clock configuration parameters and the count value; The second clock filtering unit is connected to the second register and the delay phase-locked loop, and is used to generate a third window signal based on the third control word and the frequency multiplier clock signal; The second logic unit is connected to a counter and is used to generate a second target clock signal based on the third window signal and the input clock signal.

5. A method for generating a clock signal, characterized in that, The method includes: Obtain the input clock signal and frequency multiplication configuration parameters; A delay phase-locked loop generates a frequency-multiplied clock signal and an inverted frequency-multiplied clock signal based on the input clock signal and frequency multiplication configuration parameters. The clock edge acquisition module delays the input clock signal according to the period of the frequency multiplication clock signal to generate a delayed clock signal, and generates a clock edge pulse signal based on the delayed clock signal and the input clock signal. A counter generates a count value based on two adjacent pulses in a clock edge pulse signal; The first target clock signal is generated by filtering the pulse signals of the frequency-multiplied clock signal and the inverted frequency-multiplied clock signal based on the count value through at least one first clock generation module. Specifically, this includes generating a first control word and a second control word through a first register based on clock configuration parameters and the count value. The first window signal is generated by the first clock filtering unit based on the first control word and the frequency multiplier clock signal, and the second window signal is generated based on the second control word and the inverted frequency multiplier clock signal. The first logic unit filters the pulse signal of the frequency multiplication clock signal based on the first window signal to generate a first output signal, filters the pulse signal of the inverted frequency multiplication clock signal based on the second window signal to generate a second output signal, and generates a first target clock signal based on the first output signal and the second output signal.

6. The clock signal generation method according to claim 5, characterized in that, The method further includes: The input clock signal is divided by the pre-division module to generate the input clock divided signal; A frequency-multiplied clock signal is generated by a delay phase-locked loop based on the input clock division signal and the frequency multiplication configuration parameters.

7. The clock signal generation method according to claim 5, characterized in that, The clock signal generation method includes: When the control bit of the first control word is 0, the first window signal is at a low level from the falling edge of the clock signal period corresponding to the control bit to the next adjacent falling edge. When the control bit of the first control word is 1, the first window signal is at a high level from the falling edge of the clock signal period corresponding to the control bit to the next adjacent falling edge. When the control bit of the second control word is 0, the second window signal is at a low level during the period of the inverted frequency multiplier clock signal corresponding to the control bit; when the control bit of the second control word is 1, the second window signal is at a high level during the period of the inverted frequency multiplier clock signal corresponding to the control bit.

8. The clock signal generation method according to claim 5, characterized in that, The method further includes: The third control word is generated by the second register based on the clock configuration parameters and the count value; The third window signal is generated by the second clock filtering unit based on the third control word and the frequency multiplier clock signal; The second target clock signal is generated by the second logic unit based on the third window signal and the input clock signal.

9. An audio conversion chip, characterized in that, The audio conversion chip includes a clock signal generation system as described in any one of claims 1 to 4, an analog front-end, and at least one first decimation filter; wherein... The analog front end is connected to the clock signal generation system and is used to receive the analog audio signal and oversample the analog audio signal based on the first target clock signal to generate the first sampled signal. The first decimation filter is connected to the clock signal generation system and the analog front end, and is used to generate a second sampling signal based on the first sampling signal and the first target clock signal.

10. The audio conversion chip according to claim 9, characterized in that, The audio conversion chip also includes a second decimation filter, which is connected to the clock generation system and the first decimation filter, and is used to generate a digital audio signal based on the second sampling signal and the second target clock signal.

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