A cascaded video monitoring module based on FPGA

Abstract

The application belongs to the technical field of airborne image processing, and particularly relates to a cascaded video monitoring module based on FPGA, which comprises one cascaded submodule composed of one FPGA and one embedded CPU, the FPGAs of the cascaded submodules are cascaded through an ARINC818 bus, and the embedded CPUs of the cascaded submodules are interconnected through the same network router; the input ends of the cascaded submodules are respectively connected with multiple ARINC818 video inputs; the cascaded FPGAs and embedded CPUs are used to realize the monitoring functions of video splicing, compression, recording and playback, support multiple input video resolutions, and can be cascaded to expand the number of input video channels, so that the related application scenarios of airborne video monitoring can be better met.

Description

Technical Field

[0001] This invention belongs to the field of airborne image processing technology, specifically relating to a cascaded video surveillance module based on FPGA. Background Technology

[0002] With the advancement of avionics technology, the types and quantities of airborne optoelectronic devices are increasing, and the resolutions of various airborne optoelectronic devices are becoming more diverse, placing higher demands on the multi-resolution support and interface scalability of airborne monitoring systems. Summary of the Invention

[0003] In view of this, the present invention provides a cascaded video surveillance module based on FPGA, which can better meet the relevant application scenarios of airborne video surveillance.

[0004] The technical solution of this invention is as follows:

[0005] A cascaded video surveillance module based on FPGA includes a cascaded sub-module consisting of one FPGA and one embedded CPU. The FPGAs of each cascaded sub-module are cascaded via an ARINC818 bus, and the embedded CPUs of each cascaded sub-module are interconnected via the same network router. The input terminals of each cascaded sub-module are respectively connected to multiple ARINC818 video inputs.

[0006] The cascaded video surveillance module also includes a display and control terminal; the display and control terminal is connected to the embedded CPU of one of the cascaded sub-modules, and after transmitting the display and control instructions to the connected embedded CPU, the display and control instructions are transmitted to the network router. The router forwards the display and control instructions to at least one selected cascaded sub-module, and the selected cascaded sub-module transmits the ARINC818 video it has processed to the display and control terminal according to the display and control instructions.

[0007] Furthermore, the display and control terminal is used to display single-channel input video, multi-channel spliced ​​video, or recorded playback video;

[0008] The transmission, splicing, and playback functions of single-channel input video, multi-channel monitoring spliced ​​video, or recorded playback video are completed based on the FPGA.

[0009] Furthermore, the FPGA internally consists of a MicroBlaze minimum system, a PCIE EP IP, a BT.656 timing generation module, a BT.1120 parsing module, an aggregation module, an OSD, multiple multiplexers, multiple scalers, and multiple VDMAs.

[0010] Furthermore, each of the cascaded sub-modules' FPGAs receives multiple ARINC818 video inputs, one cascaded ARINC818 video input, and one BT.1120 playback video input. After aggregation by the aggregation module, the video is sent to the first multiplexer (multiple-to-one selection). The output of the first multiplexer is scaled by the scaler and then buffered by the VDMA. Finally, MicroBlaze receives display control instructions from the embedded CPU through the PCIE interface, controlling the OSD and the first multiplexer to overlay and synthesize the images buffered in the specified VDMA at a specified resolution and position to form a monitoring spliced ​​image.

[0011] Furthermore, the multi-channel video and spliced ​​video output by the aggregation module are output to the cascaded ARINC818 output interface via a multi-select 1 second multiplexer for use by the next cascaded sub-module.

[0012] Furthermore, the FPGA is also used to send multiple video inputs to the embedded CPU via the BT.656 timing generation module for video compression and recording.

[0013] Furthermore, the embedded CPU in the cascaded submodule has at least one BT.656 interface and one BT.1120 interface that are equivalent to the number of ARINC818 video channels received by the FPGA. The embedded CPU supports PCIe interface, SATA interface and Ethernet interface.

[0014] Furthermore, the embedded CPU receives ARINC818 video forwarded by the FPGA via BT.656, compresses it, and records it to a SATA hard drive via the SATA interface; the embedded CPU receives display and control commands from the monitoring terminal via Ethernet port, and sends the display and control commands to the FPGA via the PCIe port, and the FPGA generates the monitoring splicing screen; the embedded CPU receives playback commands from the monitoring terminal via Ethernet port, reads and decompresses the specified recorded video from the SATA hard drive, and sends it to the FPGA for playback via BT.1120 interface.

[0015] The beneficial effects of this invention are:

[0016] Based on multiple cascaded FPGAs and embedded CPUs, the system implements video stitching, compression, recording, and playback monitoring functions. It supports multiple input video resolutions and the number of input video channels can be cascaded and expanded, which can better meet the relevant application scenarios of airborne video surveillance. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 For cascaded video surveillance systems

[0019] Figure 2 FPGA / CPU video surveillance cascade submodule Detailed Implementation

[0020] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0021] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0022] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using other structures and / or functionalities besides one or more of the aspects set forth herein.

[0023] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The illustrations only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0024] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0025] In one embodiment of the present invention, a cascaded video surveillance module based on FPGA is proposed, comprising a cascaded sub-module consisting of one FPGA and one embedded CPU. The FPGAs of each cascaded sub-module are cascaded via an ARINC818 bus, and the embedded CPUs of each cascaded sub-module are interconnected via the same network router. The input terminals of each cascaded sub-module are respectively connected to multiple ARINC818 video inputs.

[0026] The cascaded video surveillance module also includes a display and control terminal; the display and control terminal is connected to the embedded CPU of one of the cascaded sub-modules, and after transmitting the display and control instructions to the connected embedded CPU, the display and control instructions are transmitted to the network router. The router forwards the display and control instructions to at least one selected cascaded sub-module, and the selected cascaded sub-module transmits the ARINC818 video it has processed to the display and control terminal according to the display and control instructions.

[0027] In this embodiment, the display and control terminal is used to display single-channel input video, multi-channel spliced ​​video, or recorded playback video;

[0028] The transmission, splicing, and playback functions of single-channel input video, multi-channel monitoring spliced ​​video, or recorded playback video are completed based on the FPGA.

[0029] In this embodiment, the FPGA is internally composed of a MicroBlaze minimum system, a PCIE EP IP, a BT.656 timing generation module, a BT.1120 parsing module, an aggregation module, an OSD, multiple multiplexers, multiple scalers, and multiple VDMAs.

[0030] In this embodiment, each FPGA in the cascaded submodule receives 8 channels of ARINC818 video, 1 channel of cascaded ARINC818 video input, and 1 channel of BT.1120 playback video input. After being aggregated by the aggregation module, the video is sent to the first multiplexer with a 1-to-1 selection. The output of the first multiplexer is scaled by the scaler and then buffered by the VDMA. Finally, MicroBlaze receives the display control instructions from the embedded CPU through the PCIE interface, and controls the OSD and the first multiplexer to superimpose and synthesize the images buffered in the specified VDMA according to the specified resolution and position to form a monitoring spliced ​​image.

[0031] In this embodiment, the multi-channel video and spliced ​​video output by the aggregation module are output to the cascaded ARINC818 output interface via a multi-select 1 second multiplexer for use by the next cascaded sub-module.

[0032] In this embodiment, the FPGA is also used to send eight video inputs to the embedded CPU via the BT.656 timing generation module for video compression and recording.

[0033] In this embodiment, the embedded CPU in the cascaded submodule has at least one BT.656 interface and one BT.1120 interface that are equivalent to the number of ARINC818 video channels received by the FPGA. The embedded CPU supports PCIe interface, SATA interface and Ethernet interface.

[0034] In this embodiment, the embedded CPU receives ARINC818 video forwarded by the FPGA via BT.656, compresses it, and records it to a SATA hard drive via the SATA interface; the embedded CPU receives display and control commands from the monitoring terminal via the Ethernet port, and sends the display and control commands to the FPGA via the PCIE port, and the FPGA generates a monitoring splicing screen; the embedded CPU receives playback commands from the monitoring terminal via the Ethernet port, reads and decompresses the specified recorded video from the SATA hard drive, and sends it to the FPGA for playback via the BT.1120 interface.

[0035] This embodiment provides a scalable FPGA-based cascaded video surveillance module. This module consists of one FPGA and one embedded CPU forming an FPGA / CPU video surveillance cascaded sub-module. The FPGAs in the sub-modules are cascaded via ARINC818 chips, and the embedded CPUs are interconnected via Ethernet routers, forming a cascaded video surveillance system. Figure 1 As shown.

[0036] The FPGA internally consists of a MicroBlaze minimum system, PCIe EP IP, a BT.656 timing generation module, a BT.1120 parsing module, an aggregation module, an OSD, multiple MUX multiplexers, multiple scalers, and multiple VDMAs, such as... Figure 2 As shown, the system implements the functions of splicing output, sending to the embedded BT.656 interface for compression recording, and playing back video through the BT.1120 interface. At the same time, the FPGA has cascaded output and cascaded input ARINC818 interfaces, which enable the current module to process and use the output video of the previous stage, and to provide the current stage video to the next stage module for processing.

[0037] The embedded CPU has at least eight BT.656 interfaces and one BT.1120 interface, supporting PCIe, SATA, and Ethernet interfaces. The embedded CPU receives ARINC818 video forwarded by the FPGA via the BT.656 interface, compresses it, and records it to a SATA hard drive via the SATA interface. It also receives instructions from the monitoring terminal via the Ethernet port to read and decompress specified recorded video, which is then sent to the FPGA for playback via the BT.1120 interface.

[0038] By cascading multiple FPGA / CPU modules, the ARINC818 input video, spliced ​​video, or recorded video from any level module can be output to the monitoring terminal through the cascaded ARINC818 interface.

[0039] In this embodiment, the FPGA receives 8 channels of ARINC818 video, 1 channel of cascaded ARINC818 video input, and 1 channel of BT.1120 playback video input. These are aggregated into 10 video channels by the aggregation module and sent to each 10-to-1 MUX multiplexer. The MUX output is scaled by a scaler and buffered by VDMA. Finally, the MicroBlaze receives display control commands from the embedded CPU via the PCIe interface, controlling the OSD and the 10-to-1 MUX to overlay the specified images buffered by VDMA at a specified resolution and position to create a composite monitoring image. The 10 video channels output from the aggregation module and the composite image are then output to the cascaded ARINC818 output interface via an 11-to-1 MUX multiplexer for use by the next cascaded submodule.

[0040] The FPGA sends eight video inputs to the embedded CPU via a BT.656 timing generation module for video compression and recording. The embedded CPU in this embodiment has at least eight BT.656 interfaces and one BT.1120 interface, and supports PCIe, SATA, and Ethernet interfaces. Figure 2As shown, the embedded CPU receives ARINC818 video forwarded by the FPGA via BT.656, compresses it, and records it to a SATA hard drive via the SATA interface; it receives display commands from the monitoring terminal via Ethernet port, and sends the monitoring display commands to the FPGA via the PCIe port, where the FPGA generates the monitoring spliced ​​screen; it receives playback commands from the monitoring terminal via Ethernet port, reads and decompresses the specified recorded video from the SATA hard drive, and sends it to the FPGA for playback via BT.1120 interface. This cascaded video surveillance system consists of at least two cascaded FPGA / CPU video monitoring sub-modules. These cascaded sub-modules are connected via ARINC818 interface and Ethernet. They can receive commands from the monitoring terminal via Ethernet and output ARINC818 input video, monitoring spliced ​​video, or recorded playback video from any level module to the monitoring terminal via the cascaded ARINC818 interface.

[0041] In this embodiment, the FPGA / CPU video monitoring cascaded sub-modules are cascaded via ARINC818 interfaces and Ethernet. Commands received from the monitoring terminal can be transmitted via Ethernet, and input video, spliced ​​video, or recorded playback video from any level module can be output to the monitoring terminal through the cascaded ARINC818 interfaces. The application can select the number of cascaded modules according to its needs, providing good scalability.

[0042] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A cascaded video surveillance module based on FPGA, characterized in that, The cascaded video surveillance module comprises a cascaded submodule consisting of one FPGA and one embedded CPU. The FPGAs of each cascaded submodule are connected via an ARINC818 bus, and the embedded CPUs of each cascaded submodule are interconnected via a network router. The input terminals of each cascaded submodule are connected to multiple ARINC818 video inputs. The cascaded video surveillance module also includes a display and control terminal. The display and control terminal is connected to one of the embedded CPUs of the cascaded submodules. After transmitting display and control commands to the connected embedded CPU, the command is transmitted to the network router. The router forwards the command to at least one selected cascaded submodule. The selected cascaded submodule, according to the command, transmits its processed ARINC818 video feed to the display and control terminal. The display and control terminal is used to display single-channel input video, multi-channel monitoring spliced ​​video, or recorded playback video; the transmission, splicing, and playback functions of the single-channel input video, multi-channel monitoring spliced ​​video, or recorded playback video are completed based on the FPGA; The FPGA internally consists of a MicroBlaze minimum system, a PCIE EP IP, a BT.656 timing generation module, a BT.1120 parsing module, an aggregation module, an OSD, multiple multiplexers, multiple scalers, and multiple VDMAs. Each of the cascaded sub-modules' FPGAs receives multiple ARINC818 video inputs, one cascaded ARINC818 video input, and one BT.1120 playback video input. After aggregation by the aggregation module, the video is sent to the first multiplexer (multiple-to-one selection). The output of the first multiplexer is scaled by the Scaler and then buffered by the VDMA. Finally, MicroBlaze receives the display control instructions from the embedded CPU through the PCIE interface, controlling the OSD and the first multiplexer to overlay and synthesize the images buffered in the specified VDMA at a specified resolution and position to form a monitoring spliced ​​image. The multi-channel video and spliced ​​video output by the aggregation module are output to the cascaded ARINC818 output interface via a multi-select 1 second multiplexer for use by the next cascaded sub-module; The FPGA is also used to send multiple video inputs to the embedded CPU via the BT.656 timing generation module for video compression and recording. The embedded CPU in the cascaded submodule has at least a number of BT.656 interfaces and one BT.1120 interface that is equivalent to the number of ARINC818 video channels received by the FPGA. The embedded CPU receives ARINC818 video forwarded by the FPGA via BT.656, compresses it, and records it to a SATA hard drive via the SATA interface; the embedded CPU receives display and control commands from the monitoring terminal via Ethernet port, and sends the display and control commands to the FPGA via the PCIe port, and the FPGA generates the monitoring splicing screen; the embedded CPU receives playback commands from the monitoring terminal via Ethernet port, reads and decompresses the specified recorded video from the SATA hard drive, and sends it to the FPGA for playback via BT.1120 interface.

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