Spin orbital magnetic memory and its fabrication method

Abstract

This invention provides a spin-orbit-moment (SOM) magnetic memory and its fabrication method. The fabrication method includes: forming a stacked cell and a dielectric layer covering the stacked cell on a substrate; the stacked cell includes a magnetic tunnel junction and a SOT layer; the dielectric layer includes a top dielectric sublayer and side dielectric sublayers; forming a photolithography layer on the dielectric layer; patterning the photolithography layer to form electrical interconnect trenches; etching the dielectric layer according to the patterned photolithography layer to expose the upper surface or sidewalls of the SOT layer; depositing a conductive material to form a conductive layer covering the dielectric layer; and planarizing the conductive layer to form at least two independent conductive structures. This invention can reduce the fabrication cost of bottom-pinned SOT-MRAM.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a spin orbital moment magnetic memory and its fabrication method. Background Technology

[0002] Spin-orbit-moment magnetic RAM (SOT-MRAM) has advantages such as non-volatility, high speed, high reliability, and low power consumption, making it a storage device with great development potential.

[0003] The SOT-MRAM device cell consists of a spin-orbit moment provider (SOT) layer and a magnetic tunnel junction. The magnetic tunnel junction includes a free layer, a tunneling layer, a reference layer, and a pinning layer. Typically, SOT-MRAM device cells employ a top-pinned structure, but this faces challenges during fabrication, such as short-circuiting and damage to the magnetic tunnel junction, and over-etching of the spin-orbit moment provider layer. These issues make the fabrication of spin-orbit moment magnetic memories difficult and result in low yields. A bottom-pinned structure, where the spin-orbit moment provider layer is positioned above the magnetic tunnel junction, helps to address these problems.

[0004] However, one of the current difficulties facing bottom-pinned structures is that the process of forming spin orbital moments to provide layer electrical interconnects requires two photolithography steps to form conductive trenches and vias through hard masks, thereby achieving electrical coupling between the conductive layer and the SOT layer. The increase in the number of photolithography steps makes the fabrication cost of bottom-pinned SOT-MRAM higher.

[0005] Therefore, how to reduce the number of photolithography steps to lower the manufacturing cost of bottom-pinned SOT-MRAM has become an urgent problem to be solved. Summary of the Invention

[0006] To address the aforementioned issues, the present invention provides a spin-orbit moment magnetic memory and its fabrication method, which uses a photolithography process to etch the dielectric layer to form a conductive structure electrically coupled to the SOT layer, thereby reducing the number of photolithography steps and lowering the fabrication cost of bottom-pinned SOT-MRAM.

[0007] In a first aspect, the present invention provides a method for fabricating a spin-orbit magnetic memory, comprising:

[0008] A stacked cell and a dielectric layer covering the stacked cell are formed on a substrate. The stacked cell includes, from bottom to top, a magnetic tunnel junction and a SOT layer. The dielectric layer includes a top dielectric sublayer that overlaps with the SOT layer in the vertical direction and a side dielectric sublayer located on the periphery of the stacked cell.

[0009] A photolithography layer is formed on the dielectric layer;

[0010] A patterned photolithography layer is used to form at least two independent electrical interconnect trenches on the photolithography layer; wherein each electrical interconnect trench overlaps with a portion of the top dielectric sublayer and a portion of the side dielectric sublayer in the vertical direction, or each electrical interconnect trench overlaps with a portion of the side dielectric sublayer in the vertical direction, and the sidewall of the electrical interconnect trench overlaps with the sidewall of the SOT layer in the vertical direction.

[0011] The dielectric layer is etched according to the patterned photolithography layer so that when the electrical interconnect trench overlaps with part of the top dielectric sublayer and part of the side dielectric sublayer in the vertical direction, the upper surface of the SOT layer is exposed, and when the electrical interconnect trench overlaps with part of the side dielectric sublayer in the vertical direction and the sidewall of the electrical interconnect trench overlaps with the sidewall of the SOT layer in the vertical direction, the sidewall of the SOT layer is exposed.

[0012] Deposit conductive material to form a conductive layer covering the dielectric layer;

[0013] Planarize the conductive layer so that it forms at least two independent conductive structures.

[0014] Optionally, prior to the step of depositing the conductive material to form a conductive layer covering the dielectric layer, the method further includes:

[0015] Remove the patterned photolithography layer;

[0016] The materials for the photolithography layer include: photoresist materials, metal hard mask materials, or dielectric hard mask materials.

[0017] Optionally, when the photolithography layer is an insulating material, the step of planarizing the conductive layer to form at least two independent conductive structures includes:

[0018] The conductive layer is planarized to expose the photolithography layer or the top dielectric sublayer.

[0019] Optionally, when the photolithography layer is made of a conductive material, the step of planarizing the conductive layer to form at least two independent conductive structures includes:

[0020] The conductive layer is planarized to expose the top dielectric sublayer.

[0021] Optionally, the step of forming a stacked unit and a dielectric layer covering the stacked unit on the substrate includes:

[0022] A stacked structure, a first preparative dielectric layer, and a hard mask layer are sequentially deposited on a substrate. The stacked structure is used to form an SOT layer and a magnetic tunnel junction.

[0023] A patterned hard mask layer is formed, and a first preparatory dielectric layer and stacked structure are etched according to the patterned hard mask layer to form a top dielectric sublayer, an SOT layer and a magnetic tunnel junction.

[0024] A second preparative dielectric layer for depositing and coating the magnetic tunnel junction;

[0025] The second preparative dielectric layer is planarized to remove the hard mask layer, resulting in a side dielectric sublayer.

[0026] Optionally, the step of depositing a second preparative dielectric layer to cover the magnetic tunnel junction includes:

[0027] The first and second preparatory dielectric sublayers are deposited sequentially to coat the magnetic tunnel junction;

[0028] The steps for etching the dielectric layer based on the patterned photolithography layer include:

[0029] The first preparatory dielectric sublayer is etched, and the etching stop position of the first preparatory dielectric sublayer is higher than the lower surface of the SOT layer.

[0030] Optionally, the material of the hard mask layer includes at least one of tantalum, titanium, tantalum nitride, and titanium nitride;

[0031] The shapes of the graphical hard mask layer include: circle, ellipse, rectangle, rhombus or triangle;

[0032] The material of the first pre-dielectric sublayer includes silicon nitride, and the material of the second pre-dielectric sublayer includes silicon oxide.

[0033] Optionally, the step of etching the dielectric layer according to the patterned photolithography layer includes:

[0034] Based on the patterned photolithography layer, the dielectric layer is etched using reactive ion etching or ion beam etching.

[0035] Optionally, the material of the top dielectric sublayer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide.

[0036] In a second aspect, the present invention provides a spin-orbit moment magnetic memory, which is obtained by any of the methods described above.

[0037] The spin-orbit-moment (SOT) magnetic memory and its fabrication method provided in this invention achieve conductive interconnection of the SOT layer by patterning the photolithography layer using photolithography and etching the dielectric layer based on the patterned photolithography layer. This simplifies the process flow and reduces the fabrication cost of bottom-pinned SOT-MRAM. Simultaneously, by using a first hard mask to realize the wire structure, the contact area between the conductive structure and the SOT layer can be effectively controlled, ensuring a sufficiently high current density flowing through the SOT layer. Furthermore, retaining part or all of the top dielectric sublayer during the etching of the dielectric layer avoids damage to the effective portion of the SOT layer covered by the top dielectric sublayer. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figures 1 to 10 These are schematic structural diagrams of a spin-orbit-moment magnetic memory at various stages of its fabrication, according to an embodiment of this application.

[0040] Figure 11 This is a schematic structural diagram of a spin-orbit-moment magnetic memory during the fabrication process of an embodiment of this application.

[0041] Figure 12 This is a schematic structural diagram of a spin-orbit-moment magnetic memory during the fabrication process of a spin-orbit-moment magnetic memory according to an embodiment of this application.

[0042] Figure 13 This is a schematic structural diagram of a spin-orbit-moment magnetic memory during the fabrication process of a spin-orbit-moment magnetic memory according to an embodiment of this application.

[0043] Figure 14 and Figure 15 These are all schematic structural diagrams of a spin-orbit-moment magnetic memory at different stages of its fabrication, according to an embodiment of this application.

[0044] in, Figure 2 , Figure 5 , Figure 7 , Figure 10 and Figure 14 These are schematic top views of a spin-orbit-moment magnetic memory at different stages of its fabrication. Figure 1 , Figure 3 , Figure 4 , Figure 6 , Figure 8 , Figure 9 , Figure 11 , Figure 12 and Figure 13 These are schematic cross-sectional views of a spin-orbit-moment magnetic memory at different stages of its fabrication.

[0045] Figure label:

[0046] 1. Stacked unit; 11. Magnetic tunnel junction; 12. SOT layer; 2. Dielectric layer; 21. Top dielectric sublayer; 22. Second pre-dielectric layer; 221. First pre-dielectric sublayer; 222. Second pre-dielectric sublayer; 23. Side dielectric sublayer; 3. Photolithography layer; 31. Electrical interconnect trench; 4. Hard mask layer; 5. Conductive layer; 51. Conductive structure; 6. Substrate. Detailed Implementation

[0047] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0049] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0050] It should be noted that when an element is referred to as "fixedly connected" to another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element. Conversely, when an element is referred to as being "directly on" another element, there is no intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0051] When used herein, the singular forms "a", "an", and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0052] In a first aspect, the present invention provides a method for fabricating a spin-orbit magnetic memory, the method comprising steps S101 to S106:

[0053] Step S101: Form a stacked unit 1 and a dielectric layer 2 covering the stacked unit 1 on the substrate 6, see [link to previous step]. Figure 1 and Figure 2 .

[0054] Among them, combined Figure 3 The stacked unit 1, from bottom to top, includes a magnetic tunnel junction 11 and an SOT layer 12. The dielectric layer 2 includes a top dielectric sublayer 21 that overlaps with the SOT layer 12 in the vertical direction and a side dielectric sublayer 23 located around the stacked unit 1. The side dielectric sublayer 23 is flush with the upper surface of the top dielectric sublayer 21. It can be understood that the stacked unit 1 is the storage bit in a spin-orbit magnetic memory.

[0055] Furthermore, in combination Figure 3 The step of forming a stacked unit 1 and a dielectric layer 2 covering the stacked unit 1 on the substrate 6 includes:

[0056] A stacked structure, a first pre-dielectric layer, and a hard mask layer 4 are sequentially deposited on a substrate 6. The hard mask layer 4 is patterned, and the first pre-dielectric layer and the stacked structure are etched according to the patterned hard mask layer 4 to form a top dielectric sublayer 21, an SOT layer 12, and a magnetic tunnel junction 11. A second pre-dielectric layer 22 is deposited to cover the magnetic tunnel junction 11. The second pre-dielectric layer 22 is planarized to remove the hard mask layer 4, resulting in a side dielectric sublayer 23.

[0057] The stacked structure is used to form the SOT layer 12 and the magnetic tunnel junction 11; the material of the top dielectric sublayer 21, i.e. the first pre-dielectric layer, includes at least one of silicon oxide, silicon nitride, silicon oxynitride and silicon oxycarbide, but is not limited thereto; the material of the hard mask layer 4 includes, but is not limited to, tantalum, titanium, tantalum nitride and titanium nitride, etc., and the shape of the patterned hard mask layer 4 includes, but is not limited to, circles, ellipses, rectangles, rhombuses or triangles.

[0058] In this embodiment, the magnetic tunnel junction 11 includes, from bottom to top: an antiferromagnetic nailing layer, a reference layer, a tunneling layer, and a free layer, and the free layer is in contact with the SOT layer 12; the material of the first preparative dielectric layer is a low-k dielectric material, which is not specifically limited in this embodiment.

[0059] Step S102: Form a photolithography layer 3 on the dielectric layer 2.

[0060] The material of the photolithography layer 3 includes photoresist material, metal hard mask material or dielectric hard mask material, and this embodiment does not specifically limit it.

[0061] Step S103: Pattern the photolithography layer 3 to form at least two independent electrical interconnect trenches 31 on the photolithography layer 3, see [link to previous step]. Figure 4 and Figure 5 .

[0062] It should be noted that the specific patterning process in step S103 varies depending on the material of the photolithography layer 3.

[0063] Taking the material of photolithography layer 3 as the dielectric hard mask material as an example, step S103 includes steps S1031 to S1034. Specifically,

[0064] Step S1031: Coating, i.e., uniformly coating photoresist onto the upper surface of the photolithography layer 3; Step S1032: Exposure, exposing the photoresist according to the mask, the exposed photoresist hardens and remains on the photolithography layer 3; Step S1033: Resin Removal, the unexposed photoresist is cleaned and removed; Step S1034: Etching the photolithography layer 3, i.e., etching the photolithography layer 3, so that the part covered by the photoresist is retained, and the other part is removed.

[0065] Therefore, in step S103, the pattern transfer sequence is: mask → photoresist → photolithography layer 3. The first transfer step corresponds to photolithography, and the second transfer step is etching. When the material of the photolithography layer 3 is photoresist, only the photolithography step is required, and this embodiment will not elaborate further.

[0066] In this embodiment, there are two electrical interconnect trenches 31, that is, two electrical interconnect trenches 31 are formed on a magnetic tunnel junction 11. The two electrical interconnect trenches 31 are arranged opposite to each other, and each electrical interconnect trench 31 overlaps with a portion of the top dielectric sublayer 21 and a portion of the side dielectric sublayer 23 in the vertical direction, respectively.

[0067] The horizontal cross-sectional shape of the electrical interconnect trench 31 can be rectangular, trapezoidal, or annular, etc. In this embodiment, the horizontal cross-sectional shape of the electrical interconnect trench 31 is rectangular.

[0068] Step S104: Etch dielectric layer 2 according to the patterned photolithography layer 3 to expose the upper surface of SOT layer 12, see [link to relevant documentation]. Figure 6 and Figure 7 .

[0069] It should be noted that in step S104, in addition to exposing the upper surface of the SOT layer 12, the sidewalls of the SOT layer 12 may also be exposed simultaneously. Specifically, the stopping position of the etching dielectric layer 2 may be caused by the etching process or by the different etching rates of each dielectric layer 2.

[0070] Combination Figure 11 For example, during the over-etching process of dielectric layer 2, a suitable amount of over-etching is allowed, which leads to the exposure of the sidewalls of SOT layer 12. This not only increases the tolerance of the etching process and reduces the fabrication difficulty of spin orbital magnetic memory, but also increases the contact area between the subsequent conductive structure 51 and SOT layer 12, ensuring the stability of the performance of spin orbital magnetic memory.

[0071] Combination Figure 12 For example, the side dielectric sublayer 23 is composed of multiple inner and outer layers. By controlling the etching rate of the inner layer in the side dielectric sublayer 23 that is in contact with the SOT layer 12 to be greater than the etching rate of the outer dielectric layer 2, or by selectively etching the inner layer in the side dielectric sublayer 23 after the upper surface of the corresponding part of the SOT layer 12 is exposed, that is, the etching rate of the inner layer in the side dielectric sublayer 23 is greater than the etching rate of other materials.

[0072] In one alternative embodiment, combined with Figure 11 , Figure 12 and Figure 13 ,in, Figure 11 This is a schematic diagram of the conductive structure 51 formed in the over-etched state of the dielectric layer 2; Figure 12 A schematic diagram of a conductive structure 51 formed when the etching rate of the first preparatory dielectric sublayer 221 is greater than the etching rate of the second preparatory dielectric sublayer 222. Figure 13A schematic diagram of a conductive structure 51 formed when the etching rate of the first preparatory dielectric sublayer 221 is less than the etching rate of the second preparatory dielectric sublayer 222.

[0073] The step of depositing the second preparatory dielectric layer 22 covering the magnetic tunnel junction 11 as described above includes: sequentially depositing the first preparatory dielectric sublayer 221 and the second preparatory dielectric sublayer 222 covering the magnetic tunnel junction 11.

[0074] The steps of etching the dielectric layer 2 according to the patterned photolithography processing layer 3 include: etching the first preparatory dielectric sublayer 221, wherein the etching stop position of the first preparatory dielectric sublayer 221 is higher than the lower surface of the SOT layer 12.

[0075] The etching rates of the first pre-dielectric sublayer 221 and the second pre-dielectric sublayer 222 can be the same or different. In this optional embodiment, the material of the first pre-dielectric sublayer 221 includes silicon nitride, and the material of the second pre-dielectric sublayer 222 includes silicon oxide, but is not limited thereto.

[0076] In one optional embodiment, the step of etching the dielectric layer 2 according to the patterned photolithography layer 3 includes: etching the dielectric layer 2 using reactive ion etching or ion beam etching according to the patterned photolithography layer 3. In this optional embodiment, the reactive ion etching or ion beam etching methods will not be described in detail.

[0077] Step S105: Deposit conductive material to form a conductive layer 5 covering the dielectric layer 2, see [link to previous step]. Figure 8 .

[0078] It should be noted that when the photolithography layer 3 is a metal hard mask material, it can be used as part of the conductive layer 5. In this case, the patterned photolithography layer 3 can be removed in step S106 or before step S105. When the photolithography layer 3 is a dielectric hard mask or photoresist material, it can be used as part of the top dielectric sublayer 21. In this case, the patterned photolithography layer 3 can be removed in step S106 or before step S105, or it can be retained directly to separate different conductive structures 51 after step S106.

[0079] In this embodiment, the photolithography layer 3 is a dielectric hard mask, and its material is at least one of silicon nitride and silicon oxide, but is not limited thereto. Before the step of depositing conductive material to form the conductive layer 5 covering the dielectric layer 2, the method further includes: removing the patterned photolithography layer 3.

[0080] In an optional embodiment, when the material of the photolithography layer 3 is an insulating material, such as at least one of photoresist material and dielectric hard mask material, the step of planarizing the conductive layer 5 to form at least two independent conductive structures 51 includes: planarizing the conductive layer 5 to expose the photolithography layer 3 or the top dielectric sublayer 21.

[0081] In an optional embodiment, when the material of the photolithography layer 3 is a conductive material, such as a metal hard mask material, the step of planarizing the conductive layer 5 to form at least two independent conductive structures 51 includes: planarizing the conductive layer 5 to expose the top dielectric sublayer 21.

[0082] Step S106: Planarize the conductive layer 5 so that the conductive layer 5 forms at least two independent conductive structures 51, see [link to previous step]. Figure 9 and Figure 10 .

[0083] In this embodiment, the conductive layer 5 is planarized until the top dielectric sublayer 21 is exposed, that is, the stopping position of the planarized conductive layer 5 does not exceed the lower surface of the top dielectric sublayer 21.

[0084] It should be noted that after performing step S106, a dielectric material can be deposited to cover the conductive structure 51 and the second preparative dielectric layer 22 to form a protective layer; the conductive structure 51 is then connected to the write circuit in the spin orbital magnetic memory through the protective layer.

[0085] The method for fabricating a spin-orbit-moment (SOT) magnetic memory provided in this embodiment involves patterning the photolithography layer 3 using photolithography, and then etching the dielectric layer 2 based on the patterned photolithography layer 3. This allows for the conductive interconnection of the SOT layer 12 to be achieved in a single photolithography process, simplifying the process flow and reducing the fabrication cost of bottom-pinned SOT-MRAM. Simultaneously, by using a first hard mask to realize the wire structure, the contact area between the conductive structure 51 and the SOT layer 12 can be effectively controlled, ensuring a sufficiently high current density flowing through the SOT layer 12. Furthermore, retaining part or all of the top dielectric sublayer 21 during etching of the dielectric layer 2 avoids damage to the effective portion of the SOT layer 12 covered by the top dielectric sublayer 21.

[0086] Secondly, an embodiment of the present invention provides a method for fabricating a spin-orbit-moment magnetic memory. Based on the method for fabricating a spin-orbit-moment magnetic memory provided in the first aspect, the fabrication method in this embodiment includes steps S201 to S206:

[0087] Step S201: Form a stacked unit 1 and a dielectric layer 2 covering the stacked unit 1 on the substrate 6, see [link to previous step]. Figure 1 .

[0088] Step S202: Form a photolithography layer 3 on the dielectric layer 2.

[0089] Step S203: Pattern the photolithography layer 3 to form at least two independent electrical interconnect trenches 31 on the photolithography layer 3, see [link to previous step]. Figure 14 and Figure 15 .

[0090] Each electrical interconnect trench 31 overlaps only a portion of the side dielectric sublayer 23 in the vertical direction, and the sidewall of the electrical interconnect trench 31 overlaps with the sidewall of the SOT layer 12 in the vertical direction.

[0091] Step S204: Etch dielectric layer 2 according to the patterned photolithography layer 3 to expose the sidewalls of SOT layer 12, see [link to relevant documentation]. Figure 14 .

[0092] Step S205: Deposit conductive material to form a conductive layer 5 covering the dielectric layer 2.

[0093] Step S206: Planarize the conductive layer 5 so that the conductive layer 5 forms at least two independent conductive structures 51, see [link to previous step]. Figure 15 .

[0094] The method for fabricating the spin orbital moment magnetic memory provided in the second aspect differs from that in the first aspect in that the specific implementation methods of the two processes are different, as follows:

[0095] The first difference from the first aspect lies in the relative top dielectric sublayer 21 of the electrical interconnect trench 31 formed in step S203. In this embodiment, the electrical interconnect trench 31 formed by the patterned photolithography layer 3 overlaps with a portion of the first pre-dielectric sublayer 221 and a portion of the second pre-dielectric sublayer 222 in the vertical direction.

[0096] The second difference between the two processes lies in the location of the etching in step S204, where only the sidewalls of the SOT layer 12 are exposed. It is understood that this second difference stems from the first difference in the process itself, and this embodiment will not elaborate further on this.

[0097] Thirdly, one embodiment of the present invention provides a spin orbital moment magnetic memory, which is obtained by any of the methods described above.

[0098] The spin-orbit-moment magnetic memory provided in this embodiment requires fewer photolithography steps and has a simpler fabrication process, thus reducing the fabrication cost of the spin-orbit-moment magnetic memory.

[0099] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0100] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A method for fabricating a spin-orbit magnetic memory, characterized in that, include: A stacked unit (1) and a dielectric layer (2) covering the stacked unit (1) are formed on a substrate (6). The stacked unit (1) includes, from bottom to top, a magnetic tunnel junction (11) and an SOT layer (12). The dielectric layer (2) includes a top dielectric sublayer (21) that overlaps with the SOT layer (12) in the vertical direction and a side dielectric sublayer (23) located on the periphery of the stacked unit (1). A photolithography layer (3) is formed on the dielectric layer (2); The photolithography layer (3) is patterned to form at least two independent electrical interconnect trenches (31) on the photolithography layer (3); wherein each electrical interconnect trench (31) overlaps with a portion of the top dielectric sublayer (21) and a portion of the side dielectric sublayer (23) in the vertical direction, or each electrical interconnect trench (31) overlaps with a portion of the side dielectric sublayer (23) in the vertical direction, and the sidewall of the electrical interconnect trench (31) overlaps with the sidewall of the SOT layer (12) in the vertical direction; The dielectric layer (2) is etched according to the patterned photolithography layer (3) to expose the upper surface of the SOT layer (12) when the electrical interconnect trench (31) overlaps with a portion of the top dielectric sublayer (21) and a portion of the side dielectric sublayer (23) in the vertical direction, or to expose the sidewall of the SOT layer (12) when the electrical interconnect trench (31) overlaps with a portion of the side dielectric sublayer (23) in the vertical direction and the sidewall of the electrical interconnect trench (31) overlaps with the sidewall of the SOT layer (12) in the vertical direction. A conductive material is deposited to form a conductive layer (5) covering the dielectric layer (2); The conductive layer (5) is planarized so that the conductive layer (5) forms at least two independent conductive structures (51).

2. The method according to claim 1, characterized in that, Prior to the step of depositing the conductive material to form a conductive layer (5) covering the dielectric layer (2), the method further includes: Remove the patterned photolithography layer (3); The materials of the photolithography layer (3) include: photoresist material, metal hard mask material or dielectric hard mask material.

3. The method according to claim 1, characterized in that, When the material of the photolithography layer (3) is an insulating material, the step of planarizing the conductive layer (5) to form at least two independent conductive structures (51) in the conductive layer (5) includes: The conductive layer (5) is planarized to expose the photolithography layer (3) or the top dielectric sublayer (21).

4. The method according to claim 1, characterized in that, When the material of the photolithography layer (3) is a conductive material, the step of planarizing the conductive layer (5) to form at least two independent conductive structures (51) includes: The conductive layer (5) is planarized to expose the top dielectric sublayer (21).

5. The method according to claim 1, characterized in that, The step of forming a stacked unit (1) and a dielectric layer (2) covering the stacked unit (1) on the substrate (6) includes: A stacked structure, a first pre-dielectric layer, and a hard mask layer (4) are sequentially deposited on the substrate (6), the stacked structure being used to form the SOT layer (12) and the magnetic tunnel junction (11); The hard mask layer (4) is patterned, and the first pre-dielectric layer and the stacked structure are etched according to the patterned hard mask layer (4) to form the top dielectric sublayer (21), the SOT layer (12) and the magnetic tunnel junction (11); A second preparative dielectric layer (22) is deposited to cover the magnetic tunnel junction (11); The second preparative dielectric layer (22) is planarized to remove the hard mask layer (4) and obtain the side dielectric sublayer (23).

6. The method according to claim 5, characterized in that, The step of depositing a second preparative dielectric layer (22) covering the magnetic tunnel junction (11) includes: The first preparative dielectric sublayer (221) and the second preparative dielectric sublayer (222) are sequentially deposited to coat the magnetic tunnel junction (11); The step of etching the dielectric layer (2) according to the patterned photolithography layer (3) includes: The first preparatory dielectric sublayer (221) is etched, and the etching stop position of the first preparatory dielectric sublayer (221) is higher than the lower surface of the SOT layer (12).

7. The method according to claim 6, characterized in that, The material of the hard mask layer (4) includes at least one of tantalum, titanium, tantalum nitride and titanium nitride; The shape of the patterned hard mask layer (4) includes: circle, ellipse, rectangle, rhombus or triangle; The first pre-dielectric sublayer (221) is made of silicon nitride, and the second pre-dielectric sublayer (222) is made of silicon oxide.

8. The method according to claim 1, characterized in that, The step of etching the dielectric layer (2) according to the patterned photolithography layer (3) includes: Based on the patterned photolithography layer (3), the dielectric layer (2) is etched using reactive ion etching or ion beam etching.

9. The method according to claim 1, characterized in that, The material of the top dielectric sublayer (21) includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide.

10. A spin-orbit moment magnetic memory, characterized in that, The spin orbital moment magnetic storage device is prepared by the method described in any one of claims 1 to 9.

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