A dual-input GaN HEMT device and a manufacturing method thereof

Abstract

The present invention relates to the technical field of semiconductor devices, and discloses a dual-input GaN HEMT device and a manufacturing method thereof. The device comprises a reverse device region layer, a common drain layer and a forward device region layer epitaxially grown in sequence on a substrate, wherein the forward device region layer is provided with an external input structure including a surface source and a surface gate, and the reverse device region layer comprises an internal input structure biased toward the substrate, namely, an internal source and an internal gate, and effective transmission of internal and external input signals is achieved by providing a through hole. The present invention achieves the effect of doubling the device integration, optimizing the signal processing performance and enhancing the device reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular, to a dual-input GaN HEMT device and a manufacturing method thereof. Background Art

[0002] GaN HEMT (High Electron Mobility Transistor) devices have excellent high-frequency and high-power performance and are widely used in fields such as radio frequency communication and power electronics. Such semiconductor GaN HEMT devices that provide two-dimensional electron gas (2DEG) with gallium nitride (GaN) materials have become an ideal choice to replace traditional silicon-based devices due to their high saturation velocity, high breakdown electric field, and excellent heat conduction characteristics. However, with the continuous growth of application requirements, how to further improve the performance of GaN HEMT devices has become the focus of research. Although there are already various mature structures for GaN HEMT devices, some challenges still exist in practical applications. A common technical problem is that at high frequencies and large signal swings, the dynamic on-resistance of the device increases significantly, resulting in performance degradation. This problem not only affects the stability and reliability of the device but also to a certain extent limits its performance in high-performance applications.

[0003] Patent Invention Publication No. CN103035701A discloses a semiconductor device and a manufacturing method thereof. An AlGaN / GaN HEMT device includes: a compound semiconductor multi-layer structure, an inserted metal layer in contact with the surface of the compound semiconductor multi-layer structure, a gate insulating film formed on the inserted metal layer, and a gate formed above the inserted metal layer, wherein the gate insulating film is interposed between the gate and the inserted metal layer. By disposing the inserted metal layer on the p-GaN capping layer of the gate, the accumulation of unwanted charges is prevented, thereby minimizing the increase in on-state resistance and threshold variation. The focus of the related prior art is to improve the reliability of the MIS device and minimize the increase in on-state resistance with a gate-improved structure, and the device architecture is single-pole input.

[0004] Invention patent publication number CN103915492A discloses a high electron mobility transistor and a method for forming the same, wherein a second III-V compound layer different in composition from a first III-V compound layer is disposed on the first III-V compound layer, the first III-V compound layer being specifically a GaAs layer or an InP layer, and the second III-V compound layer being specifically an AlGaN layer. A dielectric passivation layer is disposed on the second III-V compound layer. A source component and a drain component are disposed on the second III-V compound layer and extend through the dielectric passivation layer. A gate electrode between the source component and the drain component is disposed above the second III-V compound layer. An oxygen-containing region is at least embedded in the second III-V compound layer below the gate electrode. The gate dielectric layer has a first portion and a second portion, the first portion being located below the gate electrode and on the oxygen-containing region, and the second portion being located on a portion of the outer surface of the gate electrode. In the existing related technologies, the improvement point is still in the gate. By introducing an oxygen-containing region and an optimized gate dielectric layer, part of the electrons in the carrier channel are effectively depleted, so that the HEMT is in a normally closed state, thereby improving the linearity of the device and the reliability of performance. The device architecture is still a unipolar input.

[0005] Invention patent publication number CN114497207A discloses a GaN-based double-channel HEMT device, the device includes an epitaxial structure, the epitaxial structure includes a first, a second, and a third semiconductor layer arranged in sequence along a set direction, the bandgap widths of the first, second, and third semiconductor layers increase in sequence (specifically GaN, AlGaN, AlInN), a two-dimensional electron gas is formed at the interface between any of the first and third semiconductor layers and the second semiconductor layer, and the semiconductor materials constituting the second and third semiconductor layers have the same lattice constant; the epitaxial structure is also coordinated with the source, drain, and gate. In the existing related technology, the improvement is that the second semiconductor layer (upper channel layer) that forms the upper two-dimensional gas also serves as a barrier layer for forming the lower two-dimensional gas, and the lower two-dimensional gas is formed in the third semiconductor layer (lower channel layer), which is used to increase the surface density of the two-dimensional electron gas, and improve the output current and output power density of the HEMT device. The device architecture is still a unipolar input, and only the design of the gate and source electrodes of the unipolar input is described.

[0006] Invention patent publication number CN114649403A discloses a high linearity GaN HEMT radio frequency power device with improved large signal transconductance, comprising a substrate layer, a high resistance buffer layer, a second barrier layer, a channel layer, a first barrier layer, and a protective layer arranged in sequence, and a source, a gate, and a drain are arranged above the protective layer; a first two-dimensional electron gas and a second two-dimensional electron gas are formed between the channel layer and the first barrier layer and the second barrier layer; the source, the gate, and the drain are used to access an external control signal to control the electron movement of the first two-dimensional electron gas and the second two-dimensional electron gas formed by the channel layer; wherein, when the signal is large, the electrons in the second two-dimensional electron gas will flow into the first two-dimensional electron gas. In the existing related technology, the improvement is that barrier layers (i.e., the first barrier layer and the second barrier layer) are respectively provided above and below the channel layer, and the first two-dimensional electron gas and the second two-dimensional electron gas separated in the upper and lower spaces are formed in the same layer of the channel layer; when the signal is large, the electrons in the second two-dimensional electron gas will flow into the first two-dimensional electron gas, ensuring the stability of the electron concentration in the first two-dimensional electron gas, so as to improve the linearity of the device. That is to say, the first two-dimensional electron gas serves as the main two-dimensional electron gas, the second two-dimensional electron gas serves as the backup buffer two-dimensional electron gas, the device architecture is still a unipolar input, and only the design of the dual two-dimensional electron gas is described.

[0007] In summary, existing GaN HEMT devices are generally based on the establishment of a single device with unipolar input in the same device area. Under high frequency and large signal swing, the dynamic on-resistance increases significantly, resulting in a decrease in device performance. This problem not only affects the stability and reliability of the device, but also limits its performance in high-performance applications to a certain extent. Especially in complex electromagnetic environments, the design of a single input port is often difficult to meet the requirements of diversified signal interaction, which undoubtedly restricts the expansion potential of GaN HEMT devices in higher-level application scenarios. Therefore, it is urgent to develop a new device structure that can break through the limitations of traditional architectures while maintaining existing advantages, and achieve more efficient signal processing and higher system compatibility. Summary of the invention

[0008] The main purpose of the present invention is to provide a dual-input GaN HEMT device and a semiconductor chip device using the device. The main improvement is to achieve single-sided dual input, and to establish two GaN HEMT devices with bipolar input and common drain in one device area, which can double the device integration, optimize signal processing performance and enhance device reliability.

[0009] The second main purpose of the present invention is to provide a method for manufacturing a dual-input GaN HEMT device, which is used to prepare a dual-input GaN HEMT device with optimized structure.

[0010] The main purpose of the present invention is achieved through the following technical solutions:

[0011] A dual-input GaN HEMT device is proposed, comprising:

[0012] The reverse device region layer is epitaxially grown on the substrate;

[0013] A common drain layer is epitaxially grown on the reverse device region layer;

[0014] A forward device region layer, epitaxially grown on the common drain layer;

[0015] Among them, an external input structure is arranged on the forward device region layer, and the external input structure includes a surface source and a surface gate; the reverse device region layer includes an internal input structure biased towards the substrate, and the internal input structure includes an internal source and an internal gate made of semiconductor material.

[0016] By adopting the above structural technical solution, the reverse device layer is arranged in the reverse direction to the forward device layer and the common drain layer is used together. The internal input structure of the reverse device layer includes a built-in source and a built-in gate, thereby achieving structural optimization of the dual-input GaN HEMT device. The specific effects are as follows:

[0017] 1. Reduce the size of GaN HEMT devices: Integrating two GaN HEMT devices in parallel in one chip area significantly reduces the overall size of the device and improves the integration of GaN HEMT devices;

[0018] 2. Improve the performance of GaN HEMT devices in a chip area: Based on the integration of internal input structure and external input structure, the device chip can simultaneously receive and process two input signals, effectively enhancing signal processing capabilities and flexibility;

[0019] 3. Expand the application of GaN HEMT devices: The dual-input GaN HEMT device of the present invention is particularly suitable for high-frequency and high-power application scenarios such as inverters, and can significantly increase the operating frequency of the inverter, thereby improving the overall performance of the system;

[0020] 4. Improve the reliability and stability of GaN HEMT devices: By rationally arranging the positions of the built-in source and built-in gate, the vertically symmetrical structure with a shared drain layer as the center layer reduces parasitic capacitance and resistance, and improves the reliability and stability of the device.

[0021] In a preferred example, the present invention can be further configured as follows: the longitudinal projections of the built-in source and the built-in gate are relatively offset from the longitudinal space of the surface source and the surface gate, and an upper input conduction hole is opened from the built-in source and the built-in gate to penetrate upward through the common drain layer and the forward device region layer.

[0022] By adopting the above-mentioned preferred technical features, the surface source and the surface gate can be relatively staggered by utilizing the built-in source and the built-in gate, so as to facilitate the provision of an upper input via hole with an opening facing upward, and the built-in source and the built-in gate can be extended and connected to the front side of the device; this not only achieves the spatial separation of internal and external input structures, improves the integration and reliability of the device, but also reduces the influence of parasitic capacitance and enhances the stability and efficiency of signal transmission.

[0023] In a more preferred example, the present invention can be further configured as follows: a lower output conduction hole is opened from the common drain layer and penetrates downwardly through the reverse device region layer and the substrate, and the longitudinal projection of the lower output conduction hole is relatively staggered from the longitudinal space between the built-in source and the built-in gate.

[0024] By adopting the above preferred technical features, by using the lower output conduction hole opened from the common drain layer and penetrating downwardly through the reverse device region layer and the substrate, the longitudinal projection of the lower output conduction hole is relatively staggered from the longitudinal space of the built-in source and the built-in gate, thereby effectively reducing parasitic capacitance, improving the switching speed and frequency response of the device, reducing signal delay and distortion, thereby improving the overall performance of the GaN HEMT device, and being suitable for high-frequency and high-power application scenarios.

[0025] In a variation example, the present invention can be further configured as follows: the longitudinal projections of the built-in source and the built-in gate are relatively offset from the longitudinal space of the surface source and the surface gate, a first input via hole is opened from the surface source and the surface gate and passes downward through the forward device region layer, the common drain layer, the reverse device region layer and the substrate, and a second input via hole is opened from the built-in source and the built-in gate and passes downward through the substrate.

[0026] By adopting the above preferred technical features, the surface source and the surface gate are relatively staggered by utilizing the built-in source and the built-in gate, so as to facilitate the arrangement of the first input conduction hole and the second input conduction hole with the opening facing downward, and the surface source and the surface gate as the first input control source and the built-in source and the built-in gate as the second input control source are all extended and connected to the back side of the device; thereby, a dual-input architecture is provided on the back side of the device, and the front side of the device does not need to be provided with a source and has a better output distribution surface, so that the dual-input GaN HEMT device is not only effectively reduced in size, but also has a significant improvement in electrical performance, especially in high-frequency applications, and can support higher frequency operations, and is suitable for high-power devices of inverters.

[0027] In a more preferred variation example, the present invention may be further configured as follows: an upper output via hole is opened from the common drain layer and penetrates upward through the forward device region layer, and a longitudinal projection of the upper output via hole is relatively staggered from the longitudinal space between the surface source and the surface gate.

[0028] By adopting the above preferred technical features, by using the upper output conduction hole opened from the common drain layer and penetrating upward through the forward device region layer, the longitudinal projection of the upper output conduction hole is relatively staggered from the longitudinal space between the surface source and the surface gate, and the drain can extend to the front of the device over a large area to improve the heat dissipation of the front of the device, and effectively reduce parasitic capacitance, improve the switching speed and frequency response of the device, reduce signal delay and distortion, thereby improving the overall performance of the GaN HEMT device, and being suitable for high-frequency and high-power application scenarios.

[0029] In a preferred example, the present invention may be further configured as follows: the dual-input GaN HEMT device further includes a redistribution layer disposed at the bottom of the substrate.

[0030] By adopting the above preferred technical features and using the redistribution layer to be arranged at the bottom of the substrate, the electrical connection and signal transmission performance of the source and gate on the back of the device can be effectively improved; the specific effects are as follows:

[0031] 1. Provide more connection paths on the back of the device: The redistribution layer can provide two sets of source and gate external connection paths on the back of the device, reducing signal transmission loss and improving signal integrity;

[0032] 2. It can reduce the parasitic inductance and resistance of the GaN HEMT device: the rewiring layer can change the positions of the extended connection terminals of the built-in source, the built-in gate, the surface source and the surface gate, so as to achieve the effect of redistributing the positions, and the distance between adjacent extended connection terminals is uniform and greater than the original minimum distance between the source and the gate, thereby reducing the parasitic inductance and parasitic resistance, thereby improving the high-frequency performance of the device;

[0033] 3. It can improve the heat dissipation performance of the GaN HEMT device on the back side of the device: the redistribution layer includes a circuit, a pad connected to the corresponding circuit, and a heat dissipation island surrounding the circuit and the pad. The coverage area of ​​the redistribution layer is greater than or equal to 75% of the bottom area of ​​the substrate, which can reduce and disperse heat, reduce the temperature of local hot spots, further improve the thermal management capability of the device, and enhance the reliability and life of the device.

[0034] In a preferred example, the present invention can be further configured as follows: the reverse device region layer includes a passivation layer, a high-resistance buffer layer, a first barrier layer, a first channel layer and a first current blocking layer in sequence; the forward device region layer includes a second current blocking layer, a second channel layer and a second barrier layer in sequence; and the internal input structure is located in the high-resistance buffer layer.

[0035] By adopting the above preferred technical features and utilizing the specific structures of the reverse device layer and the forward device layer, based on the internal input structure being located in the high-resistance buffer layer, not only the GaN The breakdown voltage and conductivity of the HEMT device are improved, and the control ability of the current is also enhanced; wherein, the first current blocking layer and the second current blocking layer effectively prevent the current from flowing in unnecessary areas, thereby improving the voltage resistance of the device; the presence of the high-resistance buffer layer (commonly used as a low-aluminum AlGaN buffer layer, GaN buffer layer or AlN buffer layer in which a high-resistance pattern area is formed by carbon doping or iron doping) is used to mitigate the lattice mismatch between the substrate (commonly used as a Si substrate, SiC substrate or sapphire substrate) and the first barrier layer (commonly used as an AlGaN layer, aluminum gallium nitrogen) to improve the crystal quality of the single crystal, and the high-resistance buffer layer can also be patterned to set the built-in source and the built-in gate to provide an internal source and gate; the internal input structure is located in the high-resistance buffer layer to ensure that the built-in source and the built-in gate have normal electrical connection and optimize the device performance; the reasonable arrangement of each functional layer helps to reduce leakage current and improve the reliability and stability of the device.

[0036] In a preferred example, the present invention can be further configured as follows: the first current blocking layer is patterned in the first drift layer, the first drift layer is formed on the first channel layer, the second current blocking layer is patterned in the second drift layer, the second drift layer is formed on the common drain layer, and the first drift layer and the second drift layer are sandwiched with the common drain layer.

[0037] By adopting the above-mentioned preferred technical features, the common drain layer is sandwiched between the first drift layer and the second drift layer, so that the reasonable arrangement of each functional layer helps to reduce leakage current and improve the reliability and stability of the device. The patterning of the first current blocking layer and the second current blocking layer effectively prevents the current from flowing in unnecessary areas, thereby improving the withstand voltage performance of the dual-input GaN HEMT device. The high-resistance buffer layer is used to reduce the lattice mismatch between the substrate and the first barrier layer (AlGaN layer), improve the crystal quality of the first barrier layer, and enhance the conductivity. The internal input structure is located in the high-resistance buffer layer, which is used to ensure the individual electrical connection of the built-in source and the built-in gate, and optimize the device performance.

[0038] The first main purpose of the present invention is also achieved through the following technical solutions: a semiconductor chip device is proposed, including a dual-input GaN HEMT device that can implement the feature combination as described above, to achieve high integration of GaN HEMT devices. Two GaN HEMT devices are integrated in a chip area in a vertically parallel relationship, which significantly reduces the overall size of the device and improves the integration. The structure of the internal and external input structure enables the GaN HEMT device to receive and process two input signals at the same time, enhancing the signal processing capability and flexibility. The semiconductor chip device is particularly suitable for high-frequency and high-power application scenarios such as inverters, and can significantly increase the operating frequency of the inverter, thereby improving the overall performance of the system. By arranging the positions of the built-in source and the built-in gate, the parasitic capacitance and resistance are reduced, and the reliability and stability of the GaN HEMT device are improved. In the preferred variation example, by setting a variety of vias and redistribution layers, the electrical connection and signal transmission performance of the device are further optimized, which not only reduces the physical size of the device, but also improves the performance in high-frequency and high-power applications, and is particularly suitable for inverters and other scenarios that require high operating frequencies.

[0039] The second main purpose of the present invention is achieved through the following technical solutions:

[0040] A method for manufacturing a dual-input GaN HEMT device is proposed, comprising:

[0041] Step S1, epitaxially growing a reverse device region layer on a substrate, wherein the reverse device region layer comprises an internal input structure biased toward the substrate, and the internal input structure comprises an internal source and an internal gate made of a semiconductor material;

[0042] Step S2, epitaxially growing a common drain layer on the reverse device region layer;

[0043] Step S3, epitaxially growing a forward device region layer on the common drain layer;

[0044] Step S4: Disposing an external input structure on the forward device region layer, wherein the external input structure includes a surface source and a surface gate.

[0045] By adopting the above method and technical scheme, a GaN HEMT semiconductor device with a bipolar input architecture can be efficiently prepared. By sequentially epitaxially growing a reverse device region layer, a common drain layer and a forward device region layer on a substrate, and arranging an external input structure including a surface source and a surface gate on the forward device region layer, the compact integration of the GaN HEMT device is achieved, the overall size of the GaN HEMT device is significantly reduced, and the integration of the GaN HEMT device is improved. Through the growth and formation of the internal and external input structures, the GaN HEMT device can simultaneously receive and process two input signals, enhancing the signal processing capability and flexibility. By relatively staggering the longitudinal space of the surface source and the surface gate through the longitudinal projection of the built-in source and the built-in gate, the parasitic capacitance and resistance are reduced, and the high-frequency performance and switching speed of the GaN HEMT device are improved. The prepared dual-input GaN HEMT device is particularly suitable for high-frequency and high-power application scenarios such as inverters, and can significantly increase the operating frequency of the inverter, thereby improving the overall performance of the system.

[0046] In a preferred example of the method of the present invention, the configuration may be further as follows: in step S4, the longitudinal space between the surface source and the surface gate is relatively staggered with respect to the longitudinal projections of the built-in source and the built-in gate.

[0047] By adopting the above preferred technical features, the longitudinal space between the surface source and the surface gate is used to relatively stagger the longitudinal projections of the built-in source and the built-in gate, effectively reducing the parasitic capacitance of each layer between the two, reducing the switching loss of the GaN HEMT device, and improving the operating frequency and efficiency of the GaN HEMT device. At the same time, this manufacturing method can also improve the thermal performance of the device, reduce the formation of local hot spots, and improve the reliability and stability of the manufactured GaN HEMT device.

[0048] The present invention can be further configured in a preferred example of the method as follows: the manufacturing method further includes:

[0049] S5, opening an upper input conduction hole in the forward direction, wherein the upper input conduction hole passes through the common drain layer and the forward device region layer from the built-in source and the built-in gate;

[0050] S6. Open a lower output conduction hole in the reverse direction, wherein the lower output conduction hole extends from the common drain layer through the reverse device region layer and the substrate, and a longitudinal projection of the lower output conduction hole is relatively offset from the longitudinal space between the built-in source and the built-in gate.

[0051] By adopting the above preferred technical features, using the upper input conduction hole opened in the forward direction and the lower output conduction hole opened in the reverse direction, the upper input conduction hole penetrates the common drain layer and the forward device layer from the built-in source and the built-in gate, so as to realize the arrangement of the connection terminals of the internal input structure and the connection terminals of the external input structure on the same surface; the lower output conduction hole opened in the reverse direction penetrates the reverse device layer and the substrate from the common drain layer, and relatively staggers the longitudinal space of the built-in source and the built-in gate. This manufacturing method not only improves the integration of the device, but also optimizes the current path, enhances the high-frequency performance and switching speed of the GaN HEMT device, and can effectively reduce the thermal resistance and improve the thermal stability of the GaN HEMT device.

[0052] The present invention can be further configured in a preferred example of the method as follows: the manufacturing method further includes:

[0053] S50, opening an upper output conduction hole in the forward direction, wherein the upper output conduction hole extends from the common drain layer through the forward device region layer, and a longitudinal projection of the upper output conduction hole is relatively staggered with a longitudinal space between the surface source and the surface gate;

[0054] S60, opening a first input conduction hole and a second input conduction hole in a reverse direction, wherein the first input conduction hole extends from the built-in source and the built-in gate through the substrate, and the second input conduction hole extends from the surface source and the surface gate through the forward device region layer, the common drain layer, the reverse device region layer and the substrate;

[0055] S70, disposing a redistribution layer at the bottom of the substrate.

[0056] By adopting the above-mentioned preferred technical features, by opening an upper output via hole in the forward direction and opening a first input via hole and a second input via hole in the reverse direction, the current through the upper output via hole passes from the common drain layer to the forward device layer, effectively improving the current transport capacity and overall performance of the device. By opening the first input via hole and the second input via hole in the reverse direction, the two input terminals are arranged on the back of the substrate, effectively improving the reliability and performance of the dual-input GaN HEMT device. The electrical connection and heat dissipation performance of the device can be effectively improved by setting a redistribution layer at the bottom of the substrate. Specifically, the redistribution layer can provide more interconnection paths, reduce signal transmission loss, and improve signal integrity. At the same time, the redistribution layer can also help disperse heat and reduce the temperature of local hot spots, thereby improving the reliability and life of the device.

[0057] In a preferred example of the method, the present invention can be further configured as follows: in step S1, the reverse device region layers sequentially include a passivation layer, a high-resistance buffer layer, a first barrier layer, a first channel layer and a first current blocking layer, and the internal input structure is located in the high-resistance buffer layer; in step S3, the forward device region layers sequentially include a second current blocking layer, a second channel layer and a second barrier layer.

[0058] By adopting the above-mentioned preferred technical features and utilizing the specific structure of the reverse device region layer and the forward device region layer of the dual-input GaN HEMT device, the first current blocking layer and the second current blocking layer are used to effectively prevent the current from flowing in unnecessary areas, thereby improving the voltage resistance performance of the device; the high-resistance buffer layer is used to reduce the lattice mismatch between the substrate and the GaN layer, improve the crystal quality, and enhance the conductivity; the internal input structure is located in the high-resistance buffer layer, which is used to ensure the individual electrical connection of the built-in source and the built-in gate, optimize the device performance, help reduce leakage current, and improve the reliability and stability of the device.

[0059] In a preferred example of the method, the present invention can be further configured as follows: the first current blocking layer of step S1 is patterned in the first drift layer, and the first drift layer is formed on the first channel layer; the second current blocking layer of step S3 is patterned in the second drift layer, and the second drift layer is formed on the common drain layer, and the first drift layer and the second drift layer are sandwiched with the common drain layer.

[0060] By adopting the above-mentioned preferred technical features, the first current blocking layer is patterned in the first drift layer, and the second current blocking layer is patterned in the second drift layer. The first current blocking layer and the second current blocking layer effectively prevent the current from flowing in unnecessary areas. The first drift layer and the second drift layer are used to improve the voltage resistance performance of the device, and help reduce lattice mismatch and improve crystal quality, thereby improving the conductivity of the common drain layer; the internal input structure is located in the high-resistance buffer layer to ensure the individual electrical connection of the built-in source and the built-in gate, thereby optimizing the device performance.

[0061] In summary, the present invention includes at least one of the following technical effects that contribute to the prior art:

[0062] 1. By setting an external input structure including a surface source and a surface gate on the epitaxially grown forward device layer, and an internal input structure including an internal source and an internal gate made of semiconductor material in the reverse device layer, two GaN HEMT devices are separated from each other by a common drain layer, thereby realizing a dual input function and improving the operating frequency and power density of the device;

[0063] 2. The longitudinal projections of the built-in source and the built-in gate are relatively staggered from the longitudinal space of the surface source and the surface gate, and the upper input via is opened to connect the corresponding layer and the lower output via is opened to connect the common drain layer, which effectively reduces the parasitic capacitance and resistance, reduces the dynamic on-resistance, and enhances the high-frequency performance of the dual-input GaN HEMT device;

[0064] 3. A plurality of output vias are provided in the common drain layer, wherein the longitudinal projection of the lower output via is relatively offset from the longitudinal space between the built-in source and the built-in gate, or the upper output via is relatively offset from the longitudinal space between the surface source and the surface gate. The drain metal layer can be provided on the back side of the substrate or on the forward device region layer and the external input structure, so as to optimize the current path and improve the thermal management capability and stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 Schematic cross-sectional views of dual-input GaN HEMT devices according to some preferred embodiments of the present invention are shown;

[0066] Figure 2 A schematic cross-sectional view of a dual-input GaN HEMT device at another cutting position is shown in some preferred embodiments of the present invention;

[0067] Figure 3 A block diagram illustrating a method for manufacturing a dual-input GaN HEMT device according to some preferred embodiments of the present invention;

[0068] Figure 4 The corresponding embodiments of some preferred embodiments of the present invention are shown in FIG. Figure 3 A schematic cross-sectional view of the assembly of step S1;

[0069] Figure 5 Some preferred embodiments of the present invention are shown in FIG. Figure 3 A schematic cross-sectional view of the assembly of step S2;

[0070] Figure 6 The corresponding embodiments of some preferred embodiments of the present invention are shown in FIG. Figure 3 A schematic cross-sectional view of the assembly of step S3;

[0071] Figure 7 The corresponding embodiments of some preferred embodiments of the present invention are shown in FIG. Figure 3 A schematic cross-sectional view of the assembly of step S4;

[0072] Figure 8 Some preferred embodiments of the present invention are shown in FIG. Figure 3 A schematic cross-sectional view of the assembly of step S5;

[0073] Fig. 9 Some preferred embodiments of the present invention are shown in FIG. Figure 3A schematic cross-sectional view of the assembly of step S6;

[0074] Fig.10 A schematic cross-sectional view of a dual-input GaN HEMT device according to a variant embodiment of the present invention is shown;

[0075] Fig.11 A schematic cross-sectional view of a dual-input GaN HEMT device at another cutting position is shown in a modified embodiment of the present invention;

[0076] Fig.12 A block diagram showing a method for manufacturing a dual-input GaN HEMT device according to a variant embodiment of the present invention;

[0077] Fig.13 The corresponding embodiment of the present invention is shown in FIG. Fig.12 A schematic cross-sectional view of the components of step S50;

[0078] Fig.14 The corresponding embodiment of the present invention is shown in FIG. Fig.12 A schematic cross-sectional view of the components of step S60;

[0079] Fig.15 The corresponding embodiment of the present invention is shown in FIG. Fig.12 A schematic cross-sectional view of the components in step S70.

[0080] Figure numerals: 10, substrate; 20, reverse device region layer; 21, passivation layer; 22, high resistance buffer layer; 23, first barrier layer; 24, first channel layer; 25, first current blocking layer; 26, first drift layer; 30, common drain layer; 31, drain metal layer; 40, forward device region layer; 41, second current blocking layer; 42, second channel layer; 43, second barrier layer; 44, second drift layer; 45, interlayer spacing film; 50, external input structure; 51, surface source; 52, surface gate; 60, internal input structure; 61, built-in source; 62, built-in gate; 71, upper input via; 72, lower output via; 81, upper output via; 82, first input via; 83, second input via; 90, redistribution layer. DETAILED DESCRIPTION

[0081] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments for understanding the inventive concept of the present invention, and cannot represent all the embodiments, nor are they interpreted as the only embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field on the premise of understanding the inventive concept of the present invention are within the scope of protection of the present invention.

[0082] It should be noted that if there are directional indications (such as up, down, left, right, front, back, etc.) involved in the embodiments of the present invention, the directional indications are only used to explain the relative position relationship and movement of the components in a certain posture. If the specific posture changes, the directional indications will also change accordingly. In order to facilitate the understanding of the technical solution of the present invention, the dual-input GaN HEMT device and the manufacturing method thereof of the present invention are further described and explained in detail below, but they are not limited to the protection scope of the present invention.

[0083] The drawings only illustrate the common parts of multiple embodiments, and the parts with differences or distinctions are described in text or presented in comparison with the drawings. Therefore, based on the industrial characteristics and technical essence, technicians familiar with the field should correctly and reasonably understand and judge whether the individual technical features described below or any combination of them can represent the same embodiment, or whether multiple technical features with mutually exclusive technical essences can only represent different variant embodiments respectively. Embodiments with too similar drawings will not be drawn repeatedly.

[0084] Figure 1 Schematic cross-sectional views of dual-input GaN HEMT devices in some preferred embodiments of the present invention are shown. Figure 2 A schematic cross-sectional view of the device at another cutting position is shown (the inner input structure 60 has a portion exceeding the outer input structure 50). Figure 1 and Figure 2 Some embodiments of the present invention disclose a dual-input GaN HEMT device, comprising: a reverse device region layer 20 epitaxially grown on a substrate 10, a common drain layer 30 epitaxially grown on the reverse device region layer 20, and a forward device region layer 40 epitaxially grown on the common drain layer 30; wherein epitaxial growth means that the reverse device region layer 20, the common drain layer 30 and the forward device region layer 40 are all made of semiconductor materials, an external input structure 50 is arranged on the forward device region layer 40, the external input structure 50 includes a surface source 51 and a surface gate 52, and is arranged on the forward device region layer 40, the external input structure 50 can be a semiconductor material or a metal material, and in this example is a metal material; the reverse device region layer 20 includes an internal input structure 60 biased toward the substrate 10, the internal input structure 60 includes an internal source 61 and an internal gate 62 of semiconductor material, and is arranged in the reverse device region layer 20. In this embodiment, by Figure 1 and Figure 2 The comparison shows that Figure 2In the embodiment, the built-in source 61 and the built-in gate 62 of the internal input structure 60 have contact portions that are beyond the surface source 51 and the surface gate 52 without being blocked and forming incomplete overlap, so as to lead the upper input conduction hole 71 upward; the common drain layer 30 has a relatively large coverage area, and has a contact portion at a portion beyond the built-in source 61 and the built-in gate 62, so as to lead the lower output conduction hole 72 downward. The side walls of the upper input conduction hole 71 and the lower output conduction hole 72 have an insulating layer, so as to isolate the electrical properties of the penetrated layer by the side walls.

[0085] The substrate 10 is used as a supporting base for device manufacturing, and is usually made of Si (silicon), SiC (silicon carbide), Al 2 O 3 (sapphire) or other known semiconductor materials with a single crystal structure. The Si substrate has a lower cost and is suitable for large-scale production; the SiC substrate has excellent thermal conductivity and electrical insulation properties and is suitable for high-frequency and high-power applications; the sapphire substrate is conducive to the epitaxial growth of the GaN base layer, eliminates lattice mismatch defects, and has good thermal stability, insulation and transparency. The reverse device region layer 20, the common drain layer 30 and the forward device region layer 40 are epitaxially grown in sequence on the substrate 10. The reverse device region layer 20 is epitaxially grown on the substrate 10. The reverse device region layer 20 specifically includes a passivation layer 21, a high-resistance buffer layer 22, a first barrier layer 23, a first channel layer 24, and a first current blocking layer 25. The passivation layer 21 may be formed or not formed according to the material of the substrate 10. For example, when the substrate 10 is a sapphire substrate, the passivation layer 21 may be selectively omitted or not omitted; when the substrate 10 is a silicon substrate, the epitaxially grown passivation layer 21 is usually silicon dioxide or silicon nitride; when the substrate 10 is a silicon carbide substrate, the epitaxially grown passivation layer 21 may be made of silicon nitride. In order to allow the first channel layer 24, which is specifically a GaN layer, to have a good lattice, the substrate 10 is a sapphire substrate or a silicon carbide substrate, and the material of the passivation layer 21 is aluminum nitride (AlN) or gallium oxide (GaO). 2 O 3 ), the basic material of the high-resistance buffer layer 22 is selected from aluminum gallium nitride (AlGaN) or gallium nitride (GaN) and is modified by patterned doping, and the material of the first barrier layer 23 is selected from aluminum gallium nitride (AlGaN).

[0086] The common drain layer 30 is epitaxially grown on the reverse device region layer 20, and can be made of highly doped GaN semiconductor materials, such as N-type GaN layer. The common drain layer 30 can also be made of other similar semiconductor materials, such as AlGaN or InGaN, to ensure good conductivity. Similarly, the built-in source 61 and the built-in gate 62 can be made of highly doped GaN semiconductor materials, such as N-type GaN layer, or other similar semiconductor materials, such as AlGaN or InGaN. The forward device region layer 40 is epitaxially grown on the common drain layer 30, and the forward device region layer 40 specifically includes a second current blocking layer 41, a second channel layer 42 and a second barrier layer 43. The difference between the reverse device layer 20 and the forward device layer 40 is that the preparation order of each layer structure of the reverse device layer 20 is opposite to the preparation order of each layer structure of the forward device layer 40. For example, the preparation order of the forward device layer 40, such as a normal GaN HEMT device, is: the drift layer precedes the channel layer, and the channel layer precedes the barrier layer; while the preparation order of the reverse device layer 20 is: the barrier layer precedes the channel layer, and the channel layer precedes the drift layer. Therefore, the two channel layers (the first channel layer 24 and the second channel layer 42) are separated in non-adjacent layers including at least the common drain layer 30, and different input electrical signals can be communicated. Specifically, the specific channel layer spacing layer between the second channel layer 42 and the first channel layer 24 includes the second current blocking layer 41, the second drift layer 44, the common drain layer 30, the first current blocking layer 25, and the first drift layer 26 from top to bottom. The upper and lower channel layers (the first channel layer 24 and the second channel layer 42) are respectively used to provide upper and lower separated two-dimensional electron gas (2DEG), which is located at Figure 1 and Figure 2 At the positions of the two horizontal dotted lines shown above, the upper and lower two-dimensional electron gases (2DEG) are not formed in the same material layer, have independent driving characteristics, and are not connected as a master and a slave to each other.

[0087] The implementation principle of the basic structure of the present invention is as follows. The reverse device layer 20 is arranged in the reverse direction to the forward device layer 40 and the common drain layer 30 is used together. The internal input structure 60 of the reverse device layer 20 includes a built-in source 61 and a built-in gate 62, thereby realizing the structural optimization of the dual-input GaN HEMT device. The specific effects are as follows: two GaN HEMT devices are integrated in a chip area in a parallel relationship and share a drain, which significantly reduces the overall size of the device and improves the integration of the GaN HEMT device. The GaN HEMT device in a chip area has good lifting performance. Based on the integration of the internal input structure 60 and the external input structure 50, the device chip can simultaneously receive and process two input signals, effectively enhancing the signal processing capability and flexibility. The dual-input GaN HEMT devices are particularly suitable for high-frequency, high-power application scenarios such as inverters, and can significantly increase the operating frequency of the inverter, thereby improving the overall performance of the system; by reasonably arranging the positions of the built-in source 61 and the built-in gate 62, the upper and lower symmetrical structure with the common drain layer 30 as the central layer reduces parasitic capacitance and resistance, and improves the reliability and stability of the GaN HEMT device.

[0088] See also Figure 2 In a preferred example, by utilizing the asymmetric graphic structure of the internal input structure 60 and the external input structure 50, the internal source 61 and the internal gate 62 have a portion that is not covered by the surface source 51 and the surface gate 52, and the longitudinal projections of the internal source 61 and the internal gate 62 are relatively staggered by the longitudinal space of the surface source 51 and the surface gate 52, and the upper input conduction hole 71 that penetrates upward through the common drain layer 30 and the forward device region layer 40 is opened by the internal source 61 and the internal gate 62. Based on the setting of the upper input conduction hole 71 with the opening facing upward, the internal source 61 and the internal gate 62 are extended and connected to the front of the device; in this way, not only the spatial separation of the internal and external input structures is achieved, the integration and reliability of the device are improved, but also the influence of parasitic capacitance is reduced, and the stability and efficiency of signal transmission are enhanced.

[0089] See also Figure 2In a more preferred example, the asymmetric graphic structure of the common drain layer 30 and the internal input structure 60 is used, the common drain layer 30 has an extension portion that exceeds the built-in source 61 and the built-in gate 62, and the common drain layer 30 is provided with a lower output conduction hole 72 that penetrates downward through the reverse device region layer 20 and the substrate 10, and the longitudinal projection of the lower output conduction hole 72 is relatively staggered from the longitudinal space of the built-in source 61 and the built-in gate 62. Therefore, the two input terminals are located on the front side of the device, and the common output terminal is located on the back side of the device, which effectively reduces parasitic capacitance, improves the switching speed and frequency response of the device, and reduces signal delay and distortion, thereby improving the overall performance of the GaN HEMT device, and is suitable for high-frequency and high-power application scenarios.

[0090] See also Figure 1 and Figure 2 In a preferred example, the reverse device region layer 20 includes a passivation layer 21, a high resistance buffer layer 22, a first barrier layer 23, a first channel layer 24 and a first current blocking layer 25 in the order of growth; the forward device region layer 40 includes a second current blocking layer 41, a second channel layer 42 and a second barrier layer 43 in the order of growth; the internal input structure 60 is located in the high resistance buffer layer 22. The passivation layer 21 is usually made of Si 3 N 4 or Al 2 O 3The high-resistance buffer layer 22 has a high impedance by forming a high-resistance pattern region in the GaN layer through carbon doping or iron doping. One of the functions of the high-resistance buffer layer 22 is to reduce the lattice mismatch between the substrate 10 and the first barrier layer 23 and improve the crystal quality. Another function of the high-resistance buffer layer 22 is to pattern the internal input structure 60 with a built-in source 61 and a built-in gate 62 in the layer. Another function of the high-resistance buffer layer 22 is to electrically isolate the short-circuit conduction of the built-in source 61 and the built-in gate 62 of the internal input structure 60; the material of the built-in source 61 and the built-in gate 62 can be an N-type GaN pad. Alternatively, the high-resistance buffer layer 22 can select an AlGaN buffer layer with a low aluminum content (the Al component is 10% to 20% molar ratio), a GaN buffer layer or an AlN buffer layer. The first barrier layer 23 isolates the built-in gate 62 from the first channel layer 24. The first barrier layer 23 is usually an AlGaN layer, in which Al accounts for about 20%. The thickness of the first barrier layer 23 is between 10nm and 50nm, specifically 20nm. The function of the first barrier layer 23 is to induce the first channel layer 24 to produce a high concentration of lower two-dimensional electron gas (2DEG) toward the interface of the first barrier layer 23, so the lower two-dimensional electron gas is located on the lower surface of the first channel layer 24. In the specific example, the aluminum content of the first barrier layer 23 is higher than that of the high-resistance buffer layer 22. The first channel layer 24 is specifically a single-crystal GaN layer that is undoped or lightly n-type doped, with a thickness of about 50nm to 20nm to provide high electron mobility. The first current blocking layer 25 is specifically a P-type GaN layer with a P-type pattern, which is used to prevent the current from flowing in non-essential areas, so that the current is confined to flow in the longitudinal space of the built-in gate 62. The common drain layer 30 is specifically an N-type highly doped N-type GaN layer to ensure good conductivity, and is shared by the reverse device region layer 20 and the forward device region layer 40. On the other hand, in the forward device region layer 40, the structure of the second current blocking layer 41 can be the same as the first current blocking layer 25, the structure of the second channel layer 42 can be the same as the first channel layer 24, and the structure of the second barrier layer 43 can be the same as the first barrier layer 23. The second barrier layer 43 is disposed between the second channel layer 42 and the surface gate 52. The function of the second barrier layer 43 is to induce the second channel layer 42 to generate a high concentration of upper two-dimensional electron gas (2DEG) toward the interface of the second barrier layer 43, so the upper two-dimensional electron gas is located on the upper surface of the second channel layer 42. The aforementioned lower two-dimensional electron gas and the upper two-dimensional electron gas are also separated by most of the thickness distance of the first channel layer 24, the first current blocking layer 25, the common drain layer 30, the second current blocking layer 41 and most of the thickness distance of the second channel layer 42.

[0091] Therefore, since the internal input structure 60 is located in the high-resistance buffer layer 22 , not only the breakdown voltage and the conductive performance of the GaN HEMT device are improved, but also the ability to control the current is enhanced. Among them, the staggered configuration of the patterned first current blocking layer 25 corresponding to the built-in gate 62 and the patterned second current blocking layer 41 corresponding to the surface gate 52 effectively prevents the current from flowing in unnecessary areas, thereby improving the voltage resistance performance of the device; the existence of the high-resistance buffer layer 22 (commonly a low-aluminum AlGaN buffer layer, a GaN buffer layer or an AlN buffer layer in which a high-resistance pattern area is formed by carbon doping or iron doping) is mainly used to alleviate the lattice mismatch between the substrate 10 (commonly a Si substrate, a SiC substrate or a sapphire substrate) and the first barrier layer 23 (commonly an AlGaN layer) to improve the crystal quality of the single crystal, and the patterning in the high-resistance buffer layer 22 is used to set the built-in source 61 and the built-in gate 62 to provide an internal source and gate, so the internal input structure 60 is located in the high-resistance buffer layer 22, ensuring that the built-in source 61 and the built-in gate 62 have normal electrical connection, and also optimizing the device performance; the reasonable arrangement of each functional layer helps to reduce leakage current and improve the reliability and stability of the device.

[0092] In a more preferred example, the high-resistance buffer layer 22 of the reverse device region layer 20 is made of gradient-doped AlGaN material, in which the aluminum component gradually changes from 30% at the interface of the substrate 10 to 10% at the top of the high-resistance buffer layer 22, so as to further reduce the lattice mismatch stress and improve the mobility of the two-dimensional electron gas (2DEG). In terms of specific effects, the high-resistance buffer layer 22 is made of AlGaN material with a gradient aluminum component, which can reduce the lattice mismatch between the substrate and the GaN layer, reduce carrier scattering, and increase the mobility of the two-dimensional electron gas by 15% to 20%, so as to significantly enhance the high-frequency characteristics of the device.

[0093] In a more preferred example, the first barrier layer 23 and the second barrier layer 43 are a multilayer composite structure, including an AlN insertion layer and an AlGaN main layer grown alternately, wherein the thickness of the AlN insertion layer is 1-2 nm, which is used to suppress interface defects and increase the density of the two-dimensional electron gas. When an ultra-thin AlN layer is inserted into the first barrier layer 23 and the second barrier layer 43, the AlGaN / GaN interface defects can be suppressed, the two-dimensional electron gas density is increased by 1.5 times, and the device on-resistance is reduced by 20%.

[0094] See also Figure 1 and Figure 2, in a more specific example, the first current blocking layer 25 has a first conductive notch corresponding to the longitudinal space of the buried gate 62, and the second current blocking layer 41 has a second conductive notch corresponding to the longitudinal space of the surface gate 52. The first conductive notch of the first current blocking layer 25 and the second conductive notch of the second current blocking layer 41 are arranged in a staggered manner; thereby regulating the flow direction of carriers, making the carrier distribution in the upper and lower layers uniform, and improving the overall performance and reliability of the device.

[0095] Refer to again Figure 1 and Figure 2 , in a better example, the first current blocking layer 25 is patterned and formed in the first drift layer 26, and the first drift layer 26 is formed on the first channel layer 24. The second current blocking layer 41 is patterned and formed in the second drift layer 44, and the second drift layer 44 is formed on the common drain layer 30. The first drift layer 26 and the second drift layer 44 sandwich the common drain layer 30. Generally, the first drift layer 26, the second drift layer 44, the first channel layer 24, and the second channel layer 42 are made of the same material, such as a GaN layer. Therefore, the reasonable arrangement of each functional layer helps to reduce the leakage current and improve the reliability and stability of the device. The patterning of the first current blocking layer 25 and the second current blocking layer 41 effectively prevents the current from flowing in unnecessary areas, making the longitudinal flow of the current limited to the part where the first drift layer 26 aligns with the buried gate 62 and the part where the second drift layer 44 aligns with the surface gate 52, so as to improve the breakdown voltage performance of the dual-input GaN HEMT device. The high-resistance buffer layer 22 is used to reduce the lattice mismatch between the substrate 10 and the first barrier layer 23 (AlGaN layer), improve the crystal quality of the first barrier layer 23, and enhance the conductivity. The internal input structure 60 is located in the high-resistance buffer layer 22 to ensure the individual electrical connections of the buried source 61 and the buried gate 62 and optimize the device performance. In this example, the formed thickness of the first current blocking layer 25 is less than the formed thickness of the first drift layer 26, and the first current blocking layer 25 can be closely attached under the common drain layer 30; the formed thickness of the second current blocking layer 41 is less than the formed thickness of the second drift layer 44, and the second current blocking layer 41 can be closely attached under the second channel layer 42.

[0096] In addition, the surface source 51 usually uses a multi-layer alloy material such as Ti / Al / Ti / Au and has good ohmic contact characteristics; the surface gate 52 usually uses a Ni / Au material and has a low Schottky barrier height. In different examples, the surface source 51 and the surface gate 52 can also use semiconductor materials and make them conductive. The bottom of the surface source 51 contacts the second channel layer 42, and the bottom of the surface gate 52 contacts the second barrier layer 43.

[0097] Refer to Figure 1and Figure 2 In a more specific example, a layer spacing film 45 can be set on the top surface of the device to cover the sides of the surface source 51 and the surface gate 52; a drain metal layer 31 can be set on the bottom surface of the device (specifically, the lower surface of the substrate 10), and the lower output conductive hole 72 connects the common drain layer 30 and the drain metal layer 31; thus, a dual-input source is formed on the top surface of the dual-input GaN HEMT device, and a single output source is formed on the bottom surface of the dual-input GaN HEMT device.

[0098] See also Figure 3 Some embodiments of the present invention also provide a method for manufacturing a dual-input GaN HEMT device, including steps S1 to S6, and referring to Figures 4 to 9 , explaining each step.

[0099] Figure 4Corresponding to step S1, an inverted device region layer 20 is epitaxially grown on the substrate 10, and the inverted device region layer 20 includes an internal input structure 60 biased toward the substrate 10, and the internal input structure 60 includes an internal source 61 and an internal gate 62 of a semiconductor material. In step S1, the inverted device region layer 20 includes a passivation layer 21, a high resistance buffer layer 22, a first barrier layer 23, a first channel layer 24 and a first current blocking layer 25 in sequence, and the internal input structure 60 is located in the high resistance buffer layer 22. The passivation layer 21 is deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD) technology, and has a thickness of about 50nm to 200nm. On the passivation layer 21, the high-resistance buffer layer 22 is modified by doping to form a high-resistance pattern area, and the opposite pattern of the high-resistance pattern area forms the internal input structure 60. The high-resistance buffer layer 22 is used to reduce the lattice mismatch between the substrate 10 and the first barrier layer 23, improve the crystal quality, and enhance the conductivity; the internal input structure 60 is located in the high-resistance buffer layer 22, and is used to ensure the individual electrical connection of the built-in source 61 and the built-in gate 62, optimize the device performance, help reduce leakage current, and improve the reliability and stability of the device. On the high-resistance buffer layer 22, the first barrier layer 23 is deposited by molecular beam epitaxy (MBE) or MOCVD technology, and the thickness is between 10nm and 50nm. On the first barrier layer 23, the first channel layer 24 (First Channel Layer) is formed by depositing an undoped or lightly n-type doped GaN layer by MBE or MOCVD technology, and the thickness is about 50nm to 20nm. In a specific example, in step S1, the first drift layer 26 is formed on the first channel layer 24, and the first current blocking layer 25 is patterned in the first drift layer 26. On the first channel layer 24, the first drift layer 26 is deposited by MBE or MOCVD technology, and can be made of the same material (GaN) as the first channel layer 24. The first current blocking layer 25 (First Current Blocking Layer) located in the first drift layer 26 is a P-type GaN layer using P-type patterned ion implantation technology.

[0100] Figure 5 Corresponding to step S2, epitaxially grow a common drain layer 30 on the reverse device region layer 20. The common drain layer 30 is formed to cover a large area. The common drain layer 30 (Common Drain Layer) on the reverse device region layer 20 is usually made of an N-type highly doped N-type GaN layer with conductive properties, and is formed by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD) technology.

[0101] Figure 6Corresponding to step S3, a forward device region layer 40 is epitaxially grown on the common drain layer 30. In step S3, the forward device region layer 40 includes a second current blocking layer 41, a second channel layer 42 and a second barrier layer 43 in sequence. Based on the specific structure of the reverse device region layer 20 and the forward device region layer 40 of the dual-input GaN HEMT device, the first current blocking layer 25 and the second current blocking layer 41 are used to effectively prevent the current from flowing in unnecessary areas, thereby improving the withstand voltage performance of the device. In a specific example, the second current blocking layer 41 of step S3 is patterned and formed in the second drift layer 44, and the second drift layer 44 is formed on the common drain layer 30, and the first drift layer 26 and the second drift layer 44 sandwich the common drain layer 30. The first drift layer 26 and the second drift layer 44 are used to improve the withstand voltage performance of the device, and help reduce lattice mismatch, improve crystal quality, and thus improve the conductivity of the common drain layer 30. On the common drain layer 30, the second drift layer 44 (Second Drift Layer) can be a GaN layer that is the same as the first drift layer 26, and is deposited by MBE or MOCVD technology. The second drift layer 44 is used for subsequent patterning. In the second drift layer 44, the second current blocking layer 41 (Second Current Blocking Layer) is a P-type patterned P-type GaN layer that is the same as the first current blocking layer 25, and is formed by P-type patterned ion implantation technology. On the second current blocking layer 41, the material of the second channel layer 42 (Second Channel Layer) is selected as a single crystal GaN layer, and an undoped or lightly n-doped GaN layer is deposited by MBE or MOCVD technology, with a thickness of approximately 50nm to 20nm. On the second channel layer 42, the material of the second barrier layer 43 (Second Barrier Layer) is selected as an AlGaN layer (aluminum accounts for about 20%), which is deposited by MBE or MOCVD technology, and has a thickness between 10nm and 50nm. The second barrier layer 43 is pattern-etched to expose a portion of the second channel layer 42 for disposing the surface source 51 .

[0102] Figure 7Corresponding to step S4, an external input structure 50 is arranged on the forward device layer 40, and the external input structure 50 includes a surface source 51 and a surface gate 52. In step S4, the longitudinal space of the surface source 51 and the surface gate 52 is relatively staggered from the longitudinal projection of the built-in source 61 and the built-in gate 62. Thus, the parasitic capacitance of each layer between the two is effectively reduced, the switching loss of the GaN HEMT device is reduced, and the operating frequency and efficiency of the GaN HEMT device are improved. At the same time, this manufacturing method can also improve the thermal performance of the device, reduce the formation of local hot spots, and improve the reliability and stability of the manufactured GaN HEMT device. On the forward device layer 40, the material layer corresponding to the surface source 51 and the surface gate 52 is deposited on the forward device layer 40 by electroplating or evaporation deposition technology, and then the pattern of the surface source 51 and the surface gate 52 is formed by photolithography and etching technology, and then annealing is performed to optimize the performance of the ohmic contact and Schottky contact. In addition, on the forward device layer 40, the interlayer dielectric layer 45 is usually made of SiO 2 or Si 3 N 4 Insulating materials such as MOSFET are deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD) technology to isolate the functional layers and cover the side walls of the surface source 51 and the surface gate 52 .

[0103] In the specific example of step S4, the metal contact layer of the surface source 51 and the surface gate 52 is formed by a laser annealing process, and the annealing temperature gradient decreases from the center to the edge to optimize the ohmic contact resistance and reduce edge thermal damage. The laser gradient annealing process uses non-uniform laser annealing, the central high temperature area optimizes the contact resistance, and the edge low temperature area protects the interlayer structure, and the ohmic contact resistance is reduced by 25%, so the device reliability can be improved.

[0104] Figure 8 Corresponding to step S5, a silicon through-hole process is used to open an upper input via hole 71 in the forward direction. The upper input via hole 71 passes through the common drain layer 30 and the forward device region layer 40 from the built-in source 61 and the built-in gate 62. The sidewalls of the upper input via hole 71 are electrically insulated. Since the material of the built-in source 61 and the built-in gate 62 is highly doped N-type GaN, AlGaN or InGaN, high concentrations of N-type elements, Al or In are precipitated during etching (N-type elements are precipitated as secondary waveforms), and based on element detection in semiconductor processes, the built-in source 61 and the built-in gate 62 can serve as etching stop layers for the upper input via hole 71.

[0105] Fig. 9Corresponding to step S6, after flipping the substrate 10, a silicon via process is used to reversely open a lower output via 72, wherein the lower output via 72 passes through the reverse device region layer 20 and the substrate 10 from the common drain layer 30, and the longitudinal projection of the lower output via 72 is relatively staggered from the longitudinal space of the built-in source 61 and the built-in gate 62. The sidewall of the lower output via 72 is electrically insulated. Since the material of the common drain layer 30 is an N-type highly doped N-type GaN layer, the primary waveform of the N-type element is precipitated, and the common drain layer 30 can be used as an etching stop layer for the lower output via 72.

[0106] The implementation principle of the method embodiment of the present invention is that a GaN HEMT semiconductor device with a bipolar input architecture can be efficiently prepared. By sequentially epitaxially growing a reverse device region layer 20, a common drain layer 30 and a forward device region layer 40 on a substrate 10, and arranging an external input structure 50 including a surface source 51 and a surface gate 52 on the forward device region layer 40, a compact integration of the GaN HEMT device is achieved, the overall size of the GaN HEMT device is significantly reduced, and the integration of the GaN HEMT device is improved. Through the growth and formation of the internal and external input structures, the GaN HEMT device can simultaneously receive and process two input signals, thereby enhancing the signal processing capability and flexibility. By relatively staggering the longitudinal space between the surface source 51 and the surface gate 52 through the longitudinal projections of the built-in source 61 and the built-in gate 62, the parasitic capacitance and resistance are reduced, and the high-frequency performance and switching speed of the GaN HEMT device are improved. The prepared dual-input GaN HEMT device is particularly suitable for high-frequency and high-power application scenarios such as inverters, and can specifically significantly increase the operating frequency of the inverter, thereby improving the overall performance of the system. In a specific inverter application, direct current is connected to the surface source 51 and the built-in source 61. When the surface gate 52 and the built-in gate 62 are driven at operating frequencies with a phase difference of 180 degrees, the common drain layer 30 can obtain an alternating current output frequency that is twice the gate frequency. Alternatively, the surface source 51 and the built-in source 61 can be mixed at various possible frequencies. Under the appropriate and individual driving of the surface gate 52 and the built-in gate 62, the combined output can be obtained at the common drain layer 30, and the output frequency is adjustable; because it is performed in the same device area of ​​the chip, the defect of line delay is effectively improved.

[0107] Fig.10 A schematic cross-sectional view of a dual-input GaN HEMT device in a variation of the present invention is shown. Fig.11 A schematic cross-sectional view of the device at another cutting position is shown. Fig.10, a variation of the present invention discloses a dual-input GaN HEMT device, which also includes: a reverse device region layer 20 epitaxially grown on a substrate 10, a common drain layer 30 epitaxially grown on the reverse device region layer 20, and a forward device region layer 40 epitaxially grown on the common drain layer 30; wherein an external input structure 50 is arranged on the forward device region layer 40, and the external input structure 50 includes a surface source 51 and a surface gate 52, which are arranged on the forward device region layer 40; the reverse device region layer 20 includes an internal input structure 60 biased toward the substrate 10, and the internal input structure 60 includes an internal source 61 and an internal gate 62 of a semiconductor material, which are arranged in the reverse device region layer 20. The main difference between this variation and the aforementioned embodiment is that the setting position of the through hole is different. In this variation, by Fig.10 and Fig.11 The comparison shows that Fig.11 In the embodiment, the common drain layer 30 has a relatively large coverage area, and has a contact hole portion at a portion beyond the surface source 51 and the surface gate 52 to lead the upper output conduction hole 81 upward. Fig.10 and Fig.11 The surface source 51 and the surface gate 52 have a contact portion extending beyond the built-in source 61 and the built-in gate 62 to form an incompletely overlapping contact portion, so as to lead the first input conduction hole 82 downward; Fig.10 The built-in source 61 and the built-in gate 62 have contact portions that do not spatially interfere with the first input conduction hole 82 so as to lead out the second input conduction hole 83 downward.

[0108] Reference Fig.10 and Fig.11 , the longitudinal projections of the built-in source 61 and the built-in gate 62 are relatively staggered by the longitudinal space of the surface source 51 and the surface gate 52, and the first input conduction hole 82 is opened by the surface source 51 and the surface gate 52 to penetrate downwardly through the forward device layer 40, the common drain layer 30, the reverse device layer 20 and the substrate 10, and the second input conduction hole 83 is opened by the built-in source 61 and the built-in gate 62 to penetrate downwardly through the substrate 10. The surface source 51 and the surface gate 52 as the first input control source and the built-in source 61 and the built-in gate 62 as the second input control source are all extended to the back of the device; thus, the back of the device has a dual-input structure, and the front of the device does not need to be provided with a source and has a better output distribution surface. In this way, the dual-input GaN HEMT device is not only effectively reduced in size, but also has a significant improvement in electrical performance, especially in high-frequency applications, and can support higher frequency operations, which is suitable for high-power devices of inverters.

[0109] Reference Fig.10 and Fig.11 , an upper output conduction hole 81 is opened from the common drain layer 30 and penetrates upward through the forward device region layer 40, and the longitudinal projection of the upper output conduction hole 81 is relatively staggered from the longitudinal space of the surface source 51 and the surface gate 52. Therefore, the drain can be extended to the front of the device over a large area to improve the heat dissipation of the front of the device, and effectively reduce parasitic capacitance, improve the switching speed and frequency response of the device, reduce signal delay and distortion, thereby improving the overall performance of the GaN HEMT device, and is suitable for high-frequency and high-power application scenarios.

[0110] Reference Fig.10 and Fig.11 The dual-input GaN HEMT device further includes a redistribution layer 90, which is arranged at the bottom of the substrate 10. Therefore, the electrical connection and signal transmission performance of the source and the gate on the back of the device can be effectively improved; the redistribution layer 90 can provide two sets of source and gate external connection paths on the back of the device, reduce signal transmission loss, and improve signal integrity; the redistribution layer 90 can change the positions of the extended connection terminals of the built-in source 61, the built-in gate 62, the surface source 51 and the surface gate 52, so as to achieve the effect of redistributing the positions, and the distance between adjacent extended connection terminals is uniform and greater than the original minimum distance between the source and the gate, thereby reducing parasitic inductance and parasitic resistance, thereby improving the high-frequency performance of the device; the redistribution layer 90 includes a circuit, a pad connecting the corresponding circuit, and a heat dissipation island surrounding the circuit and the pad. The coverage area of ​​the redistribution layer 90 is greater than or equal to 75% of the bottom area of ​​the substrate 10, which can reduce and disperse heat, reduce the local hot spot temperature, further improve the thermal management ability of the device, and enhance the reliability and life of the device.

[0111] See also Fig.10 and Fig.11 In a more specific example, a layer spacing film 45 can be disposed on the top surface of the device to cover the side and top surfaces of the surface source 51 and the surface gate 52; a drain metal layer 31 can be disposed on the layer spacing film 45, and an upper output via 81 connects the common drain layer 30 and the drain metal layer 31; thus, a single output source is formed on the top surface of the dual-input GaN HEMT device, and a dual input source is formed on the bottom surface of the dual-input GaN HEMT device based on the connection of the first input via 82 and the second input via 83 extending downward to the redistribution layer 90.

[0112] like Fig.12 As shown, the manufacturing method of the variation of the present invention includes steps S1 to S4 as described in the previous embodiment, and the aforementioned steps S5 and S6 may not be performed. The manufacturing method of the variation also includes steps S50, S60 and S70, and each variation step corresponds to Fig.13 , Fig.14 and Fig.15 .

[0113] Fig.13 Corresponding to step S50 , an upper output via hole 81 is opened in the forward direction. The upper output via hole 81 passes through the forward device region layer 40 from the common drain layer 30 . The longitudinal projection of the upper output via hole 81 is relatively offset from the longitudinal space between the surface source 51 and the surface gate 52 .

[0114] Fig.14 Corresponding to step S60, a first input via hole 82 and a second input via hole 83 are opened in the reverse direction. The first input via hole 82 is formed by the built-in source 61 and the built-in gate 62 penetrating the substrate 10, and the second input via hole 83 is formed by the surface source 51 and the surface gate 52 penetrating the forward device region layer 40, the common drain layer 30, the reverse device region layer 20 and the substrate 10.

[0115] Fig.15 Corresponding to step S70, a redistribution layer 90 is provided at the bottom of the substrate 10, and the thickness of the redistribution layer 90 is between 1 micron and 10 microns. The redistribution layer 90 can be made of metal material, such as copper (Cu) or aluminum (Al) and other metal materials with good electrical conductivity, and is made by photolithography and etching processes without epitaxial growth. Finally, a drain metal layer 31 is formed on the upper surface of the device.

[0116] Therefore, by opening the upper output via hole 81 in the forward direction and the first input via hole 82 and the second input via hole 83 in the reverse direction, the current through the upper output via hole 81 passes from the common drain layer 30 to the forward device layer 40, effectively improving the current transport capacity and overall performance of the device. By opening the first input via hole 82 and the second input via hole 83 in the reverse direction, the two input terminals are arranged on the back of the substrate 10, effectively improving the reliability and performance of the dual-input GaN HEMT device. The redistribution layer 90 is arranged at the bottom of the substrate 10 to effectively improve the electrical connection and heat dissipation performance of the device. Specifically, the redistribution layer 90 can provide more interconnection paths, reduce signal transmission loss, and improve signal integrity. At the same time, the redistribution layer 90 can also help disperse heat and reduce the temperature of local hot spots, thereby improving the reliability and life of the device.

[0117] The embodiment of the present invention also proposes a semiconductor chip device, including a dual-input GaN HEMT device that can implement a feature combination as described in the above embodiment or variation, so as to achieve high integration of GaN HEMT devices. Two GaN HEMT devices are integrated in a chip area in a vertically parallel relationship, which significantly reduces the overall size of the device and improves the integration. The structure of the internal and external input structure enables the GaN HEMT device to receive and process two input signals at the same time, enhancing the signal processing capability and flexibility. The semiconductor chip device is particularly suitable for high-frequency and high-power application scenarios such as inverters, and can significantly increase the operating frequency of the inverter, thereby improving the overall performance of the system. By arranging the positions of the built-in source 61 and the built-in gate 62, parasitic capacitance and resistance are reduced, and the reliability and stability of the GaN HEMT device are improved. In the preferred variation example, by setting a variety of vias and redistribution layers 90, the electrical connection and signal transmission performance of the device are further optimized, which not only reduces the physical size of the device, but also improves the performance in high-frequency and high-power applications, and is particularly suitable for inverters and other scenarios that require high operating frequencies.

[0118] In a specific application example, the chip device is integrated with a dynamic phase control module for adjusting the phase difference of the driving signal between the surface gate 52 and the internal gate 62, so that the frequency of the output signal is an integer multiple of the input signal frequency. Therefore, the dynamic phase difference adjustment of the dual input signals is realized, the output frequency is flexible and adjustable, and the rapid switching of the RF front-end frequency multiplication and mixing functions is supported, which can be extended to radar and communication system applications.

[0119] The embodiments of this specific implementation method are all preferred embodiments for facilitating the understanding or implementation of the technical solutions of the present invention, and are not intended to limit the protection scope of the present invention. All equivalent changes made based on the structure, shape, and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A dual-input GaN HEMT device, characterized in that: include: An inverse device region layer is epitaxially grown on a substrate; the inverse device region layer sequentially comprises a passivation layer, a high-resistance buffer layer, a first barrier layer, a first channel layer and a first current blocking layer, wherein the high-resistance buffer layer of the inverse device region layer is made of gradient-doped AlGaN material, wherein the aluminum component gradually changes from 30% at the substrate interface to 10% at the top of the high-resistance buffer layer, so as to further reduce lattice mismatch stress and improve the mobility of two-dimensional electron gas (2DEG); A common drain layer is epitaxially grown on the reverse device region layer; A forward device region layer is epitaxially grown on the common drain layer, and the forward device region layer sequentially comprises a second current blocking layer, a second channel layer and a second barrier layer; The forward device region layer is provided with an external input structure, the external input structure includes a surface source and a surface gate; the reverse device region layer includes an internal input structure biased toward the substrate, the internal input structure includes an internal source and an internal gate of a semiconductor material, and is located in the high-resistance buffer layer of gradient-doped AlGaN; Among them, the longitudinal projections of the built-in source and the built-in gate are relatively staggered from the longitudinal space of the surface source and the surface gate, and an upper input via hole is opened from the built-in source and the built-in gate to penetrate the common drain layer and the forward device region layer upward; a lower output via hole is opened from the common drain layer to penetrate the reverse device region layer and the substrate downward, and the longitudinal projection of the lower output via hole is relatively staggered from the longitudinal space of the built-in source and the built-in gate.

2. The dual-input GaN HEMT device according to claim 1, characterized in that: The first current blocking layer is patterned in a first drift layer formed on the first channel layer, the second current blocking layer is patterned in a second drift layer formed on the common drain layer, and the first drift layer and the second drift layer sandwich the common drain layer.

3. The dual-input GaN HEMT device according to claim 1, characterized in that: The first barrier layer and the second barrier layer are a multilayer composite structure, including an AlN insertion layer and an AlGaN main layer that are alternately grown, wherein the thickness of the AlN insertion layer is 1 to 2 nm, and is used to suppress interface defects and increase the density of the two-dimensional electron gas.

4. A semiconductor chip device, characterized in that: The invention comprises a dual-input GaN HEMT device as claimed in any one of claims 1 to 3.

5. The semiconductor chip device according to claim 4, characterized in that The semiconductor chip device is integrated with a dynamic phase control module for adjusting the phase difference of the driving signal between the surface gate and the built-in gate so that the frequency of the output signal is an integral multiple of the frequency of the input signal.

6. A method for manufacturing a dual-input GaN HEMT device, characterized in that: The manufacturing method comprises: S1. epitaxially growing a reverse device region layer on a substrate, the reverse device region layer comprising an internal input structure biased toward the substrate. In step S1, the reverse device region layer sequentially comprises a passivation layer, a high-resistance buffer layer, a first barrier layer, a first channel layer and a first current blocking layer, and the internal input structure is located in the high-resistance buffer layer; the high-resistance buffer layer of the reverse device region layer adopts a gradient-doped AlGaN material, wherein the aluminum component gradually changes from 30% at the substrate interface to 10% at the top of the high-resistance buffer layer; the internal input structure comprises an internal source and an internal gate of a semiconductor material, which are located in the high-resistance buffer layer of the gradient-doped AlGaN; S2, epitaxially growing a common drain layer on the reverse device region layer; S3, epitaxially growing a forward device region layer on the common drain layer; in step S3, the forward device region layer sequentially includes a second current blocking layer, a second channel layer and a second barrier layer; S4, setting an external input structure on the forward device region layer, the external input structure comprising a surface source and a surface gate; in step S4, the longitudinal space between the surface source and the surface gate is relatively staggered by the longitudinal projection of the built-in source and the built-in gate; The manufacturing method also includes: S5, opening an upper input conduction hole in the forward direction, wherein the upper input conduction hole passes through the common drain layer and the forward device region layer from the built-in source and the built-in gate; S6. Open a lower output conduction hole in the reverse direction, wherein the lower output conduction hole extends from the common drain layer through the reverse device region layer and the substrate, and a longitudinal projection of the lower output conduction hole is relatively offset from the longitudinal space between the built-in source and the built-in gate.

7. The method for manufacturing a dual-input GaN HEMT device according to claim 6, characterized in that: The first current blocking layer of step S1 is patterned in the first drift layer, and the first drift layer is formed on the first channel layer; the second current blocking layer of step S3 is patterned in the second drift layer, and the second drift layer is formed on the common drain layer, and the first drift layer and the second drift layer sandwich the common drain layer.

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