An epitaxial structure and its fabrication method, and an LED chip

Abstract

This invention provides an epitaxial structure and its fabrication method, as well as an LED chip. The epitaxial structure uses a built-in electric field along the growth direction, constructed by a first electric field modulation layer, to delay electrons from the N-type semiconductor layer, thereby slowing down the electrons. Simultaneously, the first electric field modulation layer can also regulate the spatial distribution of V-pits structures in the active region of the V-pits formation layer to reduce leakage channels. Furthermore, since the direction of the built-in electric field in the first electric field modulation layer is opposite to the hole injection direction, the built-in electric field of the first electric field modulation layer can retain holes in the V-pits structure, thereby effectively increasing the recombination probability of charge carriers in the active region.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diodes, and more particularly to an epitaxial structure and its fabrication method, and an LED chip. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor electronic device that emits light. An epitaxial wafer is the initial product in the LED manufacturing process. Existing LED epitaxial wafers consist of a substrate, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer. The substrate provides the growth surface for the epitaxial material, the N-type semiconductor layer provides electrons for recombination and light emission, the P-type semiconductor layer provides holes for recombination and light emission, and the active region is used for radiative recombination of electrons and holes to emit light.

[0003] III-V compound materials have attracted widespread attention and application in the fields of electrical and optical engineering due to their excellent physical and chemical properties (large bandgap, high breakdown electric field, high electron saturation mobility, etc.), such as the currently popular Micro and Mini LEDs. However, in practical applications, due to the different physical properties of electrons and holes (differences in relative mass / migration rate, etc.), an imbalance in carrier transport is inevitable. That is, electrons with relatively small mass have a higher migration rate and are prone to electron leakage; while holes with relatively large mass have a lower migration rate and are prone to insufficient injection. This results in an imbalance in carrier injection, which limits the improvement of device luminous efficiency. Therefore, reducing electron leakage and increasing hole injection has become an important path to improve LED luminous efficiency.

[0004] Currently, electron blocking layers are typically inserted into the active region near the P-type semiconductor layer. However, while blocking electron overflow, the electron blocking layer inevitably blocks hole injection as well; thus, there is still a carrier injection imbalance to varying degrees.

[0005] In view of this, the inventors specifically designed an epitaxial structure and its manufacturing method, which led to this invention. Summary of the Invention

[0006] The purpose of this invention is to provide an epitaxial structure and its fabrication method, as well as an LED chip, to solve the problem of carrier injection imbalance in existing LED chips.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] An epitaxial structure, comprising:

[0009] A substrate and an epitaxial stack disposed on the surface of the substrate; the epitaxial stack includes at least an N-type semiconductor layer, a V-pits formation layer, a first electric field modulation layer, an active region, and a P-type semiconductor layer that are sequentially stacked.

[0010] The first electric field modulation layer generates a built-in electric field along the growth direction through a heterojunction.

[0011] Preferably, the first electric field modulation layer comprises a first N-type layer, a first undoped layer, and a first P-type layer stacked sequentially.

[0012] Preferably, a first barrier layer is provided on the surface of the first P-type layer facing away from the first undoped layer.

[0013] Preferably, the first barrier layer includes an intrinsic semiconductor layer, and the thickness of the first barrier layer is not greater than the thickness of the first undoped layer.

[0014] Preferably, the thickness of the N-type semiconductor layer is D1, the thickness of the P-type semiconductor layer is D2, the thickness of the first barrier layer is D3, and the thickness of the first undoped layer is D4; then (D1+D2) / 3≤D3≤D4≤(D1+D2) / 2.

[0015] Preferably, the N-type semiconductor layer includes an N-type GaN layer, and the P-type semiconductor layer includes a P-type GaN layer; then the first N-type layer includes an N-type GaN layer, the first undoped layer includes an AlInGaN layer, and the first P-type layer includes a P-type GaN layer.

[0016] Preferably, the first barrier layer comprises an AlInGaN layer.

[0017] Preferably, a second electric field modulation layer is provided between the active region and the P-type semiconductor layer, and the second electric field modulation layer generates a built-in electric field in the reverse growth direction through the heterojunction.

[0018] Preferably, the second electric field modulation layer comprises a second P-type layer, a second undoped layer, and a second N-type layer stacked sequentially.

[0019] Preferably, a second barrier layer is provided on the surface of the second N-type layer facing away from the second undoped layer.

[0020] Preferably, the second barrier layer includes an intrinsic semiconductor layer, and the thickness of the second barrier layer is not greater than the thickness of the second undoped layer.

[0021] Preferably, the second P-type layer comprises a P-type GaN layer, the second undoped layer comprises an AlInGaN layer, and the second N-type layer comprises an N-type GaN layer.

[0022] Preferably, the second barrier layer comprises an AlInGaN layer.

[0023] Preferably, the V-pits forming layer is formed by utilizing the difference in growth rate of Ga atoms on different surfaces in the InGaN / GaN superlattice structure.

[0024] The present invention also provides a method for fabricating an epitaxial structure, comprising the following:

[0025] Provide a substrate;

[0026] An epitaxial stack is grown on the surface of the substrate, the epitaxial stack comprising at least an N-type semiconductor layer, a V-pits formation layer, a first electric field modulation layer, an active region, and a P-type semiconductor layer grown sequentially.

[0027] The first electric field modulation layer generates a built-in electric field along the growth direction through a heterojunction.

[0028] Preferably, the first electric field modulation layer comprises a first N-type layer, a first undoped layer, and a first P-type layer stacked sequentially.

[0029] Preferably, a first barrier layer is provided on the surface of the first P-type layer facing away from the first undoped layer;

[0030] Furthermore, the thickness of the first barrier layer is not greater than the thickness of the first undoped layer.

[0031] Preferably, a second electric field modulation layer is provided between the active region and the P-type semiconductor layer, and the second electric field modulation layer generates a built-in electric field in the reverse growth direction through the heterojunction.

[0032] Preferably, the second electric field modulation layer comprises a second P-type layer, a second undoped layer, and a second N-type layer stacked sequentially.

[0033] Preferably, a second barrier layer is provided on the surface of the second N-type layer facing away from the second undoped layer;

[0034] Furthermore, the thickness of the second barrier layer is not greater than the thickness of the second undoped layer.

[0035] This invention provides an LED chip, comprising:

[0036] Includes any of the extensional structures described above;

[0037] An N-type electrode is formed in contact with the N-type semiconductor layer;

[0038] The P-type electrode forms a contact with the P-type semiconductor layer.

[0039] As can be seen from the above technical solution, the epitaxial structure provided by the present invention includes: a substrate and an epitaxial stack disposed on the surface of the substrate; the epitaxial stack includes at least an N-type semiconductor layer, a V-pits formation layer, a first electric field modulation layer, an active region, and a P-type semiconductor layer grown sequentially; wherein, the first electric field modulation layer generates a built-in electric field along the growth direction through a heterojunction. Based on this, the epitaxial structure delays electrons from the N-type semiconductor layer through the built-in electric field along the growth direction constructed by the first electric field modulation layer, thereby achieving the effect of electron deceleration. At the same time, the first electric field modulation layer can also regulate the spatial distribution of the V-pits structure in the V-pits formation layer in the active region to reduce leakage channels. In addition, since the direction of the built-in electric field of the first electric field modulation layer is opposite to the direction of hole injection, the built-in electric field of the first electric field modulation layer can cause holes to be stored in the V-pits structure, thereby effectively increasing the recombination probability of carriers in the active region.

[0040] Secondly, the first electric field modulation layer includes a first N-type layer, a first undoped layer, and a first P-type layer stacked sequentially to form the built-in electric field; furthermore, a first barrier layer is provided on the surface of the first P-type layer facing away from the first undoped layer. Through the synergistic effect of the first barrier layer and the built-in electric field of the first electric field modulation layer, holes can be prevented from penetrating into the N-type semiconductor layer through V-pits, further enhancing the hole retention capacity in the V-pits structure; at the same time, the first barrier layer can also prevent the formation of a PN junction in the recombination region due to direct contact between the first electric field modulation layer and the active region.

[0041] Then, by setting "the first barrier layer includes an intrinsic semiconductor layer, and the thickness of the first barrier layer is not greater than the thickness of the first undoped layer"; further, the thickness of the N-type semiconductor layer is D1, the thickness of the P-type semiconductor layer is D2, the thickness of the first barrier layer is D3, and the thickness of the first undoped layer is D4, then (D1+D2) / 3≤D3≤D4≤(D1+D2) / 2. This avoids the impact of an excessively thin first barrier layer on the interface charge, and also avoids the deterioration of the crystal quality of the epitaxial structure due to increased strain between materials caused by an excessively thick first barrier layer.

[0042] Based on the above configuration, a second electric field modulation layer is further provided between the active region and the P-type semiconductor layer in this application. The second electric field modulation layer accelerates the holes from the P-type semiconductor layer by generating a built-in electric field in the reverse growth direction through the heterojunction. In this way, the first electric field modulation layer can work together to increase the radiative recombination probability of charge carriers in the active region.

[0043] Finally, the second electric field modulation layer includes a second P-type layer, a second undoped layer, and a second N-type layer stacked sequentially; furthermore, a second blocking layer is provided on the surface of the second N-type layer facing away from the second undoped layer, so that the electron blocking effect can be achieved while increasing hole injection.

[0044] The present invention also provides a method for preparing an LED epitaxial structure, which achieves the above-mentioned technical effects while being simple to operate and easy to implement.

[0045] The present invention also provides an LED chip formed using the aforementioned LED epitaxial structure, which has a simple structure and greatly improves the luminous efficiency and reliability of the LED chip. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of the epitaxial structure provided in an embodiment of the present invention;

[0048] Figure 2 This is a schematic diagram of the structure of the first electric field modulation layer provided in an embodiment of the present invention;

[0049] Figure 3 This is a schematic diagram of the V-pits structure and its internal electric field provided in an embodiment of the present invention;

[0050] Figure 4 This is a schematic diagram of the structure of the second electric field modulation layer provided in an embodiment of the present invention;

[0051] Figures 5 to 13 This is a schematic diagram of the structure corresponding to the steps of the method for manufacturing the epitaxial structure provided in the embodiment of the present invention.

[0052] Explanation of symbols in the diagram:

[0053] 1. Substrate;

[0054] 2. Buffer layer;

[0055] 3. Unintentionally doped layer;

[0056] 4. N-type semiconductor layer;

[0057] 5. V-pits formation layer; 51. InGaN layer; 52. GaN layer; 53. V-pits structure;

[0058] 6. First electric field modulation layer; 61. First N-type layer; 62. First undoped layer; 63. First P-type layer; 64. First barrier layer;

[0059] 7. Active region; 71. Quantum barrier; 72. Quantum well;

[0060] 8. Second electric field modulation layer; 81. Second N-type layer; 82. Second undoped layer; 83. Second P-type layer; 84. Second barrier layer;

[0061] 9. P-type semiconductor layer;

[0062] 10. Penetrating misalignment lines;

[0063] E1, the electric field direction of the first electric field modulation layer;

[0064] E2, the electric field direction of the second electric field modulation layer;

[0065] h" represents the direction of movement of the hole. Detailed Implementation

[0066] To make the content of this invention clearer, the following description, in conjunction with the accompanying drawings, further illustrates the invention. This invention is not limited to this specific embodiment. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention.

[0067] like Figure 1 As shown, an epitaxial structure includes:

[0068] Substrate 1 and an epitaxial stack disposed on the surface of substrate 1; the epitaxial stack includes at least an N-type semiconductor layer 4, a V-pits formation layer 5, a first electric field modulation layer 6, an active region 7 and a P-type semiconductor layer 9, which are sequentially stacked.

[0069] The first electric field modulation layer 6 generates a built-in electric field along the growth direction through a heterojunction.

[0070] It is worth mentioning that the type of substrate 1 is not limited in this embodiment. For example, substrate 1 includes any one of sapphire, silicon carbide, silicon, gallium nitride, and aluminum nitride.

[0071] Furthermore, based on the above embodiments of the present invention, such as Figure 2 As shown, the first electric field modulation layer 6 includes a first N-type layer 61, a first undoped layer 62, and a first P-type layer 63 stacked sequentially.

[0072] Furthermore, based on the above embodiments of the present invention, a first barrier layer 64 is provided on the surface of the first P-type layer 63 facing away from the first undoped layer 62.

[0073] Furthermore, based on the above embodiments of the present invention, the first barrier layer 64 includes an intrinsic semiconductor layer, and the thickness of the first barrier layer 64 is not greater than the thickness of the first undoped layer 62.

[0074] Furthermore, based on the above embodiments of the present invention, the thickness of the N-type semiconductor layer 4 is D1, the thickness of the P-type semiconductor layer 9 is D2, the thickness of the first barrier layer 64 is D3, and the thickness of the first undoped layer 62 is D4; then (D1+D2) / 3≤D3≤D4≤(D1+D2) / 2.

[0075] Furthermore, based on the above embodiments of the present invention, the N-type semiconductor layer 4 includes an N-type GaN layer, and the P-type semiconductor layer 9 includes a P-type GaN layer; then the first N-type layer 61 includes an N-type GaN layer, the first undoped layer 62 includes an AlInGaN layer, and the first P-type layer 63 includes a P-type GaN layer.

[0076] Furthermore, based on the above embodiments of the present invention, the first barrier layer 64 includes an AlInGaN layer.

[0077] Furthermore, based on the above embodiments of the present invention, a second electric field modulation layer 8 is provided between the active region 7 and the P-type semiconductor layer 9, and the second electric field modulation layer 8 generates a built-in electric field in the reverse growth direction through the heterojunction.

[0078] Furthermore, based on the above embodiments of the present invention, such as Figure 4 As shown, the second electric field modulation layer 8 includes a second P-type layer 83, a second undoped layer 82, and a second N-type layer 81 stacked sequentially.

[0079] Furthermore, based on the above embodiments of the present invention, a second barrier layer 84 is provided on the surface of the second N-type layer 81 facing away from the second undoped layer 82.

[0080] Furthermore, based on the above embodiments of the present invention, the second barrier layer 84 includes an intrinsic semiconductor layer, and the thickness of the second barrier layer 84 is not greater than the thickness of the second undoped layer 82.

[0081] Furthermore, based on the above embodiments of the present invention, the second P-type layer 83 includes a P-type GaN layer, the second undoped layer 82 includes an AlInGaN layer, and the second N-type layer 81 includes an N-type GaN layer.

[0082] Furthermore, based on the above embodiments of the present invention, the second barrier layer 84 includes an AlInGaN layer.

[0083] Furthermore, based on the above embodiments of the present invention, the V-pits forming layer 5 is formed by utilizing the difference in growth rate of Ga atoms on different surfaces in the InGaN / GaN superlattice structure to form V-pits.

[0084] This invention also provides a method for fabricating an epitaxial structure, using MOCVD equipment, with trimethyl / ethylgallium™Ga / TEGa, trimethylaluminum™Al, and ammonia NH3 as the Ga source, Al source, and nitrogen source, respectively, N2 as the carrier gas, and silane SiH4 and magnesium cerene CP2Mg as the N-type and P-type doping sources, respectively, comprising the following:

[0085] S01, such as Figure 5 As shown, a substrate 1 is provided;

[0086] It is worth mentioning that the type of substrate 1 is not limited in this embodiment. For example, substrate 1 includes any one of sapphire, silicon carbide, silicon, gallium nitride, and aluminum nitride.

[0087] S02, such as Figure 6 As shown, a buffer layer 2, an unintentionally doped layer 3, and an N-type semiconductor layer 4 are grown on the surface of the substrate 1;

[0088] Furthermore, based on the above embodiments of the present invention, the N-type semiconductor layer 4 includes a superlattice structure composed of an AlGaN layer and an N-type GaN layer. Thus, while ensuring that the N-type semiconductor layer 4 provides electrons, the superlattice structure can be used to further block dislocations and improve crystal quality. At the same time, the current spreading capability can be further enhanced by using discontinuous doping (i.e., doped / undoped / doped / undoped state).

[0089] Furthermore, based on the above embodiments of the present invention, the N-type semiconductor layer 4 has a through-dislocation line.

[0090] Specifically, in this step, the substrate 1 is placed in the MOCVD reaction chamber and hydrogenated for about 5 minutes with high-purity hydrogen gas at a temperature of about 1100°C. Then, the temperature is lowered to about 950°C to 970°C, and an undoped AlN buffer layer 2 with a thickness of about 10nm to 20nm is grown by introducing Al source and nitrogen source.

[0091] Continue heating to 1000℃-1150℃, turn off the Al source, and introduce the Ga source to grow an undoped GaN layer of 2um to 3um. The purpose is to reduce the lattice mismatch between the substrate 1 and the subsequent film material by growing a high-quality unintentionally doped layer 3.

[0092] Then, the temperature is adjusted to 980-1020 degrees Celsius, and an Al source is introduced to grow an AlGaN layer with a thickness of 10-20 nm. Next, the Al source is turned off, and silane is introduced to grow a 5-10 nm thick GaN layer (i.e., an N-type GaN layer) with Si doping, wherein the Si doping concentration is 5-10 × 10⁻⁶. 18 cm -3 Finally, the above cycle is repeated, with a growth cycle of N, where N is 10 to 20, to form the N-type semiconductor layer 4.

[0093] S03, such as Figure 7 As shown, a V-pits formation layer 5 is grown on the surface of the N-type semiconductor layer 4;

[0094] Furthermore, based on the above embodiments of the present invention, the V-pits forming layer 5 forms a V-pits structure 53 by utilizing the difference in growth rate of Ga atoms on different surfaces within the InGaN / GaN superlattice structure. The V-pits structure 53 is formed at the top of the penetrating dislocation line 10 to constitute a leakage current channel.

[0095] Specifically, in this step, the temperature is lowered to 800-850 degrees Celsius, the Al source and silane are turned off, and the Ga source and nitrogen source are introduced. The formation of InGaN layer 51 and GaN layer 52 is controlled by alternately controlling the introduction and shutdown of the In source (e.g., ...). Figure 8 As shown, an InGaN / GaN superlattice structure with 5-10 cycles is grown, which allows the formation of penetrating dislocation lines, thereby generating the tip initiation points of V-pits. It should be emphasized that in this embodiment, there are no specific restrictions on the slope or height of the V-pits.

[0096] S04, such as Figure 9 As shown, a first electric field modulation layer 6 is grown, wherein the first electric field modulation layer 6 generates a built-in electric field along the growth direction through a heterojunction.

[0097] Furthermore, based on the above embodiments of the present invention, such as Figure 2 As shown, the first electric field modulation layer 6 includes a first N-type layer 61, a first undoped layer 62, and a first P-type layer 63 stacked sequentially.

[0098] Furthermore, based on the above embodiments of the present invention, a first barrier layer 64 is provided on the surface of the first P-type layer 63 facing away from the first undoped layer 62.

[0099] Furthermore, based on the above embodiments of the present invention, the first barrier layer 64 includes an intrinsic semiconductor layer, and the thickness of the first barrier layer 64 is not greater than the thickness of the first undoped layer 62.

[0100] Furthermore, based on the above embodiments of the present invention, the thickness of the N-type semiconductor layer 4 is D1, the thickness of the P-type semiconductor layer 9 is D2, the thickness of the first barrier layer 64 is D3, and the thickness of the first undoped layer 62 is D4; then (D1+D2) / 3≤D3≤D4≤(D1+D2) / 2.

[0101] Furthermore, based on the above embodiments of the present invention, the N-type semiconductor layer 4 includes an N-type GaN layer, and the P-type semiconductor layer 9 includes a P-type GaN layer; then the first N-type layer 61 includes an N-type GaN layer, the first undoped layer 62 includes an AlInGaN layer, and the first P-type layer 63 includes a P-type GaN layer.

[0102] Furthermore, based on the above embodiments of the present invention, the first barrier layer 64 includes an AlInGaN layer.

[0103] Specifically, in this step, SiH4 is introduced, with a doping concentration of 5-10 × 10⁻⁶. 18 cm -3 First, an N-type GaN layer with a thickness of 1-5 nm is grown to obtain the first N-type layer 61. Next, SiH4 is turned off, and Al and In sources are introduced to grow an undoped AlInGaN layer with a thickness of 1-3 nm to obtain the first undoped layer 62. Then, Al and In sources are turned off, and Cp2Mg is introduced to grow a layer with a thickness of 1-5 nm and a doping concentration of 5-10 × 10⁻⁶. 17 cm -3 A P-type GaN layer is formed to obtain the first P-type layer 63.

[0104] Finally, Cp2Mg is turned off, and Al and In sources are introduced to grow an undoped AlInGaN layer with a thickness of 1-2 nm to obtain the first barrier layer 64.

[0105] S05, such as Figure 10 As shown, the active growth region is 7;

[0106] Furthermore, based on the above embodiments of the present invention, such as Figure 11 As shown, the active region 7 includes several alternately stacked quantum barrier 71 layers and quantum well 72 layers.

[0107] Specifically, in this step: the temperature is lowered to 700-800 degrees, the Al source and In source are turned off, and a GaN quantum barrier layer 71 with a thickness of 7nm to 16nm is grown; then the In source is introduced to grow an InGaN quantum well layer 72 with a thickness of 1nm to 5nm; finally, the above cycle is repeated, with a growth cycle of N, where N is 6 to 15, to form the active region 7.

[0108] S06, such as Figure 12As shown, a second electric field modulation layer 8 is grown, and the second electric field modulation layer 8 generates a built-in electric field in the reverse growth direction through the heterojunction.

[0109] Furthermore, based on the above embodiments of the present invention, such as Figure 4 As shown, the second electric field modulation layer 8 includes a second P-type layer 83, a second undoped layer 82, and a second N-type layer 81 stacked sequentially.

[0110] Furthermore, based on the above embodiments of the present invention, a second barrier layer 84 is provided on the surface of the second N-type layer 81 facing away from the second undoped layer 82.

[0111] Furthermore, based on the above embodiments of the present invention, the second barrier layer 84 includes an intrinsic semiconductor layer, and the thickness of the second barrier layer 84 is not greater than the thickness of the second undoped layer 82.

[0112] Furthermore, based on the above embodiments of the present invention, the second P-type layer 83 includes a P-type GaN layer, the second undoped layer 82 includes an AlInGaN layer, and the second N-type layer 81 includes an N-type GaN layer.

[0113] Furthermore, based on the above embodiments of the present invention, the second barrier layer 84 includes an AlInGaN layer.

[0114] Specifically, in this step, Cp2Mg is introduced with a doping concentration of 5-10 × 10⁻⁶. 17 cm -3 A p-type GaN layer with a thickness of 1-5 nm is grown to obtain the second p-type layer 83; then, Cp2Mg is turned off, and Al and In sources are introduced to grow an undoped AlInGaN layer with a thickness of 1-3 nm to obtain the second undoped layer 82; then, Al and In sources are turned off, and SiH4 is introduced to grow a layer with a thickness of 1-5 nm and a doping concentration of 5-10 × 10⁻⁶. 18 cm -3 An N-type GaN layer is formed to obtain the second N-type layer 81.

[0115] Finally, SiH4 is turned off, and Al and In sources are introduced to grow an undoped AlInGaN layer with a thickness of 1-2 nm to obtain the second barrier layer 84.

[0116] S07, such as Figure 13 As shown, a P-type semiconductor layer 9 is fabricated;

[0117] Specifically, based on the steps described above, in this step, the temperature is adjusted to 900-1000℃, and a TMGa source and magnesia-diocene are introduced to grow a p-type GaN layer with a thickness of 10-50 nm and a magnesium doping concentration of 5-10 × 10⁻⁶. 18 cm-3 And under N2 atmosphere, anneal at 850-900℃ for 20-30 minutes to finally form a P-type semiconductor layer 9.

[0118] This invention also provides an LED chip, comprising:

[0119] Includes any of the extensional structures described above;

[0120] An N-type electrode is formed in contact with the N-type semiconductor layer 4;

[0121] The P-type electrode is in contact with the P-type semiconductor layer 9.

[0122] As can be seen from the above technical solution, the epitaxial structure provided in this embodiment of the invention includes: a substrate 1 and an epitaxial stack disposed on the surface of the substrate 1; the epitaxial stack includes at least an N-type semiconductor layer 4, a V-pits forming layer 5, a first electric field modulation layer 6, an active region 7, and a P-type semiconductor layer 9, which are sequentially stacked and grown; wherein, the first electric field modulation layer 6 generates a built-in electric field along the growth direction through a heterojunction. Based on this, the epitaxial structure delays electrons from the N-type semiconductor layer 4 through the built-in electric field along the growth direction constructed by the first electric field modulation layer 6, thereby achieving the effect of electron deceleration. At the same time, the first electric field modulation layer 6 can also regulate the spatial distribution of the V-pits structure in the V-pits forming layer 5 in the active region 7 to reduce leakage channels. In addition, as Figure 3 As shown, since the built-in electric field direction E1 of the first electric field modulation layer 6 is opposite to the hole injection direction h", the holes can be stored in the structure of V-pits structure 53 by the action of the built-in electric field of the first electric field modulation layer 6, thereby effectively increasing the recombination probability of carriers in the active region 7.

[0123] Secondly, the first electric field modulation layer 6 includes a first N-type layer 61, a first undoped layer 62, and a first P-type layer 63 stacked sequentially to form the built-in electric field; further, a first barrier layer 64 is provided on the surface of the first P-type layer 63 facing away from the first undoped layer 62. Through the synergistic effect of the first barrier layer 64 and the built-in electric field of the first electric field modulation layer 6, holes can be prevented from penetrating into the N-type semiconductor layer 4 through V-pits 53, further enhancing the hole retention capacity in the V-pits structure 53; at the same time, the first barrier layer 64 can also prevent the formation of a PN junction in the recombination region caused by direct contact between the first electric field modulation layer 6 and the active region 7.

[0124] Then, by setting "the first barrier layer 64 includes an intrinsic semiconductor layer, and the thickness of the first barrier layer 64 is not greater than the thickness of the first undoped layer 62"; further, the thickness of the N-type semiconductor layer 4 is D1, the thickness of the P-type semiconductor layer 9 is D2, the thickness of the first barrier layer 64 is D3, and the thickness of the first undoped layer 62 is D4, then (D1+D2) / 3≤D3≤D4≤(D1+D2) / 2. This avoids the impact of an excessively thin first barrier layer 64 on the interface charge, and also avoids the deterioration of the crystal quality of the epitaxial structure due to increased strain between materials caused by an excessively thick first barrier layer 64.

[0125] Based on the above configuration, a second electric field modulation layer 8 is further provided between the active region 7 and the P-type semiconductor layer 9 in this application. The second electric field modulation layer 8 accelerates the holes from the P-type semiconductor layer 9 by generating a built-in electric field E2 in the reverse growth direction through the heterojunction. In this way, it can work in conjunction with the first electric field modulation layer 6 to increase the radiative recombination probability of charge carriers in the active region 7.

[0126] Finally, the second electric field modulation layer 8 includes a second P-type layer 83, a second undoped layer 82 and a second N-type layer 81 stacked in sequence; furthermore, a second blocking layer 84 is provided on the surface of the second N-type layer 81 facing away from the second undoped layer 82, so that while achieving the electron blocking effect, hole injection can be increased.

[0127] The present invention also provides a method for preparing an LED epitaxial structure, which achieves the above-mentioned technical effects while being simple to operate and easy to implement.

[0128] The present invention also provides an LED chip formed using the aforementioned LED epitaxial structure, which has a simple structure and greatly improves the luminous efficiency and reliability of the LED chip.

[0129] The apparatus provided in this embodiment of the invention operates on the same principle and produces the same technical effects as the aforementioned method embodiments. For the sake of brevity, any parts not mentioned in the apparatus embodiments can be referred to the corresponding content in the aforementioned method embodiments. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, apparatuses, and units described above can all be referred to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0130] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0131] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0132] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An epitaxial structure, characterized in that, include: A substrate and an epitaxial stack disposed on the surface of the substrate; the epitaxial stack includes at least an N-type semiconductor layer, a V-pits formation layer, a first electric field modulation layer, an active region, and a P-type semiconductor layer that are sequentially stacked. The first electric field modulation layer generates a built-in electric field along the growth direction through a heterojunction. The first electric field modulation layer includes a first N-type layer, a first undoped layer, and a first P-type layer stacked sequentially; the first N-type layer includes an N-type GaN layer, the first undoped layer includes an AlInGaN layer, and the first P-type layer includes a P-type GaN layer.

2. The epitaxial structure according to claim 1, characterized in that, A first barrier layer is provided on the surface of the first P-type layer that is opposite to the first undoped layer.

3. The epitaxial structure according to claim 2, characterized in that, The first barrier layer includes an intrinsic semiconductor layer, and the thickness of the first barrier layer is not greater than the thickness of the first undoped layer.

4. The epitaxial structure according to claim 3, characterized in that, The thickness of the N-type semiconductor layer is D1, the thickness of the P-type semiconductor layer is D2, the thickness of the first barrier layer is D3, and the thickness of the first undoped layer is D4; then (D1 + D2) / 3 ≤ D3 ≤ D4 ≤ (D1 + D2) / 2.

5. The epitaxial structure according to claim 1, characterized in that, The N-type semiconductor layer includes an N-type GaN layer, and the P-type semiconductor layer includes a P-type GaN layer.

6. The epitaxial structure according to claim 2, characterized in that, The first barrier layer includes an AlInGaN layer.

7. The epitaxial structure according to claim 1, characterized in that, A second electric field modulation layer is provided between the active region and the P-type semiconductor layer. The second electric field modulation layer generates a built-in electric field in the reverse growth direction through the heterojunction.

8. The epitaxial structure according to claim 7, characterized in that, The second electric field modulation layer includes a second P-type layer, a second undoped layer, and a second N-type layer stacked sequentially.

9. The epitaxial structure according to claim 8, characterized in that, A second barrier layer is provided on the surface of the second N-type layer that is opposite to the second undoped layer.

10. The epitaxial structure according to claim 9, characterized in that, The second barrier layer includes an intrinsic semiconductor layer, and the thickness of the second barrier layer is not greater than the thickness of the second undoped layer.

11. The epitaxial structure according to claim 8, characterized in that, The second P-type layer includes a P-type GaN layer, the second undoped layer includes an AlInGaN layer, and the second N-type layer includes an N-type GaN layer.

12. The epitaxial structure according to claim 9, characterized in that, The second barrier layer includes an AlInGaN layer.

13. The epitaxial structure according to claim 1, characterized in that, The V-pits forming layer is formed by utilizing the difference in growth rate of Ga atoms on different surfaces within the InGaN / GaN superlattice structure.

14. A method for fabricating an epitaxial structure, characterized in that, Including the following: Provide a substrate; An epitaxial stack is grown on the surface of the substrate, the epitaxial stack comprising at least an N-type semiconductor layer, a V-pits formation layer, a first electric field modulation layer, an active region, and a P-type semiconductor layer grown sequentially. The first electric field modulation layer generates a built-in electric field along the growth direction through a heterojunction. The first electric field modulation layer includes a first N-type layer, a first undoped layer, and a first P-type layer stacked sequentially; wherein the first N-type layer includes an N-type GaN layer, the first undoped layer includes an AlInGaN layer, and the first P-type layer includes a P-type GaN layer.

15. The method for fabricating an epitaxial structure according to claim 14, characterized in that, A first barrier layer is provided on the surface of the first P-type layer that is away from the first undoped layer; Furthermore, the thickness of the first barrier layer is not greater than the thickness of the first undoped layer.

16. The method for fabricating an epitaxial structure according to claim 14, characterized in that, A second electric field modulation layer is provided between the active region and the P-type semiconductor layer. The second electric field modulation layer generates a built-in electric field in the reverse growth direction through the heterojunction.

17. The method for fabricating an epitaxial structure according to claim 16, characterized in that, The second electric field modulation layer includes a second P-type layer, a second undoped layer, and a second N-type layer stacked sequentially.

18. The method for fabricating an epitaxial structure according to claim 17, characterized in that, A second barrier layer is provided on the surface of the second N-type layer that is opposite to the second undoped layer; Furthermore, the thickness of the second barrier layer is not greater than the thickness of the second undoped layer.

19. An LED chip, characterized in that, include; The epitaxial structure according to any one of claims 1-13; An N-type electrode is formed in contact with the N-type semiconductor layer; The P-type electrode forms a contact with the P-type semiconductor layer.

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