Display panel and display device

Abstract

This application provides a display panel and a display device. The display panel includes a display area and a non-display area located on one side of the display area; the display area includes multiple pixel circuits and multiple data lines, the data lines being used to provide data signals to the pixel circuits; the pixel circuits include storage capacitors and multiple transistors; the non-display area includes a first fan-out area, the first fan-out area including multiple first fan-out signal lines, the first fan-out signal lines being electrically connected to the data lines; the display panel further includes: a substrate; a first metal layer located on one side of the substrate, the gate of at least one transistor being located on the first metal layer; a second metal layer located on the side of the first metal layer away from the substrate, one electrode of the storage capacitor being located on the second metal layer; a third metal layer located on the side of the second metal layer away from the substrate, at least a portion of the first fan-out signal lines being located on the third metal layer; wherein the resistivity of both the first metal layer and the second metal layer is greater than the resistivity of the third metal layer.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] With the continuous development of display technology, display panels have been widely used in people's production and daily life. However, existing display panels suffer from a high data line load, which affects display quality. Summary of the Invention

[0003] The main objective of this application is to provide a display panel and a display device to at least solve the problem of high data line load in the prior art.

[0004] To achieve the above objectives, according to one aspect of this application, a display panel is provided, including a display area and a non-display area located on one side of the display area; the display area includes a plurality of pixel circuits and a plurality of data lines, the data lines being used to provide data signals to the pixel circuits; the pixel circuits include storage capacitors and a plurality of transistors; the non-display area includes a first fan-out area, the first fan-out area including a plurality of first fan-out signal lines, the first fan-out signal lines being electrically connected to the data lines; the display panel further includes: a substrate; a first metal layer located on one side of the substrate, at least one gate of the transistor being located on the first metal layer; a second metal layer located on the side of the first metal layer away from the substrate, one plate of the storage capacitor being located on the second metal layer; a third metal layer located on the side of the second metal layer away from the substrate, at least a portion of the first fan-out signal lines being located on the third metal layer; wherein the resistivity of both the first metal layer and the second metal layer is greater than the resistivity of the third metal layer.

[0005] According to another aspect of this application, based on the same inventive concept, a display device is also provided, comprising: any of the aforementioned display panels.

[0006] By applying the technical solution of this application, among the first metal layer, the second metal layer and the third metal layer arranged sequentially in the direction away from the substrate, the resistivity of the third metal layer is the smallest. At least a portion of the first fan-out signal line electrically connected to the data line is arranged in the third metal layer with low resistivity, which ensures that the resistance of the first fan-out signal line is small, so that the load of the first fan-out signal line is small, thus alleviating the problem that the display effect of the display panel is poor due to the large load of the data line. Attached Figure Description

[0007] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0008] Figure 1 A top view schematic diagram of a display panel provided in an embodiment according to this application is shown;

[0009] Figure 2 It shows along Figure 1 A schematic diagram of the cross-section obtained by the dashed line AA' in the diagram;

[0010] Figure 3 A schematic diagram of a pixel circuit provided in an embodiment of this application is shown;

[0011] Figure 4 A top view schematic diagram of a display panel provided according to an embodiment of this application is shown;

[0012] Figure 5 A top view schematic diagram of another display panel provided in an embodiment according to this application is shown;

[0013] Figure 6 A schematic diagram of the structure of a display device provided according to an embodiment of this application is shown.

[0014] The above figures include the following reference numerals:

[0015] 10. Display area; 11. Non-display area; 12. Data line; 13. Storage capacitor; 131. First electrode plate; 132. Second electrode plate; 14. Transistor; 141. Gate; 142. Active layer; 143. Drain; 144. Source; 15. First fan-out area; 16. First fan-out signal line; 17. Substrate; 18. Pixel circuit; 19. Light-emitting unit; 21. First signal trace; 22. Shorting bar circuit; 23. First control transistor; 24. Test signal line; 25. Second signal trace; 26. Driver chip; 27. Second fan-out area; 28. Bend area; 29. ​​Second fan-out signal line; 30. Power signal bus; 301. First part; 302. Second part; 31. Demultiplexing circuit; 32. Data connection line; 34. Multiplexer; 35. Second control transistor; 100. Display panel; 200. Display device. Detailed Implementation

[0016] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0017] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0018] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0019] As described in the background section, in the prior art, the data lines of display panels have a large load. To solve this technical problem, embodiments of this application provide a display panel and a display device.

[0020] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0021] This embodiment provides a display panel. Figure 1 This is a top view schematic diagram of a display panel according to an embodiment of this application. Figure 2 It is along Figure 1 A cross-sectional diagram obtained by the dashed line AA' in the diagram. (See diagram below.) Figure 1 and Figure 2 As shown, the display panel 100 includes a display area 10 and a non-display area 11 located on one side of the display area 10; the display area 10 includes a plurality of pixel circuits 18 and a plurality of data lines 12, the data lines 12 being used to provide data signals to the pixel circuits 18; the pixel circuits 18 include storage capacitors 13 and a plurality of transistors 14; the non-display area 11 includes a first fan-out area 15, the first fan-out area 15 including a plurality of first fan-out signal lines 16, the first fan-out signal lines 16 being electrically connected to the data lines 12;

[0022] The aforementioned display panel 100 also includes:

[0023] Substrate 17;

[0024] Specifically, the substrate 17 is located in the display area 10 and the non-display area 11.

[0025] A first metal layer is located on one side of the substrate 17, and the gate 141 of at least one of the transistors 14 is located on the first metal layer.

[0026] Specifically, other film layers exist between the substrate 17 and the first metal layer. The gate 141 of the transistor 14 can be a top-gate structure or a bottom-gate structure. Those skilled in the art can place the gates of some of the transistors 14 in the first metal layer, or they can place the gates 141 of all the transistors 14 in the first metal layer.

[0027] The second metal layer is located on the side of the first metal layer away from the substrate 17, and one electrode (first electrode 131) of the storage capacitor 13 is located in the second metal layer.

[0028] Specifically, there are other film layers between the first metal layer and the second metal layer.

[0029] The third metal layer is located on the side of the second metal layer away from the substrate 17, and at least a portion of the first fan-out signal line 16 is located in the third metal layer.

[0030] Specifically, other film layers exist between the second metal layer and the third metal layer. Those skilled in the art may place only a portion of the multiple first fan-out signal lines 16 on the third metal layer, or they may place all of the first fan-out signal lines 16 on the third metal layer. The first metal layer, the second metal layer, and the third metal layer are located in the display area 10 and the non-display area 11, respectively.

[0031] The resistivity of the first metal layer and the second metal layer is greater than that of the third metal layer.

[0032] In the above embodiments, among the first metal layer, the second metal layer and the third metal layer arranged sequentially in the direction away from the substrate, the third metal layer has the lowest resistivity. At least a portion of the first fan-out signal line, which is electrically connected to the data line, is arranged in the third metal layer with low resistivity, which ensures that the resistance of the first fan-out signal line is small, so that the load of the first fan-out signal line is small, thus alleviating the problem that the display panel has poor display effect due to the large load of the data line.

[0033] like Figure 2As shown, the transistor 14 further includes an active layer 142, a drain 143, and a source 144. The other plate (second plate 132) of the storage capacitor 13 may be located in the first metal layer. The pixel circuit 18 further includes a light-emitting unit 19.

[0034] Figure 3 A schematic diagram of a pixel circuit of a 7T1C according to an embodiment of this application is shown as an example. Figure 3 As shown, the pixel circuit includes seven transistors T1 to T7 and one storage capacitor 13. Transistor T2 is the driving transistor of the pixel circuit. The initialization signal terminal VREF provides the initialization signal, and the driving terminals Emit, S1, and S2 all provide driving signals. The pixel circuit operates as follows: During the initialization phase, transistor T5 is turned on, and transistor T7 is turned off. The voltage at the initialization signal terminal VREF is transmitted to the first node N1 by transistor T5, initializing the driving transistor T2. During the data writing phase, transistors T5 and T7 are both turned off, while transistors T3 and T6 are turned on. The data signal terminal DATA receives the data signal transmitted from the data line to the second node N2. The signal from the second node N2 is transmitted to the third node N3 through the driving transistor T2, and the signal from the third node N3 is transmitted to the first node N1 through transistor T3, raising the potential of the first node N1. During the light-emitting phase, transistors T3 and T6 are turned off, while transistors T1 and T4 are turned on. The driving current generated by the driving transistor T2 is transmitted to the light-emitting unit 19, causing the light-emitting unit 19 to emit light. It should be noted that... Figure 3 This application only illustrates one 7T1C mode circuit structure for the pixel circuit, but it is not limited to this. The specific circuit structure of the pixel circuit can be adapted to meet specific needs. Furthermore, the pixel circuit can also be embodied in 8T1C, 9T2C, etc., and this application does not limit it.

[0035] In one alternative, such as Figure 1 As shown, the display panel 100 further includes a first signal trace 21 and a shorting rod circuit 22. The shorting rod circuit 22 is located on the side of the first fan-out area 15 away from the display area 10. The first signal trace 21 and the shorting rod circuit 22 are electrically connected. The first signal trace 21 is electrically connected to the first fan-out signal line 16, and the first signal trace 21 and the first fan-out signal line 16 are disposed on different layers, that is, the first signal trace 21 is not located on the third metal layer. In this embodiment, disposing of the electrically connected first fan-out signal line and the first signal trace on different layers can release the static electricity accumulated on the signal line, avoid the influence of static electricity on the signal line, and ensure the stability of signal transmission.

[0036] Specifically, the first signal trace 21 and the first fan-out signal line 16 are connected across different layers via vias. There can be multiple first signal traces 21, and each of the multiple first signal traces 21 is electrically connected to the first fan-out signal line 16 in a one-to-one correspondence.

[0037] For example, such as Figure 4 As shown, the aforementioned short-circuit bar circuit 22 includes multiple first control transistors 23. Under the control of the enable signal EN, the first control transistors 23 electrically connect the first signal trace 21 and the test signal line 24. The short-circuit bar circuit allows the first signal trace to be connected to the test signal line to test some functions of the display panel, thereby quickly and accurately locating problems.

[0038] like Figure 4 As shown, there are multiple test signal lines 24. The control terminal of the first control transistor 23 receives the enable signal EN. The input terminal IN of the first control transistor 23 is electrically connected to each of the test signal lines 24. The output terminals OUT of multiple first control transistors 23 are electrically connected to the first signal trace 21. During the display test, the first control transistor 23 is turned on by the enable signal, and a display test signal is applied to the test signal lines 24. This allows the display test signal to be transmitted to the data lines of the display area via the first control transistor 23 and the first signal trace 21, thereby enabling the display panel to display images such as red, green, blue, gray, or black, achieving display testing of each sub-pixel. After the display test is completed, the short-circuit bar circuit can be cut along the cutting line to remove it, achieving a narrow bezel design for the display panel, or the short-circuit bar circuit can be retained.

[0039] In some embodiments, such as Figure 1 As shown, the display panel also includes multiple second signal traces 25, which are located in the third metal layer and electrically connected to the driver chip 26. One end of the first signal trace 21 is electrically connected to the first fan-out signal line 16, and the other end is electrically connected to the second signal traces 25. In this embodiment, the second signal traces connecting the driver chip and the first signal traces are placed in the third metal layer. Since the resistivity of the third metal layer is low, the load on the second signal traces is kept low, thereby further ensuring a better display effect of the display panel.

[0040] like Figure 2As shown, the display panel further includes a fourth metal layer, which is located between the third metal layer and the second metal layer, or on the side of the third metal layer away from the substrate 17; at least a portion of the first signal trace 21 is located on the fourth metal layer; wherein the resistivity of both the first and second metal layers is greater than the resistivity of the fourth metal layer. In this embodiment, the first signal trace is placed on the fourth metal layer with lower resistivity, ensuring that the resistance of the first signal trace is low, resulting in a lower load on the first signal trace. This further alleviates the problem of poor display effect caused by high data line load, and further ensures a better display effect of the display panel.

[0041] It should be noted that, Figure 2 The embodiment shown is merely illustrative, with the fourth metal layer located on the side of the third metal layer away from the substrate 17, and does not constitute a limitation of this application. The fourth metal layer may also be located between the third metal layer and the second metal layer.

[0042] Specifically, the resistivity of the fourth metal layer can be the same as that of the third metal layer. Alternatively, the resistivity of the fourth metal layer can be different from that of the third metal layer.

[0043] In this application, the aforementioned display panel further includes: multiple third signal traces, one end of each third signal trace being electrically connected to the first signal trace, and the other end of each third signal trace being electrically connected to the second signal trace. Some of the third signal traces are located in the first metal layer, and some are located in the second metal layer. In this embodiment, by placing the third signal traces in the first and second metal layers and connecting them in parallel across the two ends of the first signal trace with lower resistivity, the resistance of the parallel signal lines can be further reduced, thereby further reducing the signal load.

[0044] Furthermore, the plurality of the aforementioned third signal traces are alternately distributed in the aforementioned first metal layer and the aforementioned second metal layer. In other words, along the arrangement direction of the plurality of the aforementioned third signal traces, the plurality of the aforementioned third signal traces are alternately located in the first metal layer and the second metal layer.

[0045] In another alternative, such as Figure 1As shown, the display panel further includes a second fan-out area 27 and a bending area 28. The second fan-out area 27 is located between the bending area 28 and the display area 10, and the first fan-out area 15 is located on the side of the bending area 28 away from the display area 10. The second fan-out area 27 includes multiple second fan-out signal lines 29, which are electrically connected to the data line 12 and the first fan-out signal line 16, respectively. Among the multiple second fan-out signal lines 29, some of the second fan-out signal lines 29 are located in the first metal layer, and some of the second fan-out signal lines 29 are located in the second metal layer. In this embodiment, the second fan-out signal line in the second fan-out area between the bending area and the display area is set in the first metal layer and the second metal layer. By laying out the second fan-out signal line in layers, the required number of second fan-out signal lines can be laid out in a limited space, so that the spacing between adjacent second fan-out signal lines meets the signal line spacing requirements. This not only effectively reduces signal interference between adjacent second fan-out signal lines and improves the stability and reliability of signal transmission, but also facilitates the narrow bezel design of the display panel.

[0046] Furthermore, the plurality of the aforementioned second fan-out signal lines are alternately distributed in the aforementioned first metal layer and the aforementioned second metal layer. In other words, along the arrangement direction of the plurality of the aforementioned second fan-out signal lines, the plurality of the aforementioned second fan-out signal lines are alternately located in the first metal layer and the second metal layer.

[0047] And, as Figure 1 As shown, the second fan-out signal line 29 is also located in the aforementioned bend area 28.

[0048] Specifically, such as Figure 1 As shown, the display panel also includes a power signal bus 30 located in the non-display area 10. The power signal bus 30 includes a first portion 301 located in the second fan-out area 27. The first portion 301 extends along a first direction, which intersects the extension direction of the data line 12. In the thickness direction of the display panel, the first portion 301 overlaps with the second fan-out signal line 29, meaning that the orthographic projections of the first portion 301 and the second fan-out signal line 29 on the substrate overlap. The first portion 301 is located in the third metal layer. By placing the first portion of the power signal bus extending along the first direction in the third metal layer with lower resistivity, the load on the power signal bus is kept relatively low.

[0049] In one alternative, the first direction is perpendicular to the extension direction of the data line 12.

[0050] For example, such as Figure 1 and Figure 2As shown, the power signal bus 30 further includes a second portion 302 located in the first fan-out area 15; the display panel further includes a fourth metal layer, which is located between the third metal layer and the second metal layer, or the fourth metal layer is located on the side of the third metal layer away from the substrate 17; the second portion 302 is located in the fourth metal layer; the resistivity of both the first and second metal layers is greater than the resistivity of the fourth metal layer; wherein, in the thickness direction of the display panel, the second portion 302 and the first fan-out signal line 16 at least partially overlap, that is, the orthogonal projections of the second portion 302 and the first fan-out signal line 16 on the substrate overlap. In this embodiment, by placing the second portion of the power signal bus in the fourth metal layer with lower resistivity, the resistance of the power signal bus is ensured to be lower, resulting in a lower load on the power signal bus.

[0051] In practical applications, the first part 301 and the second part 302 mentioned above are electrically connected together. Figure 2 The relative positional relationship between the first part 301 and the second part 302 described above is shown only by way of example, and their electrical connection relationship is not shown.

[0052] like Figure 1 As shown, the second part 302 extends along the first direction.

[0053] Specifically, the resistivity of the fourth metal layer can be the same as that of the third metal layer. Alternatively, the resistivity of the fourth metal layer can be different from that of the third metal layer.

[0054] The power signal bus 30 includes at least one of a positive power signal bus PVDD and a negative power signal bus PVEE.

[0055] In this application, such as Figure 1 As shown, the display panel also includes a demultiplexer (demux) circuit 31, which is electrically connected to the data line 12 and the second fan-out signal line 29. That is, the data line 12 and the second fan-out signal line 29 are electrically connected through the demultiplexer circuit 31. Through this demultiplexer circuit, an input signal can be distributed to one of multiple output ports, achieving signal selection and distribution, thereby effectively reducing the number of second fan-out signal lines.

[0056] Demultiplexing circuits are widely used in display panels due to their low cost. However, as display resolution increases, the pulse width reserved by the demultiplexing circuit gradually decreases, which causes the charging process of the demultiplexing circuit to affect the uniformity of the screen. Furthermore, the demand for narrow bezels in display panels increases the load on the data lines, further deteriorating the uniformity of the screen during the charging process of the demultiplexing circuit.

[0057] By adopting the above-mentioned technical solution of this application, at least a portion of the first fan-out signal line electrically connected to the data line is disposed in a third metal layer with low resistivity, which ensures that the resistance of the first fan-out signal line is small, thereby ensuring that the signal load of the first fan-out signal line is small. This alleviates the problem of uneven display on the display panel during the charging process of the demultiplexing circuit caused by the large load of the data line, reduces the charging risk of the demultiplexing circuit caused by the large load, and effectively solves the above-mentioned problems.

[0058] like Figure 4 As shown, the demultiplexing circuit 31 includes multiple 1:n multiplexers 34, that is, each multiplexer 34 includes n second control transistors 35. The input terminals IN of the n second control transistors 35 are electrically connected together as the input terminals of the multiplexer 34. The control terminals G of the n second control transistors 35 serve as the control terminals of the multiplexer 34. The output terminals OUT of the n second control transistors 35 serve as the output terminals of the multiplexer 34. The input terminals of the multiplexer 34 are electrically connected to the second fan-out signal line 29. The control terminals of the n second control transistors 35 are electrically connected to n clock control signal lines one by one. The output terminals of the n second control transistors 35 are electrically connected to the data lines 12 one by one. The second control transistors 35 are turned on by controlling the clock control signal lines, thereby writing the data voltage onto the data lines 12.

[0059] It should be noted that, Figure 4 The example shown is only exemplarily illustrated with n=2, i.e., a 1:2 multiplexer. Those skilled in the art can also select multiplexers with other n values ​​to construct the above demultiplexing circuit, for example, a 1:4 multiplexer.

[0060] In practical applications, the materials for the first and second metal layers include molybdenum; the materials for the third metal layer include titanium and aluminum. Since the resistivity of titanium and aluminum is lower than that of molybdenum, a third metal layer with lower resistivity can be obtained. Molybdenum has a high melting point, is not easily deformed, and has strong corrosion resistance, resulting in better performance and reliability for the first and second metal layers.

[0061] Furthermore, the materials for the aforementioned fourth metal layer include titanium and aluminum. This results in a fourth metal layer with low resistivity.

[0062] In practical applications, the materials of the fourth metal layer and the third metal layer can be the same or different.

[0063] In some other embodiments, such as Figure 5 As shown, the display panel also includes a data connection cable 32, at least partially located in the display area 10. The data connection cable 32 is electrically connected to the data line 12 and to the first fan-out signal line 16. This embodiment introduces a FIAA (Fanout inactive area) design in the display panel, transferring at least a portion of the data connection cable from the original non-display area to the display area. This saves layout space in the non-display area, reduces bezel width, increases screen-to-body ratio, and facilitates narrow bezel design of the display panel.

[0064] Specifically, the aforementioned data connection line includes a first connection segment extending along a first direction and a second connection segment extending along a second direction. The first end of the first connection segment is electrically connected to the data line in the aforementioned display area, the second end of the first connection segment is electrically connected to the first end of the second connection segment, and the second end of the second connection segment is electrically connected to the aforementioned first fan-out signal line. The second direction is parallel to the extension direction of the aforementioned data line, and the first direction intersects with the aforementioned second direction.

[0065] Furthermore, the aforementioned second connecting line segment at least partially overlaps with the aforementioned data line in the aforementioned display area.

[0066] In this application, the first metal layer is also referred to as the gate metal layer, the second metal layer is also referred to as the electrode layer, and the third and fourth metal layers are also referred to as the data line layers.

[0067] This application also provides a display device. Figure 6 An exemplary structural schematic diagram of a display device 200 according to this application is shown, such as... Figure 6 As shown, the above-mentioned display device 200 includes any of the above-mentioned display panels 100.

[0068] In the above embodiments, the display device includes any of the above-described display panels. The display panel has a first metal layer, a second metal layer, and a third metal layer sequentially disposed along the direction away from the substrate. Among the three, the third metal layer has the lowest resistivity. At least a portion of the first fan-out signal line, which is electrically connected to the data line, is disposed in the third metal layer with low resistivity. This ensures that the resistance of the first fan-out signal line is low, resulting in a low load on the first fan-out signal line. This, in turn, ensures that the signal load transmitted to the data line is low, alleviating the problem of poor display effect of the display panel caused by a large load on the data line, and ensuring a better display effect of the display device.

[0069] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0070] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0071] 1) In the display panel of this application, among the first metal layer, the second metal layer and the third metal layer arranged sequentially in the direction away from the substrate, the resistivity of the third metal layer is the smallest. At least a portion of the first fan-out signal line electrically connected to the data line is arranged in the third metal layer with low resistivity, which ensures that the resistance of the first fan-out signal line is small, so that the load of the first fan-out signal line is small, thus alleviating the problem that the display effect of the display panel is poor due to the large load of the data line.

[0072] 2) The display device of this application includes any of the above-mentioned display panels. The display panel has a first metal layer, a second metal layer and a third metal layer disposed sequentially along the direction away from the substrate. Among the three, the third metal layer has the lowest resistivity. At least a portion of the first fan-out signal line electrically connected to the data line is disposed in the third metal layer with low resistivity, which ensures that the resistance of the first fan-out signal line is small, so that the load of the first fan-out signal line is small. This alleviates the problem that the display panel has poor display effect due to the large load of the data line, and ensures that the display device has a better display effect.

[0073] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, It includes a display area and a non-display area located on one side of the display area; the display area includes multiple pixel circuits and multiple data lines, the data lines being used to provide data signals to the pixel circuits; the pixel circuits include storage capacitors and multiple transistors; the non-display area includes a first fan-out area, the first fan-out area including multiple first fan-out signal lines, the first fan-out signal lines being electrically connected to the data lines; The display panel also includes: Substrate; A first metal layer is located on one side of the substrate, and the gate of at least one transistor is located on the first metal layer; A second metal layer is located on the side of the first metal layer away from the substrate, and one electrode of the storage capacitor is located on the second metal layer; A third metal layer is located on the side of the second metal layer away from the substrate, and at least a portion of the first fan-out signal line is located in the third metal layer; The resistivity of both the first and second metal layers is greater than that of the third metal layer. The display panel further includes a second fan-out area and a bending area. The second fan-out area is located between the bending area and the display area, and the first fan-out area is located on the side of the bending area away from the display area. The second fan-out area includes multiple second fan-out signal lines, which are electrically connected to the data line and the first fan-out signal line, respectively. Among the multiple second fan-out signal lines, some are located in the first metal layer, and some are located in the second metal layer. The display panel further includes a power signal bus located in the non-display area. The power signal bus includes a first portion located in the second fan-out area, extending along a first direction that intersects the extension direction of the data line. In the thickness direction of the display panel, the first portion overlaps with the second fan-out signal line, and the first portion is located in the third metal layer. The power signal bus further includes a second portion located in the first fan-out area; the display panel further includes a fourth metal layer, which is located between the third metal layer and the second metal layer, or the fourth metal layer is located on the side of the third metal layer away from the substrate; the second portion is located in the fourth metal layer; the resistivity of the first metal layer and the second metal layer is greater than the resistivity of the fourth metal layer; wherein, in the thickness direction of the display panel, the second portion and the first fan-out signal line at least partially overlap.

2. The display panel according to claim 1, characterized in that, The display panel further includes a first signal trace and a shorting bar circuit. The shorting bar circuit is located on the side of the first fan-out area away from the display area. The first signal trace and the shorting bar circuit are electrically connected. The first signal trace is electrically connected to the first fan-out signal line, and the first signal trace and the first fan-out signal line are disposed on different layers.

3. The display panel according to claim 2, characterized in that, The short-circuit bar circuit includes a plurality of first control transistors, which, under the control of an enable signal, electrically connect the first signal trace and the test signal trace.

4. The display panel according to claim 2, characterized in that, The display panel also includes multiple second signal traces, which are located on the third metal layer and electrically connected to the driver chip; one end of the first signal trace is electrically connected to the first fan-out signal line, and the other end of the first signal trace is electrically connected to the second signal trace.

5. The display panel according to claim 2, characterized in that, The display panel further includes a fourth metal layer, which is located between the third metal layer and the second metal layer, or the fourth metal layer is located on the side of the third metal layer away from the substrate; at least a portion of the first signal trace is located on the fourth metal layer; wherein the resistivity of both the first metal layer and the second metal layer is greater than the resistivity of the fourth metal layer.

6. The display panel according to claim 1, characterized in that, The power signal bus includes at least one of a positive power signal bus and a negative power signal bus.

7. The display panel according to claim 1, characterized in that, The display panel also includes a demultiplexing circuit, which is electrically connected to the data line and the second fan-out signal line respectively.

8. The display panel according to claim 1, characterized in that, The first and second metal layers are made of molybdenum; the third metal layer is made of titanium and aluminum.

9. The display panel according to claim 1, characterized in that, The display panel also includes a data connection cable, which is at least partially located in the display area. The data connection cable is electrically connected to the data line and to the first fan-out signal line.

10. A display device, characterized in that, include: The display panel according to any one of claims 1 to 9.

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