An input dc adaptive calibration circuit

Abstract

The application relates to the technical field of input direct current amplifiers, and discloses an input direct current adaptive calibration circuit. In the application, a first input signal controls a first controlled current source, a second controlled current source and a third controlled current source; the negative end of the first controlled current source is connected with one end of a first switch; the other end of the first switch is connected with one end of a second switch and one end of a buffer capacitor; the other end of the second switch is connected with the positive end of the second controlled current source; the negative end of the third controlled current source is connected with one end of a variable resistance network, the negative input end of a first comparator and the negative input end of a second comparator; the positive input end of the first comparator is connected with the highest threshold value of the first input signal; and the positive input end of the second comparator is connected with the lowest threshold value of the first input signal. The application solves the problem of output saturation caused by the input direct current of an amplifier. The application achieves the technical effects of flexibility, a large direct current input range and a fast stabilization speed.

Description

Technical Field

[0001] This invention relates to the field of input DC amplifier technology, and more particularly to an input DC adaptive calibration circuit. Background Technology

[0002] There are three main types of existing DC adaptive calibration circuits: The first type manually acquires the DC component of the input signal before the amplifier is working normally, and then uses the acquired data as a fixed bias to cancel it out after the amplifier is working normally. This method is time-consuming and labor-intensive, and it is a one-time calibration that cannot adjust the feedback voltage in real time.

[0003] The second method uses an ADC (analog-to-digital converter) to sample and quantize the amplified signal in real time, and then, after digital signal processing, controls the DAC (digital-to-analog converter) to output a feedback voltage. This approach employs a mixed-signal feedback method, but the feedback accuracy is limited by the accuracy of the DAC, which can easily lead to loop instability, and it is also more expensive.

[0004] The third method is to use analog processing, filtering the input signal and directly feeding it back to the bias voltage input of the closed-loop amplifier. However, this method is difficult to apply to low-frequency targets. When the signal frequency is low, the cutoff frequency of the filter needs to be lower than the signal frequency, which results in a very large time constant, so the loop takes a long time to stabilize.

[0005] In summary, to address the aforementioned issues, this application proposes an input DC adaptive amplifier circuit based on an analog feedback network, which utilizes the charging and discharging of current to continuously and in real-time adjust the feedback voltage. This circuit features a wide DC input range and fast stabilization speed, effectively avoiding output saturation problems caused by DC input to the amplifier. Summary of the Invention

[0006] The present invention aims to at least solve one of the technical problems existing in related technologies. To this end, the present invention provides an input DC adaptive calibration circuit, which enables the amplifier to amplify useful signals normally under a large DC offset voltage, effectively avoiding the output saturation problem caused by the amplifier input DC.

[0007] This invention provides an input DC adaptive calibration circuit, comprising: a buffer capacitor, a first controlled current source, a second controlled current source, a third controlled current source, a first comparator, a second comparator, a variable resistor network, a first switch, and a second switch; a first input signal controls the output current magnitude of the first controlled current source, the second controlled current source, and the third controlled current source; the positive terminal of the first controlled current source is connected to a power supply; the negative terminal of the first controlled current source is connected to one end of the first switch; the other end of the first switch is connected to one end of the second switch and one end of the buffer capacitor; the other end of the second switch is connected to the positive terminal of the second controlled current source; the second... The negative terminal of the controlled current source is grounded; the other end of the buffer capacitor is grounded; the positive terminal of the third controlled current source is connected to the power supply; the negative terminal of the third controlled current source is connected to one end of the variable resistor network, the negative input terminal of the first comparator, and the negative input terminal of the second comparator; the other end of the variable resistor network is grounded; the positive input terminal of the first comparator is connected to the highest threshold value of the first input signal; the output terminal of the first comparator is used to control the on / off state of the first switch and the resistance value of the variable resistor network; the positive input terminal of the second comparator is connected to the lowest threshold value of the first input signal; the output terminal of the second comparator is used to control the on / off state of the second switch and the resistance value of the variable resistor network; one end of the buffer capacitor outputs a feedback signal.

[0008] The DC adaptive calibration circuit provided by the present invention further includes: an input stage amplifier, which is a closed-loop amplifier circuit, including: a signal input terminal, a bias voltage input terminal, and a signal output terminal; the signal input terminal is connected to a second input signal; and the signal output terminal outputs a first input signal.

[0009] The input DC adaptive calibration circuit provided by the present invention further includes a first buffer, wherein the positive input terminal of the first buffer is connected to one end of a buffer capacitor; and the output terminal of the first buffer is connected to the bias voltage input terminal and the negative input terminal of the first buffer.

[0010] The DC adaptive calibration circuit provided by the present invention further includes: a driver amplifier, an NMOS driver transistor, a load resistor, and a fourth controlled current source; the positive input terminal of the driver amplifier is connected to the signal output terminal; the output terminal of the driver amplifier is connected to the gate of the NMOS driver transistor; one end of the load resistor is connected to the source of the NMOS driver transistor and the negative input terminal of the driver amplifier; the other end of the load resistor is grounded; and the negative terminal of the fourth controlled current source is connected to the drain of the NMOS driver transistor.

[0011] According to the present invention, an input DC adaptive calibration circuit is provided, wherein the input stage amplifier further includes an adder: the output terminal of the adder is connected to the signal input terminal; the first input terminal of the adder receives the DC bias component of the second input signal; and the second input terminal of the adder receives the probe signal component of the second input signal.

[0012] According to the present invention, the first switch of an input DC adaptive calibration circuit is a PMOS transistor, and the second switch is an NMOS transistor.

[0013] According to the present invention, the first controlled current source, the second controlled current source, and the third controlled current source of the input DC adaptive calibration circuit are all sub-current mirrors of a common-source cascode current mirror.

[0014] According to the present invention, the fourth controlled current source of the input DC adaptive calibration circuit is the mother current mirror of the common source cascode current mirror.

[0015] According to the present invention, when the voltage of the feedback signal is higher than the highest threshold, the resistance of the variable resistor network increases, and the voltage at the negative input terminals of the first comparator and the second comparator will jump upward. When the voltage of the feedback signal is lower than the lowest threshold, the resistance of the variable resistor network decreases, and the voltage at the negative input terminals of the first comparator and the second comparator will jump downward.

[0016] The above-described one or more technical solutions in the embodiments of the present invention have at least one of the following technical effects: the feedback loop of the present invention is flexible and adjustable, and the output current of the current source and the size of the charging capacitor can be configured according to different application scenarios, thereby controlling the feedback speed; the resistance value can be configured according to different application scenarios, thereby adjusting the threshold of the actual output voltage. The present invention has a simple structure and low cost. Since ultra-low frequency filtering is not required, ultra-large resistors or capacitors are not needed, which is beneficial for on-chip integration; reducing the operating current of the controlled current source can reduce system power consumption.

[0017] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of an input DC adaptive calibration circuit provided by the present invention.

[0020] Figure 2 This is a schematic diagram of an embodiment of an input DC adaptive calibration circuit provided by the present invention.

[0021] Figure 3 This is a simulation diagram A of the adjustment process of an input DC adaptive calibration circuit provided by the present invention.

[0022] Figure 4 This is a simulation diagram B of the adjustment process of an input DC adaptive calibration circuit provided by the present invention.

[0023] Figure label: 1. Input stage amplifier; 2. First buffer; 3. Buffer capacitor; 4. First controlled current source; 5. Second controlled current source; 6. Third controlled current source; 7. First comparator; 8. Second comparator; 9. First switch; 10. Second switch; 11. Variable resistor network; 12. Driver amplifier; 13. NMOS driver transistor; 14. Fourth controlled current source; 15. Load resistor; 16. First resistor; 17. Second resistor; 18. Third resistor; 19. First switching transistor; 20. Second switching transistor; 21. First input signal input terminal; 22. Feedback signal output terminal; 23. Highest threshold input terminal of the first input signal; 24. Lowest threshold input terminal of the first input signal; 25. First input terminal of the adder; 26. Second input terminal of the adder; 27. Power supply; 28. Output signal output terminal. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The following embodiments are used to illustrate this invention but cannot be used to limit the scope of this invention.

[0025] In the description of the embodiments of the present invention, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0026] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of the present invention based on the specific circumstances.

[0027] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0028] Example: like Figure 1 The present invention provides an input DC adaptive calibration circuit, comprising: a buffer capacitor 3, a first controlled current source 4, a second controlled current source 5, a third controlled current source 6, a first comparator 7, a second comparator 8, a variable resistor network 11, a first switch 9, and a second switch 10. The first input signal controls the output current magnitude of the first controlled current source 4, the second controlled current source 5, and the third controlled current source 6; The positive terminal of the first controlled current source 4 is connected to the power supply 27; The negative terminal of the first controlled current source 4 is connected to one end of the first switch 9; The other end of the first switch 9 is connected to one end of the second switch 10 and one end of the buffer capacitor 3; The other end of the second switch 10 is connected to the positive terminal of the second controlled current source 5; The negative terminal of the second controlled current source 5 is grounded; The other end of the buffer capacitor 3 is grounded; The positive terminal of the third controlled current source 6 is connected to the power supply 27; The negative terminal of the third controlled current source 6 is connected to one end of the variable resistor network 11, the negative input terminal of the first comparator 7, and the negative input terminal of the second comparator 8. The other end of the variable resistor network 11 is grounded; The positive input terminal of the first comparator 7 is connected to the highest threshold of the first input signal; The output of the first comparator 7 is used to control the on / off state of the first switch 9 and the resistance value of the variable resistor network 11; The positive input terminal of the second comparator 8 is connected to the lowest threshold of the first input signal; The output of the second comparator 8 is used to control the on / off state of the second switch 10 and the resistance value of the variable resistor network 11. One end of the buffer capacitor 3 outputs a feedback signal, which is output from the feedback signal output terminal 22.

[0029] The first input signal is input from the first input signal input terminal 21 and is used to control the first controlled current source 4, the second controlled current source 5, and the third controlled current source 6. All three current sources are common-source cascode current mirrors, used to proportionally replicate the first input signal onto their respective circuits. The first controlled current source 4 and the third controlled current source 6 can change according to the output voltage of the closed-loop amplifier circuit. The greater the deviation of the feedback signal's output voltage from the set threshold range, the faster the circuit's feedback adjustment speed.

[0030] The highest threshold of the first input signal is input to the positive input terminal of the first comparator 7 through the highest threshold input terminal 23 of the first input signal. The first comparator 7 is used to control the on / off state of the first switch 9 and the resistance value of the variable resistor network 11.

[0031] The minimum threshold of the first input signal is input to the positive input of the second comparator 8 through the minimum threshold input terminal 24 of the first input signal. The second comparator 8 is used to control the on / off state of the second switch 10 and the resistance value of the variable resistor network 11.

[0032] The first comparator 7, the second comparator 8, and the variable resistor network 11 can suppress interference to a certain extent, improving the noise margin of the circuit. When the output voltage of the feedback signal is slightly higher than the set maximum threshold, the resistance of the variable resistor network 11 increases, and the voltage at the negative input terminals of the first comparator 7 and the second comparator 8 will jump upward. When the output voltage of the feedback signal is slightly lower than the set minimum threshold, the resistance of the variable resistor network 11 decreases, and the voltage at the negative input terminals of the first comparator 7 and the second comparator 8 will jump downward.

[0033] Specific embodiments of the present invention are as follows: Figure 2 As shown: This embodiment of the invention also includes an input stage amplifier 1: the input stage amplifier 1 is a closed-loop amplifier circuit, including: a signal input terminal, a bias voltage input terminal, and a signal output terminal. The signal input terminal is connected to a second input signal; The output signal output terminal 28 outputs the first input signal.

[0034] This embodiment of the invention also includes a first buffer 2: The positive input terminal of the first buffer 2 is connected to one end of the buffer capacitor 3; The output terminal of the first buffer 2 is connected to the bias voltage input terminal and the negative input terminal of the first buffer 2.

[0035] This embodiment of the invention also includes a driver amplifier 12, an NMOS driver transistor 13, a load resistor 15, and a fourth controlled current source 14. The positive input terminal of the drive amplifier 12 is connected to the signal output terminal; The output terminal of the drive amplifier 12 is connected to the gate of the NMOS drive transistor 13; One end of the load resistor 15 is connected to the source of the NMOS driver transistor 13 and the negative input terminal of the driver amplifier 12; The other end of the load resistor 15 is grounded; The negative terminal of the fourth controlled current source 14 is connected to the drain of the NMOS driving transistor 13.

[0036] The input stage amplifier 1 of this embodiment of the invention also includes an adder: The output of the adder is connected to the signal input. The first input terminal 25 of the adder receives the DC bias component of the second input signal; The second input terminal 26 of the adder receives the detection signal component of the second input signal.

[0037] In this embodiment of the invention, the DC bias component of the second input signal is input through the first input terminal 25 of the adder; the probe signal component of the second input signal is input through the second input terminal 26 of the adder. The input stage amplifier 1 is a closed-loop amplifier circuit. The DC bias component and the probe signal component of the second input signal are added and amplified by the input stage amplifier 1 to obtain the first input signal, with a voltage of [voltage value missing]. The input is given to the positive input terminal of driver amplifier 12. Since driver amplifier 12 and NMOS driver transistor 13 form negative feedback, the voltage at the negative terminal of driver amplifier 12 is... The resistance value of the load resistor 15 is... The current flowing through the load resistor 15 is The first controlled current source 4, the second controlled current source 5, the third controlled current source 6, and the fourth controlled current source 14 are all current mirrors with a common source and common gate structure, capable of accurately replicating current proportionally. Furthermore, the current ratios among the four current mirrors are adjustable. Specifically, the current of the fourth controlled current source 14... The voltage of the first input signal After voltage-current-voltage conversion, it forms , For comparison voltage. The voltage is compared with the lowest threshold of the first input signal. and the highest threshold of the first input signal The first switch 9 and the second switch 10 are controlled to charge and discharge the buffer capacitor 3. In this embodiment of the invention, the first switch 9 is a PMOS transistor, and the second switch 10 is an NMOS transistor.

[0038] when At this time, both the first comparator 7 and the second comparator 8 output a high level, the first switch 9 is turned off, and the second switch 10, the first switching transistor 19, and the second switching transistor 20 are turned on. Due to the parallel connection of the first resistor 16 and the second resistor 17... The impedance at the point decreases. The voltage will experience a downward jump, buffer capacitor 3 will begin to discharge, and the feedback voltage will... The voltage drops. At this point, the first resistor 16, the second resistor 17, and the third resistor 18 are connected in parallel. It can be represented as: in, The current of the second controlled current source and the current of the fourth controlled current source The current mirror ratio, i.e. , The resistance value of the first resistor, 16. The resistance value of the second resistor 17. The resistance value of the third resistor is 18. This indicates that the resistors are connected in parallel.

[0039] Because of the resistance value of the first resistor 16 The resistance value of the second resistor 17 Generally, the resistance value is much larger than that of the third resistor, 18. .along with The decline, Gradually increase, It also rises accordingly.

[0040] when At this time, the first comparator 7 outputs a high level, the second comparator 8 outputs a low level, the second switching transistor 20 is turned on, and the first switch 9, the second switch 10, and the first switching transistor 19 are all turned off. Due to the disconnection of the first resistor 16, point... The impedance increases. An upward jump will occur, and buffer capacitor 3 will not charge or discharge. The voltage remains constant. At this time, the second resistor 17 and the third resistor 18 are connected in parallel. It can be represented as: when When both the first comparator 7 and the second comparator 8 output a low level, the first switch 9, the second switch 10, the first switching transistor 19, and the second switching transistor 20 are all turned off. This is due to the disconnection of the first resistor 16 and the second resistor 17, causing point... The impedance increases again. The voltage will jump upwards, and buffer capacitor 3 will begin to charge. The voltage rises. At this time... It can be represented as: The resistance change of the variable resistor network 11 in this invention is similar to a positive feedback effect, which can suppress interference to a certain extent and improve the noise margin of the circuit. Furthermore, the output voltage of the first input signal... The greater the deviation from the set threshold range, the greater the charging and discharging current of buffer capacitor 3, and the greater the feedback voltage. The faster the adjustment speed.

[0041] When the entire circuit is stable, the first input signal becomes the output signal, and the output signal is output from the output terminal 28.

[0042] The adjustment process in this embodiment of the invention is as follows: Figure 3 and Figure 4 As shown, the resistance value of load resistor 15 Set as The resistance value of the first resistor 16 Set as The resistance value of the second resistor 17 Set as The resistance value of the third resistor 18 Set as The capacitance value of buffer capacitor 3 is set to The current of the fourth controlled current source and the current of the third controlled current source The current mirror ratio is set to 1:10, and the current of the fourth controlled current source is... The current of the first controlled current source Current mirror of the second controlled current source The ratio is 1:1:1. The second input signal has a 1mV probe signal component and a 10kHz sine wave. The second input signal has a 0.1V DC bias DC component. The second input signal is a superimposed waveform of the probe signal component and the DC bias component. The amplification factor of input stage amplifier 1 is 250 times. The threshold of the first input signal is: , When the step signal is a rising step, the output signal will immediately saturate to 2.5V, and gradually return to normal as the feedback signal rises; when the step signal is a falling step, the output signal will immediately saturate to 0V, and gradually return to normal as the feedback signal falls. When the charging and discharging current is set to twice its original value, the feedback adjustment time is reduced to half its original value.

[0043] This invention employs an analog method to achieve continuous and rapid adjustment of the feedback voltage. The input signal is first amplified by the input stage amplifier 1, and then enters the input DC adaptive amplifier circuit. The controlled current source adjusts the current magnitude in real time according to the output voltage of the input stage amplifier 1. The comparator compares the output of the input stage amplifier 1 with the threshold voltage, adjusts the resistance value of the variable resistor network 11, and controls the switch to charge and discharge the buffer capacitor 3. Finally, the voltage on the buffer capacitor 3 is fed back to the bias voltage input terminal of the input stage amplifier 1 through the buffer.

[0044] The embodiments of the present invention can suppress interference to a certain extent and improve the noise margin of the circuit. When the output voltage of the input stage amplifier 1 is slightly higher than the set maximum threshold, the resistance of the variable resistor network 11 increases, and the voltage at the negative input terminals of the first comparator 7 and the second comparator 8 will jump upward. When the output voltage of the input stage amplifier 1 is slightly lower than the set minimum threshold, the resistance of the variable resistor network 11 decreases, and the voltage at the negative input terminals of the first comparator 7 and the second comparator 8 will jump downward.

[0045] According to the embodiments of the present invention, the output voltage of the input stage amplifier 1 can change according to the change of the output voltage of the input stage amplifier 1. The greater the deviation of the output voltage of the input stage amplifier 1 from the set threshold range, the faster the feedback adjustment speed of the circuit.

[0046] The feedback loop of this invention is flexible and adjustable. The output current of the current source and the size of the buffer capacitor 3 can be configured according to different application scenarios to control the feedback speed. The resistance value can be configured according to different application scenarios to adjust the threshold of the actual output voltage.

[0047] The embodiments of the present invention have a simple structure and low cost. Since ultra-low frequency filtering is not required, ultra-large resistors or capacitors are not needed, which is beneficial for on-chip integration. The reduced operating current of the controlled current source can reduce system power consumption.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An input DC adaptive calibration circuit, characterized in that, include: A buffer capacitor, a first controlled current source, a second controlled current source, a third controlled current source, a first comparator, a second comparator, a variable resistor network, a first switch, and a second switch: The first input signal controls the output current magnitude of the first controlled current source, the second controlled current source, and the third controlled current source; The positive terminal of the first controlled current source is connected to the power supply; The negative terminal of the first controlled current source is connected to one end of the first switch; The other end of the first switch is connected to one end of the second switch and one end of the buffer capacitor; The other end of the second switch is connected to the positive terminal of the second controlled current source; The negative terminal of the second controlled current source is grounded; The other end of the buffer capacitor is grounded. The positive terminal of the third controlled current source is connected to the power supply; The negative terminal of the third controlled current source is connected to one end of the variable resistor network, the negative input terminal of the first comparator, and the negative input terminal of the second comparator; The other end of the variable resistor network is grounded; The positive input terminal of the first comparator is connected to the highest threshold of the first input signal; The output of the first comparator is used to control the on / off state of the first switch and the resistance value of the variable resistor network. The positive input terminal of the second comparator is connected to the lowest threshold of the first input signal; The output of the second comparator is used to control the on / off state of the second switch and the resistance value of the variable resistor network; One end of the buffer capacitor outputs a feedback signal; The first switch is a PMOS transistor, and the second switch is an NMOS transistor; The first controlled current source, the second controlled current source, and the third controlled current source are all sub-current mirrors of the common-source cascode current mirror; The variable resistor network includes a first resistor, a second resistor, a first switching transistor, and a second switching transistor; Calculate the voltage V at the negative input terminals of the first and second comparators. t Through voltage V t The highest threshold voltage V of the first input signal th and minimum threshold V tl The comparison is used to charge and discharge the buffer capacitor, where V t ≤V tl When the first switch is off, the second switch, the first switch transistor, and the second switch transistor are on. Due to the parallel connection of the first and second resistors, V... t The impedance at the point decreases, V t The voltage will experience a downward jump, the buffer capacitor will begin to discharge, and the feedback voltage will decrease; when V tl <V t <V th When the second switching transistor is turned on, the first switch, the second switch, and the first switching transistor are all turned off. Due to the disconnection of the first resistor, V... t As the impedance at the point increases, V t An upward voltage jump occurs, the buffer capacitor does not charge or discharge, and the feedback voltage remains unchanged; V t ≥V th At that time, the first switch, the second switch, the first switch transistor, and the second switch transistor are all turned off, and the disconnection of the first resistor and the second resistor causes point V to be turned off. t The impedance increases again, V t The voltage will jump upwards, the buffer capacitor will start charging, and the feedback voltage will rise.

2. The input DC adaptive calibration circuit according to claim 1, characterized in that, It also includes an input stage amplifier: the input stage amplifier is a closed-loop amplifier circuit, including: a signal input terminal, a bias voltage input terminal, and a signal output terminal. The signal input terminal is connected to a second input signal; The signal output terminal outputs the first input signal.

3. The input DC adaptive calibration circuit according to claim 2, characterized in that, It also includes the first buffer: The positive input terminal of the first buffer is connected to one end of the buffer capacitor; The output terminal of the first buffer is connected to the bias voltage input terminal and the negative input terminal of the first buffer.

4. The input DC adaptive calibration circuit according to claim 2, characterized in that, It also includes a driver amplifier, an NMOS driver transistor, a load resistor, and a fourth controlled current source: The positive input terminal of the driver amplifier is connected to the signal output terminal; The output of the drive amplifier is connected to the gate of the NMOS drive transistor; One end of the load resistor is connected to the source of the NMOS driver transistor and the negative input terminal of the driver amplifier; The other end of the load resistor is grounded; The negative terminal of the fourth controlled current source is connected to the drain of the NMOS driving transistor.

5. The input DC adaptive calibration circuit according to claim 3, characterized in that, The input stage amplifier also includes an adder: The output of the adder is connected to the signal input. The first input terminal of the adder receives the DC bias component of the second input signal; The second input terminal of the adder receives the detection signal component of the second input signal.

6. The input DC adaptive calibration circuit according to claim 4, characterized in that, The fourth controlled current source is the mother current mirror of the common-source cascode current mirror.

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