Current-mode driver circuit

Abstract

The present disclosure relates to a current-mode driving circuit, comprising: an output module (10) comprising a first MOS transistor (M1); a sampling module (20) comprising a second MOS transistor (M2) configured to sample a current flowing through the first MOS transistor (M1); and a loop control module (30) comprising: a third MOS transistor (M3) and a comparison module (32) configured to compare the current sampled by the second MOS transistor (M2) with a reference current (Iref1) and output a comparison difference to a gate of the third MOS transistor (M3) so that the first MOS transistor (M1) adjusts an output current at an output end (OUT) based on the comparison difference.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to driving circuits, and particularly to current-type driving circuits. Background Technology

[0002] Some electronic devices require not only high voltage but also high frequency for driving. In traditional current-driven high-voltage drives, simultaneously meeting the requirements for speed, accuracy, and high current is challenging. This is because the accuracy and speed of the output drive current are often incompatible. Regarding frequency, traditional techniques typically use a current mirror to control the output drive current, but this method is slow and prone to significant errors in high-voltage, high-current applications. Although the drive output current can be adjusted by setting a loop, the large parasitic capacitance introduced by the high-voltage power transistors poses a significant challenge to loop stability. Therefore, the loop bandwidth is usually set to a low frequency, resulting in a very slow loop response. An improvement to the traditional current-driven drive circuit is desired. Summary of the Invention

[0003] Embodiments of this disclosure provide a current-driven circuit designed to address one or more of the problems described above, as well as other potential problems.

[0004] According to a first aspect of this disclosure, a current-mode drive circuit is provided. The current-mode drive circuit includes: an output module including a first MOSFET and an output terminal, the drain of the first MOSFET being connected to a power supply node, and the source of the first MOSFET being connected to the output terminal; a sampling module including a second MOSFET configured to sample the current flowing through the first MOSFET, the source of the second MOSFET being connected to the output terminal, and the gate of the second MOSFET being connected to the gate of the first MOSFET; and a loop control module including: a third MOSFET, a first terminal of the third MOSFET being connected to the gate of the second MOSFET and the gate of the first MOSFET; and a comparison module configured to compare the current sampled by the second MOSFET with a reference current, and output the difference between the comparisons to the gate of the third MOSFET, such that the first MOSFET adjusts the output current at the output terminal based on the difference between the comparisons.

[0005] In some embodiments, the driving circuit further includes a first voltage clamping module configured to clamp the drain voltage of the third MOSFET; the first voltage clamping module includes a first clamping MOSFET and a second clamping MOSFET; the source of the first clamping MOSFET is connected to a first terminal of the third MOSFET, the drain of the first clamping MOSFET is connected to the gate of the second MOSFET and the gate of the first MOSFET; the gate of the first clamping MOSFET is connected to the gate of the second clamping MOSFET, and a first bias current is applied to the source of the second clamping MOSFET; the first clamping MOSFET and the second clamping MOSFET are configured to withstand a first voltage, and the third MOSFET is configured to withstand a second voltage lower than the first voltage; wherein the first clamping MOSFET and the second clamping MOSFET are configured to operate in a switching mode, and the first MOSFET, the second MOSFET, and the third MOSFET are configured to operate in a proportional mode.

[0006] In some embodiments, the gates of the first clamping MOS transistor and the second clamping MOS transistor are connected to a first control node to turn the first clamping MOS transistor and the second clamping MOS transistor on or off based on the potential of the first control node.

[0007] In some embodiments, the driving circuit further includes an impedance attenuation circuit configured to reduce the impedance between the gate and the source of the first MOS transistor.

[0008] In some embodiments, the impedance attenuation circuit includes: a first impedance attenuation MOSFET, the drain of which is connected to the gate of the first MOSFET, and the source of which is connected to the output terminal; a second impedance attenuation MOSFET, the gate of which is connected to the gate of the first impedance attenuation MOSFET, the source of which is connected to the output terminal, and the drain of which is connected to the drain of a second clamping MOSFET; and a resistor, one end of which is connected to the drain of the first impedance attenuation MOSFET, and the other end of which is connected to a first connection node where the gate and drain of the second impedance attenuation MOSFET are connected.

[0009] In some embodiments, the first MOS transistor and the second MOS transistor are laterally diffused metal-oxide semiconductors (LDMOS).

[0010] In some embodiments, the driving circuit further includes a second voltage clamping module configured to clamp the drain voltage of the first MOSFET and the drain voltage of the second MOSFET. The second voltage clamping module includes a third clamping MOSFET, a fourth clamping MOSFET, and a fifth clamping MOSFET. The source of the third clamping MOSFET is connected to the drain of the second MOSFET, the source of the fourth clamping MOSFET is connected to the drain of the first MOSFET, the gate of the third clamping MOSFET is connected to the gate of the fourth clamping MOSFET, and the drain of the fifth clamping MOSFET is connected to the gate of the third clamping MOSFET. The gate of the OS transistor and the gate of the fourth clamping MOS transistor, and the source of the fifth clamping MOS transistor are subjected to a second bias current; the third clamping MOS transistor, the fourth clamping MOS transistor, and the fifth clamping MOS transistor withstand a first voltage, and the first MOS transistor and the second MOS transistor are configured to withstand a second voltage lower than the first voltage; wherein the third clamping MOS transistor, the fourth clamping MOS transistor, and the fifth clamping MOS transistor are configured to operate in a switching mode, and the first MOS transistor, the second MOS transistor, and the third MOS transistor are configured to operate in a proportional mode.

[0011] In some embodiments, the driving circuit further includes a current limiting module configured to clamp the gate voltage of the third clamping MOSFET and the gate voltage of the fourth clamping MOSFET.

[0012] In some embodiments, the current limiting module includes a Zener diode.

[0013] In some embodiments, the comparison module includes a first current mirror, which includes a first current mirror MOSFET and a second current mirror MOSFET. The first current mirror MOSFET is configured to convert the sampled current into a first sampling current. The drain of the first current mirror MOSFET is connected to the drain of the second MOSFET, the source of the first current mirror MOSFET is connected to the source of the second current mirror MOSFET, and the gate of the first current mirror MOSFET is connected to the gate of the second current mirror MOSFET.

[0014] In some embodiments, the driving circuit further includes a capacitor, one end of which is connected to a second connection node where the drain of the second current mirror MOSFET and the gate of the third MOSFET are interconnected, and the other end of which is connected to a third connection node where the source of the first current mirror MOSFET and the source of the first current mirror MOSFET are interconnected, and the third connection node is connected to a power supply node.

[0015] In some embodiments, the first current mirror further includes a first control MOS transistor, the source of which is connected to the third connection node, the drain of which is connected to the drain of the second MOS transistor, and the gate of which is connected to a second control node, so as to turn the first control MOS transistor on or off based on the potential of the second control node.

[0016] In some embodiments, the comparison module further includes a second current mirror that converts the first reference current (Iref2) into the reference current. The second current mirror includes a third current mirror MOSFET and a fourth current mirror MOSFET. The gate of the third current mirror MOSFET is connected to the gate of the fourth current mirror MOSFET, the source of the third current mirror MOSFET is connected to the source of the fourth current mirror MOSFET, the drain of the third current mirror MOSFET is connected to the second connection node, and the drain of the fourth current mirror MOSFET is configured to receive the first reference current.

[0017] In some embodiments, the second current mirror further includes a second control MOS transistor, the gate of which is connected to a third control node, and the drain of which is connected to the gate of the fourth current mirror MOS transistor and the gate of the third current mirror MOS transistor, so as to turn the second control MOS transistor on or off based on the potential of the third control node.

[0018] The loop design disclosed herein enables accurate sampling and fast response performance. Attached Figure Description

[0019] The above and other objects, features, and advantages of embodiments of this disclosure will become readily apparent from the accompanying drawings and the following detailed description. Several embodiments of this disclosure are illustrated in the drawings by way of example and not limitation.

[0020] Figure 1 A schematic circuit diagram of a current-type drive circuit according to a first embodiment of the present disclosure is shown.

[0021] Figure 2 A schematic circuit diagram of a current-type drive circuit according to a second embodiment of the present disclosure is shown.

[0022] Figure 3 A schematic circuit diagram of a current-type drive circuit according to a third embodiment of the present disclosure is shown.

[0023] In the various figures, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0024] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0025] In many electronic devices, besides requiring precise control of the drive current, high-frequency driving is also necessary. As an example, in the driving of LEDs and similar devices, the switching frequency is increasingly higher. Furthermore, these applications often involve high voltage and high current.

[0026] In traditional current-driven high-voltage drive applications, simultaneously meeting the requirements for speed, accuracy, and high current is quite challenging. In contrast, voltage-driven drives can be quickly turned on and off via logic chains, while current-driven drives face significant difficulties. As described in the background section, although the accuracy of the output current used for driving can be controlled via a loop, high-voltage power transistors introduce large parasitic capacitances during high-frequency driving, affecting loop stability. Setting the loop bandwidth to a lower frequency results in a very slow loop response, making it unsuitable for high-frequency applications.

[0027] According to this disclosure, a current-driven circuit, particularly for large drive currents, is proposed, which can solve one or more of the aforementioned technical problems. The specific implementation structure of the current-driven circuit according to embodiments of this disclosure is described in detail below with reference to the accompanying drawings.

[0028] Figure 1 A schematic circuit diagram of a current-type drive circuit 100 according to a first embodiment of the present disclosure is shown. Figure 1 As shown, the driving circuit 100 includes an output module 10, a sampling module 20, and a loop control module 30. The output module 10 includes a first MOSFET M1 and an output terminal OUT. The first MOSFET M1 is the main power transistor, and its source is connected to the output terminal OUT. The drain of the first MOSFET M1 is connected to a power node VM, which is configured to provide a high voltage, such as tens of volts. In some embodiments, the voltage is, for example, 10V to 100V. The sampling module 20 includes a second MOSFET M2, which is a sampling MOSFET and configured to sample the current flowing through the first MOSFET M1. The source of the second MOSFET M2 is connected to the output terminal OUT, and its gate is connected to the gate of the first MOSFET M1 (represented as HS_Gate in the figure). In the illustrated embodiment, M1 and M2 are high-voltage N-type LDMOS transistors; it should be understood that M1 and M2 can also be P-type LDMOS transistors.

[0029] The loop control module 30 includes a third MOSFET M3 and a comparator module 32. The first terminal of the third MOSFET M3 is connected to the gate of the second MOSFET M2 and the gate of the first MOSFET M1. In the illustrated embodiment, M3 is a PMOS transistor, and the first terminal corresponds to the drain of the PMOS transistor. It should be understood that this is merely exemplary; M3 could also be an NMOS transistor, with the first terminal corresponding to the source of the NMOS transistor. The comparator module 32 can be a differential comparator, configured to compare the current sampled by the second MOSFET M2 with a reference current Iref1. The difference generated by the comparison is output to the gate of the third MOSFET M3, and after being amplified by the third MOSFET M3, it is output to the gates of the first MOSFET M1 and the second MOSFET M2. Thus, the first MOSFET M1 adjusts the output current at its output terminal OUT based on the current from the third MOSFET M3.

[0030] According to this disclosure, the first MOSFET M1, the second MOSFET M2, and the third MOSFET M3 all operate in proportional mode, i.e., in the analog region. The output current at the output terminal OUT can be precisely adjusted by the loop control module 30 based on the reference current Iref1. During operation, the comparator module 32 compares the current sampled by the second MOSFET M2 with the reference current Iref1, and outputs the difference to the gate of the third MOSFET M3 for amplification. The amplified current is then further output to the gates of the first MOSFET M1 and the second MOSFET M2, thereby precisely controlling the output current at the output terminal OUT.

[0031] In some embodiments, such as Figure 1 As shown, the first and second MOSFETs can be high-voltage MOSFETs, such as laterally diffused metal-oxide-semiconductor (LDMOS), while the third MOSFET M3 can be a conventional MOSFET (such as a traditional NMOS or PMOS) that withstands a lower voltage than the first and second MOSFETs. This is particularly suitable for applications where the power node VM is high-voltage (e.g., tens of volts).

[0032] In some embodiments, such as Figure 1 As shown, the drive circuit 100 may further include a first voltage clamping module 40 configured to clamp the drain voltage of the third MOSFET M3. By clamping the drain voltage of the third MOSFET M3, the third MOSFET M3 can be used in high-voltage applications.

[0033] In some embodiments, such as Figure 1As shown, the first voltage clamping module 40 may include a first clamping MOSFET QM1 and a second clamping MOSFET QM2. The first clamping MOSFET QM1 and the second clamping MOSFET QM2 operate in a switching mode. The first clamping MOSFET QM1 may be connected in series between the drain of a third MOSFET M3 and the gate of the first MOSFET M1. The gate of the first clamping MOSFET QM1 may be connected to the gate of the second clamping MOSFET QM2, and a first bias current Ib may be applied to the source of the second clamping MOSFET QM2. The drain of the second clamping MOSFET QM2 may be connected to the drain of a second impedance-attenuating MOSFET ZM2. In some embodiments, the gates of the first clamping MOSFET QM1 and the second clamping MOSFET QM2 may also be connected to a control node, allowing the switching on and off of the first clamping MOSFET QM1 and the second clamping MOSFET QM2 to be controlled based on the voltage at the control node. In the illustrated embodiment, QM1 and QM2 are P-type LDMOS transistors. It should be understood that the illustrated embodiment is merely exemplary, and QM1 and QM2 may also be N-type LDMOS.

[0034] The loop design disclosed herein enables accurate sampling and fast response performance. The output current used for driving primarily comes from power transistor M1. In some embodiments, sampling transistor M1 has a detection current in the mA range, M3 has an adjustment current in the mA range, and the remaining MOSFETs have currents in the μA range. The mA-level current on M2 flows to the drive output current, which reduces the size of the power transistor to some extent; on the other hand, the current on the supply voltage VM flows into the drive output as much as possible, rather than being consumed by internal circuitry, thus reducing energy loss.

[0035] In some embodiments, M3 may employ an NMOS structure because NMOS is smaller than PMOS for the same current capability, thus reducing chip area. It should be understood that this is merely exemplary, and M3 may also employ a PMOS structure. In this disclosure, by using a MOS transistor M3 to replace the charge pump, chip area can be further reduced.

[0036] In some embodiments, it is desirable to maximize the headroom between M1 and M2. When M2 is a P-type LDMOS, its gate-source voltage Vgs is fully open, and its drain-source voltage Vds is very small. This effectively means that the drain of M3 is output to the gates of M1 and M2. When OUT approaches VM, the headroom between M1 and M2 depends on the sum of the gate-source voltages Vgs of M1 and M2 and the drain-source voltage of M3. For example, the drain-source voltage of M3 can be set to several hundred mV. In this case, the minimum headroom between OUT and VM can be between 1-2V, which meets the requirements for many applications.

[0037] According to this disclosure, a fast-response loop can be achieved through current comparison, enabling precise adjustment of the drive output current; however, the power transistors (e.g., for M1 and M2) in the drive circuit have large parasitic capacitances, which may affect loop stability. The impact of these parasitic capacitances is greater when the loop control module 30 operates in the high-frequency region. In some embodiments, the drive circuit 100 further includes an impedance attenuation circuit 50 to improve the loop bandwidth.

[0038] like Figure 1 As shown, the driving circuit 100 may further include an impedance attenuation circuit 50. The impedance attenuation circuit 50 is configured to reduce the impedance between the gate and source of the first MOS transistor M1. In some embodiments, such as Figure 1 As shown, the impedance attenuation circuit 50 may include a first impedance attenuation MOSFET ZM1, a second impedance attenuation MOSFET ZM2, and a resistor R1. The drain of the first impedance attenuation MOSFET ZM1 is connected to the gate of the first MOSFET ZM1, and the source of the first impedance attenuation MOSFET ZM1 is connected to the output terminal OUT. The gate of the second impedance attenuation MOSFET ZM2 is connected to the gate of the first impedance attenuation MOSFET ZM1, and the source of the second impedance attenuation MOSFET ZM2 is connected to the output terminal OUT. One end of the resistor R1 is connected to the drain of the first impedance attenuation MOSFET ZM1, and the other end of the resistor R1 is connected to the first connection node P1, which is connected to the gate and drain of the second impedance attenuation MOSFET ZM2.

[0039] According to this disclosure, such as Figure 1 In the illustrated embodiment, the low-impedance path formed by ZM1, ZM2, and R1 reduces the impedance between HS_Gate and the source of the first MOSFET M1. Therefore, the bias current Ib flows into ZM2 through QM2, thereby establishing a bias voltage for the low-impedance path. The bias current Ib is significantly smaller than the current in the loop containing M2. The principle behind the increased loop bandwidth of the low-impedance path is explained in detail below.

[0040] After the loop is established and the current from M3 flows to ZM2, Ib can be ignored. ZM1 and ZM2 have the same gate-source voltage and can be low-voltage MOSFETs. Both ZM1 and ZM2 operate in proportional mode. ZM2 has a low current, while ZM1 has a current in the mA range, and their currents are mirrored in a ratio of N:1. In some embodiments, the current of ZM2 is relatively small, approximately in the μA range, and in integrated circuit design, the resistor R1 is typically in the KΩ range. Therefore, the equivalent resistance of the impedance attenuation circuit can be simplified to:

[0041]

[0042] Therefore, the equivalent resistance Req can be determined by adjusting the resistance value of R1 and the mirror ratio between ZM1 and ZM2. Through the low-impedance path and the selection of the parameters described above, the bandwidth of the loop can be effectively widened even if there are high-impedance nodes (e.g., current mirrors) in the comparator module 32 and large parasitic capacitance nodes (e.g., LDMOS transistors) in the loop.

[0043] Figure 2 A schematic circuit diagram of a current-type drive circuit 200 according to a second embodiment of the present disclosure is shown. Figure 2 The illustrated embodiments and Figure 1 The embodiments shown are similar, with emphasis on describing their differences and omission of descriptions of their similarities.

[0044] In some embodiments, such as Figure 2 As shown, the comparison module 32 may further include a first current mirror and a capacitor C1. The first current mirror includes a first current mirror MOSFET JM1 and a second current mirror MOSFET JM2. The first current mirror MOSFET JM1 is configured to convert the sampled current into a first sampling current. The drain of the first current mirror MOSFET JM1 is connected to the drain of the second MOSFET JM2, the source of the first current mirror MOSFET JM1 is connected to the source of the second current mirror MOSFET JM2, and the gate of the first current mirror MOSFET JM1 is connected to the gate of the second current mirror MOSFET JM2. One end of the capacitor C1 is connected to a second connection node P2 where the drain of the second current mirror MOSFET JM2 and the gate of the third MOSFET JM3 are interconnected, and the other end of the capacitor C1 is connected to a third connection node P3 where the source of the first current mirror MOSFET JM1 and the source of the first current mirror MOSFET JM1 are interconnected. The third connection node P3 is connected to the power supply node VM. By setting the capacitor C1, the bandwidth of the loop can be further adjusted.

[0045] In some embodiments, the comparison module 32 may further include a second current mirror that converts the first reference current Iref2 into a reference current Iref1. The second current mirror includes a third current mirror MOSFET JM3 and a fourth current mirror MOSFET JM4. The gate of the third current mirror MOSFET JM3 is connected to the gate of the fourth current mirror MOSFET JM4, the source of the third current mirror MOSFET JM3 is connected to the source of the fourth current mirror MOSFET JM4, the drain of the third current mirror MOSFET JM3 is connected to the second connection node P2, and the drain of the fourth current mirror MOSFET JM4 is configured to receive the first reference current Iref2.

[0046] The design of loop stability primarily focuses on high-impedance nodes and nodes with large parasitic capacitances, as these are prone to introducing poles. The drain outputs of JM2 and JM3 are high-impedance nodes, while the gate HS_Gate of power transistors M1 and M2 are nodes with large capacitances. In some embodiments, considering low-power circuit design, JM3 and JM2 have relatively small currents and thus relatively large output impedances. Therefore, node P2 can be designed as the dominant pole of the loop; by introducing capacitor C1 into this node, the dominant pole can be set in the mid-frequency range. With the large capacitance introduced into the gate HS_Gate of power transistors M1 and M2, the pole at node P2 needs to be pushed to a higher frequency. The parasitic capacitance of power transistor M1, together with the low impedance Req, constitutes a high-frequency pole. Thus, by pushing the pole at the gate HS_Gate of the power transistors to a higher frequency, the loop bandwidth is extended to achieve a fast loop response.

[0047] In some embodiments, the drive circuit 100 may further include one or more control nodes to control the startup of corresponding modules of the drive circuit 100. In some embodiments, such as Figure 2 As shown, the gates of the first clamping MOSFET QM1 and the second clamping MOSFET QM2 are connected to a first control node. The first control node can be a logic control node HS_ctrl_B, and the first clamping MOSFET QM1 and the second clamping MOSFET QM2 are turned on or off based on the level of the logic control node HS_ctrl_B.

[0048] In some embodiments, such as Figure 2 As shown, the first current mirror may further include a first control MOSFET CM1. The source of the first control MOSFET CM1 is connected to a third connection node P3, the drain of the first control MOSFET CM1 is connected to the drain of a second MOSFET M2, and the gate of the first control MOSFET CM1 is connected to a second control node. The second control node is a logic control node HS_ctrl, and the first control MOSFET CM1 is turned on or off based on the potential of the second control node.

[0049] In some embodiments, such as Figure 2 As shown, the second current mirror may further include a second control MOS transistor CM2. The gate of the second control MOS transistor CM2 is connected to the third control node HS_ctrl_B. The drain of the second control MOS transistor CM2 is connected to the gate of the fourth current mirror MOS transistor JM4 and the gate of the third current mirror MOS transistor JM3. The second control MOS transistor CM2 is turned on or off based on the potential of the third control node.

[0050] In some embodiments, such as Figure 2 and Figure 3 As shown, the first and third control nodes are connected to the same logic potential, while the second control node is connected to the opposite logic potential. It should be understood that the logic illustrated is exemplary.

[0051] In some embodiments, such as Figure 2 As shown, HS_ctrl controls the on / off state of the drive circuit. When HS_ctrl is high, the drive circuit is on; when HS_ctrl is low, the drive circuit is off. Iref2 is the drive reference current, which can be generated externally or internally within the chip. The drive output current Iout is proportional to Iref2. VM is the high-voltage supply source, and FGND is the floating reference potential. The voltage difference between VM and FGND is low (e.g., not exceeding 5.5V). OUT is the drive output, which varies from GND to VM. ZM1 and ZM2 float in the voltage domain between OUT and the gate of the power transistor.

[0052] exist Figure 2 When the driving circuit shown operates, HS_ctrl_B is low when HS_ctrl is high, CM1 and CM2 are off, and QM1 and QM2 are on. Iref2 is mirrored to JM2 via JM1, serving as the reference current Iref1, and then the drive output current Iout is adjusted through the loop. M1 and M2 have the same gate-source voltage Vgs, and their drain-source voltage Vds differ only from the gate-source voltage of JM1. Considering the channel modulation effect of high-voltage LDMOS, the difference between the drain-source voltages of M1 and M2 is very small. In high-voltage applications of tens of volts, M2 can almost accurately sample the current of M1. It should be understood that the illustrated embodiment is merely exemplary, and the control logic of each node can be implemented in other ways based on different MOS transistors.

[0053] Figure 3 A schematic circuit diagram of a current-type drive circuit 300 according to a third embodiment of the present disclosure is shown. Figure 3 The illustrated embodiments and Figure 2 The illustrated embodiments are similar; the focus is on describing their differences while omitting descriptions of their identical parts. Figure 2 In the illustrated embodiment, power transistors M1 and M2 are both high-voltage MOSFETs (e.g., LDMOS). M1 and M2 are positioned in the loop, therefore their gain significantly impacts the loop performance. In integrated circuit manufacturing processes, the focus is on optimizing the LDMOS to achieve the minimum channel length, primarily for ease of use in voltage-type drive circuits; however, the analog characteristics of the LDMOS transistor are less of a concern. This can lead to unsatisfactory analog characteristics (i.e., proportional characteristics) of M1 and M2 in some cases. Figure 3 In the illustrated embodiment, the high-voltage power transistors M1 and M2 in the loop are replaced with low-voltage MOSFETs (e.g., NMOS or PMOS), which is beneficial for further improving loop performance.

[0054] In some embodiments, such as Figure 3As shown, M1 and M2 are low-voltage MOSFETs, such as NMOS or PMOS. The driving circuit 300 may further include a second voltage clamping module configured to clamp the drain voltage of the first MOSFET M1 and the drain voltage of the second MOSFET M2. The second voltage clamping module includes a third clamping MOSFET QM3, a fourth clamping MOSFET QM4, and a fifth clamping MOSFET QM5. The source of the third clamping MOSFET QM3 is connected to the drain of the second MOSFET M2, the source of the fourth clamping MOSFET QM4 is connected to the drain of the first MOSFET M1, the gate of the third clamping MOSFET QM3 is connected to the gate of the fourth clamping MOSFET QM4, the drain of the fifth clamping MOSFET QM5 is connected to the gates of the third clamping MOSFET QM3 and the fourth clamping MOSFET QM4, and a second bias current Ib1 is applied to the source of the fifth clamping MOSFET QM5.

[0055] According to this disclosure, the third clamping MOSFET QM3, the fourth clamping MOSFET QM4, and the fifth clamping MOSFET QM5 withstand a first voltage, while the first MOSFET M1 and the second MOSFET M2 are configured to withstand a second voltage lower than the first voltage. M1 and M2 are low-voltage MOSFETs with excellent analog characteristics. The output current of M3 adjusts the gate potentials of M1 and M2 across the equivalent impedance Req. QM3, QM4, and QM5 do not affect the loop gain. Therefore, the MOSFETs in loop adjustment are all at low voltage, further ensuring performance.

[0056] In some embodiments, such as Figure 3 As shown, the drive circuit 300 also includes a current limiting module configured to clamp the gate voltage of the third clamping MOSFET QM3 and the gate voltage of the fourth clamping MOSFET QM4. In some embodiments, the current limiting module may include a Zener diode Z1, which clamps the gate voltages of QM3 and QM4 to turn them on. Ib1 is the bias current of Z1. QM5 is, for example, a high-voltage P-type LDMOS transistor used to clamp the low-voltage MOSFET. When the high-side drive is on, QM5 is on; when the high-side drive is off, QM5 is off, there is no current on Z1, and the gate voltages of the power transistors QM3 and QM4 are pulled low.

[0057] According to this disclosure, by nesting a high-voltage LDMOS transistor with a low-voltage MOS transistor, errors introduced by the inaccuracy of the high-voltage LDMOS transistor can be avoided, allowing for better regulation of the drive output current. On the other hand, the drive circuit has a built-in current-limiting function. The gate voltage of QM3 is clamped by Z1, and this voltage is fixed, being the superposition of the gate-source voltage of QM3 and the drain-source voltage of M1. When a short circuit occurs in the OUT or reference current generation circuit, the gate-source voltage Vgs of M1 increases rapidly; if the drive output current is to be increased, the gate-source voltage Vgs of QM3 must increase, which will reduce the drain-source voltage of M1, causing M1 to enter the linear region, and eventually the currents on QM3 and M1 reach a balanced state. Thus, the current-limiting function is achieved. By limiting the maximum output current of the drive circuit, this provides protection for the drive circuit in a short-circuit state, improving the reliability of the drive circuit. On the other hand, low-voltage MOSFETs are used to regulate the output drive current in the loop. Under the same current capability, low-voltage MOSFETs have a smaller area than high-voltage LDMOS, so their gate parasitic capacitance will also be reduced. This allows the secondary point frequency to be set at a higher frequency, further increasing the loop bandwidth and making it more conducive to achieving high-speed response in order to meet the needs of high-frequency applications.

[0058] Furthermore, although the operations are described in a specific order, this should be understood as requiring that such operations be performed in the specific order shown or in sequential order, or requiring that all illustrated operations be performed to achieve the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations.

[0059] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0060] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A current-driven circuit, comprising: The output module (10) includes a first MOSFET (M1) and an output terminal (OUT). The drain of the first MOSFET (M1) is connected to a power node (VM), and the source of the first MOSFET (M1) is connected to the output terminal (OUT). The sampling module (20) includes a second MOS transistor (M2) configured to sample the current flowing through the first MOS transistor (M1), the source of the second MOS transistor (M2) being connected to the output terminal (OUT), and the gate of the second MOS transistor (M2) being connected to the gate of the first MOS transistor (M1). as well as The loop control module (30) includes: The third MOS transistor (M3) has its first terminal connected to the gate of the second MOS transistor (M2) and the gate of the first MOS transistor (M1); as well as The comparison module (32) is configured to compare the current sampled by the second MOS transistor (M2) with the reference current (Iref1) and output the difference to the gate of the third MOS transistor (M3) so that the first MOS transistor (M1) adjusts the output current at the output terminal (OUT) based on the difference. The first MOS transistor (M1), the second MOS transistor (M2), and the third MOS transistor (M3) are configured to operate in a proportional mode.

2. The driving circuit according to claim 1, wherein the driving circuit further comprises a first voltage clamping module (40) configured to clamp the drain voltage of the third MOS transistor (M3); the first voltage clamping module (40) comprises a first clamping MOS transistor (QM1) and a second clamping MOS transistor (QM2). The source of the first clamping MOS transistor (QM1) is connected to the first terminal of the third MOS transistor (M3), and the drain of the first clamping MOS transistor (QM1) is connected to the gate of the second MOS transistor (M2) and the gate of the first MOS transistor (M1). The gate of the first clamping MOSFET (QM1) is connected to the gate of the second clamping MOSFET (QM2), and a first bias current (Ib) is applied to the source of the second clamping MOSFET (QM2). The first clamping MOSFET (QM1) and the second clamping MOSFET (QM2) are configured to withstand a first voltage, and the third MOSFET (M3) is configured to withstand a second voltage lower than the first voltage; The first clamping MOSFET (QM1) and the second clamping MOSFET (QM2) are configured to operate in switching mode.

3. The driving circuit according to claim 2, wherein the gate of the first clamping MOS transistor (QM1) and the gate of the second clamping MOS transistor (QM2) are connected to a first control node to turn the first clamping MOS transistor (QM1) and the second clamping MOS transistor (QM2) on or off based on the potential of the first control node.

4. The driving circuit according to any one of claims 2-3 further includes an impedance attenuation circuit (50), the impedance attenuation circuit (50) being configured to reduce the impedance between the gate of the first MOS transistor (M1) and the source of the first MOS transistor (M1).

5. The driving circuit according to claim 4, wherein the impedance attenuation circuit (50) comprises: The first impedance-degrading MOSFET (ZM1) has its drain connected to the gate of the first MOSFET (M1) and its source connected to the output terminal (OUT). The second impedance-depleting MOSFET (ZM2) has its gate connected to the gate of the first impedance-depleting MOSFET (ZM1), its source connected to the output terminal (OUT), and its drain connected to the drain of the second clamping MOSFET (QM2). as well as A resistor (R1) is connected at one end to the drain of the first impedance-attenuating MOS transistor (ZM1), and at the other end to the first connection node (P1) where the gate of the second impedance-attenuating MOS transistor (ZM2) is connected to the drain of the second impedance-attenuating MOS transistor (ZM2).

6. The driving circuit according to any one of claims 2-3 and 5, wherein the first MOS transistor (M1) and the second MOS transistor (M2) are laterally diffused metal-oxide semiconductors (LDMOS).

7. The driving circuit according to any one of claims 1-3 and 5, wherein the driving circuit further comprises a second voltage clamping module configured to clamp the drain voltage of the first MOSFET (M1) and the drain voltage of the second MOSFET (M2). The second voltage clamping module includes a third clamping MOSFET (QM3), a fourth clamping MOSFET (QM4), and a fifth clamping MOSFET (QM5). The source of the third clamping MOSFET (QM3) is connected to the drain of the second MOSFET (M2), and the source of the fourth clamping MOSFET (QM4) is connected to the drain of the first MOSFET (M1). The gate of the third clamping MOS transistor (QM3) is connected to the gate of the fourth clamping MOS transistor (QM4). The drain of the fifth clamping MOS transistor (QM5) is connected to the gate of the third clamping MOS transistor (QM3) and the gate of the fourth clamping MOS transistor (QM4), and a second bias current (Ib1) is applied to the source of the fifth clamping MOS transistor (QM5). The third clamping MOSFET (QM3), the fourth clamping MOSFET (QM4), and the fifth clamping MOSFET (QM5) withstand a first voltage, and the first MOSFET (M1) and the second MOSFET (M2) are configured to withstand a second voltage lower than the first voltage. The third clamping MOSFET (QM3), the fourth clamping MOSFET (QM4), and the fifth clamping MOSFET (QM5) are configured to operate in switching mode, and the first MOSFET (M1), the second MOSFET (M2), and the third MOSFET (M3) are configured to operate in proportional mode.

8. The driving circuit according to claim 7 further includes a current limiting module, the current limiting module being configured to clamp the gate voltage of the third clamping MOS transistor (QM3) and the gate voltage of the fourth clamping MOS transistor (QM4).

9. The driving circuit according to claim 8, wherein the current limiting module comprises a Zener diode.

10. The driving circuit according to any one of claims 1-3, 5, 8, and 9, wherein the comparison module (32) includes a first current mirror, the first current mirror including a first current mirror MOSFET (JM1) and a second current mirror MOSFET (JM2), the first current mirror MOSFET (JM1) being configured to convert the sampled current into a first sampling current. The drain of the first current mirror MOSFET (JM1) is connected to the drain of the second MOSFET (M2), the source of the first current mirror MOSFET (JM1) is connected to the source of the second current mirror MOSFET (JM2), and the gate of the first current mirror MOSFET (JM1) is connected to the gate of the second current mirror MOSFET (JM2).

11. The driving circuit according to claim 10 further includes a capacitor (C1), one end of which is connected to a second connection node (P2) where the drain of the second current mirror MOSFET (JM2) and the gate of the third MOSFET (M3) are interconnected, and the other end of which is connected to a third connection node (P3) where the source of the first current mirror MOSFET (JM1) and the source of the second current mirror MOSFET (JM2) are interconnected, and the third connection node (P3) is connected to a power supply node (VM).

12. The driving circuit according to claim 11, wherein the first current mirror further includes a first control MOS transistor (CM1), the source of the first control MOS transistor (CM1) is connected to the third connection node (P3), the drain of the first control MOS transistor (CM1) is connected to the drain of the second MOS transistor (M2), and the gate of the first control MOS transistor (CM1) is connected to a second control node to turn the first control MOS transistor (CM1) on or off based on the potential of the second control node.

13. The driving circuit according to claim 12, wherein the comparison module (32) further comprises a second current mirror that converts the first reference current (Iref2) into the reference current (Iref1), the second current mirror comprising a third current mirror MOSFET (JM3) and a fourth current mirror MOSFET (JM4), the gate of the third current mirror MOSFET (JM3) being connected to the gate of the fourth current mirror MOSFET (JM4), the source of the third current mirror MOSFET (JM3) being connected to the source of the fourth current mirror MOSFET (JM4), the drain of the third current mirror MOSFET (JM3) being connected to the second connection node (P2), and the drain of the fourth current mirror MOSFET (JM4) being configured to receive the first reference current (Iref2).

14. The driving circuit according to claim 13, wherein the second current mirror further includes a second control MOS transistor (CM2), the gate of the second control MOS transistor (CM2) is connected to a third control node, and the drain of the second control MOS transistor (CM2) is connected to the gate of the fourth current mirror MOS transistor (JM4) and the gate of the third current mirror MOS transistor (JM3) to turn the second control MOS transistor (CM2) on or off based on the potential of the third control node.

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