Array substrate, display panel and display device

Abstract

The application provides an array substrate, a display panel and a display device. The array substrate comprises a gate drive circuit and a detection signal line. The gate drive circuit comprises a shift register group and a virtual register. The shift register group comprises N shift registers which are connected in cascade. The virtual register is connected in cascade with the Nth shift register. The detection signal line is electrically connected to the output end of the virtual register. In the embodiment of the application, the virtual register can isolate the last row of shift registers from the detection signal line, thereby reducing the load effect of the detection signal line on the output end of the last row of shift registers, reducing the load difference of the last row of shift registers relative to the output end of the other rows of shift registers, thereby reducing the display difference of the last row or several rows of light emitting elements relative to the other rows of light emitting elements, and improving the display uniformity of the display panel.

Description

Technical Field

[0001] This application relates to the field of display device technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] With the development of science and technology, the display panel industry has also made great progress and achieved diversified development. On this basis, people's requirements for display panels are increasing day by day. How to improve the reliability of display panels while meeting performance needs has become one of the research directions of manufacturers. Summary of the Invention

[0003] This application provides an array substrate, a display panel, and a display device, which can improve the reliability of the display panel.

[0004] In a first aspect, embodiments of this application provide an array substrate, which includes a gate driving circuit and a detection signal line. The gate driving circuit includes a shift register group and a virtual register. The shift register group includes N shift registers cascaded together. The virtual register is cascaded to the Nth shift register. The detection signal line is electrically connected to the output terminal of the virtual register.

[0005] Secondly, embodiments of this application provide a display panel, which includes the array substrate and light-emitting element as described in any of the foregoing embodiments.

[0006] Thirdly, embodiments of this application provide a display device, which includes the display panel in any of the foregoing embodiments.

[0007] This application provides an array substrate, a display panel, and a display device. A virtual register is added and cascaded with the Nth shift register, i.e., the virtual register is cascaded with the last row shift register. Furthermore, the detection signal line is not electrically connected to the output of the last row shift register, but rather electrically connected to the output of the virtual register. This virtual register isolates the last row shift register from the detection signal line, thereby reducing the load impact of the detection signal line on the output of the last row shift register. This reduces the load difference between the last row shift register and other row shift registers at the output, thus reducing the display difference between the last row or several rows of light-emitting elements and other rows, and improving the display uniformity of the display panel. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of a partial circuit in an array substrate provided in an embodiment of this application; Figure 2 This is a simplified structural diagram of a local circuit in an array substrate provided in an embodiment of this application; Figure 3a and Figure 3b This is a simplified circuit diagram of two pixel circuits in the array substrate provided in the embodiments of this application; Figure 4 This is a simplified structural diagram of a local circuit in an array substrate provided in another embodiment of this application; Figure 5 This is a simplified structural diagram of a local circuit in an array substrate provided in an embodiment of this application; Figure 6 This is a simplified circuit diagram of a shift register in the first gate drive circuit of an array substrate provided in an embodiment of this application; Figure 7 This is a simplified circuit diagram of a shift register in the fifth gate drive circuit of an array substrate provided in an embodiment of this application; Figure 8 This is a simplified circuit diagram of an electrostatic shielding unit in an array substrate provided in an embodiment of this application; Figure 9 This is a schematic diagram of a partial circuit in an array substrate provided in an embodiment of this application; Figure 10 This is a schematic diagram of a partial circuit in an array substrate provided in an embodiment of this application; Figure 11a and Figure 11b This is a partial cross-sectional structural diagram of the two array substrates provided in the embodiments of this application. Figure 12 This is a partial cross-sectional view of a display panel provided in an embodiment of this application; Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0010] Marker explanation: 100, Array substrate; 200, Display panel; 300, Display device; 10. Gate driver circuit; 11. Shift register; 111. Nth stage shift register; 12. Virtual register; 121. First virtual register; 122. Second virtual register; 123. Third virtual register; 13. First gate driver circuit; 10a. First type gate driver circuit; 10b. Second type gate driver circuit; 10c. Third type gate driver circuit; S. Shift register group; 20. Detection signal line; 21. First trace; 211. First sub-section; 212. Connector; 22. Second trace; 30. Electrode structure; 31. First connecting electrode; 32. Second connecting electrode; 33. First electrode group; 40. Electrostatic shielding unit; 50. Substrate; 60. Pad structure; 61. First pad; 62. Second pad; 70. Circuit board structure; P, pixel circuit; P1, pulse width modulation sub-circuit; P2, amplitude modulation sub-circuit; P3, circuit row; P4, circuit column; P5, Mth circuit row; F, light-emitting element; X, first direction; Y, second direction; Z, thickness direction. Detailed Implementation

[0011] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0012] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0013] Display panels come in various types, with micro-light-emitting display panels gaining widespread attention due to their advantages such as higher brightness and wider color gamut. Micro-light-emitting display panels utilize miniature devices such as micro-light-emitting diodes (Micro LEDs) or sub-millimeter light-emitting diodes (Mini LEDs) as light-emitting elements to achieve light-emitting display functions. Based on this, improving the display reliability of micro-light-emitting display panels has become one of the research directions for many manufacturers.

[0014] Regarding the above issues, firstly, please refer to [link / reference needed]. Figures 1 to 3a and Figure 3b This application provides an array substrate 100, which includes a gate driving circuit 10 and a detection signal line 20. The gate driving circuit 10 includes a shift register group S and a virtual register 12. The shift register group S includes N shift registers 11 cascaded together. The virtual register 12 is cascaded to the Nth shift register 111. The detection signal line 20 is electrically connected to the output terminal of the virtual register 12.

[0015] The array substrate 100 is a key component for the subsequent formation of the display panel 200, which is a device for displaying images. Besides the array substrate 100, the display panel 200 also includes a light-emitting element F, which is the main component for realizing the light-emitting function. In this embodiment, the light-emitting element F can be a micro-light-emitting diode (Micro LED) or a sub-millimeter light-emitting diode (MiniLED), etc. The light-emitting element F can have various structural forms; for example, it can be a flip-chip, a standard-mount chip, or a vertical chip. This embodiment does not limit this. Figure 1 and Figure 2 The light-emitting element F is not shown in the image, but... Figure 3a and Figure 3b The diagram shows the light-emitting element F and the circuit structure used to drive and control the light-emitting element F.

[0016] The array substrate 100 includes pixel circuits P, which are circuit structures used to drive and control whether the light-emitting elements F emit light. There are multiple pixel circuits P, and each pixel circuit P controls a different light-emitting element F to achieve the light-emitting function. The projections of the pixel circuits P and the corresponding light-emitting elements F in the thickness direction Z of the display panel 200 can overlap or be relatively staggered. This embodiment does not impose any restrictions on this.

[0017] The pixel circuit P includes a pulse width modulation sub-circuit P1 and an amplitude modulation sub-circuit P2. The pulse width modulation sub-circuit P1 is configured to control the pulse width of the driving current supplied to the light-emitting element F based on the pulse width modulation data voltage, and the amplitude modulation sub-circuit P2 is configured to control the amplitude of the driving current supplied to the light-emitting element F based on the pulse amplitude modulation data voltage. Here, the pulse width of the driving current can be understood as the duration of the driving current, and the amplitude of the driving current can be understood as the magnitude of the driving current value.

[0018] Specifically, the light-emitting element F includes a first electrode, a second electrode, and a light-emitting part. Under the combined action of the first and second electrodes, the light-emitting part enables the light-emitting display function. The pixel circuit P generates a driving current under the control of the amplitude modulation sub-circuit P2 and the pulse width modulation sub-circuit P1. The amplitude modulation sub-circuit P2 can be used to control the amplitude of the driving current, and the pulse width modulation sub-circuit P1 can be used to adjust the pulse width of the voltage applied to the second electrode of the light-emitting element F. The pulse width modulation sub-circuit P1 adjusts the actual emission period of the driving current applied to the light-emitting element F by adjusting the pulse width of the voltage applied to the second electrode of the light-emitting element F; simultaneously, it can maintain the driving current applied to the light-emitting element F at a constant level to adjust the grayscale or brightness of the display, rather than adjusting the magnitude of the driving current applied to the light-emitting element F. Therefore, the amplitude modulation sub-circuit P2 can provide driving current to the light-emitting element F, enabling it to be driven with optimal luminous efficiency. Furthermore, the pulse width modulation sub-circuit P1 adjusts the emission duty cycle (i.e., the emission period of the light-emitting element F) to regulate the grayscale or brightness displayed by the element. The output of the pulse width modulation sub-circuit P1 can be directly connected to the control terminal of a driving transistor in the amplitude modulation sub-circuit P2, or indirectly controlled via a capacitor structure. In other words, the electrical signal output from the pulse width modulation sub-circuit P1 can be directly written to the control terminal of the driving transistor, or written to the capacitor structure to control the control terminal of the driving transistor, thereby adjusting the amplitude of the driving current.

[0019] Furthermore, the specific circuit configurations of the pulse width modulation sub-circuit P1 and the amplitude modulation sub-circuit P2 are not limited in the embodiments of this application. For example, as shown... Figure 3aAs shown, the pulse width modulation sub-circuit P1 includes a first driving transistor M3, a first gate reset transistor M5, a first data writing transistor M2, a first compensation transistor M4, a first control transistor M1, a second control transistor M6, and a storage capacitor Cst. The first control transistor M1 is connected between the first power supply voltage PWM-vdd and the first terminal of the first driving transistor M3, and the second control transistor M6 is connected between the second terminal of the first driving transistor M3 and the first node N1. The first data writing transistor M2 is connected to the first data signal PWM-data and the first terminal of the first driving transistor M3, the first compensation transistor M4 is connected to the second terminal of the first driving transistor M3 and the control terminal, and the first gate reset transistor M5 is connected to the control terminal of the first driving transistor M3. The first plate of the storage capacitor Cst is connected to the control terminal of the first driving transistor M3, and the second plate of the storage capacitor Cst is connected to the sweep frequency signal SWEEP. The control terminal of the first gate reset transistor M5 receives the first scan signal PWM-S1, and the control terminals of the first data writing transistor M2 and the first compensation transistor M4 receive the second scan signal PWM-S2. The control terminals of the first control transistor M1 and the second control transistor M6 receive the first light-emitting control signal PWM-EM.

[0020] The amplitude modulation sub-circuit P2 includes a second driving transistor M9, a second gate reset transistor M11, a second data writing transistor M8, a second compensation transistor M10, a third control transistor M7, a fourth control transistor M12, and an electrode reset transistor M13. The third control transistor M7 is connected between the second power supply voltage PAM-vdd and the first electrode of the second driving transistor M9. The fourth control transistor M12 is connected between the second electrode of the second driving transistor M9 and the light-emitting element F. The second driving transistor M9 is configured to generate a driving current under the control of its control terminal voltage, i.e., the voltage of the first node N1. The second data writing transistor M8 is connected to the second data signal PAM-data and the first electrode of the second driving transistor M9. The second compensation transistor M10 is connected to the second electrode of the second driving transistor M9 and its control terminal. The second gate reset transistor M11 is connected to the control terminal of the second driving transistor M9. The electrode reset transistor M13 is connected to the second electrode of the light-emitting element F. The fourth control transistor M12 is also connected to the second electrode of the light-emitting element F. The first electrode of the light-emitting element F is connected to the third power supply voltage PVEE. Specifically, the control terminal of the second gate reset transistor M11 receives the third scan signal PAM-S1; the control terminals of the second data write transistor M8, the second compensation transistor M10, and the electrode reset transistor M13 receive the fourth scan signal PAM-S2. The control terminals of the third control transistor M7 and the fourth control transistor M12 receive the second light emission control signal PAM-EM.

[0021] Or such as Figure 3bAs shown, both the amplitude modulation sub-circuit P2 and the pulse width modulation sub-circuit P1 include an initialization unit 111' / 121', a data writing unit 112 / 122', a threshold compensation unit 113 / 123', a light-emitting control unit 114 / 124, storage capacitors C1, C2, and C3, a compensation module 115, an electrode reset module 116, a voltage regulator module 125, and a driving transistor PAM-DR / PWM-DR. The amplitude modulation sub-circuit P2 includes an initialization unit 111', a data writing unit 112, a threshold compensation unit 113, a light-emitting control unit 114, a storage capacitor C2, a voltage regulator module 125, and a driving transistor PAM-DR; the pulse width modulation sub-circuit P1 includes an initialization unit 121', a data writing unit 122', a threshold compensation unit 123', a light-emitting control unit 124, storage capacitors C2 and C3, a compensation module 115, an electrode reset module 116, and a driving transistor PWM-DR. The storage capacitor C3 is located within the compensation module 115, and the compensation module 115 also includes multiple transistor structures.

[0022] Initialization unit 111' / 121' is electrically connected between initialization signal VREF and first node N1 / N2. Initialization unit 111' / 121' is used to provide initialization signal VREF to first node N1 and second node N2 during the initialization phase. (The initialization signal provided by the initialization signal terminal of amplitude modulation sub-circuit P2 can have the same or different value as the initialization signal of pulse width modulation sub-circuit P1.) Figure 3bThe diagram illustrates the case where the initialization signal VREF includes both PAM-REF and PWM-REF. Data writing units 112 / 122' are electrically connected between the data signal PAM-DATA / PWM-DATA and the first terminal of the driving transistor PAM-DR / PWM-DR. The control terminal of the driving transistor PAM-DR / PWM-DR and the first plate of the storage capacitor C2 / C1 are electrically connected to the first node N1 and the second node N2. During the data writing phase, data writing units 112 / 122' provide the data signal PAM-DATA / PWM-DATA to the first node N1 and the second node N2 via the driving transistor PAM-DR / PWM-DR. Threshold compensation units 113 / 123' are electrically connected to the second terminal of the driving transistor PAM-DR / PWM-DR. Threshold compensation units 113 / 123' are used to compensate the threshold voltage of the driving transistor PAM-DR / PWM-DR to the first node N1 and the second node N2. Electrode reset module 116 is electrically connected between the second reset signal PAM-INIT and the second electrode of the light-emitting element F. Electrode reset module 116 provides an initial second reset signal PAM-REF to the second electrode during the initialization phase to reset the second electrode. Compensation module 115 is electrically connected to the second plate of storage capacitor C2 to compensate for voltage drops in the pixel circuit P. Voltage regulator module 125 is electrically connected between the second plate of storage capacitor C1 and the voltage regulator signal SWEEP-GND. Voltage regulator module 125 stabilizes the potential of the second node N2 when the sweep frequency signal SWEEP is not active.

[0023] In addition to the pixel circuit P, the array substrate 100 also includes a gate driving circuit 10 and a detection signal line 20. The gate driving circuit 10 is a circuit structure used to provide corresponding gate control signals to the control terminals of the transistors in the pixel circuit P. Depending on the actual needs, the array substrate 100 can have various types of gate driving circuits 10. For example, multiple gate driving circuits 10 can be used to transmit multiple of the following: a first scan signal PWM-S1, a second scan signal PWM-S2, a third scan signal PAM-S1, a fourth scan signal PAM-S2, a first light emission control signal PWM-EM, a second light emission control signal PAM-EM, and a sweep frequency signal line SWEEP. Depending on the actual needs, at least one of the first light emission control signal PWM-EM, the second light emission control signal PAM-EM, and the sweep frequency signal SWEEP can also be directly driven by directly connecting a driver chip to a specific signal trace. In this case, the multiple gate driving circuits 10 may not include a gate driving circuit 10 for transmitting at least one of the first light emission control signal PWM-EM, the second light emission control signal PAM-EM, and the sweep frequency signal SWEEP.

[0024] The gate drive circuit 10 includes a shift register group S and a virtual register 12. The shift register group S is a circuit structure composed of N cascaded shift registers 11. The shift register 11 is a sequential logic circuit, mainly used for storing and transmitting specific signals. The specific number of N is not limited in this embodiment; N is a positive integer greater than 1. The first-level shift register 11 is the first-row shift register 11, and the Nth-level shift register 111 is the last-row shift register 11.

[0025] The output of shift register 11 is electrically connected to the control terminal of the transistor in pixel circuit P through a specific signal line. Multiple pixel circuits P arranged in a specific direction can jointly form circuit row P3. Depending on the actual needs, the output of a single shift register 11 can be electrically connected only to the control terminal of multiple transistors located in a single circuit row P3, or the output of a single shift register 11 can be electrically connected to the control terminal of multiple transistors located in different circuit rows P3 at the same time. This application embodiment does not limit this.

[0026] The specific positional relationship of the shift register 11 relative to the pixel circuit P is not limited in this embodiment. For example, the shift register 11 can be positioned corresponding to the left or right border of the display panel 200. Alternatively, considering that the array substrate 100 provided in this embodiment is used to form a display panel 200 using micron-sized or sub-millimeter-sized light-emitting diodes as light-emitting elements, the shift register 11 can be positioned between adjacent pixel circuits P to facilitate a near-borderless display effect. Furthermore, the shift register 11 can be positioned between adjacent circuit rows P3, or between adjacent circuit columns P4.

[0027] Similar to shift register 11, virtual register 12 is also a register structure and is used to store and transmit specific signals. However, unlike shift register 11, whose output is electrically connected to the control terminal of the transistor in pixel circuit P via specific signal traces, virtual register 12's output is not electrically connected to the transistor's control terminal. In other words, shift register 11 can provide specific control signals to meet the operational needs of pixel circuit P, while virtual register 12 is not used to meet the operational needs of pixel circuit P.

[0028] It should be noted that a single gate drive circuit 10 will simultaneously contain a shift register 11 and a virtual register 12. The shift register 11 and the virtual register 12 in a single gate drive circuit 10 can employ the same circuit structure or different circuit structures. Similarly, for different gate drive circuits 10, the circuit structures corresponding to different shift registers 11 located in different gate drive circuits 10 can remain the same or different. Likewise, the circuit structures corresponding to different virtual registers 12 located in different gate drive circuits 10 can remain the same or different.

[0029] The detection signal line 20 is a signal trace that enables the detection function of the gate driving circuit 10. Specifically, during the fabrication of the array substrate 100, a motherboard structure is first formed. The motherboard structure includes multiple array regions arranged at intervals. Each array region includes a gate driving circuit 10 and a detection signal line 20. The detection signal line 20 is electrically connected to the gate driving circuit 10 located within the array region and the detection circuit located outside the array region, respectively. Then, the gate driving circuit 10 is detected by the detection circuit. After the detection is completed, the multiple array regions are cut off to form multiple array substrates 100. In this way, the array substrate 100 formed only contains the gate driving circuit 10 and the detection signal line 20, and does not retain the detection circuit, thereby reducing the space occupied by the detection circuit and facilitating a thinner and lighter design.

[0030] In related technologies, the detection signal line 20 is connected to the output terminal of the last row shift register 11 of the gate drive circuit 10. Since the detection signal line 20 itself has a certain resistance, the presence of the detection signal line 20 will increase the load difference between the last row shift register 11 and other row shift registers 11, making the last row shift register 11 more likely to cause display differences between the last row or several rows of light-emitting elements corresponding to the last row shift register 11 and other row light-emitting elements, that is, it is easy to cause the problem of uneven display.

[0031] Therefore, this embodiment adds a virtual register 12 and cascades it to the Nth shift register 11, i.e., the virtual register 12 is cascaded to the last row shift register 11. Based on this, the detection signal line 20 is not electrically connected to the output of the last row shift register 11, but is electrically connected to the output of the virtual register 12. In this way, the virtual register 12 isolates the last row shift register 11 from the detection signal line 20, thereby reducing the load impact of the detection signal line 20 on the output of the last row shift register 11, reducing the load difference between the last row shift register 11 and other row shift registers 11 at the output, thus reducing the display difference of the last row or several rows of light-emitting elements relative to other rows of light-emitting elements, and improving the display uniformity of the display panel 200.

[0032] It should be noted that, depending on the actual needs, the array substrate 100 may or may not include a virtual pixel circuit. The virtual pixel circuit and the pixel circuit P have the same circuit structure, but the difference is that the pixel circuit P can be electrically connected to the light-emitting element to meet the light-emitting display needs of the light-emitting element, while the virtual pixel circuit is not electrically connected to the light-emitting element; that is, the virtual pixel circuit is not used to meet the light-emitting display needs of the light-emitting element. Furthermore, when the array substrate 100 includes a virtual pixel circuit, the output terminal of the virtual register 12 can be electrically connected to the virtual pixel circuit.

[0033] Based on this, considering that the array substrate 100 provided in this application embodiment is used to form a display panel 200 using micron-sized or sub-millimeter-sized light-emitting diodes as light-emitting elements, and that this type of display panel 200 can be designed as a borderless display panel 200, that is, the display panel 200 does not include a border area for setting virtual pixel circuits. Therefore, in some optional embodiments, the array substrate 100 only contains virtual registers 12, and does not contain virtual pixel circuits.

[0034] Furthermore, for multiple gate drive circuits 10, virtual registers 12 may be provided in all gate drive circuits 10, or virtual registers 12 may be provided in only some gate drive circuits 10. This application embodiment does not limit this.

[0035] In some embodiments, such as Figure 1 and Figure 2 As shown, the array substrate 100 further includes M circuit rows P3. The array substrate 100 includes multiple pixel circuits P. The circuit rows P3 include multiple pixel circuits P arranged along a first direction X. The M circuit rows P3 are arranged in a second direction Y. Both the first direction X and the second direction Y are parallel to the plane of the substrate 50 and intersect each other. The Nth stage shift register 111 provides a gate control signal to the Mth circuit row P5. Figure 1 The image shows a pixel circuit P in the Mth circuit row P5.

[0036] The first direction X is the row direction, and the second direction Y is the column direction. Multiple pixel circuits P arranged in the first direction X can form a circuit row P3, and similarly, multiple pixel circuits P arranged in the second direction Y can form a circuit column P4. Taking a square structure of the array substrate 100 as an example, the row direction mentioned here is not limited to the width direction of the array substrate 100, and the column direction is not limited to the length direction of the array substrate 100. The first direction X and the second direction Y only represent two different arrangement directions corresponding to the multiple pixel circuits P. Both the first direction X and the second direction Y are parallel to the plane of the substrate 50, that is, the first direction X and the second direction Y intersect the thickness direction Z of the array substrate 100. Optionally, the first direction X, the second direction Y, and the thickness direction Z of the array substrate 100 are arranged perpendicularly to each other.

[0037] The array substrate 100 includes a total of M circuit rows P3, while the shift register group S includes a total of N cascaded shift registers 11. The relationship between M and N is not limited in this embodiment. For example, M can be greater than N, meaning one row of shift registers 11 can drive multiple circuit rows P3, achieving a one-to-many driving mode. Alternatively, M can be equal to N, meaning one row of shift registers 11 drives only one circuit row P3, achieving a one-to-one driving mode.

[0038] In this embodiment, the Nth-level shift register 111 provides a gate control signal to the Mth circuit row P5, that is, the last-row shift register 11 transmits the corresponding gate control signal to the last-row circuit row P5. Furthermore, each circuit row P3 can receive the gate control signal transmitted from the shift register 11, and does not need to receive the signal output from the virtual register 12. This reduces the impact of the virtual register 12's output signal on the display effect and helps improve display uniformity.

[0039] In some embodiments, please refer to Figure 2 and Figure 4 In the second direction Y, the shift register 11 is located between adjacent circuit rows P3; or, the array substrate 100 includes a plurality of circuit columns P4, each circuit column P4 including a plurality of pixel circuits P arranged along the second direction Y, and in the first direction X, the shift register 11 is located between adjacent circuit columns P4.

[0040] Taking shift register 11 located between adjacent circuit rows P3 as an example, depending on the actual needs, there can be only one shift register 11 between adjacent circuit rows P3, or there can be multiple shift registers 11. Here, "multiple shift registers 11" can refer to shift registers 11 located in the same gate drive circuit 10, or to shift registers 11 located in different gate drive circuits 10. Furthermore, for shift registers 11 located in the same gate drive circuit 10 but between different circuit rows P3, there can be only one circuit row P3 between adjacent shift registers 11, or there can be multiple circuit rows P3 simultaneously. This embodiment does not impose any restrictions on this, and the same applies to the case where shift register 11 is located in adjacent circuit column P4. Figure 2 The diagram illustrates a scenario where only one shift register 11 is located between adjacent circuit rows P3 within a single gate drive circuit 10. Figure 4 This illustrates a scenario where each shift register in a single gate drive circuit 10 is positioned between adjacent circuit columns P4.

[0041] In this embodiment, the shift register 11 is not located on the same side of all pixel circuits P, but rather between some adjacent pixel circuits P. The area where the pixel circuits P are located typically corresponds to the light-emitting area of ​​the display panel 200. Therefore, in this embodiment, the shift register 11 is integrated within the light-emitting area of ​​the display panel 200. This design helps to achieve a borderless display effect and improves the user experience. Furthermore, the shift register 11 can be positioned between adjacent circuit rows P3, or it can be positioned between adjacent circuit columns P4, thus meeting the actual layout needs of different display panels 200, demonstrating strong practicality and flexibility.

[0042] The specific positional relationship of the virtual register 12 relative to the pixel circuit P is not limited in this embodiment. The virtual register 12 can be located on the same side of all pixel circuits P, or it can be located between some adjacent circuit rows P3, or it can be located between adjacent circuit columns P4, as long as the virtual register 12 can be cascaded to the last row shift register 11, and the output of the virtual register 12 does not transmit gate control signals to any circuit row P3.

[0043] In some embodiments, such as Figure 1 and Figure 2 As shown, in the second direction Y, shift register 11 is located between adjacent circuit rows P3, and the Mth circuit row P5 is located between the Nth shift register 111 and the virtual register 12.

[0044] Based on the foregoing, the array substrate 100 has a total of M circuit rows P3, and the Mth circuit row P5 is the last circuit row P5; and the shift register group S includes N cascaded shift registers 11, and the Nth shift register 111 is the last shift register 11.

[0045] Based on this, the Mth circuit row P5 is located between the Nth level shift register 111 and the virtual register 12. This means that the last circuit row P5 is located between the last shift register 11 and the virtual register 12, the last shift register 11 is located between adjacent circuit rows P3, and the virtual register 12 is located on the same side of all circuit rows P3. The last shift register 11 can be located between the last circuit row P5 and the second-to-last circuit row P3, or it can be located between any two adjacent circuit rows P3 other than the last circuit row P5. This embodiment does not limit this, as long as the last circuit row P5 is located between the last shift register 11 and the virtual register 12, and the last shift register 11 is located between adjacent circuit rows P3. Figure 1 The diagram shows the position of shift register 11 between the last circuit line P5 and the second-to-last circuit line P3.

[0046] In this embodiment, since the virtual register 12 is located on the same side of all circuit rows P3, the detection signal line 20, which is electrically connected to the output of the virtual register 12, is also located on the same side of all circuit rows P3. In this case, the detection signal line 20 will not overlap with the pixel circuit P in the thickness direction Z of the array substrate 100, which helps to reduce the risk of parasitic capacitance between the detection signal line 20 and some conductor structures in the pixel circuit P, and improves the operational reliability of the pixel circuit P.

[0047] In some embodiments, please refer to Figure 1 , Figure 2 as well as Figure 5 The array substrate 100 also includes a plurality of electrode structures 30. Each electrode structure 30 includes a first connecting electrode 31 and a second connecting electrode 32 that are insulated from each other. The second connecting electrode 32 is connected to the pixel circuit P. The plurality of electrode structures 30 includes a first electrode group 33 connected to the Mth circuit row P5. In the second direction Y, the virtual register 12 is located between the first electrode group 33 and the Mth circuit row P5.

[0048] The light-emitting element includes a first electrode, a second electrode, and a light-emitting portion. Under the combined action of the first electrode and the second electrode, the light-emitting portion can realize the light-emitting display function. The electrode structure 30 is a structure in the array substrate 100 used to connect and fix the two electrodes in the light-emitting element. The first connecting electrode 31 is a structure in the electrode structure 30 used to bond to the first electrode, and the second connecting electrode 32 is a structure in the electrode structure 30 used to bond to the second electrode.

[0049] To meet the control requirements of the light-emitting element, the second connecting electrode 32 needs to be connected to the pixel circuit P, while the first connecting electrode 31 needs to transmit the second power signal PVEE. Furthermore, the first connecting electrode 31 and the second connecting electrode 32 in the same electrode structure 30 are insulated from each other. For different electrode structures 30, each electrode structure 30 includes a first connecting electrode 31 and a second connecting electrode 32, and different electrode structures 30 are respectively configured for different light-emitting elements. That is, in the thickness direction Z of the array substrate 100, the projection of the light-emitting element overlaps with the projection of the corresponding electrode structure 30.

[0050] It should be noted that, in order to meet the independent control requirements of different light-emitting elements, the second connecting electrodes 32 in different electrode structures 30 need to be insulated from each other, while the first connecting electrodes 31 in different electrode structures 30 can be connected as a whole or insulated from each other. Optionally, at least some of the first connecting electrodes 31 in different electrode structures 30 are connected as a whole.

[0051] The first electrode group 33 is a single electrode row composed of multiple electrode structures 30 arranged along the first direction X. The second connecting electrode 32 of each of the multiple electrode structures 30 within the first electrode group 33 can be electrically connected to multiple pixel circuits P in the last row circuit row P5, respectively, to meet the control requirements of multiple light-emitting elements corresponding to the last row circuit row P5. Typically, the last row circuit row P5 controls the last row of light-emitting elements. Therefore, the first electrode group 33 is the last row electrode structure 30, and the multiple light-emitting elements connected to the first electrode group 33 are the last row of light-emitting elements. Figure 1 The image shows three adjacent electrode structures 30 located in the first electrode group 33, but this does not indicate that the first electrode group 33 includes only three electrode structures 30. Furthermore, Figure 1 The light-emitting elements corresponding to the three electrode structures 30 can be combined to form a repeating unit, and multiple repeating units are arranged repeatedly along the first direction X and the second direction Y.

[0052] In this embodiment, the projections of the first electrode group 33 and the last row of circuit P5 onto the array substrate 100 in the thickness direction Z are not overlapping. Instead, the first electrode group 33 is located along the second direction Y on the side of the last row of circuit P5 that is away from other circuit rows P3. Based on this, considering that the projections of the first electrode group 33 and the corresponding last row of light-emitting elements onto the array substrate 100 are usually overlapping, the projections of the last row of light-emitting elements and the last row of circuit P5 onto the array substrate 100 in the thickness direction Z will also not overlap.

[0053] Therefore, the virtual register 12 is located between the first electrode group 33 and the Mth circuit row P5 along the second direction Y. This means that the virtual register 12 will be located between the last row of light-emitting elements and the last row of circuit row P5. The last row of circuit row P5 is located on the side of the last row of light-emitting elements facing other light-emitting elements. Therefore, the virtual register 12 will be located between adjacent rows of light-emitting elements, rather than on the same side of all light-emitting elements. In other words, the virtual register 12 will be integrated into the light-emitting area of ​​the display panel 200, rather than in the border area. This helps to eliminate the border area of ​​the display panel 200 and achieve a borderless effect.

[0054] It should be noted that the positional relationship of different rows of light-emitting elements relative to the virtual register 12 is not limited in this embodiment. For example, the side of the virtual register 12 furthest from the last row of circuit line P5 may only have the last row of light-emitting elements, or it may have the second-to-last row of light-emitting elements or even more rows of light-emitting elements. Similarly, the area between the virtual register 12 and the last row of circuit line P5 may have light-emitting elements, or it may not have any light-emitting elements. Furthermore, the projection of the virtual register 12 in the thickness direction Z of the array substrate 100 may overlap with the projections of the electrode structure 30 and the corresponding light-emitting elements, or it may not overlap with the light-emitting elements.

[0055] Regarding the positional relationship between the last row of light-emitting elements and the detection signal line 20, this embodiment does not impose any restrictions. The orthographic projection of the last row of light-emitting elements on the array substrate 100 may overlap with the detection signal line 20, or they may not overlap.

[0056] Furthermore, although the last row of circuits P5 is not positioned corresponding to the last row of light-emitting elements, the positions of other row circuits P3 and their corresponding light-emitting elements can overlap, or they can be non-overlapping; this embodiment does not impose any limitations on this. Optionally, the distance between adjacent row light-emitting elements in the second direction Y is kept the same or similar, the distance between adjacent circuit rows P3 in the second direction Y is kept the same or similar, and the distance between adjacent row light-emitting elements is greater than the distance between adjacent circuit rows P3, thereby helping to improve the display uniformity of the display panel 200. At the same time, the light-emitting area of ​​the display panel 200 can cover and extend beyond the area where all pixel circuits P are located. Thus, in a portion of the area outside the pixel circuit P but within the light-emitting area, device structures or signal traces, such as virtual register 12, can be arranged, thereby eliminating or reducing the border area of ​​the display panel 200 and achieving a borderless display effect.

[0057] In summary, this embodiment adjusts the position of the first electrode group 33 corresponding to the last row of circuit line P5, so that it is not projected to overlap with the last row of circuit line P5, but is located on one side of the last row of circuit line P5 along the second direction Y, and the virtual register 12 is located between the first electrode group 33 and the last row of circuit line P5. Since the position of the first electrode group 33 usually corresponds to the position of the last row of light-emitting elements, under this design, the virtual register 12 can be located on the side of the last row of light-emitting elements facing other row light-emitting elements, that is, the virtual register 12 can be located within the light-emitting area of ​​the display panel 200, thereby eliminating or reducing the border area of ​​the display panel 200, achieving a borderless display effect, and improving the user experience of the display panel 200.

[0058] In some embodiments, N=M, that is, the number of shift registers 11 cascaded in the shift register group S is equal to the number of circuit rows P3 in the array substrate 100. Based on this, each shift register 11 can transmit gate control signals to the corresponding single circuit row P3 to realize a one-to-one driving mode.

[0059] In this embodiment, considering that the array substrate 100 can be used to form a borderless display panel 200, and the borderless setting means that it is impossible to set a virtual circuit row P3 including virtual pixel circuit P, by setting the shift register 11 and the circuit row P3 in a one-to-one manner, it is possible to keep the number of circuit rows P3 driven by the last row shift register 11 consistent with the number of circuit rows P3 driven by the other row shift registers 11 without adding additional virtual circuit rows P3. This helps to reduce the display difference between the last row light-emitting elements and the other row light-emitting elements and improve display uniformity.

[0060] In some embodiments, N < M.

[0061] In this embodiment, the number of shift registers 11 cascaded in the shift register group S can also be less than the number of circuit rows P3 in the array substrate 100, thereby realizing a one-to-many driving mode. This helps to reduce the overall number of shift registers 11 in the array substrate 100 and reduce the layout difficulty of signal traces and device structures in the array substrate 100.

[0062] In some embodiments, the circuit structures of the virtual registers 12 in at least some of the different gate drive circuits 10 are different; and / or, the circuit structures of the virtual registers 12 in at least some of the gate drive circuits 10 are consistent.

[0063] The phrase "maintaining consistent circuit structure" refers to the fact that the number and types of components, such as transistors and capacitors, included in different virtual registers 12, as well as the connection methods between these components, remain the same, regardless of the size and shape of the different virtual registers 12. In other words, the dimensions of different virtual registers 12 in the first direction X or the second direction Y can be the same or different. Similarly, the phrase "different circuit structures" refers to the fact that at least one of the following—the number and types of components, such as transistors and capacitors, included in different virtual registers 12, as well as the connection methods between these components—may differ, regardless of the size and shape of the different virtual registers 12.

[0064] Depending on the specific needs, the circuit structures of the virtual registers 12 in each of the different gate drive circuits 10 can be different, or they can all be the same. Alternatively, the circuit structures of the virtual registers 12 in some of the different gate drive circuits 10 can be the same, while the circuit structures of the virtual registers 12 in some of the different gate drive circuits 10 can be different.

[0065] As can be seen from the foregoing, unlike shift register 11, the output of virtual register 12 is not electrically connected to the control terminal of the transistor in pixel circuit P. That is, shift register 11 is used to drive pixel circuit P, while virtual register 12 is not used to drive pixel circuit P. In other words, virtual register 12 does not play the same role as shift register 11 in output gate control signal. Therefore, the circuit structure of virtual register 12 can be flexibly adjusted or changed according to different actual needs.

[0066] Based on this, in the embodiments of this application, the circuit structure of the virtual register 12 in at least some different gate drive circuits 10 can be set differently, or the circuit structure of the virtual register 12 in at least some gate drive circuits 10 can be set to be the same, so as to meet the layout needs of different situations, and has strong flexibility and practicality.

[0067] In some embodiments, in a single gate drive circuit 10, the circuit structure in the virtual register 12 is consistent with the circuit structure in the shift register 11.

[0068] In this embodiment, by setting the circuit structure of the virtual register 12 in a single gate drive circuit 10 to be consistent with that of the shift register 11, the design difficulty of the virtual register 12 is reduced, and the structural load of the virtual register 12 in the single gate drive circuit 10 is the same as that of the shift register 11. The "structural load of the virtual register 12" mentioned here refers to the load value corresponding to the structure of the virtual register 12 itself, not the load value corresponding to other structures connected to the output of the virtual register 12. The structural load of the shift register 11 is similar.

[0069] Based on this, since the output of the last row shift register 11 is electrically connected to the virtual register 12 in a single gate drive circuit 10, while the outputs of other row shift registers 11 are electrically connected to the shift register 11, this design helps to reduce the load difference at the output of the last row shift register 11 relative to other row shift registers 11, thereby reducing the display difference of the last row or several rows of light-emitting elements relative to other rows of light-emitting elements and improving the display uniformity of the display panel 200.

[0070] It should be noted that for different gate drive circuits 10, the circuit structure of the shift register 11 included therein can be consistent or different. Based on this, whether the circuit structure of the corresponding virtual register 12 in different gate drive circuits 10 is the same depends on whether the circuit structure of the shift register 11 in different gate drive circuits 10 is the same, and this application embodiment does not impose any limitations.

[0071] Furthermore, in a single gate drive circuit 10, although the virtual register 12 has the same circuit structure as the shift register 11, the corresponding space occupied by the two can be the same or different. For example, the size of the virtual register 12 in the first direction X can be greater than, less than or equal to the size of the shift register 11 in the first direction X, and the size of the virtual register 12 in the second direction Y can also be greater than, less than or equal to the size of the shift register 11 in the second direction Y.

[0072] In some embodiments, such as Figure 1 and Figure 2 As shown, in a single gate drive circuit 10, the virtual register 12 and the shift register 11 have the same size in the first direction X; and / or, in a single gate drive circuit 10, the virtual register 12 and the shift register 11 have the same size in the second direction Y.

[0073] In the embodiments of this application, the virtual register 12 and the shift register 11 in a single gate drive circuit 10 can not only have the same circuit structure, but also have the same size in at least one of the first direction X and the second direction Y. This helps to further improve the consistency between the virtual register 12 and the shift register 11 in a single gate drive circuit 10 and reduce the design difficulty of the virtual register 12.

[0074] Alternatively, in a single gate drive circuit 10, the positional relationship of the virtual register 12 relative to the last row shift register 11 is the same as the positional relationship of the last row shift register 11 relative to the penultimate row shift register 11. This allows the multiple shift registers 11 and virtual registers 12 in a single gate drive circuit 10 to be arranged in a consistent and uniform manner, thereby helping to reduce the difficulty of layout of device structures and signal traces inside the array substrate 100.

[0075] In some embodiments, the plurality of gate driving circuits 10 include a first type of gate driving circuit 10a and a second type of gate driving circuit 10b. The first type of gate driving circuit 10a is used to control the writing of data signals into the pixel circuit P, and the second type of gate driving circuit 10b is used to control the writing of reset signals into the pixel circuit P. At least one of the first type of gate driving circuit 10a and the second type of gate driving circuit 10b includes a virtual register 12.

[0076] The first type of gate driving circuit 10a is a circuit structure that controls the writing of data signals into the pixel circuit P, while the second type of gate driving circuit 10b is a circuit structure that controls the writing of reset signals into the pixel circuit P. The data signals include a first data signal PWM-data and a second data signal PAM-data, and the reset signals include a first reset signal PWM-REF and a second reset signal PAM-REF.

[0077] Based on this, combined Figure 3a For example, the first type of gate drive circuit 10a may include two types of gate drive circuits 10, one of which is used to transmit the second scan signal PWM-S2 to the control terminal of the first data writing transistor M2, and the other is used to output the fourth scan signal PAM-S2 to the control terminal of the second data writing transistor M8. Similarly, the second type of gate drive circuit 10b may include two types of gate drive circuits 10, one of which is used to transmit the first scan signal PWM-S1 to the control terminal of the first gate reset transistor M5, and the other is used to output the third scan signal PAM-S3 to the control terminal of the second gate reset transistor M11.

[0078] In this embodiment of the application, considering that the array substrate 100 includes various types of gate driving circuits 10, the virtual register 12 can be set only in a specific type of gate driving circuit 10, or it can be set in all gate driving circuits 10. It can be flexibly adjusted according to the actual layout needs, and has strong practicality and flexibility.

[0079] For example, the first type of gate driving circuit 10a is used to control the writing of data signals into the pixel circuit P. The first type of gate driving circuit 10a is the gate driving circuit 10 that has the greatest impact on brightness. Therefore, a virtual register 12 can be provided only in the first type of gate driving circuit 10a to improve the light emission brightness and light emission accuracy of the display panel 200. At the same time, the virtual register 12 can be omitted in the second type of gate driving circuit 10b. In this way, other signal traces or device structures can be set in the area below the second type of gate driving circuit 10b to reduce the layout pressure of the array substrate 100.

[0080] Of course, in other embodiments, the virtual register 12 may be provided only in the second type of gate driving circuit 10b, while the virtual register 12 may not be provided in the first type of gate driving circuit 10a, or the virtual register 12 may be provided in both the first type of gate driving circuit 10a and the second type of gate driving circuit 10b.

[0081] In some embodiments, the pixel circuit P includes an amplitude modulation sub-circuit P2 and a pulse width modulation sub-circuit P1. The first type of gate driving circuit 10a includes a first gate driving circuit and a second gate driving circuit, and the second type of gate driving circuit 10b includes a third gate driving circuit and a fourth gate driving circuit. The first gate driving circuit is used to control the first data signal PWM-data to be written into the pulse width modulation sub-circuit P1, the second gate driving circuit is used to control the second data signal PAM-data to be written into the amplitude modulation sub-circuit P2, the third gate driving circuit is used to control the first reset signal PWM-REF to be written into the pulse width modulation sub-circuit P1, and the fourth gate driving circuit is used to control the second reset signal PAM-REF to be written into the amplitude modulation sub-circuit P2.

[0082] Combination Figure 3a Specifically, the output of the first gate drive circuit can transmit the second scan signal PWM-S2 to the control terminal of the first data write transistor M2 via signal traces, so that the first data write transistor M2 is turned on, thereby controlling the first data signal PWM-data to be written to the pulse width modulation sub-circuit P1. Similarly, the output of the second gate drive circuit can transmit the fourth scan signal PAM-S2 to the control terminal of the second data write transistor M8 via signal traces, so that the second data write transistor M8 is turned on, thereby controlling the second data signal PAM-data to be written to the amplitude modulation sub-circuit P2.

[0083] The output of the third gate drive circuit can transmit the first scan signal PWM-S1 to the control terminal of the first gate reset transistor M5 via a signal trace, so that the first gate reset transistor M5 is in the open state, thereby controlling the first reset signal PWM-REF to be written into the pulse width modulation sub-circuit P1. The output of the fourth gate drive circuit can transmit the third scan signal PAM-S1 to the control terminal of the second gate reset transistor M11 via a signal trace, so that the second gate reset transistor M11 is in the open state, thereby controlling the second reset signal PAM-REF to be written into the amplitude modulation sub-circuit P2.

[0084] Furthermore, in the embodiments of this application, a virtual register 12 can be selectively provided in one or more of the first gate driving circuit, the second gate driving circuit, the third gate driving circuit, and the fourth gate driving circuit, thereby improving the reliability of the output signal of the last row shift register 11 in the corresponding gate driving circuit 10, and having strong practicality and flexibility.

[0085] In some embodiments, please refer to Figure 5 and Figure 6 The first type of gate driving circuit 10a includes a first virtual register 121, and the second type of gate driving circuit 10b includes a second virtual register 122. The circuit structures in the first virtual register 121 and the second virtual register 122 are consistent.

[0086] The scanning signals in the pixel circuit P include a first scanning signal PWM-S1, a second scanning signal PWM-S2, a third scanning signal PAM-S1, and a fourth scanning signal PAM-S2. For these four types of scanning signals, the circuit structure of the shift register 11 in the corresponding gate driving circuit 10 can be kept consistent. In other words, the first gate driving circuit, the second gate driving circuit, the third gate driving circuit, and the fourth gate driving circuit all include shift registers 11 with the same circuit structure.

[0087] The following embodiments of this application will describe the structure of the shift register 11 in the first gate driving circuit with reference to the accompanying drawings. The shift register 11 in the second, third, and fourth gate driving circuits can adopt the same structure, and will not be described again in this application.

[0088] like Figure 6As shown, the shift register 11 includes a first output module K1, a second output module K2, a first control module K3, and a second control module K4. The first output module K1 is connected between the second clock terminal XCKS and the shift output terminal GOUT. The control terminal of the first output module K1 is connected to a third node N3, and the potential of the third node N3 controls the on / off state of the first output module K1. The first output module K1 includes a transistor T8 and a capacitor C4. The control terminal of transistor T8 is connected to the third node N3, and its first and second terminals are respectively connected to the second clock terminal XCKS and the shift output terminal GOUT. The two plates of capacitor C4 are also connected to the second clock terminal XCKS and the shift output terminal GOUT.

[0089] The second output module K2 is connected between the first power supply terminal VGH and the shift output terminal GOUT. The control terminal of the second output module K2 is connected to the fourth node N4, and the potential of the fourth node N4 controls the on / off state of the second output module K2. The second output module K1 includes a transistor T7 and a capacitor C5. The control terminal of transistor T7 is connected to the fourth node N4, and its first and second terminals are connected to the first power supply terminal VGH and the shift output terminal GOUT, respectively. The two plates of capacitor C5 are also connected to the first power supply terminal VGH and the shift output terminal GOUT, respectively.

[0090] The first control module K3 is connected to the third node N3 and is used to control the on / off state of the first output module K1. The first control module K3 includes transistors T1, T4, T5, and T6. The control terminal of transistor T1 is connected to the first clock terminal CKS, and its first and second terminals are connected to the input terminal STVS and the fifth node N5, respectively. The control terminal of transistor T4 is connected to the second clock terminal XCKS, and its first and second terminals are connected to the fifth node N5 and transistor T5, respectively. The control terminal of transistor T5 is connected to the fourth node N4, and its first and second terminals are connected to transistor T4 and the first power supply terminal VGH, respectively. The control terminal of transistor T6 is connected to the second power supply terminal VGL, and its first and second terminals are connected to the fifth node N5 and the third node N3, respectively. The first power supply terminal VGH is a low-voltage terminal, the second power supply terminal VGL is a high-voltage terminal, and the input terminal STVS is connected to the output terminal GOUT of the previous stage shift register 11.

[0091] The second control module K4 is connected to the fourth node N4 and is used to control the on / off state of the second output module K2. The second control module K4 includes transistors T2 and T3. The control terminal of transistor T2 is connected to the fifth node N5, and its first and second terminals are connected to the first clock terminal CKS and the fourth node N4, respectively. The control terminal of transistor T3 is connected to the first clock terminal CKS, and its first and second terminals are connected to the second power supply terminal VGL and the fourth node N4, respectively.

[0092] It should be noted that the above content is only one structural form of the shift register 11 in the first gate drive circuit, and it does not constitute a limitation on the circuit structure of the shift register 11. Depending on the actual needs, the shift register 11 can also adopt other circuit structure forms. For example, in some other embodiments, the shift register 11 also includes a first output module K1, a second output module K2, a first control module K3, and a second control module K4. However, the first output module K1 is no longer connected to the second clock terminal XCKS, but to the second power supply terminal VGL. Of course, the corresponding circuit structures of the first control module K3 and the second control module K4 also need to be adjusted at this time. This application embodiment does not limit this.

[0093] Based on this, considering that the circuit structures of the shift register 11 and the virtual register 12 can be kept consistent in a single gate drive circuit 10, when the first type of gate drive circuit 10a includes a first virtual register 121, the first virtual register 121 can be kept consistent with the circuit structure of the shift register 11 in the first type of gate drive circuit 10a. When the second type of gate drive circuit 10b includes a second virtual register 122, the second virtual register 122 can be kept consistent with the circuit structure of the shift register 11 in the second type of gate drive circuit 10b.

[0094] Furthermore, since the shift register 11 in the first type of gate driving circuit 10a and the shift register 11 in the second type of gate driving circuit 10b can have the same circuit structure, it is also possible to set the circuit structure of the first virtual register 121 and the second virtual register 122 to be consistent, which helps to further reduce the design difficulty of the virtual register 12 and improve the layout reliability of the internal structure of the array substrate 100.

[0095] It should be noted that, for the first type of gate driving circuit 10a, the first virtual register 121 may be provided only in the first gate driving circuit, or only in the second gate driving circuit, or simultaneously in both the first and second gate driving circuits. Similarly, for the second type of gate driving circuit 10b, the second virtual register 122 may be provided only in the third gate driving circuit, or only in the fourth gate driving circuit, or simultaneously in both the third and fourth gate driving circuits.

[0096] In some embodiments, please refer to Figures 5 to 7The multiple gate driving circuits 10 also include a third type of gate driving circuit 10c, which is used to output a light emission control signal or a sweep frequency signal SWEEP. The first type of gate driving circuit 10a includes a first virtual register 121, and the third type of gate driving circuit 10c includes a third virtual register 123. The circuit structures of the first virtual register 121 and the third virtual register 123 are different.

[0097] Combination Figure 3a The light emission signal includes a first light emission control signal PWM-EM and a second light emission control signal PAM-EM. The third type of gate driving circuit 10c may include at least one of a fifth gate driving circuit, a sixth gate driving circuit, and a seventh gate driving circuit. The fifth gate driving circuit is used to transmit the first light emission control signal PWM-EM to the control terminals of the first control transistor M1 and the second control transistor M6. The sixth gate driving circuit is used to transmit the second light emission control signal PAM-EM to the control terminals of the third control transistor M7 and the fourth control transistor M12. The seventh gate driving circuit is used to transmit the sweep frequency signal SWEEP to the second plate of the storage capacitor Cst.

[0098] It should be noted that, depending on the actual needs, the third type of gate drive circuit 10c may simultaneously include a fifth gate drive circuit, a sixth gate drive circuit, and a seventh gate drive circuit, or one or two gate drive circuits 10 may be omitted. For example, the third type of gate drive circuit 10c includes a fifth gate drive circuit and a sixth gate drive circuit, but does not include a seventh gate drive circuit. In this case, the sweep frequency signal SWEEP can be directly driven and transmitted by directly connecting to the driver chip via signal traces.

[0099] For ease of description, this application will use a third type of gate drive circuit 10c, including a fifth gate drive circuit, as an example. Figure 7As shown, in the fifth gate drive circuit, the control terminal of transistor T1' is connected to the first clock terminal CKS, the first terminal of transistor T1' is connected to the frame start signal line STV, and the second terminal of transistor T1' is connected to node N1'. The control terminal of transistor T2' is connected to node N1', the first terminal of transistor T2' is connected to the first clock terminal CKS, and the second terminal of transistor T2' is connected to node N2'. The control terminal of transistor T3' is connected to the first clock terminal CKS, the first terminal of transistor T3' is connected to the second power supply terminal VGL, and the second terminal of transistor T3' is connected to node N2'. The control terminal of transistor T4' is connected to node N9', the first terminal of transistor T4' is connected to the second clock terminal XCKS, and the second terminal of transistor T4' is connected to node N5'. The control terminal of transistor T5' is connected to node N2', the first terminal of transistor T5' is connected to the first power supply terminal VGH, and the second terminal of transistor T5' is connected to node N5'.

[0100] The control terminal of the sixth transistor T6' is connected to node N6', the first terminal of transistor T6' is connected to the second clock terminal XCKS, and the second terminal of transistor T6' is connected to node N3'. The control terminal of transistor T7' is connected to the second clock terminal XCKS, the first terminal of transistor T7' is connected to node N3', and the second terminal of transistor T7' is connected to node N4'. The control terminal of transistor T8' is connected to node N1, the first terminal of transistor T8' is connected to the first power supply terminal VGH, and the second terminal of transistor T8' is connected to node N4'. The control terminal of transistor T9' is connected to node N4', the first terminal of transistor T9' is connected to the first power supply terminal VGH, and the second terminal of transistor T9' is connected to the shift output terminal GOUT. The control terminal of transistor T10' is connected to node N7', the first terminal of transistor T10' is connected to the second power supply terminal VGL, and the second terminal of transistor T10' is connected to the shift output terminal GOUT.

[0101] The control terminal of transistor T11' is connected to the second power supply terminal VGL, the first terminal of transistor T11' is connected to node N2', and the second terminal of transistor T11' is connected to node N6'. The control terminal of transistor T12' is connected to the second power supply terminal VGL, the first terminal of transistor T12' is connected to node N1', and the second terminal of transistor T12' is connected to node N7. The control terminal of transistor T13' is connected to the reset terminal RESET, the first terminal of transistor T13' is connected to the first power supply terminal VGH, and the second terminal of transistor T13' is connected to node N1'. The control terminal of transistor T14' is connected to the first clock terminal CKS, the first terminal of transistor T14' is connected to the frame start signal line STV, and the second terminal of transistor T14' is connected to node N8'. The control terminal of transistor T15' is connected to the second power supply terminal VGL, the first terminal of transistor T15' is connected to node N8', and the second terminal of transistor T15' is connected to node N9'. The control terminal of transistor T16' is connected to node N9'. The first terminal of transistor T16' is connected to node N7', and the second terminal of transistor T16' is connected to node N9'.

[0102] The first plate of capacitor C1' is connected to node N6', and the second plate is connected to node N3'. The first plate of capacitor C2' is connected to node N4', and the second plate is connected to the first power supply terminal VGH. The first plate of capacitor C3' is connected to node N5', and the second plate is connected to node N9'.

[0103] It should be noted that the above content is only one structural form of the shift register 11 in the fifth gate drive circuit, and it does not constitute a limitation on the circuit structure of the shift register 11. Depending on the actual needs, the shift register 11 can also adopt other circuit structures. Furthermore, through comparison... Figure 6 and Figure 7 It can be seen that the circuit structure of the shift register 11 located in the first type of gate drive circuit 10a in the array substrate 100 is usually designed differently from the circuit structure of the shift register 11 located in the third type of gate drive circuit 10c.

[0104] Based on this, in this embodiment of the application, the first virtual register 121 corresponding to the first type of gate driving circuit 10a is set to be different from the second virtual register 122 corresponding to the third type of gate driving circuit 10c, so that the circuit structure of the first virtual register 121 can be consistent with the cascaded shift register 11, and the circuit structure of the second virtual register 122 can be consistent with the cascaded shift register 11, thereby further improving the structural matching between the virtual register 12 and the shift register 11 in a single gate driving circuit 10, which helps to reduce the design and fabrication difficulty of the array substrate 100.

[0105] In some embodiments, such as Figure 5 As shown, the array substrate 100 also includes an electrostatic shielding unit 40, and the output terminal of the virtual register 12 is electrically connected to the detection signal line 20 through the electrostatic shielding unit 40.

[0106] The electrostatic shielding unit 40 is a circuit structure used to reduce electrostatic damage to the gate drive circuit 10. During the use of the display panel 200, the electrostatic shielding unit 40 can detect the voltage peak received from the gate drive circuit 10 and quickly activate when a high voltage is detected to limit the voltage to a safe range, thereby reducing the damage caused by electrostatic discharge to the gate drive circuit 10. This protection mechanism improves the operational reliability of the display panel 200 when subjected to electrostatic shock.

[0107] Next, the specific structural composition of the electrostatic shielding unit 40 will be described in conjunction with the accompanying drawings. Please refer to the attached drawings. Figure 8 The electrostatic shielding unit 40 includes transistors T9 and T10. The first terminal of transistor T9 is connected to the low-voltage signal VGL1, and the control terminal and second terminal of transistor T9 are connected to node N. The control terminal and first terminal of transistor T10 are connected to the high-voltage signal VGH1, and the second terminal of transistor T10 is connected to node N. Furthermore, the input terminal IN and output terminal OUT of the electrostatic shielding unit 40 are connected to node N. Further, considering the virtual register 12 and the detection signal line 20, the input terminal IN of the electrostatic shielding unit 40 is also connected to the output terminal of the virtual register 12 via a signal trace, and the output terminal OUT of the electrostatic shielding unit 40 is also connected to the detection signal line 20.

[0108] It should be noted that the number of transistors T9 and T10 is not limited to two; depending on the actual needs, the number of transistors T9 and T10 can be more. The above description is only one circuit configuration of the electrostatic shielding unit 40, and other circuit configurations can be used for the electrostatic shielding unit 40 depending on the actual needs. Furthermore, in the final display panel 200, there may only be an electrostatic shielding unit 40 corresponding to the gate driving circuit 10, or there may be an electrostatic shielding structure corresponding to other circuits or conductor structures, such as an electrostatic shielding structure corresponding to the touch lead configuration. This application embodiment does not impose any limitations on this.

[0109] In this embodiment, the electrostatic shielding unit 40 is not directly electrically connected to the output of the shift register 11, but is first electrically connected to the output of the virtual register 12. This allows the virtual register 12 to separate the electrostatic shielding unit 40 from the shift register 11, thereby reducing the impact of the electrostatic shielding unit 40 on the load at the output of the last row shift register 11, reducing the load difference between the last row shift register 11 and other row shift registers 11 at the output, and improving the display uniformity of the display panel 200. Simultaneously, the output of the virtual register 12 needs to be connected to the detection signal line 20 via the electrostatic shielding unit 40, thereby reducing the adverse effects of external static electricity on the shift register 11 and improving the operational reliability of the gate drive circuit 10.

[0110] In some embodiments, such as Figure 5 As shown, the detection signal line 20 includes a first trace 21, which includes a first sub-section 211 extending along a first direction X and a connecting section 212 connecting the first sub-section 211 and the electrostatic shielding unit 40. In the second direction Y, the first sub-section 211 is located between the electrostatic shielding unit 40 and the virtual register 12.

[0111] The detection signal line 20 includes at least a first trace 21. The first sub-section 211 is a trace structure that extends along the first direction X, i.e., along the row direction, in the first trace 21. In the motherboard structure, the first sub-section 211 can be led out to the outside of the corresponding array area, i.e., extended to the outside of the array substrate 100 to meet the detection needs of the relevant signals.

[0112] The connecting part 212 is a connection structure used to connect the first sub-part 211 and the electrostatic shielding unit 40. The connecting part 212 has various film layer composition methods and wiring forms, as long as the connecting part 212 can connect the first sub-part 211 and the electrostatic shielding unit 40 and does not contact or interfere with other device structures and signal wiring.

[0113] Optionally, the connecting portion 212 includes a first portion extending along the second direction Y and a second portion extending along the first direction X. The two ends of the first portion in the second direction Y are respectively connected to the first sub-portion 211 and the second portion, and the two ends of the second portion in the first direction X are respectively connected to the first portion and the electrostatic shielding unit 40. Further, the first portion and the second portion are located in the same film layer and include the same conductive material.

[0114] Regarding the connecting portion 212 and the first sub-portion 211, they can be located in different film layers. Optionally, the first sub-portion 211 can be located in the same film layer as the control terminal of the transistor in the pixel circuit P, while the connecting portion 212 can be located in the same film layer as the signal trace used to transmit data signals.

[0115] In addition, in this embodiment, in the second direction Y, the first sub-part 211 is located between the electrostatic shielding unit 40 and the virtual register 12, that is, the first sub-part 211 is located on the side of the virtual register 12 away from the shift register 11. In this way, the existence of the virtual register 12 can not only isolate the first sub-part 211 from the last row shift register 11 at the electrical connection level, but also increase the distance between the first sub-part 211 and the last row shift register 11 in the second direction Y at the physical level, reduce the risk of parasitic capacitance between the two, and help to further improve the operational reliability of the gate drive circuit 10.

[0116] It should be noted that since both the first sub-part 211 and the electrostatic shielding unit 40 are located on the side of the virtual register 12 away from the shift register 11, the connecting part 212 used to connect the first sub-part 211 and the electrostatic shielding unit 40 is also located on the side of the virtual register 12 away from the shift register 11. Therefore, the present application embodiment can further increase the distance between the connecting part 212 and the last row shift register 11 in the second direction Y, reducing the risk of parasitic capacitance between the two.

[0117] In some embodiments, such as Figure 5 As shown, the detection signal line 20 also includes a second trace 22, which connects to at least one of the electrostatic shielding unit 40 and the first trace 21, and at least a portion of the structure of the second trace 22 extends along the second direction Y away from the gate drive circuit 10.

[0118] Both the first trace 21 and the second trace 22 are part of the structure of the detection signal line 20. The difference is that the first trace 21 includes a first sub-section 211 extending along the first direction X, so that during the detection phase, the first trace 21 can be led out of the array substrate 100 along the first direction X. At least a portion of the structure of the second trace 22 extends along the second direction Y away from the gate drive circuit 10, so that during the detection phase, the second trace 22 can be led out of the array substrate 100 along the second direction Y. In other words, during the detection phase, the first trace 21 and the second trace 22 need to be led out from different edge positions of the array substrate 100 to meet the respective needs of different detections.

[0119] The second trace 22 connects to at least one of the electrostatic shielding unit 40 and the first trace 21. That is, the second trace 22 can be directly connected to the electrostatic shielding unit 40, or it can be connected to the first trace 21. Optionally, the second trace 22 is connected to the connecting portion 212. Further optionally, the second trace 22 and the connecting portion 212 can be an integral structure, that is, both are located in the same film layer and include the same conductive material, and are formed in the same process.

[0120] Depending on the internal layout of the array substrate 100, the second trace 22 can extend entirely along the second direction Y, or a portion of the second trace 22 can extend along the first direction X, thereby fulfilling the need for some device structures or signal traces to avoid obstacles. This application embodiment does not limit this, as long as the general extension trend of the second trace 22 is to extend along the second direction Y.

[0121] In this embodiment, the detection signal line 20 includes a first trace 21 extending partially along the first direction X and a second trace 22 extending at least partially along the second direction Y. The combination of the two results in the detection signal line 20 having a large load. Based on this, by adding a virtual register 12, the virtual register 12 can block the adverse effects of the load of the detection signal line 20 on the shift register 11, reduce the load difference of the last row shift register 11 relative to other row shift registers 11 at the output end, and improve the display uniformity of the display panel 200.

[0122] In some embodiments, such as Figure 1 and Figure 5 As shown, the array substrate 100 also includes multiple electrode structures 30. Each electrode structure 30 includes a first connecting electrode 31 and a second connecting electrode 32 that are insulated from each other. The second connecting electrode 32 is connected to the pixel circuit P. The multiple electrode structures 30 include a first electrode group 33 connected to the Mth circuit row P5. In the second direction Y, an electrostatic shielding unit 40 is located between the first electrode group 33 and the virtual register 12.

[0123] Based on the foregoing, the Mth circuit row P5 is the last circuit row P5, which typically controls the last row of light-emitting elements. Therefore, the first electrode group 33 is the last row electrode structure 30, and the multiple light-emitting elements connected to the first electrode group 33 are the last row light-emitting elements. Furthermore, the projections of the first electrode group 33 and the corresponding last row light-emitting elements on the array substrate 100 are typically overlapped.

[0124] In this embodiment, the electrostatic shielding unit 40 is located between the first electrode group 33 and the virtual register 12, meaning that the electrostatic shielding unit 40 is located on the side of the last row of light-emitting elements facing the other row of light-emitting elements, rather than on the same side of all the row of light-emitting elements. In other words, the electrostatic shielding unit 40 is integrated into the light-emitting area of ​​the display panel 200, rather than located in the bezel area, thereby helping to eliminate the bezel area of ​​the display panel 200 and achieve a bezel-less effect.

[0125] In some embodiments, in the second direction Y, the virtual register 12 is located between the Mth circuit row P5 and the electrostatic shielding unit 40, and the distance L1 between the virtual register 12 and the electrostatic shielding unit 40 is greater than the distance L2 between the virtual register 12 and the Mth circuit row P5.

[0126] The Mth circuit row P5 is the last circuit row P5, and its corresponding shift register 11 is the last shift register 11. The last shift register 11 will be located on the side of the last circuit row P5 facing other circuit rows P3. At the same time, since the virtual register 12 is located between the last circuit row P5 and the electrostatic shielding unit 40, the virtual register 12 and the last shift register 11 will be located on both sides of the last circuit row P5 in the second direction Y.

[0127] Based on this, the present application embodiment limits the distance L2 between the virtual register 12 and the last row circuit line P5 in the second direction Y to be less than the distance L1 between the virtual register 12 and the electrostatic shielding unit 40 in the second direction Y. In other words, compared with the electrostatic shielding unit 40, the virtual register 12 is set closer to the last row circuit line P5 in the second direction Y. This helps to reduce the distance between the virtual register 12 and the last row shift register 11 in the second direction Y, thereby reducing the length of the cascaded trace used to connect the virtual register 12 and the last row shift register 11, reducing the load problem caused by the excessive extension size of the cascaded trace, reducing the load difference of the last row shift register 11 relative to other row shift registers 11 at the output end, and improving the display uniformity of the display panel 200.

[0128] In some embodiments, please refer to Figures 9 to 11a and Figure 11b The array substrate 100 also includes a substrate 50, a plurality of electrode structures 30, and a plurality of pad structures 60. The electrode structure 30 includes a first connection electrode 31 and a second connection electrode 32 that are insulated from each other. The second connection electrode 32 is connected to the pixel circuit P. The pad structure 60 includes a first pad 61, which is located on the same side of the substrate 50 as the electrode structure 30.

[0129] Optionally, the pad structure 60 may also include a second pad 62 located on the side of the substrate 50 away from the first pad 61.

[0130] The multiple electrode structures 30 include a first electrode group 33 connected to the Mth circuit row P5. In the second direction Y, the first electrode group 33 is located between the first pad 61 and the electrostatic shielding unit 40, and the distance between the first electrode group 33 and the electrostatic shielding unit 40 is greater than the distance between the first electrode group 33 and the first pad 61.

[0131] The substrate 50 is a film structure on the array substrate 100 that plays a supporting role. The thickness direction Z of the substrate 50 is usually parallel to the thickness direction Z of the array substrate 100 itself. In the thickness direction Z of the substrate 50, the substrate 50 includes two opposing surfaces. The light-emitting element, the electrode structure 30 and the first pad 61 are all located on one side of one surface of the substrate 50, while the second pad 62 and the driving chip are all located on the other side of the substrate 50.

[0132] The pad structure 60 serves as a bridge to facilitate electrical connections between different device structures or signal traces located on either side of the substrate 50. For example, a driver chip uses the pad structure 60 to achieve electrical connections with data signal lines.

[0133] Depending on the specific needs, the pad structure 60 can take different forms, specifically, such as Figure 11a As shown, the pad structure 60 includes a first pad 61 disposed on one side of the substrate 50. The substrate 50 has a side trace 63 and a package protection portion 64 disposed on one side in the second direction Y. The side trace 63 is connected to the first pad 61 and bends to the side of the substrate opposite to the first pad 61. The package protection portion 64 is attached to the surface of the side trace 63 to provide protection. A portion of the side trace 63 located on the side of the substrate opposite to the first pad 61 extends beyond the package protection portion 64 in the second direction Y and is connected to the circuit board structure 70.

[0134] Or such as Figure 11b As shown, the pad structure 60 includes a first pad 61 and a second pad 62 disposed on both sides of the substrate 50. Multiple first pads 61 and second pads 62 are arranged side-by-side along the first direction X. The multiple first pads 61 and multiple second pads 62 can be arranged correspondingly to each other, and the second pads 62 can be connected to the circuit board structure 70. The substrate 50 has a side trace 63 and a package protection part 64 on one side of the second direction Y. The side trace 63 connects to both the first pad 61 and the second pad 62 to meet the electrical connection requirements between the first pad 61 and the second pad 62. The package protection part 64 covers the side trace 63 to protect it.

[0135] For the first pad 61, the first pad 61 is usually disposed adjacent to the surface of the array substrate 100 in the second direction Y, and it is located on the side of the last row of light-emitting elements away from the other row of light-emitting elements. As can be seen from the above description, the position of the last row of light-emitting elements in the thickness direction Z of the array substrate 100 is usually overlapping with the position of the first electrode group 33 in the thickness direction Z of the array substrate 100.

[0136] Based on this, the distance between the first electrode group 33 and the first pad 61 in the second direction Y is set to be less than that between the first electrode group 33 and the electrostatic shielding unit 40, so that the last row of light-emitting elements is set closer to the first pad 61 relative to the electrostatic shielding unit 40. In this way, during the operation of the display panel 200, the light-emitting area corresponding to the last row of light-emitting elements can cover the area where the first pad 61 is located, and may even cover the edge of the array substrate 100 in the second direction Y, thereby achieving a borderless display effect and improving the user experience.

[0137] In some embodiments, such as Figure 1 and Figure 9 As shown, in the second direction Y, the virtual register 12 overlaps with the pixel circuit P; and / or, in the second direction Y, the virtual register 12 overlaps with the shift register 11; and / or, in the second direction Y, the virtual register 12 overlaps with the electrostatic shielding unit 40.

[0138] The phrase "overlapping arrangement in the second direction Y" refers to the following: at least some of the different structures are located at the same position in the first direction X, so that the projections of the different structures in the thickness direction Z of the array substrate 100 can overlap accordingly in the second direction Y.

[0139] In this embodiment, the virtual register 12 can be selectively overlapped with at least one of the pixel circuit P, the shift register 11, and the electrostatic shielding unit 40 in the second direction Y. This helps to reduce the risk of the array substrate 100 increasing in size in the first direction X due to the presence of the virtual register 12. While satisfying the rationality of the internal structural layout of the array substrate 100, it is beneficial to reduce the size of the subsequently formed display panel 200 in the first direction X, thereby improving the user experience.

[0140] In some alternative embodiments, in the second direction Y, the virtual register 12 is simultaneously arranged to overlap with the pixel circuit P, the shift register 11 and the electrostatic shielding unit 40.

[0141] In some embodiments, the electrostatic shielding unit 40 includes a first signal terminal and a second signal terminal. The first signal terminal is configured to receive a high-voltage signal VGH1, and the second signal terminal is configured to receive a low-voltage signal VGL1. Specifically, at least some of the first signal terminals of the electrostatic shielding units 40 receive different low-voltage signals VGL1; and / or, at least some of the second signal terminals of different electrostatic shielding units 40 receive different high-voltage signals VGH1.

[0142] Combination Figure 8In this context, the first signal terminal is the first electrode of transistor T9, and the second signal terminal is the control terminal and the first electrode of body transistor T10. The array substrate 100 typically includes multiple electrostatic shielding units 40, each used to provide electrostatic shielding for different device structures or signal traces. Based on this, in this embodiment, different first signal terminals of different electrostatic shielding units 40 are configured to receive different low-voltage signals VGL1, or different second signal terminals are configured to receive different high-voltage signals VGH1. This allows different electrostatic shielding units 40 to be independently configured, thereby reducing mutual interference between different electrostatic shielding units 40 and their corresponding device structures or signal traces, and improving the operational reliability of the internal structure of the array substrate 100.

[0143] In some embodiments, the pixel circuit P includes an amplitude modulation sub-circuit P2 and a pulse width modulation sub-circuit P1. The plurality of gate driving circuits 10 include a fourth type of gate driving circuit for controlling the pulse width modulation sub-circuit P1 and a fifth type of gate driving circuit for controlling the amplitude modulation sub-circuit P2. The plurality of electrostatic shielding units 40 include a first type of electrostatic shielding unit and a second type of electrostatic shielding unit. The first type of electrostatic shielding unit is electrically connected to the output terminal of the virtual register 12 of the fourth type of gate driving circuit, and the second type of electrostatic shielding unit is electrically connected to the output terminal of the virtual register 12 of the fifth type of gate driving circuit. The first signal terminal of the first type of electrostatic shielding unit and the first signal terminal of the second type of electrostatic shielding unit receive different high-voltage signals VGH1; and / or, the second signal terminal of the first type of electrostatic shielding unit and the second signal terminal of the second type of electrostatic shielding unit receive different low-voltage signals VGL1.

[0144] The fourth and fifth type gate drive circuits are gate drive circuits 10 that respectively drive and control the pulse width modulation sub-circuit P1 and the amplitude modulation sub-circuit P2. (Combined) Figure 3a In general, the fourth type of gate drive circuit includes at least a first gate drive circuit and a third gate drive circuit. The output of the first gate drive circuit can transmit the second scan signal PWM-S2 to the control terminal of the first data writing transistor M2 through signal traces. The output of the third gate drive circuit can transmit the first scan signal PWM-S1 to the control terminal of the first gate reset transistor M5 through signal traces.

[0145] Furthermore, depending on the actual needs, the fourth type of gate driving circuit may also include at least one of a fifth gate driving circuit and a seventh gate driving circuit. The fifth gate driving circuit is used to transmit the first light-emitting control signal PWM-EM to the control terminals of the first control transistor M1 and the second control transistor M6, and the seventh gate driving circuit is used to transmit the sweep frequency signal SWEEP to the second plate of the storage capacitor Cst. Of course, in some other embodiments, the fourth type of gate driving circuit may not include the fifth gate driving circuit and the seventh gate driving circuit.

[0146] The fifth type of gate drive circuit includes at least a second gate drive circuit and a fourth gate drive circuit. The output of the second gate drive circuit can transmit the fourth scan signal PAM-S2 to the control terminal of the second data writing transistor M8 through signal lines. The output of the fourth gate drive circuit can transmit the third scan signal PAM-S1 to the control terminal of the second gate reset transistor M11 through signal lines.

[0147] Furthermore, depending on the specific needs, the fifth type of gate driving circuit may also optionally include a sixth gate driving circuit. This sixth gate driving circuit is used to transmit the second light-emitting control signal PAM-EM to the control terminals of the third control transistor M7 and the fourth control transistor M12. Of course, in some other embodiments, the fifth type of gate driving circuit may not include a sixth gate driving circuit.

[0148] In this embodiment, the fourth type of gate driving circuit and the fifth type of gate driving circuit are gate driving circuits 10 that drive and control the pulse width modulation sub-circuit P1 and the amplitude modulation sub-circuit P2, respectively. Based on this, by setting the first signal terminal of the first type of electrostatic shielding unit corresponding to the fourth type of gate driving circuit to receive different high voltage signals VGH1, or setting the second signal terminals of the first type of electrostatic shielding unit and the second type of electrostatic shielding unit to receive different low voltage signals VGL1, it helps to improve the signal independence of the fourth type of gate driving circuit and the first type of electrostatic shielding unit relative to the fifth type of gate driving circuit and the second type of electrostatic shielding unit, reduce the risk of mutual interference between the fourth type of gate driving circuit and the fifth type of gate driving circuit, and improve the operational reliability of the pixel circuit P.

[0149] Secondly, please refer to Figure 12 This application provides a display panel 200, which includes the array substrate 100 and light-emitting elements as described in any of the foregoing embodiments.

[0150] It should be noted that the display panel 200 provided in this application embodiment has the beneficial effects of the array substrate 100 in any of the foregoing embodiments. For details, please refer to the foregoing description of the beneficial effects of the array substrate 100. This application embodiment will not repeat the description.

[0151] In some embodiments, the light-emitting element includes a micro light-emitting diode.

[0152] In this embodiment, the display panel 200 uses micro-light-emitting diodes to achieve the light-emitting display function. In this case, the display panel 200 can be designed as a borderless display panel 200, that is, the display panel 200 does not include a border area for setting the virtual pixel circuit P. In view of this, the array substrate 100 can only have the virtual register 12 and not the virtual pixel circuit P. This can not only meet the requirements of borderless display, but also isolate the last row shift register 11 from the detection signal line 20 by means of the virtual register 12, reduce the load influence of the detection signal line 20 on the last row shift register 11 at the output end, reduce the load difference of the last row shift register 11 relative to other row shift registers 11 at the output end, thereby reducing the display difference of the last row or several rows of light-emitting elements relative to other rows of light-emitting elements, and improving the display uniformity of the display panel 200.

[0153] Thirdly, please refer to Figure 13 This application provides a display device 300, which includes the display panel 200 in any of the foregoing embodiments.

[0154] It should be noted that the display device 300 provided in this application embodiment has the beneficial effects of the display panel 200 in any of the foregoing embodiments. For details, please refer to the foregoing description of the beneficial effects of the array substrate 100 and the display panel 200. This application embodiment will not repeat the description.

[0155] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit the invention. Any person skilled in the art to which this application pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

[0156] The above description is merely a specific embodiment of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, substitutions for other connection methods described above can be made by referring to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application.

Claims

1. An array substrate, characterized by, include: A gate drive circuit includes a shift register group and a virtual register. The shift register group includes N shift registers cascaded together, and the virtual register is cascaded to the Nth shift register. A detection signal line is electrically connected to the output terminal of the virtual register; M circuit rows, each circuit row comprising a plurality of pixel circuits arranged along a first direction, and the M circuit rows arranged along a second direction, both the first direction and the second direction being parallel to the plane of the array substrate and intersecting each other; An electrostatic shielding unit is provided, and the output terminal of the virtual register is electrically connected to the detection signal line through the electrostatic shielding unit. The array substrate satisfies at least one of the following: In the second direction, the virtual register is located between the Mth circuit row and the electrostatic shielding unit, and the distance between the virtual register and the electrostatic shielding unit is greater than the distance between the virtual register and the Mth circuit row; or, The array substrate further includes a substrate, multiple electrode structures, and multiple pad structures. The electrode structures include a first connection electrode and a second connection electrode that are insulated from each other. The pad structures include a first pad, and the first pad and the electrode structures are located on the same side of the substrate. The plurality of electrode structures include a first electrode group connected to the Mth circuit row, wherein in the second direction, the first electrode group is located between the first pad and the electrostatic shielding unit, and the distance between the first electrode group and the electrostatic shielding unit is greater than the distance between the first electrode group and the first pad.

2. The array substrate according to claim 1, characterized in that, The Nth stage shift register provides gate control signals to the Mth circuit row.

3. The array substrate of claim 2, wherein, In the second direction, the shift register is located between adjacent circuit rows; or, The array substrate includes multiple circuit columns, each circuit column including multiple pixel circuits arranged along the second direction, and the shift register is located between adjacent circuit columns in the first direction.

4. The array substrate of claim 3, wherein, In the second direction, the shift register is located between adjacent circuit rows, and the Mth circuit row is located between the Nth level shift register and the virtual register.

5. The array substrate of claim 3, wherein, It also includes multiple electrode structures, each electrode structure comprising an insulated first connecting electrode and a second connecting electrode, the second connecting electrode being connected to the pixel circuit; The plurality of electrode structures include a first electrode group connected to the Mth circuit row, wherein, in the second direction, the virtual register is located between the first electrode group and the Mth circuit row.

6. The array substrate of claim 2, wherein, N=M.

7. The array substrate of claim 2, wherein, N < M.

8. The array substrate of claim 2, wherein, The circuit structures in the virtual registers of at least partially different gate drive circuits are different; and / or, The circuit structure in the virtual register of at least some of the different gate drive circuits is consistent with that of the virtual register.

9. The array substrate according to claim 8, characterized in that, In a single gate drive circuit, the circuit structure in the virtual register is consistent with the circuit structure in the shift register.

10. The array substrate according to claim 8, characterized in that, In a single gate drive circuit, the virtual register and the shift register have the same size in the first direction; and / or, In a single gate drive circuit, the virtual register and the shift register are the same size in the second direction.

11. The array substrate according to claim 2, characterized in that, The plurality of gate driving circuits include a first type of gate driving circuit and a second type of gate driving circuit. The first type of gate driving circuit is used to control data signals to be written into the pixel circuit, and the second type of gate driving circuit is used to write reset signals into the pixel circuit. The first type of gate driving circuit and the second type of gate driving circuit include at least one of the virtual registers.

12. The array substrate according to claim 11, characterized in that, The pixel circuit includes an amplitude modulation sub-circuit and a pulse width modulation sub-circuit, the first type of gate driving circuit includes a first gate driving circuit and a second gate driving circuit, and the second type of gate driving circuit includes a third gate driving circuit and a fourth gate driving circuit. The first gate driving circuit is used to control the first data signal to be written into the pulse width modulation sub-circuit, the second gate driving circuit is used to control the second data signal to be written into the amplitude modulation sub-circuit, the third gate driving circuit is used to control the first reset signal to be written into the pulse width modulation sub-circuit, and the fourth gate driving circuit is used to control the second reset signal to be written into the amplitude modulation sub-circuit.

13. The array substrate according to claim 11, characterized in that, The first type of gate driving circuit includes a first virtual register, and the second type of gate driving circuit includes a second virtual register. The circuit structure in the first virtual register and the second virtual register are consistent.

14. The array substrate according to claim 11, characterized in that, The plurality of gate driving circuits further include a third type of gate driving circuit, which is used to output a light emission control signal or a frequency sweep signal. The first type of gate driving circuit includes a first virtual register, and the third type of gate driving circuit includes a third virtual register. The circuit structures in the first virtual register and the third virtual register are different.

15. The array substrate according to claim 1, characterized in that, The detection signal line includes a first trace, the first trace including a first sub-section extending along the first direction and a connecting portion connecting the first sub-section and the electrostatic shielding unit; In the second direction, the first sub-part is located between the electrostatic shielding unit and the virtual register.

16. The array substrate according to claim 15, characterized in that, The detection signal line further includes a second trace, which is connected to at least one of the electrostatic shielding unit and the first trace, and at least a portion of the structure of the second trace extends along the second direction and away from the gate driving circuit.

17. The array substrate according to claim 1, characterized in that, It also includes multiple electrode structures, each electrode structure comprising an insulated first connecting electrode and a second connecting electrode, the second connecting electrode being connected to the pixel circuit; The plurality of electrode structures include a first electrode group connected to the Mth circuit row, wherein, in the second direction, the electrostatic shielding unit is located between the first electrode group and the virtual register.

18. The array substrate according to claim 1, characterized in that, In the second direction, the virtual register overlaps with the pixel circuit; and / or, In the second direction, the virtual register overlaps with the shift register; and / or, In the second direction, the virtual register overlaps with the electrostatic shielding unit.

19. The array substrate according to claim 15, characterized in that, The electrostatic shielding unit includes a first signal terminal and a second signal terminal, wherein the first signal terminal is configured to receive a high-voltage signal and the second signal terminal is configured to receive a low-voltage signal. Wherein, at least a portion of the first signal terminal of the electrostatic shielding unit receives different low-voltage signals; and / or, at least a portion of the second signal terminal of the electrostatic shielding unit receives different high-voltage signals.

20. The array substrate according to claim 19, characterized in that, The pixel circuit includes an amplitude modulation sub-circuit and a pulse width modulation sub-circuit, and the plurality of gate driving circuits include a fourth type of gate driving circuit for controlling the pulse width modulation sub-circuit and a fifth type of gate driving circuit for controlling the amplitude modulation sub-circuit. The plurality of electrostatic shielding units include a first type of electrostatic shielding unit and a second type of electrostatic shielding unit. The first type of electrostatic shielding unit is electrically connected to the output terminal of the virtual register of the fourth type of gate driving circuit, and the second type of electrostatic shielding unit is electrically connected to the output terminal of the virtual register of the fifth type of gate driving circuit. Wherein, the first signal terminal of the first type of electrostatic shielding unit and the first signal terminal of the second type of electrostatic shielding unit receive different high-voltage signals; and / or, the second signal terminal of the first type of electrostatic shielding unit and the second signal terminal of the second type of electrostatic shielding unit receive different low-voltage signals.

21. A display panel, characterized in that, It includes the array substrate and the light-emitting element as described in any one of claims 1 to 20.

22. The display panel according to claim 21, characterized in that, The light-emitting element includes a micro light-emitting diode.

23. A display device, characterized in that, Includes the display panel as described in claim 21 or 22.

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