Embedded package substrate structure and fabrication method

Abstract

This invention discloses an embedded packaging substrate structure and its fabrication method, relating to the field of embedded packaging substrate technology. The method includes: preparing a substrate body; forming a first conductive post on the substrate body; depositing a first dielectric material with adhesive properties on the surface of the substrate body; placing a chip on the surface of the first dielectric material; pressing the chip into the first dielectric material using a vacuum laminator; depositing a second dielectric material with adhesive properties on the surface of the first dielectric material; fabricating blind vias communicating with the first conductive post and the chip within the second dielectric material; and fabricating a first circuit communicating with the blind vias on the surface of the second dielectric material, thus forming an embedded packaging substrate structure. The fabrication method of the embedded packaging substrate structure according to embodiments of this invention solves the reliability problem caused by CTE mismatch due to different materials, and reduces the depth of the vias, which is beneficial for the blind vias to be filled and flattened by subsequent electroplating.

Description

Technical Field

[0001] This invention relates to the field of embedded packaging substrate technology, and in particular to an embedded packaging substrate structure and manufacturing method. Background Technology

[0002] With the continuous development of the electronics industry, multifunctionality and miniaturization of electronic products have become development trends. In the field of packaging substrates, embedding components inside the substrate can help electronic products achieve the development needs of high integration, multifunctionality, and miniaturization. Currently, there are generally two methods to embed components into the substrate: 1. First, prefabricate a substrate with cavities, and then embed the components into the cavities; 2. Use solder paste or DAF (die attach film, a type of adhesive film) or adhesive resin materials to mount the components onto the substrate, then encapsulate the components, and then use laser drilling or sandblasting drilling to make interlayer electrical connections.

[0003] The first method has a long process flow, which is not conducive to shortening the manufacturing cycle and reducing costs. The second method requires the use of multiple materials for component mounting and fixing, such as solder paste, DAF, or adhesive resin materials. The difference in the coefficient of thermal expansion (CTE) between different materials poses a reliability risk. Furthermore, completing the device encapsulation first, and then using laser burning or sandblasting to form interlayer vias results in excessively deep vias. Existing electroplating filling capabilities cannot completely fill these vias, leading to increased risks of via filling depressions and voids, which is detrimental to product quality. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes an embedded packaging substrate structure and a method for manufacturing it.

[0005] On one hand, the method for fabricating an embedded packaging substrate structure according to an embodiment of the present invention includes the following steps:

[0006] Prepare the substrate body;

[0007] A first conductive post is formed on the substrate body;

[0008] A first dielectric material with adhesive properties is disposed on the surface of the substrate body; the first dielectric material covers the first conductive post;

[0009] A chip is placed on the surface of the first dielectric material;

[0010] The chip is pressed into the first dielectric material using a vacuum laminator;

[0011] A second, adhesive medium material is disposed on the surface of the first medium material; the first medium material and the second medium material are the same material.

[0012] A blind via is fabricated within the second dielectric material, which communicates with the first conductive post and the chip;

[0013] A first line connected to the blind via is formed on the surface of the second dielectric material to form an embedded packaging substrate structure.

[0014] According to some embodiments of the present invention, the step of preparing the substrate body includes:

[0015] Obtain the substrate;

[0016] A second conductive post is provided in the substrate, and the second conductive post penetrates the upper surface and the lower surface of the substrate;

[0017] A second circuit connected to the second conductive post is formed on the upper and lower surfaces of the substrate to form the substrate body.

[0018] According to some embodiments of the present invention, the step of forming the first conductive post on the substrate body includes:

[0019] A metal seed layer is formed on the surface of the substrate body;

[0020] A photosensitive dry film is attached to the surface of the metal seed layer;

[0021] The photosensitive dry film is exposed and developed to form a first window corresponding to the first conductive post;

[0022] The substrate body is electroplated to form the first conductive post at the first window;

[0023] Remove the photosensitive dry film and etch the metal seed layer on the surface of the substrate body.

[0024] According to some embodiments of the present invention, the step of applying a first dielectric material with adhesive properties to the surface of the substrate body includes:

[0025] A first dielectric material with adhesive properties is pressed onto the surface of the substrate body using a vacuum laminator, so that the first dielectric material covers the surface of the substrate body and the first conductive post.

[0026] According to some embodiments of the present invention, the bottom of the chip is provided with connection terminals; the step of pressing the chip into the first dielectric material using a vacuum laminator includes:

[0027] The chip is placed upside down on the surface of the first dielectric material, with the connection terminals facing upwards;

[0028] The chip is pressed into the first dielectric material using the vacuum laminator, so that the surface of the chip is connected to the second circuit.

[0029] According to some embodiments of the present invention, the step of fabricating a blind via communicating with the first conductive post and the chip within the second dielectric material includes:

[0030] Laser drilling is performed on the second dielectric material to form a through hole penetrating the second dielectric material;

[0031] The blind hole is formed by electroplating inside the through hole, and the blind hole is connected to the first conductive post and the connecting terminal.

[0032] On the other hand, the embedded packaging substrate structure according to an embodiment of the present invention includes:

[0033] substrate body;

[0034] The first conductive post is disposed on the surface of the substrate body;

[0035] A first dielectric material with adhesive properties is disposed on the surface of the substrate body and covers the first conductive post;

[0036] The chip is disposed within the first dielectric material;

[0037] A second, viscous medium material is disposed on the surface of the first medium material, wherein the first medium material and the second medium material are the same material;

[0038] A blind via is disposed within the second dielectric material, and the blind via is connected to the first conductive post and the chip.

[0039] A first line is disposed on the surface of the second dielectric material, and the first line is connected to the blind hole.

[0040] According to some embodiments of the present invention, the substrate body includes a substrate, a second conductive post, and a second circuit. The second conductive post is disposed within the substrate and penetrates the upper and lower surfaces of the substrate. The second circuit is disposed on the upper and lower surfaces of the substrate and is in communication with the second conductive post.

[0041] According to some embodiments of the present invention, a connection terminal is provided at the bottom of the chip, the connection terminal is connected to the blind via, and the surface of the chip is connected to the second line.

[0042] According to some embodiments of the present invention, the chip is pressed into the first dielectric material by a vacuum laminator.

[0043] The embedded packaging substrate structure and manufacturing method according to the embodiments of the present invention have at least the following beneficial effects: using the same first dielectric material and second dielectric material to bond the chip and encapsulate the chip solves the reliability problem caused by CTE mismatch due to different embedded chip materials in the prior art; before installing the chip, a portion of the interlayer conductive pillars (i.e., the first conductive pillar 200) can be prefabricated to reduce the depth of the vias, which is beneficial for blind vias to be filled and filled by subsequent electroplating.

[0044] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0045] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0046] Figure 1 This is a flowchart illustrating the steps of a method for fabricating an embedded packaging substrate structure according to an embodiment of the present invention.

[0047] Figure 2 This is a schematic diagram of the structure of the substrate body according to an embodiment of the present invention;

[0048] Figure 3 This is a schematic diagram of the structure after the first conductive post is formed on the substrate body according to an embodiment of the present invention;

[0049] Figure 4 This is a schematic diagram of the structure after a first dielectric material is applied to the surface of the substrate body according to an embodiment of the present invention;

[0050] Figure 5 This is a schematic diagram of the structure after placing a chip on the surface of the first dielectric material according to an embodiment of the present invention;

[0051] Figure 6 This is a schematic diagram of the structure after the chip is pressed into the first dielectric material according to an embodiment of the present invention;

[0052] Figure 7 This is a schematic diagram of the structure of the second dielectric material disposed on the surface of the first dielectric material according to an embodiment of the present invention;

[0053] Figure 8 This is a schematic diagram of the embedded packaging substrate structure according to an embodiment of the present invention;

[0054] Figure label:

[0055] The substrate body 100, substrate 110, second conductive post 120, second circuit 130, first conductive post 200, first dielectric material 300, chip 400, connection terminal 410, second dielectric material 500, blind via 600, and first circuit 700. Detailed Implementation

[0056] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0057] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0058] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0059] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0060] With the continuous development of the electronics industry, multifunctionality and miniaturization of electronic products have become development trends. In the field of packaging substrates, embedding components inside the substrate can help electronic products achieve the development needs of high integration, multifunctionality, and miniaturization. Currently, there are generally two methods to embed components into the substrate: 1. First, prefabricate a substrate with cavities, and then embed the components into the cavities; 2. Use solder paste or DAF (die attach film, a type of adhesive film) or adhesive resin materials to mount the components onto the substrate, then encapsulate the components, and then use laser drilling or sandblasting drilling to make interlayer electrical connections.

[0061] The first method has a long process flow, which is not conducive to shortening the manufacturing cycle and reducing costs. The second method requires the use of multiple materials for component mounting and fixing, such as solder paste, DAF, or adhesive resin materials. The difference in the coefficient of thermal expansion (CTE) between different materials poses a reliability risk. Furthermore, completing the device encapsulation first, and then using laser burning or sandblasting to form interlayer vias results in excessively deep vias. Existing electroplating filling capabilities cannot completely fill these vias, leading to increased risks of via filling depressions and voids, which is detrimental to product quality.

[0062] To address this, this invention proposes an embedded packaging substrate structure and its fabrication method. It uses a first dielectric material and a second dielectric material of the same type to bond the chip and encapsulate it, thus solving the reliability problem caused by CTE mismatch due to different embedded chip materials in the prior art. Before chip installation, a portion of the interlayer conductive pillars (i.e., the first conductive pillar 200) can be fabricated in advance to reduce the depth of the vias, which is beneficial for blind vias to be filled and filled by subsequent electroplating.

[0063] The following is in conjunction with the appendix Figure 1 To be continued Figure 8 The embedded packaging substrate structure and manufacturing method of the present invention are described in detail in the embodiments of the present invention.

[0064] On the one hand, such as Figure 1 As shown, the method for fabricating an embedded packaging substrate structure according to an embodiment of the present invention includes the following steps:

[0065] Step S100: Prepare the substrate body 100;

[0066] Step S200: Form a first conductive post 200 on the substrate body 100;

[0067] Step S300: A first dielectric material 300 with adhesive properties is disposed on the surface of the substrate body 100; the first dielectric material 300 covers the first conductive post 200;

[0068] Step S400: Place chip 400 on the surface of the first dielectric material 300;

[0069] Step S500: Press the chip 400 into the first dielectric material 300 using a vacuum laminator;

[0070] Step S600: A second medium material 500 with adhesive properties is disposed on the surface of the first medium material 300; the first medium material 300 and the second medium material 500 are the same material;

[0071] Step S700: A blind via 600 is formed in the second dielectric material 500, which is connected to the first conductive post 200 and the chip 400;

[0072] Step S800: A first line 700 connected to the blind via 600 is formed on the surface of the second dielectric material 500 to form an embedded packaging substrate structure.

[0073] Specifically, such as Figure 2 As shown, in this example, the substrate body 100 includes a substrate 110, a second conductive post 120, and a second circuit 130. The substrate 110 can be made of FR4 or epoxy resin containing glass fiber, which has good strength and rigidity. The second conductive post 120 penetrates the upper and lower surfaces of the substrate 110. The second circuit 130 is provided on both the upper and lower surfaces of the substrate 110, and the second circuit 130 is connected to the second conductive post 120. The second circuit 130 on the upper surface of the substrate 110 is connected to the second circuit 130 on the lower surface through the first conductive post 120 disposed within the substrate 110. In this example, step S100: preparing the substrate body 100, specifically includes the following three steps:

[0074] (1) Obtain substrate 110;

[0075] (2) A second conductive post 120 is provided in the substrate 110, and the second conductive post 120 penetrates the upper surface and the lower surface of the substrate 110.

[0076] (3) A second line 130 connected to the second conductive post 120 is formed on the upper and lower surfaces of the substrate 110 to form the substrate body 100.

[0077] It should be noted that, in order to set the second conductive post 120 in the substrate 110, the second conductive post 120 can be formed in the substrate 110 by drilling and electroplating. In order to fabricate the second circuit 130 on the upper and lower surfaces of the substrate 110, a dry film lamination-exposure-development method can be used to open windows in the dry film to form windows corresponding to the second circuit 130, and then electroplating is performed on the entire board to form the second circuit 130 at the windows.

[0078] After preparing the substrate body 100, as follows Figure 3 As shown, a first conductive post 200 needs to be formed on the substrate body 100. It should be noted that the first conductive post 200 is located on the surface of the second line 130, thereby communicating with the second line 130. In this example, step S200 above: forming the first conductive post 200 on the substrate body 100, includes the following five steps:

[0079] (1) A metal seed layer is formed on the surface of the substrate body 100;

[0080] (2) A photosensitive dry film is attached to the surface of the metal seed layer;

[0081] (3) Expose and develop the photosensitive dry film to form a first window corresponding to the first conductive post 200;

[0082] (4) Electroplating is performed on the substrate body 100 to form a first conductive post 200 at the first window;

[0083] (5) Remove the photosensitive dry film and etch the metal seed layer on the surface of the substrate body 100.

[0084] Specifically, a metal seed layer is formed on the surface of the substrate body 100 by methods such as magnetron sputtering, which facilitates subsequent electroplating on the substrate body 100. Then, a photosensitive dry film is attached to the surface of the metal seed layer to protect the areas of the substrate body 100 that do not require electroplating. The photosensitive dry film is then exposed and developed to create a window on the photosensitive dry film corresponding to the position of the first conductive post 200, forming a first window. Finally, the entire substrate body 100 is electroplated to form the first conductive post 200 at the first window.

[0085] like Figure 4 As shown, in some embodiments of the present invention, step S300 above, the step of providing a first dielectric material 300 with adhesive properties on the surface of the substrate body 100, includes:

[0086] A first dielectric material 300 with adhesive properties is applied to the surface of the substrate body 100 using a vacuum laminator, so that the first dielectric material 300 covers the surface of the substrate body 100 and the first conductive post 200.

[0087] It should be noted that the first dielectric material 300 can simultaneously serve the functions of bonding the chip 400 and encapsulating the chip 400.

[0088] like Figure 5 As shown, in some embodiments of the present invention, a connection terminal 410 is provided at the bottom of the chip 400, and the chip 400 is placed upside down on the surface of the first dielectric material 300. Since the first dielectric material 300 is adhesive, it can fix the chip 400.

[0089] Then, as Figure 6 As shown, the chip 400 needs to be pressed into the first dielectric material 300 using a vacuum laminator, specifically:

[0090] Chip 400 is placed upside down on the surface of the first dielectric material 300, with the connection terminal 410 facing upwards;

[0091] The chip 400 is pressed into the first dielectric material 300 by a vacuum laminator, so that the surface of the chip 400 is connected to the second line 130.

[0092] It should be noted that the chip 400 is directly pressed into the first dielectric material 300 using a vacuum laminator, without the need for a pre-set cavity to place the chip 400. This direct placement and encapsulation of the chip 400 simplifies the process, shortens the product manufacturing cycle, and improves production efficiency. The surface of the chip 400 needs to be connected to the second circuit 130 to achieve electrical connection between the chip 400 and the circuit.

[0093] like Figure 7 As shown, after pressing the chip 400 into the first dielectric material 300, a second dielectric material 500 needs to be pressed onto the surface of the first dielectric material 300. It should be noted that the first dielectric material 300 and the second dielectric material 500 are made of the same material. By using the same material for the packaging medium, the reliability risks caused by the difference in the coefficient of thermal expansion (CTE) between different materials can be avoided.

[0094] Furthermore, such as Figure 8 As shown, in some embodiments of the present invention, step S700 above, which involves creating a blind via 600 communicating with the first conductive post 200 and the chip 400 within the second dielectric material 500, includes the following two steps:

[0095] (1) Laser drilling is performed on the second dielectric material 500 to form a through hole penetrating the second dielectric material 500;

[0096] (2) A blind hole 600 is formed by electroplating in the through hole, and the blind hole 600 is connected to the first conductive post 200 and the connecting terminal 410.

[0097] By creating a blind hole 600 in the second dielectric material 500 that is connected to the first conductive post 200 and the connecting terminal 410, the lines on the surface of the second dielectric material 500 can be connected to the second line 130 and the chip 400 through the blind hole.

[0098] Finally, as Figure 8As shown, on the surface of the second dielectric material 500, the first line 700 is fabricated by applying dry film, exposing, developing, electroplating, and removing film. The first line 700 is connected to the blind via 600, and then to the chip 400 and the second line 130.

[0099] According to the method for fabricating the embedded packaging substrate structure of the present invention, a first dielectric material 300 and a second dielectric material 500 are used to bond the chip 400 and to encapsulate the chip 400 in plastic, which solves the reliability problem caused by CTE mismatch due to different materials of the embedded chip 400 in the prior art; before installing the chip 400, a portion of the interlayer conductive pillars (i.e., the first conductive pillar 200) can be fabricated in advance to reduce the depth of the vias and facilitate the subsequent electroplating to fill and flatten the blind vias 600.

[0100] On the other hand, embodiments of the present invention also propose an embedded packaging substrate structure, such as... Figures 2 to 8 As shown, it includes:

[0101] substrate main body 100;

[0102] The first conductive post 200 is disposed on the surface of the substrate body 100;

[0103] A first dielectric material 300 with adhesive properties is disposed on the surface of the substrate body 100 and covers the first conductive post 200;

[0104] Chip 400 is disposed within the first dielectric material 300;

[0105] A second medium material 500 with adhesive properties is disposed on the surface of the first medium material 300, and the first medium material 300 and the second medium material 500 are the same material;

[0106] A blind via 600 is disposed within the second dielectric material 500, and the blind via 600 is connected to the first conductive post 200 and the chip 400;

[0107] The first line 700 is disposed on the surface of the second dielectric material 500, and the first line 700 is connected to the blind hole 600.

[0108] Specifically, such as Figure 2As shown, in this example, the substrate body 100 includes a substrate 110, a second conductive post 120, and a second circuit 130. The substrate 110 can be made of FR4 or an epoxy resin containing glass fiber, possessing good strength and rigidity. The second conductive post 120 penetrates both the upper and lower surfaces of the substrate 110. The second circuit 130 is provided on both the upper and lower surfaces of the substrate 110, and the second circuit 130 communicates with the second conductive post 120. The second circuit 130 on the upper surface of the substrate 110 is connected to the second circuit 130 on the lower surface of the substrate 110 through the first conductive post 120 disposed within the substrate 110.

[0109] It should be noted that, in order to set the second conductive post 120 in the substrate 110, the second conductive post 120 can be formed in the substrate 110 by drilling and electroplating. In order to fabricate the second circuit 130 on the upper and lower surfaces of the substrate 110, a dry film lamination-exposure-development method can be used to open windows in the dry film to form windows corresponding to the second circuit 130, and then electroplating is performed on the entire board to form the second circuit 130 at the windows.

[0110] After preparing the substrate body 110, as follows Figure 3 As shown, a first conductive post 200 needs to be formed on the substrate body 100. It should be noted that the first conductive post 200 is located on the surface of the second circuit 130, thus communicating with the second circuit 130. To form the first conductive post 200, a metal seed layer is first formed on the surface of the substrate body 100 using methods such as magnetron sputtering, facilitating subsequent electroplating on the substrate body 100. Then, a photosensitive dry film is attached to the surface of the metal seed layer to protect areas of the substrate body 100 that do not require electroplating. The photosensitive dry film is then exposed and developed, creating a window on the photosensitive dry film corresponding to the position of the first conductive post 200, forming a first window. Finally, the entire substrate body 100 is electroplated, forming the first conductive post 200 at the first window.

[0111] Then, using a vacuum laminator, an adhesive first dielectric material 300 is applied to the surface of the substrate body 100, so that the first dielectric material 300 covers the surface of the substrate body 100 and the first conductive post 200. It should be noted that the first dielectric material 300 can simultaneously serve to bond the chip 400 and encapsulate the chip 400.

[0112] like Figure 5 As shown, in some embodiments of the present invention, a connection terminal 410 is provided at the bottom of the chip 400, and the chip 400 is placed upside down on the surface of the first dielectric material 300. Since the first dielectric material 300 is adhesive, it can fix the chip 400. Then, as... Figure 6As shown, the chip 400 needs to be pressed into the first dielectric material 300 by a vacuum laminator so that the surface of the chip 400 is connected to the second line 130.

[0113] It should be noted that the chip 400 is directly pressed into the first dielectric material 300 using a vacuum laminator, without the need for a pre-set cavity to place the chip 400. This direct placement and encapsulation of the chip 400 simplifies the process, shortens the product manufacturing cycle, and improves production efficiency. The surface of the chip 400 needs to be connected to the second circuit 130 to achieve electrical connection between the chip 400 and the circuit.

[0114] like Figure 7 As shown, after pressing the chip 400 into the first dielectric material 300, a second dielectric material 500 needs to be pressed onto the surface of the first dielectric material 300. It should be noted that the first dielectric material 300 and the second dielectric material 500 are made of the same material. By using the same material for the packaging medium, the reliability risks caused by the difference in the coefficient of thermal expansion (CTE) between different materials can be avoided.

[0115] like Figure 8 As shown, a blind hole 600 is formed in the second dielectric material 500 to communicate with the first conductive post 200 and the connecting terminal 410, so that the lines on the surface of the second dielectric material 500 can communicate with the second line 130 and the chip 400 through the blind hole.

[0116] Finally, as Figure 8 As shown, on the surface of the second dielectric material 500, the first line 700 is fabricated by applying dry film, exposing, developing, electroplating, and removing film. The first line 700 is connected to the blind via 600, and thus connected to the chip 400 and the second line 130.

[0117] According to the embedded packaging substrate structure of the present invention, a first dielectric material 300 and a second dielectric material 500 are used to bond the chip 400 and to encapsulate the chip 400 in plastic, which solves the reliability problem caused by CTE mismatch due to different materials of the embedded chip 400 in the prior art; before installing the chip 400, a portion of the interlayer conductive pillars (i.e., the first conductive pillar 200) can be prefabricated to reduce the depth of the vias and facilitate the subsequent electroplating to fill and flatten the blind via 600.

[0118] Although specific embodiments are described herein, those skilled in the art will recognize that many other modifications or alternative embodiments are also within the scope of this disclosure. For example, any of the functions and / or processing capabilities described in connection with a particular device or component can be performed by any other device or component. Furthermore, while various exemplary embodiments and architectures have been described according to embodiments of this disclosure, those skilled in the art will recognize that many other modifications to the exemplary embodiments and architectures described herein are also within the scope of this disclosure.

[0119] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A method for fabricating an embedded packaging substrate structure, characterized in that, Includes the following steps: Prepare the substrate body; A first conductive post is formed on the substrate body; A first dielectric material with adhesive properties is disposed on the surface of the substrate body; The first dielectric material covers the first conductive post; A chip is placed on the surface of the first dielectric material; The chip is pressed into the first dielectric material using a vacuum laminator; A second, viscous medium material is disposed on the surface of the first medium material; The first medium material and the second medium material are the same material; A blind via is fabricated within the second dielectric material, which communicates with the first conductive post and the chip; A first line communicating with the blind via is fabricated on the surface of the second dielectric material to form an embedded packaging substrate structure; The step of preparing the substrate body includes: Obtain the substrate; A second conductive post is provided in the substrate, and the second conductive post penetrates the upper surface and the lower surface of the substrate; A second circuit connected to the second conductive post is formed on the upper and lower surfaces of the substrate to form the substrate body; The chip has a connection terminal at its bottom; the step of pressing the chip into the first dielectric material using a vacuum laminator includes: The chip is placed upside down on the surface of the first dielectric material, with the connection terminals facing upwards; The chip is pressed into the first dielectric material using the vacuum laminator, so that the surface of the chip is connected to the second circuit.

2. The method of claim 1, wherein The step of forming the first conductive post on the substrate body includes: A metal seed layer is formed on the surface of the substrate body; A photosensitive dry film is attached to the surface of the metal seed layer; The photosensitive dry film is exposed and developed to form a first window corresponding to the first conductive post; The substrate body is electroplated to form the first conductive post at the first window; Remove the photosensitive dry film and etch the metal seed layer on the surface of the substrate body.

3. The method of claim 1, wherein The step of applying a first adhesive dielectric material to the surface of the substrate body includes: A first dielectric material with adhesive properties is pressed onto the surface of the substrate body using a vacuum laminator, so that the first dielectric material covers the surface of the substrate body and the first conductive post.

4. The method of claim 1, wherein The step of fabricating a blind via communicating with the first conductive post and the chip within the second dielectric material includes: Laser drilling is performed on the second dielectric material to form a through hole penetrating the second dielectric material; The blind hole is formed by electroplating inside the through hole, and the blind hole is connected to the first conductive post and the connecting terminal.

5. A flip chip package substrate structure, comprising: The embedded packaging substrate structure is manufactured by the method of manufacturing the embedded packaging substrate structure according to any one of claims 1-4, the embedded packaging substrate structure comprising: substrate body; The first conductive post is disposed on the surface of the substrate body; A first dielectric material with adhesive properties is disposed on the surface of the substrate body and covers the first conductive post; The chip is disposed within the first dielectric material; A second, viscous medium material is disposed on the surface of the first medium material, wherein the first medium material and the second medium material are the same material; A blind via is disposed within the second dielectric material, and the blind via is connected to the first conductive post and the chip. A first line is disposed on the surface of the second dielectric material, and the first line is connected to the blind hole; The substrate body includes a substrate, a second conductive post, and a second circuit. The second conductive post is disposed within the substrate and penetrates the upper and lower surfaces of the substrate. The second circuit is disposed on the upper and lower surfaces of the substrate and is connected to the second conductive post. The bottom of the chip is provided with a connection terminal, which is connected to the blind hole, and the surface of the chip is connected to the second line.

6. The flip-chip package substrate structure of claim 5, wherein, The chip is pressed into the first dielectric material by a vacuum press.

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