A digital filter structure based on FPGA

Abstract

This invention relates to the field of digital filter technology and proposes an FPGA-based digital filter structure. This structure combines the Radix-4 Booth multiplier structure with the DA algorithm, and includes a multiplier encoder generator, a partial product generation and superposition unit, and a shift accumulator. The multiplier encoder generator produces three-dimensional coefficients for generating partial products; the partial product generation and superposition unit obtains the partial product based on the three-dimensional coefficients and input data, and superimposes it with the intermediate result from the previous stage to obtain the intermediate result of the current stage; the shift accumulator performs shift-based summation of the partial products. Compared with traditional structures, this invention shortens the number of clock cycles and reduces hardware resources, resulting in significant advantages in overall performance.

Description

Technical Field

[0001] This invention relates to the field of digital filter technology, and specifically to a digital filter structure and construction method on an FPGA. Background Technology

[0002] Currently, digital filters are a key technology in the field of digital signal processing. They are mainly used to reduce useless information or enhance useful information from input signals. With the development of information technology, digital filters are being used more and more widely, such as in audio processing, image processing, and communication systems.

[0003] Digital filters can be classified into infinite impulse response (IIR) filters and finite impulse response (FIR) filters based on the nature of their impulse response. Compared with IIR filters, FIR filters have advantages such as better linear phase characteristics, stronger stability, and readily available hardware implementation.

[0004] FPGA-based FIR filters are one of the more popular research directions in the field of digital signal processing. Adders and multipliers, as important components of FIR filters, directly affect the overall performance of the filter due to their speed, area, and other properties.

[0005] Distributed algorithms (DA) are commonly used in the optimization design of FIR filters. This algorithm splits the input digital signal bit by bit, transforming the multiplication and addition operations with fixed coefficients into simple lookup table operations and shift-accumulation operations.

[0006] For an FIR filter containing N product terms, its output y is the input. Sum of coefficients The sum of the products:

[0007] in, and (0≤k≤N-1) represent the k-th coefficient and its corresponding input, respectively; for a coefficient with a bit width of L... , can be represented as:

[0008] yes The The value of the bit. Therefore, the output y can be expanded as:

[0009] Partial product in the above formula There are N inputs With corresponding coefficient The kth position The sum of the products For partial accumulation The output y is obtained by shifting and accumulating.

[0010] Booth multipliers are efficient signed multipliers widely used in hardware design. Their basic principle is to encode the multiplier, combining multiple basic multiplication operations into a single, more complex operation, thus reducing the number of partial products and consequently the number of additions required. The Radix-4 Booth multiplier is an extension of the traditional Booth multiplier, using 3-bit groups to encode the multiplier. For example, in 8-bit multiplication, assuming the multiplier is B, its expansion is:

[0011]

[0012] Based on the expansion of B above, we can obtain ; among which part of the product With multiplier encoding The correspondence is shown in Table 1: Table 1. Correspondence between multiplier codes and partial products 000 0 001 A 010 A 011 2A 100 -2A 101 -A 110 -A 111 0 Summary of the Invention

[0013] This invention proposes a novel digital filter structure that combines the Radix-4 Booth multiplier structure with the DA algorithm concept, and implements it using a Xilinx FPGA. This invention reduces the number of clock cycles required by traditional DA algorithms while also reducing the required hardware resources.

[0014] The algorithm proposed in this invention substitutes the Radix-4 Booth expansion of the coefficients into the FIR filter output formula, as shown in the following formula:

[0015]

[0016] Where N represents the number of product terms in the FIR filter, and M represents the coefficients. bit width, It is a partial product sum.

[0017] Figure 1 The filter structure diagram of the present invention is shown;

[0018] like Figure 1 As shown, the present invention comprises three parts: a coefficient encoding generator, a partial product generation and superposition unit, and a shift accumulator.

[0019] The coefficient encoder generator is used to generate the three-dimensional coefficients used to generate the partial product in the above algorithm. };

[0020] Partial product generation and superposition units consist of three-dimensional coefficients Input data Obtain the partial product and combine it with the intermediate result from the previous level. The intermediate results at this level are obtained by superposition. ;

[0021] Figure 1 As shown That is, the sum of partial products;

[0022] A shift accumulator is used to perform shift summation of partial products. Attached Figure Description

[0023] Figure 1 This is a structural diagram of the FIR filter of the present invention;

[0024] Figure 2 This is a structural diagram of the coefficient encoding generator of the present invention;

[0025] Figure 3 This is a structural diagram of the partially multiplied superimposed unit generated by the present invention. Detailed Implementation

[0026] To make the structure, technical solution, and advantages of the invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not constitute a limitation thereof.

[0027] Figure 2 A structural diagram of the three-digit coefficient generation part is given;

[0028] like Figure 2 As shown, two LUT6-2 (six-input two-output lookup tables in Xilinx FPGAs) are configured as two-output 32-bit shift registers, where Q is the output of bit 0 of the shift register and Q31 is the output of bit 32 of the shift register. Shift register 1 stores the numbers at the odd-numbered positions of the coefficients. }, Shift register 2 stores the number of even-numbered bits of the coefficient. } Therefore, the Q31 pin of shift register 1 and the Q and Q31 ports of shift register 2 generate the required three-dimensional coefficients. }

[0029] Figure 3 The structural diagram of the partially multiplied superimposed unit is given;

[0030] like Figure 3 As shown, the partial product generation stacking unit consists of multiple LUT6-2s and CARRY (a carry chain structure in Xilinx FPGA); the LUT6-2 inputs are three-digit coefficients and inputs respectively. and the intermediate results of the previous level ;CARRY's output is the intermediate result of this level. (Where k represents the k-th product term, and n represents the n-th bit of the input / output signal). The sum of the partial products can be obtained by cascading multiple partial product units (the number of cascaded units is the number of product terms in the FIR filter);

[0031] Because the three coefficients are updated with each clock cycle, a new sum of partial products is obtained each clock cycle.

[0032] Figure 1 The shift accumulator in the clock cycle right-shifts the accumulated result of the previous clock cycle by two bits and sums the partial product of this sum with the result of the current clock cycle. This process is repeated. Repeat this process until the final result, the output of the FIR filter, is obtained.

[0033] To further demonstrate the advantages of the structure of this invention, the structure proposed in this invention and the formula in

[0006] were designed and implemented using a hardware description language. The corresponding direct implementation structure is then synthesized, and a comprehensive performance index is calculated as "number of LUTs consumed * number of computation cycles used * maximum path delay". A lower number of LUTs consumed indicates less hardware resource consumption, while a lower number of computation cycles and maximum path delay indicate faster computation speed. Therefore, the smaller the value of "number of LUTs consumed * number of computation cycles used * maximum path delay", the better the overall performance of the corresponding circuit.

[0034] Table 2 summarizes the results of the present invention for different numbers of product terms and filter coefficients. ) and input data ( The overall performance of the FIR filter implementation circuit with a bit width is ("number of LUTs consumed * number of cycles used in operation * maximum path delay").

[0035] Table 2. Overall performance of the circuit structure of this invention 4 360.16 1134.24 2353.698 3966.4 8 972.944 3065.952 6440.352 10959.912 16 3010.608 9291.424 19483.686 32832 32 10345.716 31508.232 6514.02 108715.392

[0036] Table 3 summarizes the direct implementation structure of FIR filters for different numbers of product terms and filter coefficients. ) and input data ( The overall performance of the FIR filter implementation circuit with a bit width is ("number of LUTs consumed * number of cycles used in operation * maximum path delay").

[0037] Table 3. Overall performance of the FIR filter direct implementation circuit. 4 448.448 1502.14 4403.488 7953.18 8 1500.96 4503.844 13117.08 22692.208 16 6399.991 14941.098 39762.24 69363.864 32 20876.744 54541.408 134899.792 231272.184

[0038] By comparing the statistical results in Tables 2 and 3, the overall performance of the structure proposed in this invention has obvious advantages, and these advantages increase significantly with the increase of the order.

[0039] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

Claims

1. A digital filter structure based on FPGA, characterized in that: The digital filter structure, comprising a coefficient encoder generator, a partial product generation and superposition unit, and a shift accumulator, adopts a design combining a Radix-4 Booth multiplier structure with a distributed algorithm (DA). Substituting the Radix-4 Booth expansion into the FIR filter output formula, the filter output is achieved through three-digit coefficient encoding, partial product superposition, and shift accumulation. The specific formula is as follows: N represents the number of product terms in the FIR filter, and M represents the coefficients. bit width, It is a partial product sum; The coefficient encoder consists of two output 32-bit shift registers configured as LUT6-2s in two Xilinx FPGAs; shift register 1 stores the odd-numbered bits of the coefficients. }, shift register 2 stores the number of even-numbered bits of the coefficient. }, i=0,1… Three-dimensional coefficients are generated through the Q31 input of shift register 1 and the Q and Q31 ports of shift register 2. }; Partial product generation stacking units are directly composed of LUT6-2 and CARRY, based on three-dimensional coefficients. Input data Generate a partial product and combine it with the intermediate result from the previous level. The intermediate results at this level are obtained by superposition. The sum of partial products can be obtained by cascading multiple partial product units to generate a superposition unit. A shift accumulator is used to achieve the shift summation of the partial product.

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