All-digital-to-analog converter based on shift current mirror architecture and multi-segment data weighted average algorithm, and preparation method and device thereof

Abstract

A kind of full comprehensive digital-analog converter based on shift current mirror architecture and multi-section data weighted average algorithm, and its preparation method and equipment, DAC adopts shift current mirror architecture and multi-section data weighted average (MSeDWA) algorithm, by integrating programmable bias current generator, the influence of process, voltage and temperature (PVT) variation on circuit performance is effectively compensated, the stability and adaptability of DAC are significantly improved.In addition, the introduction of power gating standard cell makes the selection of current mirror type more flexible, thereby widening the operating voltage range of DAC.In terms of circuit design, the present application adopts multi-stage separation and gain configuration strategy, including fixed gain stage and variable gain stage, to optimize conversion linearity and meet the needs of different application scenarios.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit design and electronic engineering, and in particular to a fully integrated digital-to-analog converter based on a shift current mirror architecture and a multi-segment data weighted averaging algorithm. Background Technology

[0002] In integrated circuit and electronic system design, digital-to-analog converters (DACs) play a crucial role in converting digital signals into analog signals, serving as a bridge for interaction between electronic systems and real-world analog environments. For example, fields such as audio output, sensor signal processing, and wireless communication rely on high-performance DACs to ensure that digital data is accurately converted into analog signals, thereby enabling efficient information transmission and processing.

[0003] In recent years, with the advancement of CMOS technology and the maturity of digital circuit design methodologies, fully integrated DAC technology has emerged and become a research hotspot. Fully integrated DACs abandon the complex design of traditional analog circuits, instead employing a circuit design method entirely based on digital standard cells. They automatically generate circuit netlists and layouts using Electronic Design Automation (EDA) tools, thereby reducing design difficulty and time. Fully integrated DACs not only possess high portability and scalability, making them suitable for designs under rapid process evolution, but also can leverage the design characteristics of standard cells to reuse them in different manufacturing processes.

[0004] Existing fully integrated DAC designs are mainly divided into two categories: DACs based on calibration algorithms and DACs based on logic gate arrays. The former uses digital pulse modulators (such as Δ-Σ modulators) to calibrate the unit DAC output, improving the DAC's resolution and linearity by eliminating high-frequency noise in a low-pass filter. While this method can achieve high resolution at low speeds, it requires a high sampling rate to maintain signal accuracy, resulting in a significant trade-off between power consumption and speed. The latter utilizes standard logic gates (such as NAND and NOR gates) to generate voltage or current outputs, supporting conversion speeds at the Nyquist frequency. However, its driving capability is limited by the matching performance of P / N channel transistors, making it difficult to achieve high linearity, especially in high-speed applications.

[0005] While existing fully integrated DACs meet certain application requirements to some extent, they still present numerous challenges in areas such as PVT adaptability, operating voltage range, linearity, and energy efficiency. Therefore, exploring more efficient, stable, and low-power fully integrated DAC design technologies is of paramount importance. Summary of the Invention

[0006] To address the aforementioned issues, this invention proposes a fully integrated DAC based on a shifted current mirror architecture and a multi-segment weighted average (MSeDWA) algorithm. It is entirely based on standard digital cells and utilizes electronic design automation (EDA) tools for automated circuit netlist generation and placement, exhibiting high portability and scalability. The introduction of a programmable bias current generator effectively suppresses the impact of PVT variations on the circuit, improving DAC stability. Simultaneously, the use of power-gated standard cells allows for flexible selection of the current mirror, thereby expanding the operating voltage range. The multi-segment weighted average algorithm further optimizes linearity and reduces THD, meeting the requirements for high-precision and high-efficiency conversion. By optimizing the circuit gain configuration, this invention can also achieve high-efficiency output in various application scenarios, making it suitable for systems with stringent requirements for linearity, power consumption, and energy efficiency.

[0007] The technical solution of the present invention is as follows:

[0008] A fully integrated digital-to-analog converter with a shift current mirror architecture and a multi-segment data weighted averaging algorithm, characterized by including:

[0009] The programmable bias current generator, consisting of a digital-to-analog voltage converter (DAC) composed of NAND logic gates, is used to generate and control the bias current of the current mirror and dynamically adjust the current output to achieve dynamic compensation for process, voltage and temperature (PVT) variations in the circuit.

[0010] The shifted current mirror architecture divides the current mirror into multiple controllable segments, each containing several current units, which can be turned on or off step by step as needed to reduce mismatch errors between current segments and improve linearity.

[0011] The Multi-Segment Data Weighted Average (MSeDWA) module is used to perform segmented weighted processing on the DAC input data and dynamically adjust the weight of the current in each segment to reduce signal distortion caused by mismatch.

[0012] The system includes a fixed gain stage and a variable gain stage, wherein the fixed gain stage is used for gain amplification of the base current, and the variable gain stage is used for further current regulation, thereby optimizing the overall conversion accuracy through multi-stage gain configuration. The all-digital standard unit is used to implement the DAC function and automatically generates the circuit netlist and layout through electronic design automation tools, improving portability and scalability.

[0013] Furthermore, the programmable bias current generator also includes a standard power gating unit for converting voltage signals into the required bias current and enabling flexible switching between different current mirror types to adapt to different operating conditions and current requirements.

[0014] Furthermore, each current unit in the shift current mirror architecture is independently controlled by a programmable gain factor to achieve precise adjustment of the current amplification factor.

[0015] Furthermore, the MSeDWA module divides the input data into several segments, assigning different weighting coefficients to each segment to reduce signal distortion caused by mismatch and to reduce total harmonic distortion (THD).

[0016] Furthermore, it also includes an automated gain configuration process, enabling fixed-gain and variable-gain stages to flexibly adjust their gain values ​​according to the input control signal to adapt to different frequency and current output requirements.

[0017] Furthermore, the EDA tool employs a dedicated layout algorithm to achieve the optimal arrangement of current elements, thereby reducing the differences in current transmission paths and parasitic effects between elements and improving the accuracy of current output.

[0018] Second, the present invention also provides a method for manufacturing the above-mentioned DAC, characterized in that it includes: a) designing the circuit netlist and layout of the DAC using electronic design automation (EDA) tools; b) manufacturing the hardware circuit of the DAC according to the designed circuit netlist and layout; c) calibrating and testing the manufactured DAC to ensure that it meets predetermined performance requirements.

[0019] Third, the present invention also provides an electronic device, characterized in that it includes the above-mentioned DAC, which is used to convert digital signals into analog signals and is suitable for application scenarios such as wireless communication, precision sensors and Internet of Things devices.

[0020] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0021] 1) It boasts advantages such as high integration, low power consumption, and high energy efficiency, effectively addressing the shortcomings of traditional DACs in terms of accuracy, linearity, and PVT adaptability. By implementing circuit functions using standard digital units, the DAC of this invention can be quickly ported to different process platforms, making it suitable for a wide range of applications, such as precision sensors, wireless communication, the Internet of Things, and high-performance audio equipment.

[0022] 2) Tests show that the DAC of the present invention can provide low power consumption and high energy efficiency output performance when operating in the frequency range of 14 MHz to 56 MHz, and its total harmonic distortion (THD) remains below 39.9 dB.

[0023] 3) The addition of a programmable bias current generator enables the circuit to suppress current drift by more than 2.7 times under varying PVT conditions, further improving the circuit's applicability and stability. It has broad application prospects in applications requiring high precision and efficiency, such as wireless communication, precision sensors, the Internet of Things, and audio signal processing.

[0024] 4) This design overcomes the shortcomings of traditional fully integrated DACs in terms of accuracy, linearity, and PVT adaptability. It not only boasts high energy efficiency, low power consumption, and high integration, but is also suitable for various applications with high DAC performance requirements. Through a fully digital design approach, this invention achieves low-cost, short-cycle product development, providing a novel and effective solution for high-performance DAC design. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a fully integrated digital-to-analog converter architecture based on standard cells;

[0026] Figure 2 This is a schematic diagram of a flexibly configurable current mirror architecture based on a power gating unit.

[0027] Figure 3 A schematic diagram illustrating the working principle of a weighted average algorithm for multiple data segments;

[0028] Figure 4 A flowchart for the automated generation of a fully integrated DAC circuit. Detailed Implementation

[0029] To make the objectives, advantages, technical solutions, and implementation methods of this invention clearer, the invention will be further described in detail below with reference to the embodiments and accompanying drawings, but this should not limit the scope of protection of this invention.

[0030] This embodiment provides a fully integrated digital-to-analog converter (DAC) based on a shift current mirror architecture and a multi-segment data weighted average (MSeDWA) algorithm. This DAC is composed entirely of standard digital units and utilizes electronic design automation (EDA) tools to achieve automated circuit netlist generation and layout design. This not only improves the portability and scalability of the DAC, but also effectively reduces design costs and shortens the development cycle.

[0031] like Figure 1 As shown, this DAC mainly consists of a programmable bias current generator, a fixed gain stage, a variable gain stage, and a multi-segment data weighted averaging (MSeDWA) module. These components work together to achieve high-precision, low-distortion digital-to-analog conversion. The specific circuit implementation method is as follows:

[0032] First, this invention designs a programmable bias current generator to generate and control the bias current of a current mirror, thereby achieving dynamic compensation for PVT (process, voltage, and temperature) variations in the circuit. This bias current generator constructs a 5-bit digital-to-analog voltage converter (DAC) using NAND logic gates, generating different bias voltage signals based on the input digital signal. This voltage signal is then converted into the desired bias current after passing through a standard power-gated cell. The current mirror architecture amplifies the bias current and drives the DAC's output stage to achieve higher signal strength and voltage output range. Figure 2 As shown, through the power supply gating unit, the programmable bias current generator can flexibly switch between different current mirror types without affecting the overall performance of the circuit, thereby adapting to different working conditions and current requirements, and improving the reliability and operating range of the circuit.

[0033] In the design of the current mirror architecture, this invention employs a shifted current mirror approach to reduce mismatch errors between various current sources. The shifted current mirror structure divides the current mirror into multiple controllable segments, each containing several current units that can be turned on or off sequentially as needed, reducing current deviation and improving linearity. The current mirror architecture includes a "fixed gain" stage and a "variable gain" stage. The "fixed gain" stage is used for gain amplification of the base current, while the "variable gain" stage is used for further current regulation, optimizing overall conversion accuracy through multi-stage gain configuration. In the "fixed gain" stage, this invention uses a power gating unit as a key unit in forming the current mirror. Through a programmable gain factor, the current amplification factor is adjusted to ensure current output requirements under different application scenarios. This design effectively reduces current drift caused by PVT variations, enabling the circuit to remain stable under high temperature and low voltage environments.

[0034] To further reduce mismatch error, this invention also introduces a multi-segment weighted average (MSeDWA) algorithm. For example... Figure 3 As shown, the MSeDWA algorithm reduces signal distortion caused by mismatch by dynamically adjusting the weight of each segment of the DAC input data through segmented weighting. Specifically, the algorithm divides the input data into several segments, assigning different weighting coefficients to each segment to balance the overall current output. This technique effectively reduces the total harmonic distortion (THD) of the signal and improves the linearity of the DAC output. Through multi-segment weight adjustment, the MSeDWA algorithm can compensate for mismatches between current mirror units and suppress unwanted frequency components in the high-frequency region, thus forming a cleaner analog signal at the output. This design not only ensures high-precision DAC output but also achieves dynamic correction of mismatch errors.

[0035] Furthermore, to meet varying frequency and accuracy requirements, this invention employs an automated gain configuration process. This allows the current mirror's "fixed gain" and "variable gain" stages to flexibly adjust their gain values ​​based on the input control signal, adapting to different frequency and current output demands. In implementation, the current mirror's gain configuration provides an independent gain factor for each input current segment, ensuring the DAC's output stability and linearity under diverse operating conditions. Especially in high-frequency output scenarios, by adjusting the gain setting of the "variable gain" stage, the DAC can quickly respond to frequency changes and maintain a stable output current amplitude, thereby meeting complex signal conversion requirements.

[0036] Regarding netlist generation and placement, the DAC design of this invention is entirely based on standard digital cells. The circuit netlist is automatically generated using EDA tools, and a dedicated placement algorithm achieves the optimal arrangement of current-carrying elements. With the assistance of EDA tools, this invention can consider the impact of random mismatches and process mismatches on circuit performance during the design process, thereby optimizing the placement of current mirror cells to achieve optimal linearity and minimize circuit area. The placement algorithm automatically distributes each current cell and adjusts the position of components based on circuit simulation results to reduce differences in current transport paths and parasitic effects between components, thereby improving the accuracy of current output.

[0037] By employing a fully integrated design approach, the implementation process of the DAC in this invention is significantly simplified. It can shorten the design cycle and reduce development costs without sacrificing performance, while simultaneously achieving higher reliability and process adaptability. Its automated design process is as follows: Figure 4 As shown in the figure. Test results demonstrate that the DAC of this invention provides low power consumption and high energy efficiency when operating in the frequency range of 14 MHz to 56 MHz, with its total harmonic distortion (THD) remaining below 39.9 dB, exhibiting good linearity and energy efficiency. Furthermore, the addition of a programmable bias current generator improves the current offset suppression under varying PVT conditions by more than 2.7 times, further enhancing the circuit's applicability and stability. This design has broad application prospects in applications requiring high precision and high efficiency, such as wireless communication, precision sensors, the Internet of Things, and audio signal processing.

[0038] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A fully integrated digital-to-analog converter with a shift current mirror architecture and a multi-segment data weighted averaging algorithm, characterized in that, include: The programmable bias current generator, consisting of a digital-to-analog voltage converter (DAC) composed of NAND logic gates, is used to generate and control the bias current of the current mirror and dynamically adjust the current output to achieve dynamic compensation for process, voltage and temperature (PVT) variations in the circuit. The shifted current mirror architecture divides the current mirror into multiple controllable segments, each containing several current units, which can be turned on or off step by step as needed to reduce mismatch errors between current segments and improve linearity. The Multi-Segment Data Weighted Average (MSeDWA) module is used to perform segmented weighted processing on the DAC input data and dynamically adjust the weight of the current in each segment to reduce signal distortion caused by mismatch. The system includes a fixed gain stage and a variable gain stage, wherein the fixed gain stage is used for gain amplification of the base current, and the variable gain stage is used for further current adjustment. The overall conversion accuracy is optimized through multi-stage gain configuration. A fully digital standard unit is used to implement the DAC function and automatically generate circuit netlists and layouts through electronic design automation tools, improving portability and scalability. Among them, the programmable bias current generator, fixed gain stage and variable gain stage are cascaded in sequence, all built by the shift current mirror architecture, and the multi-segment data weighted average (MSeDWA) module is used to generate the control signal for the shift current mirror of each stage circuit; This DAC circuit is built using all-digital standard cells and automatically generates the circuit netlist and layout using electronic design automation tools, improving portability and scalability. The programmable bias current generator also includes a standard power gating unit for converting voltage signals into the required bias current and enabling flexible switching between different current mirror types to adapt to different operating conditions and current requirements.

2. The fully integrated digital-to-analog converter with shift current mirror architecture and multi-segment data weighted averaging algorithm according to claim 1, characterized in that, Each current unit in the shift current mirror architecture is independently controlled by a programmable gain factor to achieve precise adjustment of the current amplification factor.

3. The fully integrated digital-to-analog converter with shift current mirror architecture and multi-segment data weighted averaging algorithm according to claim 1, characterized in that, The Multi-Segment Data Weighted Average (MSeDWA) module divides the input data into several segments, assigning different weighting coefficients to each segment to reduce signal distortion caused by mismatch and reduce total harmonic distortion (THD).

4. The fully integrated digital-to-analog converter based on the shift current mirror architecture and multi-segment data weighted averaging algorithm according to any one of claims 1-3, characterized in that, It also includes an automated gain configuration process, enabling fixed-gain and variable-gain stages to flexibly adjust their gain values ​​according to the input control signal to adapt to different frequency and current output requirements.

5. The fully integrated digital-to-analog converter with shift current mirror architecture and multi-segment data weighted averaging algorithm according to claim 1, characterized in that, The electronic design automation tool employs a dedicated layout algorithm to achieve optimal arrangement of current components, thereby reducing differences in current transmission paths and parasitic effects between components and improving the accuracy of current output.

6. A method for manufacturing a fully integrated digital-to-analog converter with a shift current mirror architecture and a multi-segment data weighted averaging algorithm as described in any one of claims 1 to 5, characterized in that, include: a) Design the circuit netlist and layout of the DAC using electronic design automation (EDA) tools; b) Based on the designed circuit netlist and layout, manufacture the hardware circuitry for the DAC; c) The manufactured DAC is calibrated and tested to ensure that it meets the predetermined performance requirements.

7. An electronic device, characterized in that, The DAC included in any one of claims 1 to 5 is used to convert digital signals into analog signals and is suitable for wireless communication, precision sensor and Internet of Things (IoT) device applications.

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