A multi-queue scheduler and scheduling method

Abstract

The application provides a multi-queue scheduler and a scheduling method, the multi-queue scheduler comprising: a queue type distinguishing module for classifying data packets; a port scheduler module for calculating a port characteristic value of a port to which data packet information belongs when receiving data; and calculating an optimal port when scheduling out of queue; a queue scheduler module for calculating a queue characteristic value and entering data packet information when receiving data; and calculating an optimal queue and scheduling out of queue when scheduling out of queue. The application has the advantages that: the scheduling algorithm can be independently modified and replaced without affecting other parts of the scheduler, and the application has good flexibility, scalability and maintainability; the application can be customized and expanded according to the requirements and characteristics of the system, the number of queues can be increased or modified according to the actual situation, the priority rules and the scheduling algorithm can be adjusted, the characteristic value state called by the queue scheduler is maintained in the BRAM, the scalability is strong, and the resource consumption is basically unchanged within the BRAM depth.

Description

Technical Field

[0001] This invention belongs to the field of data communication technology, and specifically relates to programmable switching devices such as FPGA-based programmable switches or ASIC-based programmable switching chips, and to multi-queue schedulers and scheduling algorithms, specifically to a multi-queue scheduler and scheduling method. Background Technology

[0002] In high-speed network switching and application layer multicast, multiple input and output ports exist, leading to a mismatch between input traffic and output bandwidth. When a sudden surge in input traffic occurs, the volume of input traffic may exceed the port's output capacity within a short period, potentially causing the output port's hardware queue to overflow and resulting in packet loss. Traditional schedulers typically use a single queue to manage all tasks; however, with the development of computer systems and the widespread adoption of multi-core processors, single-queue schedulers have gradually revealed several problems:

[0003] 1. Fairness issues caused by a single queue: In traditional single-queue schedulers, all incoming packets are placed in the same queue. However, different data streams may require different priorities. For example, some data streams may have high real-time requirements, while others may not have strict limitations on bandwidth consumption. A single queue cannot meet this diverse need of different data streams.

[0004] 2. Performance issues caused by a single queue: When processing large data streams, the performance of a single-queue scheduler may be affected. Because all packets need to wait in the queue, the waiting time can increase with the amount of data flowing through the stream, potentially causing delays for some packets.

[0005] 3. Inability to handle bursts of traffic: In certain situations, such as large data transfers, video streaming, or gaming, data traffic may burst. A single-queue scheduler may not be able to effectively handle such bursts because it does not provide a dedicated channel for them.

[0006] 4. Lack of fine-grained control: A single-queue scheduler cannot provide fine-grained control over each data stream. For example, it cannot set higher priorities for specific data streams or provide lower latency for certain data streams. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of existing schedulers, such as poor fairness, low performance, inability to effectively handle burst traffic, and lack of fine-grained control.

[0008] To achieve the above objectives, this invention proposes a multi-queue scheduler, which includes: a queue type differentiation module, a port scheduler module, and a queue scheduler module; wherein,

[0009] The queue type differentiation module is used to classify data packets according to the data packet description information when the multi-queue scheduler receives the data packet description information;

[0010] The port scheduler module is used to calculate the port feature value of the port to which the description information of the incoming data packet belongs and update the port information according to the port scheduling policy when receiving data; when scheduling out of the queue, it obtains the port with the best port feature value by comparison and updates the port information.

[0011] The queue scheduler module is used to calculate the queue feature value of the data packet description information according to the queue scheduling policy and queue type when receiving data, and to enqueue the data packet description information; when scheduling dequeue, it compares and selects the head element of the queue with the best feature value under the port, and then schedules the dequeue.

[0012] As an improvement to the aforementioned multi-queue scheduler, the port scheduler module includes logical resources; port numbers and corresponding port feature values ​​are maintained in the logical resources; the port scheduler selects a suitable port by comparing the port feature values ​​generated according to the port scheduling strategy.

[0013] As an improvement to the aforementioned multi-queue scheduler, the port scheduler module also includes multiple peer comparators, each of which is responsible for scheduling a portion of the ports.

[0014] As an improvement to the aforementioned multi-queue scheduler, the queue scheduler module includes on-chip memory and logical resources. Using the port number as the address index, the on-chip memory stores the queue characteristic value of the data packet description information for each queue under each port.

[0015] As an improvement to the aforementioned multi-queue scheduler, the multi-queue scheduler further includes a port scheduling policy module for storing port scheduling policies; the port scheduler module obtains the port scheduling policy from the port scheduling policy module.

[0016] As an improvement to the aforementioned multi-queue scheduler, the multi-queue scheduler further includes a queue scheduling policy module for storing queue scheduling policies; the queue scheduler module obtains the queue scheduling policy from the queue scheduling policy module.

[0017] The present invention also provides a multi-queue scheduling method, implemented based on the above-mentioned multi-queue scheduler, the method comprising:

[0018] When the multi-queue scheduler receives data packet description information, the queue type differentiation module classifies the data packets according to the data packet description information;

[0019] The port scheduler module calculates the port characteristic value of the port to which the description information of the incoming data packet belongs, and updates the port information according to the port scheduling policy;

[0020] The queue scheduler module calculates queue feature values ​​for packet description information based on the queue scheduling policy and queue type, and then enqueues the packet description information.

[0021] As an improvement to the above method, the method further includes:

[0022] When scheduling out of the queue, the port scheduler module obtains the port with the best port characteristic value by comparison;

[0023] The queue scheduler module compares and selects the head element of the queue with the best feature value under the port, and then schedules it to be dequeued.

[0024] The port scheduler module updates port information.

[0025] As an improvement to the above method, in the port scheduler module, the port information is updated when data packets are enqueued and dequeued;

[0026] When a queue ID is enqueued for a previously empty port, the port information is updated, and the port participates in port scheduling contention. When a packet description is dequeued, the head element of the queue it maps to is also scheduled away. The port that stores the queue ID of the packet description then deletes the queue ID. If there is still data in the queue, it needs to be re-enqueued.

[0027] Compared with the prior art, the advantages of the present invention are:

[0028] 1. This invention decouples the scheduler from the scheduling algorithm, allowing the scheduling algorithm to be modified and replaced independently without affecting other parts of the scheduler, thus exhibiting good flexibility, scalability, and maintainability;

[0029] 2. It adopts a two-level scheduling structure, which can be customized and expanded according to the needs and characteristics of the system, and the number of queues can be increased or modified according to the actual situation, and priority rules and scheduling algorithms can be adjusted.

[0030] 3. The characteristic value status of the queue scheduler call is maintained in BRAM, which has strong scalability. The resource consumption remains basically unchanged when the number of expansions is within 512. Attached Figure Description

[0031] Figure 1 The diagram shown is an overall framework diagram of the multi-queue scheduler.

[0032] Figure 2 The diagram shown is an architecture diagram of the multi-queue scheduling module;

[0033] Figure 3 The diagram shown is a multi-comparator architecture diagram of the port scheduler module.

[0034] Figure 4 The diagram shows the signal format when a data packet descriptor is enqueued.

[0035] Figure 5 The diagram shows the packet descriptor format of the multi-queue scheduler's output.

[0036] Figure 6 The diagram shown is a flowchart of the port scheduler module information re-entry queue. Detailed Implementation

[0037] To achieve a multi-queue scheduler capable of providing higher throughput and better handling network traffic bursts, this invention proposes a multi-queue scheduler and scheduling method, applicable to switching devices such as FPGA-based programmable switches or ASIC-based programmable switching chips. The scheduler's operation is as follows: After data packets are stored in the buffer, their description information is passed to the scheduler. After flow classification, the port scheduling module enqueues the corresponding port information and calculates the corresponding port feature value according to the port scheduling policy; the queue scheduling module calculates the feature value of the enqueued data packet element according to the queue scheduling policy. During dequeueing, a two-level scheduling process is performed, scheduling the highest-priority queue element under the port with the highest priority feature value.

[0038] The multi-queue scheduler and scheduling method provided by this invention include a queue type differentiation module, a queue scheduler module, a port scheduler module, a port scheduling strategy module, and a queue scheduling strategy module. The specific process is as follows: the entire scheduling structure adopts a two-level scheduling approach. When data packet information enters the scheduler, it first enters the queue type differentiation module for feature parsing. The port scheduling module calculates the feature value of the port to which the incoming data packet belongs based on the port scheduling strategy. The queue scheduling module also calculates the feature value of the data packet based on the queue scheduling strategy and queue type. When scheduling dequeueing, the port scheduler first obtains the port with the best feature value through comparison, and the queue scheduler then selects the head element of the queue with the best feature value under the port with the best feature value through comparison and performs dequeueing.

[0039] The implementation steps of the queue type differentiation module are as follows: Different feature values ​​need to be extracted and differentiated for queues when different scheduling algorithms are used. When the multi-queue scheduler receives a data packet, it classifies the data packet according to the data packet description information. For example, it distinguishes between priority and non-priority, and between order-preserving and non-order-preserving, etc. Feature value mapping needs to be performed according to the specific scheduling algorithm used.

[0040] The implementation steps of the queue scheduler module are as follows: The queue scheduler can allocate appropriate resources to different queues or tasks based on resource availability and demand. When receiving data, the queue scheduler module calculates the queue characteristic value of the data packet according to the queue scheduling policy and queue type, and enqueues the data packet information. When dequeuing, the queue scheduler module compares and selects the head element of the queue with the best characteristic value under the port, and then performs the dequeueing. The queue scheduler module includes on-chip memory (BRAM) and logic resources (logic gates, registers, lookup tables, etc.), using the port number as the address index, and stores the queue characteristic value of each data packet under each port in the on-chip memory.

[0041] The queue scheduler module ensures that each queue or task receives the necessary computational, storage, and communication resources for optimal performance and efficiency. It can also determine the execution order of queues or tasks based on their priorities. By setting different priorities for different queues or tasks, high-priority queues or tasks can be processed promptly, thus meeting the time sensitivity requirements of critical tasks. Most importantly, the queue scheduler uses specific scheduling algorithms to determine when to execute tasks in which queue. These algorithms can schedule and order tasks based on various strategies and objectives, such as fairness, response time, and throughput.

[0042] The implementation steps of the port scheduler module are as follows: The port scheduler manages and allocates input / output (I / O) port resources to meet the needs of multiple devices or tasks for these ports. When receiving data, the port scheduler module calculates the port characteristic value of the port to which the incoming data packet belongs, according to the port scheduling policy, and updates the port information. When scheduling data out of the queue, the port scheduler module compares the ports to find the port with the best characteristic value and updates the port information. The port scheduler module includes logical resources (registers or BlockRAM); the port number and corresponding port characteristic value are maintained in the logical resources; by comparing the port characteristic values ​​generated according to the port scheduling policy, a suitable port is selected. The port scheduler module may also include multiple peer comparators, each responsible for scheduling a portion of the ports.

[0043] A port scheduler can select appropriate ports to allocate to requesters based on predefined rules, priorities, or policies to meet the needs of devices or tasks. When multiple tasks simultaneously request the same port resource, conflicts may occur. The port scheduler can handle these conflicts by using appropriate algorithms or policies to determine which device or task has priority in obtaining the required port resource. This avoids errors or performance degradation caused by resource contention and conflicts. Furthermore, the port scheduler uses specific scheduling algorithms to determine when to allocate port resources to different devices or tasks. These algorithms can determine the order and method of port allocation based on various objectives, such as fairness, priority, and bandwidth requirements. This allows for resource management based on actual needs, achieving optimal performance in resource utilization, and releasing or reallocating idle port resources when necessary. This effectively utilizes and manages port resources in the system, avoiding resource waste and congestion.

[0044] The implementation steps of the port scheduling strategy module are as follows: The port scheduler's scheduling algorithm can vary depending on the specific needs of the application and the characteristics of the system. For example, First-Come, First-Served (FIFO) allocates ports according to the order of requests. When multiple devices or tasks request port resources simultaneously, ports are allocated according to their request order. This algorithm is relatively simple, but may lead to resource starvation and fairness issues. Round-Robin scheduling allocates port resources to each requester in a round-robin manner, achieving fair resource allocation, but may cause some devices or tasks to wait for too long. Priority scheduling assigns a priority to each requester, and the order of port resource allocation is determined by the priority. Devices or tasks with higher priority will obtain port resources first. This algorithm can meet the real-time requirements of critical tasks, but may lead to resource starvation problems for low-priority tasks. Weighted scheduling assigns a weight value to each requester, and port resources are allocated according to the weight value. Devices or tasks with higher weights can obtain more port resources, while devices or tasks with lower weights will obtain fewer resources. This algorithm can flexibly allocate port resources based on the importance or needs of devices or tasks. Besides common port scheduler algorithms, other more complex scheduling algorithms and strategies may exist in practice. In short, scheduling algorithms can determine the order and method of port allocation based on different objectives, such as fairness, priority, and bandwidth requirements. The specific choice of scheduling algorithm requires a trade-off and decision based on the specific application scenario and performance requirements.

[0045] The implementation steps of the queue scheduling strategy module are as follows: Queue scheduling algorithms are applied to manage and schedule tasks or messages in task queues or message queues. For example, First-In-First-Out (FIFO) executes or processes tasks or messages sequentially according to their arrival order in the queue. The earliest arriving task or message is processed first, while later arriving tasks or messages wait in the queue. Priority Queuing (PQ) strictly schedules according to queue priority; lower priority messages are only scheduled after all high-priority messages have been scheduled. Weighted Fair Queuing (WFQ) fairly allocates bandwidth based on the weight of data flows and quality of service requirements to ensure that each data flow receives appropriate network resources. In the WFQ algorithm, each data flow is assigned a weight value. Higher-weighted data flows receive a larger share of bandwidth, while lower-weighted data flows receive a smaller share. This allows for dynamic quality of service scheduling based on the importance and demand of data flows. These queue scheduling algorithms have their own advantages and characteristics in different scenarios and applications. Choosing a suitable queue scheduling algorithm depends on specific application requirements, task characteristics, and system performance requirements. Some scheduling algorithms focus on response time, while others prioritize fairness and resource utilization.

[0046] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings. These examples are for illustrative purposes only and are not intended to limit the scope of protection of the present invention. In specific embodiments, an FPGA-based programmable switch is used as an example, and on-chip state maintenance is exemplified by BRAM. These examples are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0047] Figure 1The diagram shows the overall system framework. First, the entire scheduler adopts a two-level scheduling structure: the first level is the port scheduler, and the second level is the queue scheduler. In this example, there are four ports, each with eight queues. The port scheduling strategy is a token bucket algorithm with an MTU of 8192B, and the queue scheduling strategy is an LLQ algorithm with no rate limit for priority queues. Queues with queue IDs 0-5 within each port are WFQ (Weighted Fair Queuing) queues, while queue IDs 6-7 are priority queues, with queue ID = 7 having higher priority. Specifically, after data packets are enqueued, they first enter the queue type differentiation module, which distinguishes between WFQ queues and priority queues based on the queue ID information. Data packets from priority queues and WFQ queues are output from different paths of the queue type differentiation module. After the WFQ queue data packets pass through the WFQ module, the scheduling time for each packet is calculated. Priority queue data packets, since they do not require Layer 2 rate limiting, only need a specific scheduling time value. Both types of packets enter the QueueScheduler to await scheduling. Simultaneously, when the packet description information is enqueued by the multi-queue scheduler module, the corresponding port information needs to be enqueued in the Port Scheduler. Each port's sendtime (qualified time) is calculated by the rate-limiting token bucket module and passed to the PortScheduler to await scheduling. The Port Scheduler module determines which port to output, and this port ID is returned to the QueueScheduler to schedule the highest-priority queue element for that port. A global timer calculates the current time; all checks regarding packet scheduling or sendtime require time comparison.

[0048] by Figure 2The diagram illustrating the queue scheduling module is provided below. In this example, the Queue Scheduler module primarily consists of BRAMs, used to store the sendtime of data packet elements for each queue under each port. Taking a 2P6Q (2 priority queues, 6 WFQ queues) configuration as an example, each port has 8 queues. Eight BRAMs are used to store the sendtime of each queue element, and eight register arrays are used to store whether any packets are in the eight queues. Specifically, when the sendtime of a queue is written to the corresponding address, its corresponding register is set to 1; when the element is dequeued, the register bit is reset to zero to prevent an element from being scheduled multiple times. When multiple ports exist, the port ID is used as the read / write address for the BRAM or register array. In this application scenario (four ports, 8 queues per port, 2P6Q), when an element needs to be enqueued, the sendtime (64 bits) is written to the corresponding BRAM for the corresponding port. The sendtime of the priority queue is a very small constant. During dequeue scheduling, the Port Scheduler first selects a port based on port rate limiting conditions. Then, using this port ID as the read address, it simultaneously reads from eight BRAMs, obtaining the eight sendtimes for each of the eight queue elements under that port. The Priority Encoder compares these eight sendtimes to determine the one with the highest priority, obtaining the queue ID of the dequeue element, and finally outputs the selected queue information.

[0049] by Figure 3The port scheduling module shown is described below. The Port Scheduler consists of multiple small comparators to optimize comparator timing. During scheduling and dequeuing, the Port Scheduler first selects a port based on the port rate limiting condition and passes it to the Queue Scheduler. The Queue Scheduler then selects the highest priority queue for that port for dequeueing. Internally, the number of comparators in the Port Scheduler can be configured. If the comparator NUM is greater than 1, the MUX (Multiplexer) module is used; otherwise, a fast channel is used, thus saving latency introduced by the MUX module. When there are multiple comparators, each comparator is only responsible for scheduling a subset of port IDs. For example, if comparator NUM = 4, when scheduling 32 ports, each comparator schedules 8 port ID elements. After an element enters the PortScheduler, based on its port ID range, the DEMUX (Demultiplexer) module assigns it to the corresponding comparator for enqueueing, and then it awaits scheduling. During writing, the port ID information for all elements is written as 0, and the original port ID is stored as data. In the code, DEMUX is not a physical module; it directly selects the corresponding comparator module based on the high-order bits of the port ID. Each comparator has a corresponding counter module. When an element is enqueued into the comparator, the counter increments by 1; when an element is dequeued, the counter decrements by 1. When the comparator is scheduled to output, the dequeue port is always 0, because it is 0 when written. Additionally, it must ensure that the current time is greater than the element's scheduling time and that the comparator is not empty. Furthermore, since the comparator's scheduling delay is 2, when scheduling is enabled, the element will actually leave the comparator in the second clock cycle. During this process, the comparator's prefetch signal remains unchanged. Therefore, to avoid an element being scheduled multiple times, an intermittent scheduling method is used. This ensures that the previous clock cycle did not involve scheduling and that the current comparator is not empty, maintaining the same state as before. This prevents the last enqueued element from being repeatedly scheduled and avoids an empty comparator being scheduled.

[0050] by Figure 4 The diagram illustrating the signal format during packet descriptor enqueueing is provided below. The example uses four ports, each with eight queues. By default, queue numbers 0-7 belong to the first port, queue numbers 8-15 to the second port, and so on. Therefore, the input descriptor information only needs to include the queue ID and the packet length information required by the token bucket algorithm.

[0051] by Figure 5The diagram illustrates the format of the packet descriptor output by the scheduler. In the example, when the head element of a queue is scheduled, the scheduler only needs to output the queue ID and related handshake signals to the packet sharing buffer module to complete the packet dequeueing.

[0052] by Figure 6 The flowchart illustrating the port information re-enqueueing process in the port scheduler is provided below. Under the port scheduler, port information updates occur during descriptor enqueueing and dequeueing. When a queue ID is enqueued for a previously empty port, the port information needs to be updated and it enters the token bucket to participate in port scheduling contention. When a descriptor is dequeued, the head element of its mapped queue is also scheduled out, and the port storing the descriptor's queue ID needs to have its queue ID information removed. If the queue is still not empty in the on-chip cache, it needs to be re-enqueued.

[0053] This application provides an FPGA-based multi-queue scheduler and scheduling method that decouples the scheduler from the scheduling algorithm, allowing for independent modification, replacement, or upgrades without significantly impacting other components. It also enables more flexible adjustments and optimizations without requiring modifications to the entire scheduler. When the system scales up or requirements change, the scheduling algorithm can be optimized or replaced without restructuring the scheduler. This better addresses system expansion and changes, improving maintainability and adaptability. Furthermore, this application employs a two-level scheduling structure, allowing for customization and expansion based on system needs and characteristics, increasing or modifying the number of queues, and adjusting priority rules and scheduling algorithms as needed.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A multi-queue scheduler, characterized in that, The multi-queue scheduler includes: a queue type differentiation module, a port scheduler module, and a queue scheduler module; wherein... The queue type differentiation module is used to classify data packets according to the data packet description information when the multi-queue scheduler receives the data packet description information; The port scheduler module is used to calculate the port feature value of the port to which the description information of the incoming data packet belongs and update the port information according to the port scheduling policy when receiving data; when scheduling out of the queue, it obtains the port with the best port feature value by comparison and updates the port information. The queue scheduler module is used to calculate the queue feature value of the data packet description information according to the queue scheduling policy and queue type when receiving data, and to enqueue the data packet description information; when scheduling dequeue, it compares and selects the head element of the queue with the best feature value under the port, and then schedules the dequeue. The multi-queue scheduler also includes a port scheduling policy module for storing port scheduling policies; the port scheduler module obtains port scheduling policies from the port scheduling policy module. The multi-queue scheduler also includes a queue scheduling policy module for storing queue scheduling policies; the queue scheduler module obtains the queue scheduling policy from the queue scheduling policy module.

2. The multi-queue scheduler according to claim 1, characterized in that, The port scheduler module includes logical resources; port numbers and corresponding port feature values ​​are maintained in the logical resources; the port scheduler selects a suitable port by comparing the port feature values ​​generated according to the port scheduling strategy.

3. The multi-queue scheduler according to claim 2, characterized in that, The port scheduler module also includes multiple peer comparators, each of which is responsible for scheduling a portion of the ports.

4. The multi-queue scheduler according to claim 1, characterized in that, The queue scheduler module includes on-chip memory and logical resources. Using the port number as the address index, the on-chip memory stores the queue feature value of the data packet description information for each queue under each port.

5. A multi-queue scheduling method, implemented based on any one of the multi-queue schedulers of claims 1-4, the method comprising: When the multi-queue scheduler receives data packet description information, the queue type differentiation module classifies the data packets according to the data packet description information; The port scheduler module calculates the port characteristic value of the port to which the description information of the incoming data packet belongs, and updates the port information according to the port scheduling policy; The queue scheduler module calculates queue feature values ​​for packet description information based on the queue scheduling policy and queue type, and then enqueues the packet description information.

6. The multi-queue scheduling method according to claim 5, characterized in that, The method further includes: When a port is dequeued, the port scheduler module compares the ports to find the one with the best port characteristic value. The queue scheduler module compares and selects the head element of the queue with the best feature value under the port, and then schedules it to be dequeued. The port scheduler module updates port information.

7. The multi-queue scheduling method according to claim 6, characterized in that, In the port scheduler module, port information updates occur when data packets are enqueued and dequeued. When a queue ID is enqueued for a previously empty port, the port information is updated, and the port participates in port scheduling contention. When a packet description is dequeued, the head element of the queue it maps to is also scheduled away. The port that stores the queue ID of the packet description then deletes the queue ID. If there is still data in the queue, it needs to be re-enqueued.

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