Master synchronization method and apparatus, base station communication device, and readable storage medium

Abstract

The application relates to a primary synchronization method and device, a base station communication device and a computer readable storage medium. The method comprises the following steps: receiving a primary synchronization signal (PSS) sequence serially issued by a central processing unit (CPU), determining a correlation sequence of a downlink synchronization signal and a current PSS sequence; when the correlation sequence meets a preset condition, performing primary synchronization according to the current PSS sequence; and the preset condition comprises that a correlation peak value of the correlation sequence exceeds a first preset threshold. The method can reduce resource occupation.

Description

Technical Field

[0001] This application relates to the field of wireless communication technology, and in particular to a master synchronization method, apparatus, base station communication equipment, and computer-readable storage medium. Background Technology

[0002] For a terminal to access a 5G New Radio (NR) network, a cell search process is required. This process includes establishing / maintaining clock and frequency synchronization between the terminal and the base station. Currently, cell search is defined by a Primary Synchronization Signal (PSS) and a Secondary Synchronization Signal (SSS). The PSS is the first signal used by the terminal in the cell search to access the 5G NR network and is used for transmission. (Parameters used to determine the cell identifier) ​​The ability to effectively and quickly detect the PSS synchronization sequence to achieve primary synchronization is the key to user network access.

[0003] In current distributed base stations, three sets of PSS sequences are typically pre-stored in a Field Programmable Gate Array (FPGA). The downlink synchronization signal is correlated with the three sets of PSS sequences in parallel. The maximum correlation peak is found in the obtained correlation sequences, and the PSS sequence corresponding to the maximum correlation peak and the peak position of the maximum correlation peak are obtained. Based on this, the system determines... However, since three sets of PSS sequences need to be stored in the FPGA, this master-synchronization method occupies multiple DSP resources simultaneously, resulting in excessive resource consumption. Summary of the Invention

[0004] Therefore, it is necessary to provide a master synchronization method, apparatus, base station communication equipment, computer-readable storage medium, and computer program product that can reduce resource consumption in response to the above-mentioned technical problems.

[0005] In a first aspect, this application provides a master synchronization method, which is applied to a field-programmable gate array (FPGA) in a base station, comprising:

[0006] Receive the master synchronization signal (PSS) sequence serially sent by the central processing unit (CPU) and determine the correlation sequence between the downlink synchronization signal and the current PSS sequence;

[0007] When the relevant sequence meets the preset conditions, primary synchronization is performed based on the current PSS sequence; the preset conditions include the correlation peak value of the relevant sequence exceeding a first preset threshold.

[0008] Secondly, this application also provides a master synchronization method, which is applied to the central processing unit (CPU) of a base station, comprising:

[0009] Obtain the master synchronization signal (PSS) sequence;

[0010] The PSS sequence is serially sent to the FPGA so that the FPGA can determine the correlation sequence between the downlink synchronization signal and the current PSS sequence, and perform master synchronization according to the current PSS sequence when the correlation sequence meets the preset conditions.

[0011] Thirdly, this application also provides a master synchronization device, which is applied to a field-programmable gate array (FPGA) in a base station, comprising:

[0012] The receiving module is used to receive the master synchronization signal (PSS) sequence serially transmitted by the central processing unit (CPU) and determine the correlation sequence between the downlink synchronization signal and the current PSS sequence.

[0013] The detection module is used to perform primary synchronization based on the current PSS sequence when the relevant sequence meets preset conditions; the preset conditions include the correlation peak value of the relevant sequence exceeding a first preset threshold.

[0014] Fourthly, this application also provides a master synchronization device, which is applied to the central processing unit (CPU) of a base station, comprising:

[0015] The acquisition module is used to acquire the master synchronization signal (PSS) sequence.

[0016] The transmitting module is used to serially send the PSS sequence to the field programmable gate array (FPGA) so that the FPGA can determine the correlation sequence between the downlink synchronization signal and the current PSS sequence, and perform master synchronization according to the current PSS sequence when the correlation sequence meets the preset conditions.

[0017] Fifthly, this application also provides a base station communication device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in either the first or second aspect above.

[0018] Sixthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in either the first or second aspect above.

[0019] In a seventh aspect, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method described in either the first or second aspect above.

[0020] The aforementioned master synchronization method, apparatus, base station communication equipment, computer-readable storage medium, and computer program product determine the correlation sequence between the downlink synchronization signal and the current PSS sequence by receiving the master synchronization signal PSS sequence serially sent by the central processing unit (CPU). When the correlation sequence meets preset conditions, master synchronization is performed based on the current PSS sequence. The preset conditions include that the correlation peak of the correlation sequence exceeds a first preset threshold. Each set of PSS sequences can be pre-stored in the central processing unit (CPU) outside the FPGA. During the master synchronization process, the CPU serially sends the PSS sequence to the FPGA, so that the FPGA only stores and processes one set of PSS sequences at any given time, reducing resource consumption. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the parallel PSS synchronization process in an FPGA.

[0023] Figure 2 This is a flowchart illustrating the master synchronization method in one embodiment;

[0024] Figure 3 This is a flowchart illustrating the master synchronization method in another embodiment;

[0025] Figure 4 This is a flowchart illustrating a PSS synchronization method based on FPGA and CPU in one embodiment.

[0026] Figure 5 This is an interactive flowchart of a PSS synchronization method based on FPGA and CPU in one embodiment;

[0027] Figure 6 This is an interactive flowchart of the master synchronization method in one embodiment. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0029] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0030] In traditional techniques, reference Figure 1 The master synchronization of a distributed base station involves pre-storing three sets of PSS sequences in an FPGA. The FPGA processes the received signal through frequency shifting, downsampling, and filtering. Then, it performs correlation calculations on the processed received signal in parallel with the three sets of PSS sequences to obtain three sets of correlation sequences. The correlation peak of each sequence is determined, and the largest correlation peak is selected. If the largest correlation peak exceeds a pre-set correlation peak threshold, the PSS sequence corresponding to the largest correlation peak is used to determine... This completes the master synchronization. Therefore, it is evident that traditional techniques require storing three sets of PSS sequences on the FPGA, simultaneously occupying multiple DSPs, resulting in significant resource consumption.

[0031] Based on the above-mentioned traditional technology, the master synchronization method provided in this application pre-stores three sets of PSS sequences in the CPU outside the FPGA. When master synchronization is required, the CPU serially sends the PSS sequence to the FPGA, so that the FPGA only stores and processes one set of PSS sequences at any time, reducing resource consumption.

[0032] It should be noted that the beneficial effects or technical problems solved by the embodiments of this application are not limited to this one, but may also be other implicit or related problems. For details, please refer to the description of the embodiments below.

[0033] In one exemplary embodiment, such as Figure 2 As shown, a master synchronization method is provided. Taking the application of this method to an FPGA base station (including but not limited to a pico base station) as an example, the method includes the following steps:

[0034] Step S102: Receive the master synchronization signal (PSS) sequence serially sent by the central processing unit (CPU) and determine the correlation sequence between the downlink synchronization signal and the current PSS sequence.

[0035] The current PSS sequence can be the PSS sequence currently issued by the CPU. The downlink synchronization signal can be a synchronization signal used for cell search, including but not limited to the Synchronization Signal and PBCH block (SSB). The correlation sequence can be the result of correlation calculations performed on the downlink synchronization signal and the current PSS sequence.

[0036] In a specific implementation, the base station can be equipped with an FPGA and a CPU. The FPGA is connected to the CPU. Three PSS sequences are pre-stored in the CPU. When master synchronization is required, the CPU can serially send the three PSS sequences to the FPGA. For the currently received PSS sequence, the FPGA can calculate its correlation sequence with the downlink synchronization signal.

[0037] For example, three sets of local PSS sequences can be pre-stored in the CPU. , , When a downlink synchronization signal is detected to arrive in the FPGA, the CPU can first set the first local PSS sequence. Distribute to FPGA, FPGA stores And calculate the downlink synchronization signal and Correlation sequences between .

[0038] Step S104: When the relevant sequence meets the preset conditions, perform master synchronization based on the current PSS sequence; the preset conditions include the relevant peak value of the relevant sequence exceeding the first preset threshold.

[0039] The preset conditions can be pre-defined selection criteria for the PSS sequence used for master synchronization. The correlation peak can be the maximum correlation peak of the correlation sequence. The first preset threshold can be a pre-defined correlation peak threshold.

[0040] In the specific implementation, the FPGA can determine whether the current PSS sequence and the related sequence of the downlink synchronization signal meet the preset conditions. If they meet the preset conditions, the FPGA performs master synchronization based on the current PSS sequence. Otherwise, if they do not meet the preset conditions, the FPGA continues to receive the next PSS sequence sent by the CPU, updates the current PSS sequence to the next PSS sequence to save storage resources, and continues to detect whether the next PSS sequence and the related sequence of the downlink synchronization signal meet the preset conditions.

[0041] For example, FPGAs can determine related sequences. If the maximum correlation peak exceeds the preset correlation peak threshold, then the first set of local PSS sequences is used. Sure Otherwise, if If the maximum correlation peak does not exceed the correlation peak threshold, the FPGA continues to receive the second set of local PSS sequences sent by the CPU. ,Will Updated to Calculate the downlink synchronization signal and Correlation sequences between ,judge Does the maximum correlation peak exceed the correlation peak threshold?

[0042] The aforementioned master synchronization method receives the master synchronization signal PSS sequence serially sent by the central processing unit (CPU), determines the correlation sequence between the downlink synchronization signal and the current PSS sequence, and performs master synchronization based on the current PSS sequence when the correlation sequence meets preset conditions. The preset conditions include that the correlation peak of the correlation sequence exceeds a first preset threshold. Each set of PSS sequences can be pre-stored in the CPU outside the FPGA. During the master synchronization process, the CPU serially sends the PSS sequence to the FPGA, so that the FPGA only stores and processes one set of PSS sequences at any given time, reducing resource consumption.

[0043] In an exemplary embodiment, the above-described master synchronization method may further include: when the relevant sequence does not meet the preset conditions, receiving the next PSS sequence of the current PSS sequence and updating the current PSS sequence to the next PSS sequence; detecting whether the relevant sequence of the downlink synchronization signal and the next PSS sequence meets the preset conditions.

[0044] In the specific implementation, if the FPGA determines that the current PSS sequence and the related sequence of the downlink synchronization signal do not meet the preset conditions, it can continue to receive the next PSS sequence sent by the CPU, update the current PSS sequence to the next PSS sequence, and check whether the related sequence of the next PSS sequence and the downlink synchronization signal meet the preset conditions. If they meet the preset conditions, the FPGA performs master synchronization based on the next PSS sequence. Otherwise, if they do not meet the preset conditions, the above process is repeated, and the FPGA continues to receive the next PSS sequence sent by the CPU and check whether the related sequence of the next PSS sequence and the downlink synchronization signal meet the preset conditions.

[0045] For example, if the FPGA determines the relevant sequence If the maximum correlation peak does not exceed the correlation peak threshold, then continue receiving the second set of local PSS sequences sent by the CPU. , store the previously stored Updated to Calculate the downlink synchronization signal and Correlation sequences between ,judge If the maximum correlation peak exceeds the correlation peak threshold, then proceed according to the second set of local PSS sequences. Sure Otherwise, if If the maximum correlation peak does not exceed the correlation peak threshold, the FPGA continues to receive the third set of local PSS sequences sent by the CPU. ,Will Updated to Calculate the downlink synchronization signal and Correlation sequences between ,judge If the maximum correlation peak exceeds the correlation peak threshold, then the third set of local PSS sequences is used. Sure Otherwise, if If the maximum correlation peak does not exceed the correlation peak threshold, the FPGA determines that master synchronization cannot be achieved.

[0046] In this embodiment, when the relevant sequence does not meet the preset conditions, the next PSS sequence of the current PSS sequence is received, the current PSS sequence is updated to the next PSS sequence, and the correlation sequence between the downlink synchronization signal and the next PSS sequence is detected to meet the preset conditions. Each PSS sequence serially sent by the CPU can be detected in sequence, reducing resource consumption.

[0047] In an exemplary embodiment, the above-described master synchronization method may further include: determining the power value of the synchronization signal block SSB; and reporting the power value to the CPU so that the CPU serially sends out the PSS sequence according to the power value.

[0048] In the specific implementation, the FPGA can extract the signal at the location of the SSB from the received signal, calculate the power value of the signal, and report the power value to the CPU. The CPU determines whether the received power value exceeds a second preset threshold. If it does, the synchronization process is initiated, and the CPU serially sends the PSS sequence to the FPGA. Otherwise, if the power value received by the CPU does not exceed the second preset threshold, the synchronization process is not initiated, and the CPU remains in a waiting state. The second preset threshold can be a pre-set detection power of the SSB.

[0049] In this embodiment, by determining the power value of the synchronization signal block SSB, the power value is reported to the CPU, so that the CPU serially sends out the PSS sequence according to the power value. When an SSB is detected to arrive, the synchronization process can be started, and the CPU serially sends out three sets of local PSS sequences to the FPGA, avoiding resource waste.

[0050] In an exemplary embodiment, step S102 may specifically include: receiving the SSB frequency point sent by the CPU, and the PSS sequence sent by the CPU in turn for the SSB frequency point.

[0051] Among them, the SSB frequency point can be the frequency band for primary synchronization.

[0052] In the specific implementation, when the synchronization process starts, the CPU can send SSB frequency points to the FPGA in sequence, and send three PSS sequences in turn for each SSB frequency point. The FPGA receives each SSB frequency point and its corresponding three PSS sequences.

[0053] For example, in addition to pre-storing three sets of local PSS sequences, the CPU can also pre-storing SSB frequency information. When an SSB is detected, the CPU can first send the first SSB frequency to the FPGA, and then send the three sets of local PSS sequences sequentially. , , Then, the CPU can send the second SSB frequency point to the FPGA, and then send three sets of local PSS sequences serially. , , And so on, until the last SSB frequency point.

[0054] Understandably, the FPGA can update the original SSB frequency to the new SSB frequency or the original PSS sequence to the new PSS sequence each time it receives a new SSB frequency or a new PSS sequence, in order to further reduce resource consumption.

[0055] In this embodiment, by receiving the SSB frequency points sent by the CPU and the PSS sequences sent by the CPU in turn for the SSB frequency points, primary synchronization of different SSB frequency points can be achieved, thereby improving the accuracy of cell synchronization.

[0056] In an exemplary embodiment, step S102 may specifically include: performing correlation processing on the downlink synchronization signal and the current PSS sequence to obtain a correlation sequence.

[0057] In practice, the FPGA can perform correlation calculations between the downlink synchronization signal and the current PSS sequence sent by the CPU to obtain the correlation sequence corresponding to the current PSS sequence.

[0058] In practical applications, FPGAs can perform frequency shifting, downsampling, and filtering on the received signal to obtain a downlink synchronization signal. This downlink synchronization signal is then correlated with a set of local PSS sequences currently sent by the CPU to obtain a correlation sequence. The specific formula can be:

[0059] ,

[0060] in, This is a set of local PSS sequences currently issued by the CPU. This is a downlink synchronization signal. For time-domain data indexing, is the length of the PSS sequence.

[0061] It is understood that the current PSS sequence can be one of the three local PSS sequences described in the aforementioned embodiments. , , Any set of signals, meaning the FPGA can match the downlink synchronization signal with the signal currently sent by the CPU. , or Perform relevant calculations to obtain the corresponding correlation sequences. , or .

[0062] In this embodiment, by performing correlation processing between the downlink synchronization signal and the current PSS sequence to obtain a correlation sequence, the received downlink synchronization signal can be correlated with the PSS sequence currently issued by the CPU, and the cell identifier can be determined based on the result of the correlation calculation, thereby improving the accuracy of cell synchronization.

[0063] In one exemplary embodiment, such as Figure 3 As shown, a master synchronization method is provided. Taking the application of this method to the CPU of a base station as an example, the method includes the following steps:

[0064] Step S202: Obtain the master synchronization signal PSS sequence;

[0065] Step S204: Serially send the PSS sequence to the FPGA so that the FPGA can determine the correlation sequence between the downlink synchronization signal and the current PSS sequence, and perform master synchronization according to the current PSS sequence when the correlation sequence meets the preset conditions.

[0066] In practice, three PSS sequences can be predetermined and stored in the CPU. When master synchronization is required, the CPU serially sends the three PSS sequences to the FPGA. For the currently received PSS sequence, the FPGA calculates its correlation sequence with the downlink synchronization signal. If the maximum correlation peak of the calculated correlation sequence exceeds the preset correlation peak threshold, master synchronization is performed based on the current PSS sequence.

[0067] Since the specific processing procedure of the CPU has been described in detail in the foregoing embodiments, it will not be repeated here.

[0068] In this embodiment, the PSS sequence is obtained and serially sent to the FPGA. Each set of PSS sequences can be pre-stored in the CPU outside the FPGA. During the main synchronization process, the CPU serially sends the PSS sequence to the FPGA, so that the FPGA only stores and processes one set of PSS sequences at any time, reducing resource consumption.

[0069] In an exemplary embodiment, the above-described master synchronization method may further include: when the relevant sequence read from the FPGA does not meet the preset conditions, sending the next PSS sequence of the current PSS sequence to the FPGA; when the relevant sequence read from the FPGA meets the preset conditions, stopping the sending of the PSS sequence.

[0070] In the specific implementation, the CPU can read from the FPGA whether the maximum correlation peak of the current correlation sequence exceeds the correlation peak threshold. If it does not exceed the correlation peak threshold, it means that the current correlation sequence does not meet the preset conditions, and the CPU can continue to send the next PSS sequence to the FPGA for the FPGA to detect. Otherwise, if the maximum correlation peak of the current correlation sequence exceeds the correlation peak threshold, it means that the current correlation sequence meets the preset conditions, and the FPGA can perform master synchronization based on the current PSS sequence. At this time, the CPU stops sending the PSS sequence.

[0071] In this embodiment, when the relevant sequence read from the FPGA does not meet the preset conditions, the next PSS sequence of the current PSS sequence is sent to the FPGA. When the relevant sequence read from the FPGA meets the preset conditions, the sending of the PSS sequence is stopped. Information on whether to continue sending the PSS sequence can be obtained from the FPGA, realizing the sequential detection of the PSS sequence and reducing resource consumption.

[0072] In an exemplary embodiment, step S204 may specifically include: receiving the power value of the synchronization signal block SSB reported by the FPGA; and when the power value exceeds a second preset threshold, serially sending a PSS sequence to the FPGA.

[0073] In the specific implementation, the FPGA can extract the signal at the location of the SSB from the received signal, calculate the power value of the signal, and report the power value to the CPU. The CPU determines whether the received power value exceeds the second preset threshold. If it exceeds the second preset threshold, the synchronization process is started and the PSS sequence is serially sent to the FPGA. Otherwise, if the power value received by the CPU does not exceed the second preset threshold, the synchronization process is not started and the CPU remains in the waiting state.

[0074] In this embodiment, by receiving the power value of the synchronization signal block SSB reported by the FPGA, when the power value exceeds the second preset threshold, the PSS sequence is serially sent to the FPGA. The synchronization process can be started when an SSB is detected, so that the CPU serially sends three sets of local PSS sequences to the FPGA, avoiding resource waste.

[0075] In an exemplary embodiment, step S202 may specifically include: determining a pseudo-random sequence; performing subcarrier mapping on the pseudo-random sequence to obtain a subcarrier sequence; and performing orthogonal frequency division multiplexing (OFDM) processing on the subcarrier sequence to obtain a PSS sequence.

[0076] The pseudo-random sequence includes, but is not limited to, the m-sequence. Orthogonal Frequency Division Multiplexing (OFDM) processing can be the inverse Fourier transform processing in OFDM.

[0077] In the specific implementation, the CPU can determine three pseudo-random sequences. For each pseudo-random sequence, it first maps it to a subcarrier to obtain the corresponding subcarrier sequence. Then, the subcarrier sequence is combined with other subcarriers for orthogonal frequency division multiplexing modulation to obtain the corresponding PSS time domain signal. The PSS time sequence signal can be stored on the CPU as a PSS sequence.

[0078] In practical applications, the PSS sequence in 5G NR is used for transmission. SSS sequences are used for transmission The Physical Cell Identifier (PCI) can be determined based on the PSS and SSS sequences, using the following formula: ,in, , This allows us to define 1008 PCIs. The PSS sequence can be an m-sequence of length 127, as shown in the following formula:

[0079] ,

[0080] in, ,

[0081] ,

[0082] correspond There are three possible m-sequences, but only one can be used per physical cell. For each m-sequence, it can be mapped to a subcarrier, resulting in a subcarrier sequence consisting of 127 consecutive subcarriers. The subcarrier sequence is a frequency domain sequence. The subcarrier sequence can be combined with other subcarriers within the transmission bandwidth and modulated using orthogonal frequency division multiplexing to obtain the corresponding time domain signal. The time domain signal corresponding to the subcarrier sequence is stored as a PSS sequence on the CPU. Thus, three sets of local PSS sequences can be pre-stored on the CPU.

[0083] It should be noted that this embodiment can be executed by a CPU, but is not limited to that executed by a CPU. For example, it can also be executed by a base station, a terminal, or a core network, as long as the obtained three PSS sequences can be stored in the CPU.

[0084] In this embodiment, by determining a pseudo-random sequence, subcarrier mapping is performed on the pseudo-random sequence to obtain a subcarrier sequence, and orthogonal frequency division multiplexing processing is performed on the subcarrier sequence to obtain a PSS sequence. Three sets of PSS sequences can be stored in advance on the CPU, reducing the storage and processing resources of the FPGA and reducing resource consumption.

[0085] To facilitate a deeper understanding of the embodiments of this application by those skilled in the art, a specific example will be used for illustration below.

[0086] This application proposes a low-cost PSS synchronization method based on FPGA and CPU, which can reduce the demand for analog-to-digital converters (ADCs) and FPGAs, thereby reducing the overall implementation cost. First, this application employs joint decoding of synchronization information by FPGA and CPU. The FPGA performs PSS synchronization, while the CPU sends the PSS sequence and performs subsequent SSS synchronization, reducing the resource consumption of the FPGA synchronization module and lowering the overall implementation cost. Second, the CPU polls and sends three sets of PSS sequences to the FPGA, which performs related calculations serially on the three sets of PSS sequences internally, saving FPGA resources and reducing the overall implementation cost. The low-cost PSS synchronization system based on this method consists of an FPGA module and a CPU module, which collaboratively achieve PSS synchronization, reducing the overall implementation cost.

[0087] Figure 4 A flowchart illustrating a low-cost PSS synchronization method based on FPGA and CPU is provided. According to... Figure 4 The PSS synchronization method may include the following steps:

[0088] Step S301: Generate three sets of PSS sequences by cyclically shifting the basic m sequence, modulate them into time-domain signals, and store them in the CPU.

[0089] In 5G NR, each physical cell identifier is determined by a combination of the PSS sequence and the SSS sequence. Compared to LTE's 504 PCIs, 5G NR offers greater flexibility in cell deployment. Unlike LTE's 504 physical cell numbers, NR defines 1008 PCIs, among which... , .

[0090] The ZC sequence (Zadoff-Chu sequence) is a subcarrier phase sequence, using phase modulation at arbitrary angles. 5G applications include high-frequency bands from 5G to 60GHz. Using arbitrary-angle phase modulation results in a larger frequency offset for the ZC sequence at high frequencies, affecting its correlation, manifesting as a decrease in correlation peak-to-peak value and an increase in false detections. Therefore, the m-sequence is used instead. The PSS sequence is a pseudo-random sequence of length 127, with the specific formula as follows:

[0091] ,

[0092] in, ,

[0093] .

[0094] For a physical cell, the m-sequence can only be one of three types. After the NR PSS m-sequence is mapped to the subcarriers, it forms a subcarrier sequence consisting of 127 consecutive subcarriers. The 127 frequency-domain subcarriers, together with other subcarriers, undergo OFDM conversion to modulate into an OFDM time-domain signal. The three sets of PSS time-domain signals are stored as PSS sequences in the CPU.

[0095] In step S302, the CPU reads the SSB power inside the FPGA and determines whether the SSB power is greater than the threshold value. If the SSB power is greater than the threshold, the synchronization process is started.

[0096] After the FPGA processes the received signal by frequency shifting, downsampling, and filtering, it calculates the SSB power value and uploads it to the CPU. The CPU reads the SSB power value and determines whether it is greater than a preset threshold (second preset threshold). If it is less than or equal to the preset threshold, it stays in the waiting state. If it is greater than the preset threshold, it starts the synchronization process.

[0097] In step S303, the CPU serially sends each PSS sequence and SSB frequency point information to the FPGA.

[0098] The three sets of PSS sequences in the time domain, along with information including SSB frequency points, are pre-stored in the CPU. After the synchronization process is triggered, the CPU sends out the SSB frequency points in turn, and then sends out the three sets of PSS sequences in turn. The FPGA processes the PSS sequences sent by the CPU through the overload coefficient module and uses them for related calculations. Each time the CPU sends out a new set of PSS sequences, the FPGA refreshes the stored PSS sequences.

[0099] In step S304, the FPGA performs a serial correlation with the three sets of PSS sequences in the time domain based on the received downlink synchronization signal.

[0100] The FPGA processes the received signal through frequency shifting, downsampling, and filtering to extract the PSS (Downlink Synchronization Signal). This information is then correlated with the PSS sequence sent by the CPU using a sliding correlation expression. ,in, The PSS sequence sent by the CPU. This is the downsampled downlink received signal (downlink synchronization signal). For time-domain data indexing, The length of the PSS sequence sent by the CPU.

[0101] Step S305: Find the three sets of correlation maximum values. The PSS sequence corresponding to the correlation peak is the synchronization sequence, and the corresponding position is the PSS synchronization point.

[0102] If the calculation result is 0, it indicates that the PSS sequence in the received signal and the CPU-transmitted sequence are not from the same group; if the calculation result is not 0, it indicates that the PSS sequence in the received signal and the CPU-transmitted sequence are not from the same group, but may be other interference signals; if the calculation result is not 0, and the calculation result is the predetermined maximum value (the maximum correlation peak exceeds the correlation peak threshold), it indicates that the PSS sequence in the received signal and the CPU-transmitted sequence are from the same group, and the cell's... .

[0103] Figure 5 An interactive flowchart of a PSS synchronization method based on FPGA and CPU is provided. (Reference) Figure 5The FPGA can perform frequency shifting, downsampling, and filtering on the received signal, extract the SSB from the received signal, calculate the SSB power value, and the CPU reads the SSB power value and checks whether the SSB power value is greater than a second preset threshold. If it is less than or equal to the second preset threshold, it maintains a waiting state and continues to read the SSB power value. If it is greater than the second preset threshold, it serially sends the SSB frequency point information and three sets of PSS sequences to the FPGA. The FPGA reloads the currently sent PSS sequence and performs correlation calculations between the received downlink synchronization signal and the currently sent PSS sequence to obtain a set of correlation sequences. If the maximum correlation peak of the correlation sequence exceeds the PSS threshold (the first preset threshold or the correlation peak threshold), the main synchronization process is completed. Otherwise, if the maximum correlation peak of the correlation sequence does not exceed the PSS threshold, the CPU continues to send the next set of PSS sequences and repeats the above correlation sequence calculation and correlation peak detection process until the maximum correlation peak exceeds the PSS threshold, and main synchronization is performed according to the corresponding PSS sequence.

[0104] The aforementioned PSS synchronization method employs a collaborative approach between FPGA and CPU. Three sets of PSS sequences are pre-stored in the CPU. When the CPU detects that the SSB power exceeds a threshold, it sends the three sets of PSS coefficients to the FPGA in a polling manner. The FPGA then performs serial calculations on the three sets of PSS sequences to find relevant peaks, thus locating the corresponding PSS sequences and their positions, thereby achieving PSS synchronization. This approach allows for joint decoding of synchronization information by the FPGA and CPU, reducing the resource consumption of the FPGA synchronization module and lowering the overall implementation cost. Furthermore, by having the CPU send the three sets of PSS coefficients to the FPGA in a polling manner, and the FPGA then performs serial calculations on the three sets of PSS sequences, FPGA resources are saved while reducing the overall implementation cost.

[0105] In one embodiment, such as Figure 6 As shown, a master synchronization method is provided, including the following steps:

[0106] Step S401: Determine three pseudo-random sequences, perform subcarrier mapping on each pseudo-random sequence to obtain three subcarrier sequences, perform orthogonal frequency division multiplexing on the three subcarrier sequences to obtain three PSS sequences, and store the three PSS sequences in the CPU.

[0107] Step S402: The FPGA reports the power value of the synchronization signal block SSB to the CPU;

[0108] Step S403: The CPU detects whether the power value exceeds the second preset threshold. When the power value exceeds the second preset threshold, the CPU sends the first PSS sequence to the FPGA.

[0109] Step S404: The FPGA determines the correlation sequence between the downlink cell synchronization signal and the first PSS sequence;

[0110] Step S405: If the relevant sequence meets the preset conditions, the FPGA performs master synchronization based on the first PSS sequence.

[0111] Step S406: If the relevant sequence does not meet the preset conditions, the CPU sends a second PSS sequence to the FPGA;

[0112] Step S407: The FPGA determines the correlation sequence between the downlink cell synchronization signal and the second PSS sequence;

[0113] Step S408: If the relevant sequence meets the preset conditions, the FPGA performs master synchronization based on the second PSS sequence;

[0114] Step S409: If the relevant sequence does not meet the preset conditions, the CPU sends the third PSS sequence to the FPGA;

[0115] Step S410: The FPGA determines the correlation sequence between the downlink cell synchronization signal and the third PSS sequence;

[0116] Step S411: If the relevant sequence meets the preset conditions, the FPGA performs master synchronization based on the third PSS sequence.

[0117] In specific implementation, three pseudo-random sequences can be subcarrier mapped and OFDM modulated to obtain three PSS sequences. These PSS sequences are stored in the CPU. The FPGA reports the SSB power value to the CPU. The CPU checks whether the received SSB power value exceeds a second preset threshold. If it does, the CPU sends the first PSS sequence to the FPGA. The FPGA performs correlation calculations between the downlink synchronization signal and the first PSS sequence to obtain a correlation sequence. If the maximum correlation peak of the correlation sequence exceeds the correlation peak threshold, primary synchronization is performed based on the first PSS sequence. Otherwise, if the maximum correlation peak of the correlation sequence does not exceed the correlation peak threshold, the CPU continues to send the first PSS sequence to the FPGA. The GA sends out the second PSS sequence, the FPGA refreshes the PSS sequence, and performs correlation calculations between the downlink synchronization signal and the current second PSS sequence to obtain a correlation sequence. If the maximum correlation peak of the correlation sequence exceeds the correlation peak threshold, then primary synchronization is performed based on the second PSS sequence. Otherwise, if the maximum correlation peak of the correlation sequence does not exceed the correlation peak threshold, the CPU continues to send the third PSS sequence to the FPGA. The FPGA refreshes the PSS sequence and performs correlation calculations between the downlink synchronization signal and the current third PSS sequence to obtain a correlation sequence. If the maximum correlation peak of the correlation sequence exceeds the correlation peak threshold, then primary synchronization is performed based on the third PSS sequence.

[0118] In this context, refreshing the PSS sequence on the FPGA can be understood as deleting the previously stored PSS sequence and storing the PSS sequence currently issued by the CPU, or updating the previously stored PSS sequence to the PSS sequence currently issued by the CPU. Furthermore, when the CPU issues a new PSS sequence, the FPGA can not only refresh the PSS sequence but also refresh previously stored correlation sequences, maximum correlation peaks, etc., further reducing resource consumption.

[0119] The aforementioned master synchronization method receives the master synchronization signal PSS sequence serially sent by the central processing unit (CPU), determines the correlation sequence between the downlink synchronization signal and the current PSS sequence, and performs master synchronization based on the current PSS sequence when the correlation sequence meets preset conditions. The preset conditions include that the correlation peak of the correlation sequence exceeds a first preset threshold. Each set of PSS sequences can be pre-stored in the CPU outside the FPGA. During the master synchronization process, the CPU serially sends the PSS sequence to the FPGA, so that the FPGA only stores and processes one set of PSS sequences at any given time, reducing resource consumption.

[0120] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0121] Based on the same inventive concept, this application also provides a master synchronization device for implementing the master synchronization method described above. The solution provided by this device is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more master synchronization device embodiments provided below can be found in the limitations of the master synchronization method described above, and will not be repeated here.

[0122] In one exemplary embodiment, a master synchronization device is provided, the device being applied to a field-programmable gate array (FPGA) of a base station, comprising:

[0123] The receiving module is used to receive the master synchronization signal (PSS) sequence serially transmitted by the central processing unit (CPU) and determine the correlation sequence between the downlink synchronization signal and the current PSS sequence.

[0124] The detection module is used to perform primary synchronization based on the current PSS sequence when the relevant sequence meets preset conditions; the preset conditions include the correlation peak value of the relevant sequence exceeding a first preset threshold.

[0125] In an exemplary embodiment, the detection module is further configured to, when the related sequence does not meet the preset conditions, receive the next PSS sequence of the current PSS sequence, update the current PSS sequence to the next PSS sequence, and detect whether the related sequence of the downlink synchronization signal and the next PSS sequence meets the preset conditions.

[0126] In an exemplary embodiment, the master synchronization device further includes a reporting module for determining the power value of the synchronization signal block SSB and reporting the power value to the CPU so that the CPU serially sends the PSS sequence according to the power value.

[0127] In an exemplary embodiment, the receiving module is further configured to receive the SSB frequency point sent by the CPU, and the PSS sequence sent by the CPU in turn for the SSB frequency point.

[0128] In an exemplary embodiment, the receiving module is further configured to perform correlation processing between the downlink synchronization signal and the current PSS sequence to obtain the correlation sequence.

[0129] In one exemplary embodiment, another master synchronization device is provided, the device being applied to the central processing unit (CPU) of a base station, comprising:

[0130] The acquisition module is used to acquire the master synchronization signal (PSS) sequence.

[0131] The transmitting module is used to serially send the PSS sequence to the field programmable gate array (FPGA) so that the FPGA can determine the correlation sequence between the downlink synchronization signal and the current PSS sequence, and perform master synchronization according to the current PSS sequence when the correlation sequence meets the preset conditions.

[0132] In an exemplary embodiment, the above-described sending module is further configured to send the next PSS sequence of the current PSS sequence to the FPGA when the relevant sequence read from the FPGA does not meet the preset conditions; and to stop sending the PSS sequence when the relevant sequence read from the FPGA meets the preset conditions.

[0133] In an exemplary embodiment, the above-mentioned sending module is further configured to receive the power value of the synchronization signal block SSB reported by the FPGA; when the power value exceeds a second preset threshold, the PSS sequence is serially sent to the FPGA.

[0134] In an exemplary embodiment, the acquisition module is further configured to determine a pseudo-random sequence; perform subcarrier mapping on the pseudo-random sequence to obtain a subcarrier sequence; and perform orthogonal frequency division multiplexing (OFDM) processing on the subcarrier sequence to obtain the PSS sequence.

[0135] Each module in the aforementioned master synchronization device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of the communication device in hardware form or independent of it, or stored in the memory of the communication device in software form, so that the processor can call and execute the corresponding operations of each module.

[0136] In an exemplary embodiment, a communication device is provided, which may be a base station. The communication device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is connected to the system bus via the I / O interfaces. The processor of the communication device provides computing and control capabilities. The memory of the communication device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database of the communication device stores master synchronization data. The I / O interfaces of the communication device are used for exchanging information between the processor and external devices. The communication interface of the communication device is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a master synchronization method.

[0137] Those skilled in the art will understand that the above structure is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the communication device to which the present application is applied. Specific communication devices may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0138] In one embodiment, a base station communication device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0139] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0140] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0141] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0142] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0143] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0144] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A master synchronization method, characterized in that, The method is applied to a field-programmable gate array (FPGA) in a base station. The base station also includes a central processing unit (CPU). The FPGA is connected to the CPU, and the CPU pre-stores three master synchronization signal (PSS) sequences. The method includes: The CPU reports the power value of the synchronization signal block SSB. When the CPU determines that the received power value exceeds the second preset threshold, it receives the SSB frequency point sent by the CPU and the PSS sequence serially sent by the CPU for the SSB frequency point, and determines the correlation sequence between the downlink synchronization signal and the current PSS sequence. When the relevant sequence meets the preset conditions, primary synchronization is performed based on the current PSS sequence; the preset conditions include the correlation peak value of the relevant sequence exceeding a first preset threshold.

2. The master synchronization method according to claim 1, characterized in that, The method further includes: When the relevant sequence does not meet the preset condition, the next PSS sequence of the current PSS sequence is received, and the current PSS sequence is updated to the next PSS sequence; The correlation sequence between the downlink synchronization signal and the next PSS sequence is checked to see if it meets the preset conditions.

3. The master synchronization method according to claim 1, characterized in that, The method further includes: When a new SSB frequency is received, the original SSB frequency is updated to the new SSB frequency.

4. The master synchronization method according to claim 1, characterized in that, The second preset threshold is the pre-set SSB detection power.

5. The master synchronization method according to claim 1, characterized in that, The determination of the correlation sequence between the downlink synchronization signal and the current PSS sequence includes: The downlink synchronization signal is correlated with the current PSS sequence to obtain the correlation sequence.

6. A master synchronization method, characterized in that, The method is applied to the central processing unit (CPU) of a base station, which also includes a field-programmable gate array (FPGA) connected to the CPU. The CPU pre-stores three master synchronization signal (PSS) sequences. The method includes: Obtain the PSS sequence; The system receives the power value of the synchronization signal block SSB reported by the FPGA. When the power value exceeds a second preset threshold, it sends the SSB frequency point to the FPGA and serially sends the PSS sequence for the SSB frequency point so that the FPGA can determine the correlation sequence between the downlink synchronization signal and the current PSS sequence. When the correlation sequence meets the preset conditions, the system performs primary synchronization according to the current PSS sequence.

7. The master synchronization method according to claim 6, characterized in that, The method further includes: When the relevant sequence read from the FPGA does not meet the preset conditions, the next PSS sequence of the current PSS sequence is sent to the FPGA; When the relevant sequence read from the FPGA meets the preset conditions, the issuance of the PSS sequence is stopped.

8. The master synchronization method according to claim 6, characterized in that, The process of obtaining the PSS sequence includes: Determine the pseudo-random sequence; Subcarrier mapping is performed on the pseudo-random sequence to obtain a subcarrier sequence; The subcarrier sequence is subjected to orthogonal frequency division multiplexing (OFDM) processing to obtain the PSS sequence.

9. A master synchronization device, characterized in that, The device is applied to a field-programmable gate array (FPGA) in a base station. The base station also includes a central processing unit (CPU). The FPGA is connected to the CPU, and the CPU pre-stores three master synchronization signal (PSS) sequences. The device includes: The receiving module is used to report the power value of the synchronization signal block SSB to the CPU. When the CPU determines that the received power value exceeds the second preset threshold, it receives the SSB frequency point sent by the CPU and the PSS sequence serially sent by the CPU for the SSB frequency point, and determines the correlation sequence between the downlink synchronization signal and the current PSS sequence. The detection module is used to perform primary synchronization based on the current PSS sequence when the relevant sequence meets preset conditions; the preset conditions include the correlation peak value of the relevant sequence exceeding a first preset threshold.

10. A master synchronization device, characterized in that, The device is applied to the central processing unit (CPU) of a base station. The base station also includes a field-programmable gate array (FPGA), which is connected to the CPU. The CPU pre-stores three master synchronization signal (PSS) sequences. The device comprises: The acquisition module is used to acquire the PSS sequence; The transmitting module is used to receive the power value of the synchronization signal block SSB reported by the FPGA. When the power value exceeds a second preset threshold, it sends the SSB frequency point to the FPGA and serially sends the PSS sequence for the SSB frequency point so that the FPGA can determine the correlation sequence between the downlink synchronization signal and the current PSS sequence. When the correlation sequence meets the preset conditions, it performs primary synchronization according to the current PSS sequence.

11. A base station communication device, comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5 or 6 to 8.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5 or 6 to 8.

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