Semiconductor device and method of manufacturing the same

Abstract

The application discloses a semiconductor device and a preparation method thereof. The application forms multiple lightly-doped drain regions with different doping concentration gradients in the lateral direction by using a multi-layer structure side wall, self-alignment as an ion implantation blocking layer, and multiple ion implantation in multiple sections, so that the doping concentration of the lightly-doped drain structure formed by the multiple lightly-doped drain regions is gradually distributed, the heat carrier buffer can be effectively increased, the peak electric field can be further reduced, and the purpose of further improving the heat carrier injection effect is achieved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor process technology, and in particular to a semiconductor device capable of improving the HCI effect and its fabrication method. Background Technology

[0002] As process dimensions continue to shrink, the supply voltage does not decrease proportionally with the reduction in device channel length, junction depth, and gate oxide thickness, nor with the increase in substrate doping concentration. This leads to a significant increase in both the transverse and longitudinal electric fields of the channel. The high electric field accelerates carrier movement, transforming them into high-energy hot carriers, resulting in the hot carrier injection (HCI) effect. The HCI effect is a common problem in integrated circuit device design and a major factor affecting device characteristics and reliability. High-voltage complementary metal-oxide-semiconductor (CMOS) utilizes a lightly doped drain (LDD) structure to reduce the peak electric field near the gate to drain. The LDD structure acts as a transition region, introducing a gradual change in the electric field and weakening the peak electric field intensity, thus mitigating the HCI effect.

[0003] Currently, the traditional device manufacturing process involves: after gate etching, ion implantation (IMP) of the LDD structure is performed, followed by masking of the corresponding LDD structure region using a spacer process, and then ion implantation of the source / drain (S / D) region. This implantation sequence, due to the post-implantation thermal annealing (S / D at a higher temperature than LDD), causes the LDD region to be affected by the thermal budget of the S / D annealing, leading to further ion diffusion in the LDD region and thus reducing the HCI effect. However, the electric field change in the junction region after each LDD ion implantation is significant, resulting in a relatively high HCI. Another approach involves adding a second sidewall growth and removal process, achieving two LDD ion implantations. While this reduces the LDD ion concentration gradient, it requires process modifications to include the additional sidewall growth and removal processes, increasing both process time and cost.

[0004] Therefore, how to effectively increase the buffering of hot carriers and reduce the peak electric field based on the existing sidewall structure without adding new processes, thereby improving the HCI effect, has become an urgent technical problem to be solved. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a semiconductor device and its fabrication method, which can effectively increase the buffering of hot carriers and reduce the peak electric field based on the existing sidewall structure without adding new processes, thereby achieving the purpose of improving the HCI effect and saving process time and cost.

[0006] To address the aforementioned problems, an embodiment of the present invention provides a method for fabricating a semiconductor device, the method comprising the following steps: forming a substrate, the substrate comprising a substrate having an active region, a gate oxide layer covering the top surface of the substrate, a gate formed on the gate oxide layer, a pocket implantation region formed in the active region on both sides of the gate, and a first initial lightly doped drain region; forming a first sidewall material layer covering the gate, and performing lightly doped drain ion implantation in the first initial lightly doped drain region to form a second initial lightly doped drain region, wherein the first initial lightly doped drain region between the second initial lightly doped drain region and the pocket implantation region serves as the first lightly doped drain region; forming a layer covering the first sidewall material layer. A second sidewall material layer is formed by implanting lightly doped drain ions to form a third initial lightly doped drain region. The second initial lightly doped drain region between the third initial lightly doped drain region and the first lightly doped drain region serves as the second lightly doped drain region. An etching process is performed, and the remaining second sidewall material layer and the first sidewall material layer of the gate sidewall together form a sidewall. A source / drain region is formed in the third initial lightly doped drain region under the self-alignment of the sidewall. The third initial lightly doped drain region between the source / drain region and the second lightly doped drain region serves as the third lightly doped drain region. The first lightly doped drain region, the second lightly doped drain region, and the third lightly doped drain region, with their doping concentrations increasing sequentially, together constitute a lightly doped drain structure.

[0007] To address the above problems, one embodiment of the present invention also provides a semiconductor device, which is fabricated using the semiconductor device fabrication method described in the present invention.

[0008] The above technical solution, without requiring additional processes, utilizes a multi-layered sidewall structure. Self-aligned layers act as a barrier for ion implantation, and multi-segment ion implantation forms multiple lightly doped drain regions with varying lateral doping concentration gradients. The resulting lightly doped drain structure exhibits a progressively increasing doping concentration distribution, effectively increasing the buffering of hot carriers and further reducing the peak electric field, thereby improving the hot carrier injection effect. The presence of the pocket-shaped implantation region reduces the depletion degree of the depletion region, resulting in a smaller penetration current. By performing pocket-shaped ion implantation to form the pocket-shaped implantation region before forming the second protective layer, and then performing lightly doped drain ion implantation to form the first initial lightly doped drain region after forming the second protective layer, the concentration gradient between the pocket-shaped implantation region and the first initial lightly doped drain region is reduced, resulting in a gradual change in the electric field. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0011] Figure 2 This is a schematic diagram of the device structure of a substrate provided in an embodiment of the present invention;

[0012] Figure 3 This is a schematic diagram of the device structure after forming the bag-shaped injection region according to an embodiment of the present invention;

[0013] Figure 4 This is a schematic diagram of the device structure after forming a silicon nitride material layer according to an embodiment of the present invention;

[0014] Figure 5 This is a schematic diagram of the device structure after the formation of the second protective layer according to an embodiment of the present invention;

[0015] Figure 6 This is a schematic diagram of the device structure after forming a first initial lightly doped drain region according to an embodiment of the present invention;

[0016] Figure 7 This is a schematic diagram of the device structure after forming the first sidewall material layer according to an embodiment of the present invention;

[0017] Figure 8 This is a schematic diagram of the device structure after forming a second initial lightly doped drain region according to an embodiment of the present invention;

[0018] Figure 9 This is a schematic diagram of the device structure after forming the second sidewall material layer according to an embodiment of the present invention;

[0019] Figure 10 This is a schematic diagram of the device structure after forming a third initial lightly doped drain region according to an embodiment of the present invention;

[0020] Figure 11 This is a schematic diagram of the device structure after forming the third sidewall material layer according to an embodiment of the present invention;

[0021] Figure 12 This is a schematic diagram of the device structure after the sidewalls are formed, according to an embodiment of the present invention;

[0022] Figure 13This is a schematic diagram of the device structure after the source and drain regions are formed, according to an embodiment of the present invention;

[0023] Figure 14 A comparison diagram of the electric field distribution between single-segment ion implantation and three-segment ion implantation provided in an embodiment of the present invention. Detailed Implementation

[0024] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] One embodiment of the present invention provides a method for fabricating a semiconductor device.

[0026] Please refer to the following: Figures 1 to 13 ,in, Figure 1 This is a schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the device structure of a substrate provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the device structure after forming the bag-shaped injection region according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the device structure after forming a silicon nitride material layer according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the device structure after the formation of the second protective layer according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the device structure after forming a first initial lightly doped drain region according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the device structure after forming the first sidewall material layer according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the device structure after forming a second initial lightly doped drain region according to an embodiment of the present invention; Figure 9 This is a schematic diagram of the device structure after forming the second sidewall material layer according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the device structure after forming a third initial lightly doped drain region according to an embodiment of the present invention; Figure 11 This is a schematic diagram of the device structure after forming the third sidewall material layer according to an embodiment of the present invention; Figure 12 This is a schematic diagram of the device structure after the sidewalls are formed, according to an embodiment of the present invention; Figure 13 This is a schematic diagram of the device structure after the source and drain regions are formed, according to an embodiment of the present invention.

[0027] like Figure 1As shown, the method for fabricating the semiconductor device in this embodiment includes the following steps: S1, forming a substrate, the substrate including a substrate having an active region, a gate oxide layer covering the top surface of the substrate, a gate formed on the gate oxide layer, a pocket implantation region formed in the active region on both sides of the gate, and a first initial lightly doped drain region; S2, forming a first sidewall material layer covering the gate, and performing lightly doped drain ion implantation in the first initial lightly doped drain region to form a second initial lightly doped drain region, the first initial lightly doped drain region between the second initial lightly doped drain region and the pocket implantation region serving as the first lightly doped drain region; S3, forming a second sidewall material layer covering the first sidewall material layer. A third initial lightly doped drain region is formed by implanting lightly doped drain ions into the third initial lightly doped drain region and the second initial lightly doped drain region between the third initial lightly doped drain region and the first lightly doped drain region; S4, an etching process is performed, and the remaining second sidewall material layer of the gate sidewall and the first sidewall material layer together form a sidewall; and S5, a source / drain region is formed in the third initial lightly doped drain region under the self-alignment of the sidewall, and the third initial lightly doped drain region between the source / drain region and the second lightly doped drain region serves as the third lightly doped drain region. The first lightly doped drain region, the second lightly doped drain region, and the third lightly doped drain region, with their doping concentrations increasing sequentially, together constitute a lightly doped drain structure.

[0028] Please refer to step S1 and Figure 6 A substrate is formed, comprising a substrate 20 having an active region AA, a gate oxide layer 21 covering the top surface of the substrate 20, a gate 22 formed on the gate oxide layer 21, pocket implantation regions 23 formed in the active regions AA on both sides of the gate 22, and a first initial lightly doped drain region 240. Specifically, a first direction D1 is defined to be parallel to the top surface of the substrate 20, and a second direction D2 is defined to be perpendicular to the top surface of the substrate 20.

[0029] In this embodiment, in a first direction D1 parallel to the top surface of the substrate 20, the bag-shaped implantation region 23 and the first initial lightly doped drain region 240 are sequentially moved away from the gate 22.

[0030] In this embodiment, the step of forming the substrate specifically includes: (1) providing a substrate 20, wherein the active region AA is isolated in the substrate 20 by an isolation structure (not shown), the top surface of the substrate 20 is covered with the gate oxide layer 21, and the gate 22 is formed on the gate oxide layer 21, such as Figure 2 As shown; (2) A first protective layer 31 is formed covering the gate 22, and bag-shaped ion implantation is performed to form a bag-shaped implantation region 23 located partially below the gate 22 in the active region AA, as shown. Figure 3As shown; (3) a second protective layer 51 is formed covering the first protective layer 31 of the gate 22 sidewall, and lightly doped drain ions are implanted into the active region AA to form a first initial lightly doped drain region 240 located on the side of the bag-shaped implantation region 23 away from the gate 22, as shown. Figure 6 As shown.

[0031] The presence of the pocket implantation region 23 can reduce the depletion degree of the depletion region, thereby generating a smaller penetration current. In this embodiment, by performing pocket ion implantation (Pocket IMP) to form the pocket implantation region 23 before forming the second protective layer 51, and then performing lightly doped drain ion implantation (LDDIMP) to form the first initial lightly doped drain region 240 after forming the second protective layer 51, the concentration gradient between the pocket implantation region 23 and the first initial lightly doped drain region 240 can be reduced, resulting in a gradual change in the electric field.

[0032] In some embodiments, the substrate 20 is used to support the device structure above it, and the device structure can also be formed in the substrate. In this embodiment, the substrate 20 may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.; the substrate 20 may also be a stacked structure, such as a silicon / silicon germanium stack. The gate oxide layer 21 may be made of silicon dioxide (SiO2), and the silicon dioxide film layer covering the top surface of the substrate 20 can prevent subsequent processes from damaging the top surface of the substrate 20.

[0033] In this embodiment, the material of the gate 22 is polysilicon, and the step of forming the first protective layer 31 covering the gate 22 specifically includes: performing an oxidation process to oxidize the polysilicon on the surface of the gate 22 to form a silicon dioxide layer covering the gate 22 as the first protective layer 31.

[0034] In this embodiment, the step of forming a second protective layer 51 covering the first protective layer 31 covering the sidewall of the gate 22 specifically includes: (31) depositing silicon nitride (SiN) material to form a silicon nitride material layer 510 covering the gate oxide layer 21 and the first protective layer 31, such as Figure 4 As shown; (32) The silicon nitride material layer 510 outside the sidewall of the gate 22 is etched away using an anisotropic etching process, and the remaining silicon nitride material layer 510 forms the second protective layer 51, as shown. Figure 5As shown. Specifically, the thickness of the silicon nitride material layer 510 is 90 to 110 angstroms; for example, it can be 90 angstroms, 95 angstroms, 100 angstroms, 105 angstroms, 110 angstroms, etc.

[0035] Anisotropic etching can be understood as etching only downwards, without lateral etching. Because the silicon nitride material layer 510 is supported by a silicon dioxide layer serving as the first protective layer 31, the etching stops on the silicon dioxide layer and does not affect the substrate 20. Specifically, after etching using the anisotropic etching process, the first protective layer 31 on top of the gate 22 is retained, the silicon nitride material layer 510 outside the sidewalls of the gate 22 is etched away, and the silicon nitride material layer 510 on the sidewalls of the gate 22 is retained to form the second protective layer 51. The total width of the first protective layer 31 and the second protective layer 51 on the sidewalls of the gate 22 is the length of the subsequently formed first lightly doped drain region 24.

[0036] Please refer to step S2 and Figure 7 , Figure 8 A first sidewall material layer 710 is formed to cover the gate 22, such as... Figure 7 As shown; and lightly doped drain ions are implanted into the first initial lightly doped drain region 240 to form a second initial lightly doped drain region 250. The first initial lightly doped drain region 240 between the second initial lightly doped drain region 250 and the bag-shaped implantation region 23 serves as the first lightly doped drain region 24. Figure 8 As shown. The thickness of the first sidewall material layer 710 is sufficient to allow ion implantation to pass through the layer.

[0037] After the first sidewall material layer 710 is formed, lightly doped drain ion implantation is performed directly. Ion implantation can penetrate the relatively thin first sidewall material layer 710, and normal ion implantation can be achieved while reducing the number of etching steps.

[0038] In this embodiment, in a first direction D1 parallel to the top surface of the substrate 20, the bag-shaped implantation region 23 and the first lightly doped drain region 24 are sequentially moved away from the gate 22; the second initial lightly doped drain region 250 is located on the side of the first lightly doped drain region 24 away from the bag-shaped implantation region 23.

[0039] In this embodiment, the material of the first sidewall material layer 710 is TEOS. TEOS generally refers to tetraethoxysilane, also known as tetraethyl silicate, which is an organic compound mainly used as an electrical insulating material. At the same time, the decomposition reaction of TEOS can reduce the thickness of the second protective layer 51 using SIN, thereby reducing the film stress of SIN.

[0040] Please refer to step S3 and Figure 9 , Figure 10 Forming a second sidewall material layer 910 covering the first sidewall material layer 710, such as Figure 9 As shown; and lightly doped drain ion implantation is performed to form a third initial lightly doped drain region 260, the second initial lightly doped drain region 250 between the third initial lightly doped drain region 260 and the first lightly doped drain region 24 serves as the second lightly doped drain region 25, as shown. Figure 10 As shown. The total thickness of the second sidewall material layer 910 and the first sidewall material layer 710 is sufficient to allow ion implantation to penetrate the total film layer.

[0041] After the second sidewall material layer 910 is formed, lightly doped drain ion implantation is performed directly. Ion implantation can penetrate the thinner second sidewall material layer 910 and the first sidewall material layer 710, thus achieving normal ion implantation while reducing the number of etching steps.

[0042] In this embodiment, in a first direction D1 parallel to the top surface of the substrate 20, the bag-shaped implantation region 23 and the first lightly doped drain region 24 are sequentially moved away from the gate 22; the second lightly doped drain region 25 is located on the side of the first lightly doped drain region 24 away from the bag-shaped implantation region 23; and the third initial lightly doped drain region 260 is located on the side of the second lightly doped drain region 25 away from the first lightly doped drain region 24.

[0043] In this embodiment, the material of the second sidewall material layer 910 is silicon nitride (SiN).

[0044] like Figure 11 As shown, to reduce the film stress of silicon nitride (SiN), one embodiment of the present invention further includes, after the step of forming the third initial lightly doped drain region 260, performing TEOS deposition again to form a third sidewall material layer 110 covering the second sidewall material layer 910. The TEOS in the third sidewall material layer 110 undergoes a decomposition reaction, which can reduce the film thickness of the silicon nitride film layer of the second sidewall material layer 910. Correspondingly, in the subsequent step S4, the third sidewall material layer 110 is also partially etched. The remaining third sidewall material layer 110, the second sidewall material layer 910, and the first sidewall material layer 710 on the sidewall of the gate 22 together form the sidewall 29, as shown. Figure 12 As shown.

[0045] Please refer to step S4 and Figure 12 An etching process is performed, and the remaining second sidewall material layer 910 and the first sidewall material layer 710 on the sidewall of the gate 22 together form the sidewall 29.

[0046] When the third sidewall material layer 110 is formed after the step of forming the third initial lightly doped drain region 260, the third sidewall material layer 110 is also partially etched in the etching process described in step S4. The remaining third sidewall material layer 110, the second sidewall material layer 910, and the first sidewall material layer 710 on the sidewall of the gate 22 together form the sidewall 29. Simultaneously, the first protective layer 31 and the second protective layer 51 at the sidewall of the gate 22 can also serve as part of the sidewall 29.

[0047] Please refer to step S5 and Figure 13 Under the self-alignment of the sidewall 29, a source / drain region 28 is formed in the third initial lightly doped drain region 260. The third initial lightly doped drain region 260 between the source / drain region 28 and the second lightly doped drain region 25 serves as the third lightly doped drain region 26. The first lightly doped drain region 24, the second lightly doped drain region 25, and the third lightly doped drain region 26, with their doping concentrations increasing sequentially, together constitute a lightly doped drain structure. That is, by utilizing the sidewalls of the existing sandwich structure as barriers, three-stage LDD ion implantation is directly achieved through multi-segment ion implantation without adding any new processes.

[0048] In this embodiment, in a first direction D1 parallel to the top surface of the substrate 20, the bag-shaped implantation region 23 and the first lightly doped drain region 24 are sequentially located away from the gate 22; the second lightly doped drain region 25 is located on the side of the first lightly doped drain region 24 away from the bag-shaped implantation region 23; the third lightly doped drain region 26 is located on the side of the second lightly doped drain region 25 away from the first lightly doped drain region 24; and the source / drain region 28 is located on the side of the third lightly doped drain region 26 away from the second lightly doped drain region 25.

[0049] In this embodiment, with a straight line passing through the center of the gate 22 and perpendicular to the top surface of the substrate 20 as the axis of symmetry 131, the bag-shaped implantation region 23, the lightly doped drain structure, and the source / drain region 28 are symmetrically distributed on both sides of the gate 22.

[0050] In this embodiment, the lightly doped drain ions implanted in the first lightly doped drain region 24, the second lightly doped drain region 25, and the third lightly doped drain region 26 are all N-type lightly doped drain ions (NLDD); correspondingly, the formed transistor is an NMOS transistor. NLDD ion implantation is low-energy, shallow-junction, and low-doped arsenic (As) ion implantation, which can effectively weaken the hot carrier injection (HCI) effect of NMOS. In some embodiments, the lightly doped drain ion implantation energy is 2.8–7K and the dose is 5–8E14 As; the second lightly doped drain region implantation energy is 2–5K and the dose is 5–8E14 As; and the third lightly doped drain region implantation energy is 2.8–7K and the dose is 5–8E14 As. This effectively increases the buffering of hot carriers on the band diagram, further reducing the peak electric field and reducing the HCI effect by 30%.

[0051] Please see Figure 14 This figure shows a comparison of the electric field distribution of single-segment and three-segment ion implantation according to an embodiment of the present invention. In the figure, reference numeral 141 represents the electric field distribution of single-segment ion implantation in the prior art, and reference numeral 143 represents the electric field distribution of three-segment ion implantation according to the present invention. Figure 14 It can be seen that the semiconductor device fabrication method provided by the present invention can effectively increase the buffer of hot carriers and further reduce the peak electric field, thereby achieving the purpose of further improving the hot carrier injection effect.

[0052] In the above embodiments of the present invention, without the need for additional processes, a multi-layer structure sidewall is used as a barrier layer for ion implantation through self-alignment. By performing multi-segment ion implantation, multiple lightly doped drain regions with different lateral doping concentration gradients are formed. The doping concentration of the lightly doped drain structure formed by the multiple lightly doped drain regions is gradually distributed, which can effectively increase the buffering of hot carriers and further reduce the peak electric field, thereby achieving the purpose of further improving the hot carrier injection effect.

[0053] Based on the same inventive concept, one embodiment of the present invention provides a semiconductor device, which is formed by using the above-described semiconductor device fabrication method of the present invention to form a lightly doped drain structure semiconductor device composed of a first lightly doped drain region, a second lightly doped drain region, and a third lightly doped drain region with sequentially increasing doping concentrations.

[0054] Please refer to the following: Figures 2 to 13 The semiconductor device provided in one embodiment of the present invention is formed by the semiconductor device fabrication method described above. The lightly doped drain structure of the semiconductor device is composed of a first lightly doped drain region, a second lightly doped drain region, and a third lightly doped drain region with sequentially increasing doping concentration.

[0055] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context; it should be understood that such use of data can be interchanged where appropriate. The term "one or more" depends at least in part on the context and can be used to describe features, structures, or characteristics in a singular sense, or in a plural sense to describe combinations of features, structures, or characteristics. The term "based on" can be understood as not necessarily intended to express an exclusive set of factors, but can instead, also at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, embodiments and features in embodiments of this invention can be combined with each other without conflict. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar / identical parts between embodiments can be referred to mutually.

[0056] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The method includes the following steps: A substrate is formed, the substrate including a substrate having an active region, a gate oxide layer covering the top surface of the substrate, a gate formed on the gate oxide layer, a bag-shaped implantation region formed in the active region on both sides of the gate, and a first initial lightly doped drain region; A first sidewall material layer is formed to cover the gate, and lightly doped drain ions are implanted into the first initial lightly doped drain region to form a second initial lightly doped drain region. The first initial lightly doped drain region between the second initial lightly doped drain region and the bag implantation region is used as the first lightly doped drain region. The film thickness of the first sidewall material layer is sufficient to allow ion implantation to penetrate the first sidewall material layer. A second sidewall material layer is formed covering the first sidewall material layer, and lightly doped drain ion implantation is performed to form a third initial lightly doped drain region. The second initial lightly doped drain region between the third initial lightly doped drain region and the first lightly doped drain region is called the second lightly doped drain region. The total thickness of the second sidewall material layer and the first sidewall material layer satisfies that the ion implantation can penetrate the second sidewall material layer and the first sidewall material layer. The etching process is performed, and the remaining second sidewall material layer and the first sidewall material layer of the gate sidewall together form the sidewall; A source / drain region is formed in the third initial lightly doped drain region under the self-alignment of the sidewall. The third initial lightly doped drain region between the source / drain region and the second lightly doped drain region serves as the third lightly doped drain region. The first lightly doped drain region, the second lightly doped drain region, and the third lightly doped drain region, with their doping concentrations increasing sequentially, together constitute a lightly doped drain structure.

2. The method according to claim 1, characterized in that, In a first direction parallel to the top surface of the substrate, the bag-shaped implantation region and the first initial lightly doped drain region are sequentially located away from the gate, the second initial lightly doped drain region is located on the side of the first initial lightly doped drain region away from the bag-shaped implantation region, the third initial lightly doped drain region is located on the side of the second initial lightly doped drain region away from the first lightly doped drain region, and the source / drain region is located on the side of the third initial lightly doped drain region away from the second lightly doped drain region.

3. The method according to claim 1, characterized in that, With a straight line passing through the center of the gate and perpendicular to the top surface of the substrate as the axis of symmetry, the bag-shaped implantation region, the lightly doped drain structure, and the source / drain region are symmetrically distributed on both sides of the gate.

4. The method according to claim 1, characterized in that, The steps for forming the substrate specifically include: A substrate is provided in which the active region is isolated by an isolation structure, the top surface of the substrate is covered with the gate oxide layer, and the gate is formed on the gate oxide layer; A first protective layer is formed to cover the gate, and bag-shaped ion implantation is performed to form a bag-shaped implantation region partially located below the gate in the active region; A second protective layer is formed to cover the first protective layer on the gate sidewall, and lightly doped drain ions are implanted into the active region to form a first initial lightly doped drain region located on the side of the bag implantation region away from the gate.

5. The method according to claim 4, characterized in that, The gate is made of polycrystalline silicon, and the step of forming a first protective layer covering the gate specifically includes: performing an oxidation process to oxidize the polycrystalline silicon on the gate surface to form a silicon dioxide layer covering the gate as the first protective layer.

6. The method according to claim 4, characterized in that, The step of forming a second protective layer covering the first protective layer of the gate sidewall specifically includes: A silicon nitride material layer is formed by depositing silicon nitride material to cover the gate oxide layer and the first protective layer; An anisotropic etching process is used to etch away the silicon nitride material layer other than the gate sidewall, and the remaining silicon nitride material layer forms the second protective layer.

7. The method according to claim 6, characterized in that, The thickness of the silicon nitride material layer is 90~110 angstroms.

8. The method according to claim 1, characterized in that, The material of the first sidewall material layer is TEOS, and the material of the second sidewall material layer is silicon nitride.

9. The method according to claim 8, characterized in that, The step of forming the third initial lightly doped drain region further includes: TEOS deposition is performed again to form a third sidewall material layer covering the second sidewall material layer. The TEOS in the third sidewall material layer undergoes a decomposition reaction, which can reduce the film thickness of the silicon nitride film layer of the second sidewall material layer. In the step of performing the etching process, the third sidewall material layer is also partially etched, and the remaining third sidewall material layer, the second sidewall material layer, and the first sidewall material layer of the gate sidewall together form the sidewall.

10. A semiconductor device, characterized in that, The semiconductor device is fabricated using the semiconductor device fabrication method according to any one of claims 1 to 9, and the lightly doped drain structure of the semiconductor device is composed of a first lightly doped drain region, a second lightly doped drain region, and a third lightly doped drain region with sequentially increasing doping concentration.

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