Copper metal reversed polarity red light emitting diode and preparation method thereof

Abstract

The invention discloses a copper metal reversed polarity red light emitting diode and a preparation method thereof. The light emitting diode comprises an n electrode, a passivation layer, an epitaxial layer structure, a SiO2 dielectric material layer, an ohmic contact layer, a bonding layer, a Si substrate and a back gold layer. The bonding layer adopts a multi-layer design of Au, Ti, Pt and Cu, a face-centered cubic structure of Cu is formed, and the lt is preferably exposed; 111gt, 111gt; and according to the crystal face, reliable combination of the epitaxial layer and the Si substrate is realized through high vacuum of the Cu layer and a two-section type low-temperature bonding process. According to the invention, the usage amount of precious metal is effectively reduced, the interface voidage is reduced, and the light extraction efficiency and long-term use reliability of the chip are improved.

Description

Technical Field

[0001] The invention relates to the field of semiconductor devices, and in particular to a copper metal reverse polarity red light emitting diode and a preparation method thereof. Background Art

[0002] The reverse polarity LED chip replaces the substrate by removing the GaAs substrate with large light absorption and bonding the epitaxial layer to a Si substrate or sapphire substrate. This structure can effectively improve the light extraction efficiency of the chip.

[0003] The bonding layer material of the reverse polarity product generally uses Au-Au or Au-In or Ag-In as the two-layer bonding metal material. This manufacturing method is costly and has a complicated process. For example, in the prior art, Chinese patent CN105047788A proposes a thin-film structure LED chip based on silver-based metal bonding and its preparation method, using AgCuIn alloy as the bonding metal layer. This manufacturing method uses precious metal Ag, and on the other hand, the process is complicated, resulting in problems such as high cost and low yield.

[0004] Therefore, how to simplify the substrate replacement process, reduce manufacturing costs and improve the quality of the bonding interface has become an urgent problem to be solved in the current technology. In response to the above problems, the present invention proposes an efficient bonding process based on the Cu layer, which significantly improves the performance and reliability of the reverse polarity LED chip by optimizing material design and process conditions. Summary of the invention

[0005] The present invention provides a copper metal reverse polarity red light emitting diode and a preparation method thereof, aiming to improve the luminous efficiency, heat dissipation performance and bonding strength of the device through innovative structural design and manufacturing process, while reducing the manufacturing cost.

[0006] The technical solution of the present invention is as follows: A copper metal reverse polarity red light emitting diode, comprising the following structure: (1) The n-electrode is located at the top of the chip and is composed of Au, AuGeNi and Au multilayer metals. It is used to directly connect to the n-GaAs ohmic contact layer and provide a negative electrical interface. (2) a passivation layer covering the surface of the epitaxial layer, used to protect the epitaxial layer and improve light extraction efficiency, wherein the passivation layer is made of SiNx and has a thickness of 100-300 nm; (3) An epitaxial layer structure, located below the passivation layer, comprising: n-GaAs ohmic contact layer, used for the introduction of electrons; n-AlGaInP roughened extension layer to expand current distribution and improve light extraction efficiency; Multiple quantum well (MQW) light-emitting active layer, used for the recombination of electrons and holes to generate light; p-AlInP is an electron confinement layer used to limit the excessive diffusion of electrons from the multi-quantum well (MQW) light-emitting active layer to the p-type region; p-GaP ohmic contact layer, used to provide low resistance contact with the p-type region; (4) a SiO2 dielectric material layer, disposed below the epitaxial layer, for protecting the epitaxial layer and defining a light-emitting area, wherein a plurality of openings having a diameter of 4-6 μm and a spacing of 6-10 μm are formed on the surface of the SiO2 dielectric material layer, for defining the light-emitting area; (5) an ohmic contact layer, located below the SiO2 dielectric material layer, for providing a low-resistance electrical connection, directly connected to the p-GaP ohmic contact layer through the opening, and having a thickness of 100-300 nm; (6) Bonding layer: The bonding layer includes a first bonding layer arranged at the bottom of the epitaxial layer and a second bonding layer arranged at the top of the Si substrate; The first bonding layer and the second bonding layer each include: Au layer; Ti layer; Pt layer; Cu layer, wherein the Cu layer has a thickness of 500-900nm, has a face-centered cubic (FCC) structure, and forms <111> Preferred orientation of crystal planes; The Cu layer of the first bonding layer is bonded to the Cu layer of the second bonding layer to form a strong bonding interface for connecting the epitaxial layer to the Si substrate; (7) a Si substrate, disposed below the second bonding layer, for providing mechanical support, thermal conduction and electrical conduction paths; (8) Back gold layer, located at the bottom of the chip, including Ti layer or Au layer, used as the P-electrode conductive layer to connect to the negative pole of the external circuit.

[0007] Preferably, the carbon (C) doping concentration of the p-GaP ohmic contact layer is greater than 5×10 19 atoms·cm -3 , with a thickness of 1500-2500Å, is used to provide a low resistance contact.

[0008] Preferably, the thickness of the SiO2 dielectric material layer is 200-500 nm.

[0009] Preferably, the ohmic contact layer comprises an AuZn layer with a thickness of 100-300 nm.

[0010] Preferably, the thickness of each of the Au layer, the Ti layer and the Pt layer is 100-300 nm.

[0011] Preferably, the back gold layer is a Ti layer or an Au layer with a thickness of 50-200 nm.

[0012] The method for preparing the copper metal reverse polarity red light emitting diode comprises the following steps: (1) Epitaxial growth: The following layer structures are formed in sequence by epitaxial growth on a GaAs substrate: GaAs buffer layer; GaInP etch stop layer; n-GaAs ohmic contact layer; n-AlGaInP roughened extension layer; Multiple quantum well (MQW) light-emitting active layer; p-AlInP electron confinement layer; p-GaP ohmic contact layer; (2) Dielectric material deposition: depositing a SiO2 dielectric material layer on the surface of the p-GaP ohmic contact layer with a thickness of 200-500 nm; (3) Opening pattern production: forming a plurality of openings on the SiO2 dielectric material layer by photolithography, wherein the diameter of the openings is 4-6 μm and the spacing between the openings is 6-10 μm; (4) Formation of an ohmic contact layer: evaporating an AuZn layer with a thickness of 100-300 nm on the surface of the SiO2 dielectric material layer, and directly contacting the p-GaP ohmic contact layer; (5) Bonding layer preparation: forming an Au layer, a Ti layer, a Pt layer and a Cu layer in sequence at the bottom of the epitaxial layer; An Au layer, a Ti layer, a Pt layer and a Cu layer are sequentially formed on the surface of the Si substrate; (6) Bonding the epitaxial layer to the Si substrate: bonding the epitaxial layer to the Cu layer on the Si substrate to form a strong bonding interface; (7) Removing the substrate: removing the GaAs substrate, the GaAs buffer layer and the GaInP etching stop layer in sequence by wet etching to expose the n-GaAs ohmic contact layer; (8) Electrode formation: Vapor depositing an n-electrode on the surface of the n-GaAs ohmic contact layer, which is composed of Au, AuGeNi and Au multilayer metals; (9) Preparation of passivation layer: A SiNx passivation layer with a thickness of 100-300 nm is deposited on the surface of the epitaxial layer to protect the epitaxial layer and improve light extraction efficiency; x represents the stoichiometric ratio of silicon and nitrogen; (10) Formation of back gold layer: A Ti layer or an Au layer is sequentially formed at the bottom of the Si substrate to serve as a P electrode.

[0013] Preferably, each layer in the bonding layer is prepared by evaporation, the temperature of the Cu layer is 100-120° C., and the deposition rate is 5-8 Å / s.

[0014] Preferably, the bonding of the epitaxial layer to the Si substrate comprises the following steps: (1) Perform preliminary bonding of the epitaxial layer and the Cu layer of the Si substrate at 200-220°C for 2-5 minutes, with a heating rate of 2-5°C / second; (2) Perform secondary bonding at 280-300°C for 15-20 minutes with a heating rate of 2-3°C / s to eliminate interface voids and form a strong bonding interface.

[0015] Preferably, the bonding process is carried out within 10 -2 -10 -1 Pa under vacuum.

[0016] The present invention uses a multilayer bonding material composed of Au, Ti, Pt and Cu, and improves the bonding strength and thermal conductivity between the epitaxial layer and the Si substrate through reasonable material selection and process optimization. When the Cu layer is evaporated, the temperature (100-120°C) and the deposition rate (5-8Å / s) are controlled to promote the Cu atoms to form a face-centered cubic (FCC) structure and preferentially expose <111> The crystal plane has the highest atomic diffusion rate and the least dangling bonds. During the bonding process, high vacuum (10 -2 -10 -1 The Pa) environment suppresses the formation of oxides, and adopts a two-stage partial pressure variable temperature bonding process. The first stage (200-220℃) is used for rapid bonding to reduce the oxide layer, and the second stage (280-300℃) is used for slow heating to optimize the interface structure and eliminate voids, forming a high-strength, low-void rate copper-copper bonding interface, thereby achieving reliable connection between the epitaxial layer and the Si substrate.

[0017] The following technical effects are achieved by designing the material combination of the present invention and optimizing the process conditions: (1) Cost reduction: reducing the use of precious metals (such as Au) while maintaining good optical reflective properties; (2) Improved optical performance: The bonding process is carried out under high vacuum and low temperature conditions, which inhibits the formation of oxides, maintains the metal mirror reflectivity, and improves light extraction efficiency; (3) Interface quality optimization: Through a two-stage bonding process, oxides and interface voids are reduced to form a flat and uniform bonding interface; (4) Excellent mechanical properties and thermal conductivity: FCC structure of Cu layer and <111> The crystal face characteristics ensure that the interface has high bonding strength and thermal conductivity; (5) Long-term reliability: The copper-copper bond provides excellent mechanical strength and heat resistance, meeting the application requirements of large-current, large-size reverse polarity red light-emitting diode chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic structural diagram of the copper metal reverse polarity red light emitting diode of the present invention. DETAILED DESCRIPTION

[0019] The present invention is further described below in conjunction with the accompanying drawings and specific examples, but the present invention is not limited to the following examples. In the embodiments of the present invention, the specific process conditions, parameter ranges and material selections described are all for the purpose of clearly and completely illustrating the technical solution of the present invention, and are not intended to limit the scope of protection of the present invention. Those skilled in the art may adjust or equivalently replace the implementation methods according to specific needs without departing from the spirit and essence of the present invention, and these adjustments or replacements should be deemed to fall within the scope of protection of the present invention.

[0020] Embodiment 1: Structural design of copper metal reverse polarity red light emitting diode.

[0021] 1. N electrode 207 Located at the top of the chip, it is composed of multiple layers of Au, AuGeNi and Au metals, and is directly connected to the n-GaAs ohmic contact layer to provide a negative electrical interface.

[0022] 2. Passivation layer 205 Covering the surface of the epitaxial layer to protect the epitaxial layer and improve light extraction efficiency. The passivation layer material is SiNx with a thickness of 100-300nm.

[0023] 3. Epitaxial layer structure The epitaxial layer structure includes: n-GaAs ohmic contact layer 101 (doping concentration greater than 5×10 19 atoms·cm -3 ), used for the import of electrons; n-AlGaInP roughened extension layer 102, used to expand current distribution and improve light extraction efficiency; The multi-quantum well (MQW) light-emitting active layer 103 is composed of GaInP and AlGaInP quantum wells and is used for electron-hole recombination to generate red light with a wavelength of 610-630nm; p-AlInP electron confinement layer 104, p-GaP ohmic contact layer 105 (doping concentration greater than 5×10 19 atoms·cm -3, with a thickness of 1500-2500Å) to provide a low-resistance contact to the p-type region.

[0024] 4. SiO2 dielectric material layer 201 It is set below the epitaxial layer, with a thickness of 200-500nm, and multiple openings (with a diameter of 4-6μm and a spacing of 6-10μm) are formed on the surface to define the light-emitting area and current channel.

[0025] 5. Ohmic contact layer 202 Located below the SiO2 dielectric material layer, it is composed of an AuZn layer (thickness 100-300nm) and is directly connected to the p-GaP ohmic contact layer through the opening of the SiO2 dielectric material layer to provide a low-resistance electrical interface.

[0026] 6. Bonding layer 203 The method comprises a first bonding layer disposed at the bottom of the epitaxial layer and a second bonding layer disposed on the top of the Si substrate. Both layers include Au, Ti, Pt and Cu metal layers, wherein the Cu layer has a thickness of 500-900 nm, forms a face-centered cubic (FCC) structure and preferably exposes <111> The first bonding layer and the second bonding layer Cu layer are placed in a high vacuum (10 -2 Pa-10 -1 A strong bonding interface is formed by two-stage bonding under high temperature (Pa) and low temperature conditions.

[0027] 7. Si substrate 300 It is arranged below the second bonding layer to provide mechanical support and thermal conduction channels.

[0028] 8. Back gold layer 206 It is located at the bottom of the chip and consists of a Ti layer and an Au layer (thickness 50-200nm). It is used to connect to the negative electrode of the external circuit and provide heat dissipation.

[0029] Example 2: Preparation method of copper metal reverse polarity red light emitting diode.

[0030] 1. Epitaxial Growth The following layer structures are epitaxially grown on the GaAs substrate in sequence: GaAs buffer layer; GaInP etch stop layer; n-GaAs ohmic contact layer 101; n-AlGaInP roughened extension layer 102; A multi-quantum well (MQW) light-emitting active layer 103; p-AlInP electron confinement layer 104; p-GaP ohmic contact layer 105 .

[0031] 2. Dielectric material deposition A SiO2 dielectric material layer 201 is deposited on the surface of the epitaxial layer with a thickness of 200-500 nm.

[0032] 3. Opening pattern production A plurality of openings are formed on the surface of the SiO2 dielectric material layer 201 by photolithography and wet etching, with a diameter of 4-6 μm and a spacing of 6-10 μm.

[0033] 4. Formation of Ohmic Contact Layer 202 An AuZn layer (thickness 100-300 nm) is evaporated on the surface of the SiO 2 dielectric material layer 201 and is directly connected to the p-GaP ohmic contact layer 105 through the opening.

[0034] 5. Preparation of bonding layer 203 An Au layer, a Ti layer, a Pt layer and a Cu layer are sequentially evaporated on the bottom of the epitaxial layer; An Au layer, a Ti layer, a Pt layer and a Cu layer are sequentially evaporated on the surface of a Si substrate.

[0035] The thickness of each layer of Au, Ti and Pt is controlled at 100-300nm, the temperature of Cu layer during evaporation is controlled at 100-120℃, and the deposition rate is 5-8Å / s to ensure that the Cu layer forms a face-centered cubic (FCC) structure, preferably exposed <111> Before bonding, the Cu layer was cleaned with a combination of ACE and citric acid to reduce oxide and organic residues, maintain surface roughness, and improve bonding interface strength and uniformity.

[0036] 6. Bonding the epitaxial layer to the Si substrate 300 Perform preliminary bonding between the epitaxial layer and the Cu layer of the Si substrate at 200-220°C for 2-5 minutes, with a heating rate of 2-5°C / second; Then, secondary bonding is performed at 280-300°C for 15-20 minutes with a heating rate of 2-3°C / second to eliminate interface voids and form a strong bonding interface.

[0037] 7. Substrate Removal The GaAs substrate, the GaAs buffer layer and the GaInP etching stop layer are removed in sequence by wet etching to expose the n-GaAs ohmic contact layer.

[0038] 8. Electrode Formation After the photolithography process, the required pad pattern is formed, and the n-electrode (composed of Au, AuGeNi and Au multilayer metals) is evaporated on the surface of the n-GaAs ohmic contact layer by electron beam evaporation; the thickness is 0.2-2μm, and the photoresist is removed after the evaporation is completed; The above chips are subjected to high temperature annealing, the annealing temperature is 280-300°C, and the time is 10-15min; The surface of the n-AlGaInP roughened extension layer of the above chip is roughened by chemical wet method; Through the photolithography process, a pattern of the required size of the light-emitting layer is formed, and the GaP layer is etched using the ICP method to remove the photoresist.

[0039] 9. Deposition of passivation layer 205 A SiNx passivation layer (thickness 100-300nm) is deposited on the surface of the epitaxial layer to protect the epitaxial layer and improve light extraction efficiency. After the photolithography process, the metal surface in the pad electrode area is exposed, and the exposed SiNx layer is removed using a buffered oxide etchant (BOE) to remove the photoresist.

[0040] 10. Formation of back gold layer 206 A Ti layer and an Au layer are sequentially evaporated on the bottom of the Si substrate to serve as a P electrode and provide a negative connection.

[0041] Through the description of the above embodiments, those skilled in the art can clearly understand the technical solutions of the present invention and its beneficial effects. However, it should be pointed out that the above embodiments are only specific implementations of the present invention and do not limit the scope of protection of the present invention. The scope of protection of the present invention shall be based on the claims, and any modification, equivalent replacement or improvement within the core concept and technical framework of the present invention shall be deemed to be included in the scope of protection of the present invention.

Claims

1. A copper metal reverse polarity red light emitting diode, characterized in that: Includes the following structures: (1) The n-electrode is located at the top of the chip and is composed of Au, AuGeNi and Au multilayer metals. It is used to directly connect to the n-GaAs ohmic contact layer and provide a negative electrical interface. (2) a passivation layer covering the surface of the epitaxial layer, used to protect the epitaxial layer and improve light extraction efficiency, wherein the passivation layer is made of SiNx and has a thickness of 100-300 nm; (3) An epitaxial layer structure, located below the passivation layer, comprising: n-GaAs ohmic contact layer, used for the introduction of electrons; n-AlGaInP roughened extension layer to expand current distribution and improve light extraction efficiency; A multi-quantum well light-emitting active layer is used to generate light through the recombination of electrons and holes; The p-AlInP electron confinement layer is used to limit the excessive diffusion of electrons from the multi-quantum well light-emitting active layer to the p-type region; p-GaP ohmic contact layer, used to provide low resistance contact with the p-type region; (4) a SiO2 dielectric material layer, disposed below the epitaxial layer, for protecting the epitaxial layer and defining a light-emitting area, wherein a plurality of openings having a diameter of 4-6 μm and a spacing of 6-10 μm are formed on the surface of the SiO2 dielectric material layer, for defining the light-emitting area; (5) an ohmic contact layer, located below the SiO2 dielectric material layer, for providing a low-resistance electrical connection, directly connected to the p-GaP ohmic contact layer through the opening, and having a thickness of 100-300 nm; (6) Bonding layer: The bonding layer includes a first bonding layer arranged at the bottom of the epitaxial layer and a second bonding layer arranged at the top of the Si substrate; The first bonding layer and the second bonding layer each include: Au layer; Ti layer; Pt layer; Cu layer, wherein the thickness of the Cu layer is 500-900nm, has a face-centered cubic structure, and forms <111> Preferred orientation of crystal planes; The Cu layer of the first bonding layer is bonded to the Cu layer of the second bonding layer to form a strong bonding interface for connecting the epitaxial layer to the Si substrate; (7) a Si substrate, disposed below the second bonding layer, for providing mechanical support, thermal conduction and electrical conduction paths; (8) Back gold layer, located at the bottom of the chip, including Ti layer or Au layer, used as the P-electrode conductive layer to connect to the negative pole of the external circuit.

2. The copper metal reverse polarity red light emitting diode according to claim 1, characterized in that: The doping concentration of the p-GaP ohmic contact layer is greater than 5×10 19 atoms·cm -3 , with a thickness of 1500-2500Å, is used to provide a low resistance contact.

3. The copper metal reverse polarity red light emitting diode according to claim 1, characterized in that: The thickness of the SiO2 dielectric material layer is 200-500nm.

4. The copper metal reverse polarity red light emitting diode according to claim 1, characterized in that: The ohmic contact layer includes an AuZn layer with a thickness of 100-300 nm.

5. The copper metal reverse polarity red light emitting diode according to claim 1, characterized in that: The thickness of each of the Au layer, Ti layer and Pt layer is 100-300nm.

6. The copper metal reverse polarity red light emitting diode according to claim 1, characterized in that: The back gold layer is a Ti layer or an Au layer, and has a thickness of 50-200 nm.

7. The method for preparing the copper metal reverse polarity red light emitting diode according to any one of claims 1 to 6, characterized in that: The following steps are involved: (1) Epitaxial growth: The following layer structures are formed in sequence by epitaxial growth on a GaAs substrate: GaAs buffer layer; GaInP etch stop layer; n-GaAs ohmic contact layer; n-AlGaInP roughened extension layer; Multiple quantum well light emitting active layer; p-GaP ohmic contact layer; (2) Dielectric material deposition: depositing a SiO2 dielectric material layer on the surface of the p-GaP ohmic contact layer with a thickness of 200-500 nm; (3) Opening pattern production: forming a plurality of openings on the SiO2 dielectric material layer by photolithography, wherein the diameter of the openings is 4-6 μm and the spacing between the openings is 6-10 μm; (4) Formation of an ohmic contact layer: evaporating an AuZn layer with a thickness of 100-300 nm on the surface of the SiO2 dielectric material layer, and directly contacting the p-GaP ohmic contact layer; (5) Bonding layer preparation: forming an Au layer, a Ti layer, a Pt layer and a Cu layer in sequence at the bottom of the epitaxial layer; An Au layer, a Ti layer, a Pt layer and a Cu layer are sequentially formed on the surface of the Si substrate; (6) Bonding the epitaxial layer to the Si substrate: bonding the epitaxial layer to the Cu layer on the Si substrate to form a strong bonding interface; (7) Removing the substrate: removing the GaAs substrate, the GaAs buffer layer and the GaInP etching stop layer in sequence by wet etching to expose the n-GaAs ohmic contact layer; (8) Electrode formation: Vapor depositing an n-electrode on the surface of the n-GaAs ohmic contact layer, which is composed of Au, AuGeNi and Au multilayer metals; (9) Preparation of passivation layer: A SiNx passivation layer with a thickness of 100-300 nm is deposited on the surface of the epitaxial layer to protect the epitaxial layer and improve light extraction efficiency; (10) Back gold layer formation: A Ti layer or an Au layer is sequentially formed at the bottom of the Si substrate to provide a negative electrode connection and a heat dissipation channel.

8. The method according to claim 7, characterized in that Each layer in the bonding layer is prepared by evaporation, the temperature of the Cu layer is 100-120°C, and the deposition rate is 5-8Å / s.

9. The method according to claim 7, characterized in that: The bonding of the epitaxial layer to the Si substrate comprises the following steps: (1) Perform preliminary bonding of the epitaxial layer and the Cu layer of the Si substrate at 200-220°C for 2-5 minutes, with a heating rate of 2-5°C / second; (2) Perform secondary bonding at 280-300°C for 15-20 minutes with a heating rate of 2-3°C / s to eliminate interface voids and form a strong bonding interface.

10. The method according to claim 9, characterized in that The bonding process is 10 -2 -10 -1 Pa under vacuum.

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