Driving circuit, display device, and in-cell touch panel device

Abstract

The present application provides a driving circuit capable of preventing a characteristic change of a transistor in a latch circuit, a display device, and an in-cell touch panel device. A gate driving circuit includes a latch circuit (22). The latch circuit (22) includes: nodes (N21 to N23), a transistor (T22), a node (N21), a transistor (T21) supplied with an RSM signal at the end of a stop period, and a transistor (T28) supplied with a TRS signal supplied after a time point at which the stop period starts and before a time point at which the RSM signal is supplied. The node (N23) and the node (N22) are turned on by supplying the TRS signal to the transistor (T28).

Description

Technical Field

[0001] This disclosure relates to a driving circuit, a display device, and an embedded touch panel device. Background Technology

[0002] Patent Document 1 discloses a drive circuit capable of stopping operation midway through a scan. The drive circuit (shift register) includes multiple unit circuits, each constituting multiple stages. The multiple unit circuits include: a first unit circuit that outputs shift pulses to the gate bus and subsequent stages; and a second unit circuit that outputs shift pulses to subsequent stages. The second unit circuit includes: a transistor having a first electrode connected to a subsequent stage; and an internal node connected to the control electrode of the transistor. The potential of the internal node is continuously maintained at a high level during the period when the drive circuit stops operating. Then, at a time point before the time when the drive circuit is to restart, the level of the signal supplied to the second electrode of the transistor becomes high. Thus, the transistor, which is in a conducting state by maintaining a high-level internal node, outputs shift pulses to subsequent stages, and the operation of the drive circuit restarts. Existing technical documents Patent documents

[0003] Patent Document 1: International Publication No. 2017 / 006815 Summary of the Invention The technical problem to be solved by the present invention

[0004] In the shift register described in Patent Document 1, during the period when the operation is stopped, the internal node continuously connected to the control electrode (gate electrode) of the transistor in the second unit circuit (latch circuit) becomes high. Therefore, by continuously applying a high-level (conduction level) voltage to the gate electrode of the transistor, the characteristics of the transistor sometimes change.

[0005] Therefore, this disclosure was made to solve the above-mentioned problems, and its purpose is to provide a drive circuit, a display device, and an embedded touch panel device that can prevent changes in the characteristics of transistors in a latching circuit. Solution for solving the problem

[0006] To address the aforementioned problems, the first aspect of this disclosure involves a driving circuit comprised of multiple stages that supplies driving signals to a scan signal line group based on multiple input clock signals. It includes multiple unit circuits constituting each of the multiple stages, comprising: a shift register unit circuit connected to a scan signal line within the scan signal line group, supplying an output signal to the scan signal line and subsequent stages of the shift register unit circuit; a latch circuit that holds the output signal input from a previous stage during a stop period when the supply of the multiple clock signals is stopped and the operation of the driving circuit is stopped, and supplies an output signal to subsequent stages of the latch circuit at the end of the stop period; the latch circuit includes: a signal holding node; an on-circuit that changes the level of the signal holding node from a cutoff level to an on level based on the output signal input from the preceding stage; and a first output node connected to the... The subsequent stages include: a first transistor having a first electrode to which a first control signal is supplied at the end of the stop period, a second electrode connected to the first output node, and a first control electrode; a second output node connected to the first control electrode; a second transistor having a third electrode connected to the signal holding node; a fourth electrode connected to the second output node; and a second control electrode to which a second control signal is supplied, the second control signal being supplied after the start of the stop period and before the first control signal is supplied to the first electrode, the second transistor turning on the signal holding node and the second output node by supplying the second control signal to the second control electrode, the first transistor turning on through the signal holding node and the second output node, the level of the second output node changing from a cutoff level to a turn-on level, thereby supplying the first control signal as an output signal to the first output node.

[0007] The second approach involves a display device including: the driving circuit described in the first approach; and a display having the scanning signal line group.

[0008] The third approach involves an embedded touch panel device comprising: the driving circuit described in the first approach; and an embedded touch panel configured with the scanning signal line group, which detects the touch of the indicator during the stop period. Invention Effects

[0009] According to the above configuration, during the stop period when the operation of the drive circuit stops, the first control electrode of the first transistor in the latch circuit is disconnected from the signal holding node that maintains the conduction level. This prevents the continuous application of a conduction level voltage to the first control electrode of the first transistor during the stop period. Consequently, it prevents changes in the characteristics of the first transistor in the latch circuit. Attached Figure Description

[0010] Figure 1 This is a block diagram showing the configuration of the display device 100 according to the first embodiment. Figure 2 This is a schematic circuit diagram showing the configuration of the display unit 10. Figure 3 This is a diagram showing the configuration of touch panel 1. Figure 4 This is a diagram showing a partial configuration of the gate drive circuit 20. Figure 5 This is a circuit diagram showing the configuration of the shift register unit circuit 21. Figure 6 This is a circuit diagram showing the configuration of latch circuit 22. Figure 7 This is a timing diagram of the control signals input to the gate drive circuit 20. Figure 8 This is a diagram showing the configuration of the gate drive circuit 220 of the display device 200 according to the second embodiment. Figure 9 This is a circuit diagram of the latch circuit 222 according to the second embodiment. Figure 10 This is a circuit diagram of the latch circuit 322 of the gate drive circuit 320 according to the second embodiment. Figure 11 This is a diagram showing the configuration of the gate drive circuit 420 according to the fourth embodiment. Figure 12 This is a circuit diagram of the latch circuit 522 of the first variant of the first to fourth embodiments. Figure 13 This is a circuit diagram of the latch circuit 622 of the second variation of the first to fourth embodiments. Detailed Implementation

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, the same or corresponding parts in the drawings will be labeled with the same reference numerals, and their descriptions will not be repeated. In addition, to facilitate understanding, the components are shown in a simplified or schematic manner in the following drawings, or some components may be omitted. Furthermore, the dimensional ratios between the components shown in the figures do not necessarily represent actual dimensional ratios.

[0012] [First Implementation Method] (Overall structure of the display device) The configuration of the display device 100 according to the first embodiment will be described. Figure 1 This is a block diagram showing the configuration of the display device 100 according to the first embodiment. Figure 2 This is a schematic circuit diagram showing the configuration of the display unit 10. Figure 3 This is a diagram showing the configuration of touch panel 1.

[0013] like Figure 1 As shown, the display device 100 includes a touch panel 1 and a control circuit 2. In the first embodiment, the touch panel 1 is configured as an embedded touch panel that performs touch detection and image display functions. That is, the touch panel 1 also functions as a display. Furthermore, in the first embodiment, the display device 100 is an embedded touch panel device.

[0014] The control circuit 2 includes a processor that performs control processing on the display device 100. Then, the control circuit 2 sends a control signal to the touch panel 1 based on the input image signal. The touch panel 1 displays the image based on the control signal. Additionally, the control circuit 2 sends a touch detection instruction to the touch panel 1 and receives information indicating the touch coordinates of the pointer from the touch panel 1 (hereinafter referred to as "touch detection processing"). Furthermore, the control circuit 2 performs display processing and touch detection processing that cause the gate drive circuit 20 to operate in a time-division manner within one frame. That is, within one frame, there is a touch detection period TP (refer to...) which is the period for performing touch detection processing. Figure 7 ) and the display period TD (refer to) during the display processing. Figure 7 The control circuit 2 performs touch detection processing multiple times during one frame, for example. Furthermore, during the touch detection processing, the operation of the gate drive circuit 20 is stopped. Additionally, during the period when the operation of the gate drive circuit 20 is stopped, i.e., the stop period TR (see reference...). Figure 7 The text contains TP during touch detection.

[0015] like Figure 1 As shown, the touch panel 1 includes a display unit 10, a gate driving circuit 20, a source driving circuit 30, and a touch detection control circuit 40. Furthermore, in Figure 1 The diagram illustrates a touch panel 1 containing a gate drive circuit 20, a source drive circuit 30, and a touch detection control circuit 40. However, at least one of these circuits can also be disposed on another substrate located outside the touch panel 1. In this case, at least one of the touch panel 1, the gate drive circuit 20, the source drive circuit 30, and the touch detection control circuit 40 is connected via wiring or a flexible printed circuit board.

[0016] like Figure 2 As shown, the display unit 10 includes multiple gate lines 11, multiple source lines 12, multiple transistors 13, multiple pixel electrodes 14, and multiple common electrodes 15. The multiple gate lines 11 intersect with the multiple source lines 12 when viewed from above. Furthermore, transistors 13 and pixel electrodes 14 are arranged in each region divided by the multiple gate lines 11 and multiple source lines 12. The transistor 13 includes a gate electrode 13a, a source electrode 13b, and a drain electrode 13c. The gate electrode 13a is connected to the gate line 11. The source electrode 13b is connected to the source line 12. The drain electrode 13c is connected to the pixel electrode 14. The multiple gate lines 11 are an example of a scan signal line group. Furthermore, in... Figure 2 The example shown is a gate drive circuit 20 arranged on one side of the display unit 10, but gate drive circuits 20 can also be arranged on both sides of the display unit 10.

[0017] A gate driving circuit 20 is formed on the substrate of the touch panel 1 (formed as a monolithic chip). The gate driving circuit 20 sequentially outputs gate signals to multiple gate lines 11. A source driving circuit 30 is mounted on the substrate of the touch panel 1. The source driving circuit 30 receives image signals and source control signals output from the control circuit 2, and generates source signals (data signals) based on the image signals and source control signals. Then, the source driving circuit 30 supplies source signals to multiple source lines 12 respectively. Then, when a gate signal is supplied to the transistor 13 (becoming the gate on voltage), the source signal is written to the pixel electrode 14 via the transistor 13. As a result, an electric field is generated between the pixel electrode 14 and the common electrode 15, driving a liquid crystal layer (not shown), and displaying an image on the touch panel 1.

[0018] like Figure 3 As shown, multiple common electrodes 15 are arranged, for example, in a matrix. A touch detection control circuit 40 is connected to each of the multiple common electrodes 15 via wiring 16. The electrostatic capacitance of each common electrode 15 changes due to capacitive coupling with the indicator. During touch detection processing (touch detection period TP), the touch detection control circuit 40 supplies touch drive signals (pulse signals) to the multiple common electrodes 15. The waveform of the pulse signal varies according to the magnitude of the electrostatic capacitance of the common electrodes 15. Based on the waveform of the pulse signal from the common electrodes 15, the touch detection control circuit 40 detects the touch of the indicator (the touched position). That is, the common electrodes 15 also serve as touch detection electrodes. The touch panel 1 is a self-capacitive touch panel. However, not limited to this example, the touch panel 1 may also be configured as a mutual-capacitive touch panel.

[0019] (Configuration of gate drive circuit 20) Next, refer to Figures 4 to 6Explain the configuration of the gate drive circuit 20. Figure 4 This is a diagram showing a partial configuration of the gate drive circuit 20. Figure 5 This is a circuit diagram showing the configuration of the shift register unit circuit 21. Figure 6 This is a circuit diagram showing the configuration of latch circuit 22.

[0020] like Figure 4 As shown, the gate drive circuit 20 consists of multiple stages and is a shift register that supplies gate signals to multiple gate lines 11 according to multiple input clock signals. Figure 4 The diagram shows the nth level (where n is a natural number), the four levels before the nth level, and the three levels after the nth level.

[0021] The gate drive circuit 20 includes a shift register unit circuit 21 that forms part of multiple stages and a latch circuit 22 that forms part of multiple stages. Figure 4 The diagram illustrates an example where latch circuit 22 constitutes the nth stage, and multiple shift register unit circuits 21 constitute the n-4 to n-1 stages and the n+1 to n+3 stages. Furthermore, in... Figure 4 The diagram shows a latch circuit 22, but multiple latch circuits 22 can also be provided on the gate drive circuit 20.

[0022] like Figure 4 As shown, control circuit 2 (refer to...) Figure 1 As control signals, multiple clock signals (hereinafter referred to as "CLK1A signal, CLK2A signal, CLK1B signal, and CLK2B signal," and referred to as "CLK signal" if there is no distinction between CLK1A signal, CLK2A signal, CLK1B signal, and CLK2B signal), VSS signal, RSM signal, VDD signal, VTP signal, TRS signal, and TPC signal are supplied to the gate drive circuit 20. The VSS signal is a signal with a reference potential (low level, off level). The RSM signal is a signal indicating that the gate drive circuit 20 has restarted operation. The VDD signal is a signal with a reference potential (high level, on level). The VTP signal is a signal supplied during the stop period (during the touch detection process). The TRS signal is a signal indicating that node N22, described later, is being charged. Furthermore, node N22 is an example of a "second output node." Additionally, although in Figure 4 Although not shown in the diagram, the control circuit 2 supplies the gate start pulse (GSP) signal as a SET signal to the shift register unit circuits 21 of the first and second stages.

[0023] The CLK, VDD, VTP, and VSS signals are input to the shift register unit circuit 21. The shift register unit circuit 21 supplies the output signal Q to the gate line 11 and subsequent stages of the shift register unit circuit 21. Furthermore, in the following description, the output signal Q of the nth stage is referred to as "output signal Qn". For example, taking m as a natural number, the mth shift register unit circuit 21 inputs the output signal Qm as a SET signal to the (m+2)th stage. Additionally, the mth shift register unit circuit 21 inputs the output signal Qm as a RESET signal to the (m-3)th stage. Furthermore, the TPC signal is input as a RESET signal to the shift register unit circuits 21 in stages n-3 to n-1.

[0024] The RSM, VDD, VTP, and VSS signals are input to the latch circuit 22. Furthermore, during a period when the supply of multiple clock signals (CLK1A, CLK2A, CLK1B, and CLK2B) is stopped and the operation of the gate drive circuit 20 is halted, the latch circuit 22 holds the output signal Q (SET signal) input from the previous stage. For example, when the output signal Qn-1 is input as the LSET signal (the setting signal used by the latch circuit 22) to the latch circuit 22 constituting the nth stage, the latch circuit 22 stops the operation of the gate drive circuit 20.

[0025] Then, at the end of the stop period, latch circuit 22 supplies an output signal (SET signal) to the subsequent stages of latch circuit 22. For example, when the TRS signal and the RSM signal are input to latch circuit 22, the output signal Lout (output signal Qn) is output to the shift register unit circuits 21 of stages (n+1) and (n+2). As a result, the operation of gate drive circuit 20 restarts.

[0026] <Circuit Structure of Shift Register Unit Circuit 21> like Figure 5 As shown, the shift register unit circuit 21 includes transistors T11 to T18, capacitor C1, and nodes N11 to N13. Figure 5 The diagram shows the shift register unit circuit 21 that constitutes the m-th stage.

[0027] Transistor T11 has a drain electrode for supplying the CLK signal, a source electrode connected to node N11, and a gate electrode connected to node N12. Transistor T12, based on the output signal Qm-2 input from a previous stage (e.g., the (m-2)th stage), forms a conduction circuit that changes the level of node N12 from a cutoff level (low level) to a conduction level (high level). The output signal Qm-2 is input to the gate electrode of transistor T12 as a SET signal. The VDD signal is input to the drain electrode of transistor T12. The source electrode of transistor T12 is connected to node N12.

[0028] Transistor T13, based on the output signal Qm+3 input from a subsequent stage (e.g., stage m+3), forms a cutoff circuit that changes the level of node N12 from on to off. The output signal Qm+3 is input as a RESET signal to the gate electrode of transistor T13. The drain electrode of transistor T13 is connected to node N12. The VSS signal is input to the source electrode of transistor T13.

[0029] Transistors T14 to T16 constitute a stabilizing circuit 21a, which maintains node N12 at a cutoff level during periods other than when node N12 is on. Transistor T14 connects the VDD signal to the diode at node N13. Node N12 is connected to the gate electrode of transistor T15, and when node N12 becomes on, it switches node N13 from on to off. When node N13 is on, transistor T16 supplies the VSS signal to node N12, keeping node N12 at a cutoff level.

[0030] Transistor T17 constitutes a stabilizing circuit 21b, which is used to maintain node N11 at a cutoff level during periods other than when node N12 is on. When node N13 is on, transistor T17 supplies a VSS signal to node N11, keeping node N11 at a cutoff level.

[0031] During touch detection, the VTP signal supplied in TP is input to the gate electrode of transistor T18. When the VTP signal is input to transistor T18, transistor T18 becomes on, and node N11 becomes off.

[0032] Capacitor C1 is positioned between nodes N11 and N12. Capacitor C1 is a bootstrap capacitor.

[0033] Node N11 is connected to gate line 11 and the (m+2)th stage.

[0034] <Circuit configuration of latch circuit 22> like Figure 6As shown, the latch circuit 22 includes transistors T21 to T28, capacitors C2 and C3, and nodes N21 to N24.

[0035] Transistor T21 has a drain electrode T21d that is supplied with an RSM signal at the end of the stop period TR, a source electrode T21s connected to node N21, and a gate electrode T21g. Transistor T21 is a buffer transistor. Furthermore, the RSM signal is an example of the "first control signal" of this disclosure. The drain electrode T21d is an example of the "first electrode" of this disclosure. The source electrode T21s is an example of the "second electrode" of this disclosure. The gate electrode T21g is an example of the "first control electrode" of this disclosure.

[0036] Transistor T22, based on the output signal Qn-1 input from a previous stage (e.g., stage n-1), forms a conduction circuit that changes the level of node N23 from a cutoff level (high level) to a conduction level (low level). The output signal Qn-1 is input to the gate electrode of transistor T22 as the LSET signal. The VDD signal is input to the drain electrode of transistor T22. The source electrode of transistor T22 is connected to node N23.

[0037] Transistor T23a, based on the output signal Qn+3 input from a subsequent stage (e.g., stage n+3), forms a cutoff circuit that changes the voltage level of node N23 from on to off. The output signal Qn+3 is input to the gate electrode of transistor T23a as the LRESET signal (latch reset signal). The drain electrode of transistor T23a is connected to node N23. The VSS signal is input to the source electrode of transistor T23a.

[0038] Transistor T23b, based on the output signal Qn+3 input from a subsequent stage (e.g., stage n+3), forms a cutoff circuit that changes the level of node N22 from on to off. The output signal Qn+3 is input to the gate electrode of transistor T23b ​​as the LRESET signal (latch reset signal). The drain electrode of transistor T23b ​​is connected to node N22. The VSS signal is input to the source electrode of transistor T23b.

[0039] Transistors T24 to T26 constitute a stabilizing circuit 22a, which is used to maintain node N22 at the off level during periods other than the stop period TR. Transistor T24 connects the VDD signal to the diode at node N24. Node N23 is connected to the gate electrode of transistor T25. When node N23 becomes on, it switches node N24 from the on level to the off level. When node N24 is on, transistor T26 supplies the VSS signal to node N22, keeping node N22 at the off level.

[0040] Transistor T27 constitutes stabilization circuit 22b, which is used to maintain node N21 at the off level during periods other than the stop period TR. When node N24 is at the on level, transistor T27 supplies a VSS signal to node N21, thereby maintaining node N21 at the off level.

[0041] Transistor T28 has a drain electrode T28d connected to node N23, a source electrode T28s connected to node N22, and a gate electrode T28g supplied with a TRS signal. This TRS signal is supplied after the point at which the TR signal has started during the stop period and before the point at which the RSM signal is supplied to the drain electrode T21d of transistor T21. Furthermore, the TRS signal is an example of the "second control signal" of this disclosure. The drain electrode T28d is an example of the "third electrode" of this disclosure. The source electrode T28s is an example of the "fourth electrode" of this disclosure. The gate electrode T28g is an example of the "second control electrode" of this disclosure.

[0042] Capacitor element C2 is disposed between node N22 and node N21. Capacitor element C2 is a bootstrap capacitor. Furthermore, capacitor element C2 is an example of the "second capacitor element" of this disclosure.

[0043] Capacitor C3 is positioned between node N23 and the VSS signal line. The capacitance of capacitor C3 is greater than that of capacitor C2. For example, the capacitance of capacitor C3 is more than three times that of capacitor C2. Therefore, because the amount of charge stored in capacitor C3 is greater, capacitor C2 connected to node N22 can be fully charged after transistor T28 is turned on.

[0044] Node N21 is connected to the (n+1)th and (n+2)th stages. Node N22 is connected to the gate electrode T21g. Node N23 is a node used to maintain the on-level (signal) when the operation of the gate drive circuit 20 stops. Furthermore, node N21 is an example of the "first output node" of this disclosure. Node N22 is an example of the "second output node" of this disclosure. Node N23 is an example of the "signal holding node" of this disclosure.

[0045] In this first embodiment, node N21 is not connected to gate line 11. Therefore, since the latch circuit 22 is not connected to gate line 11 even if the characteristics of transistor T21 in the latch circuit 22 change, the change in the characteristics of transistor T21 will not affect the display of the touch panel 1.

[0046] (Operation of gate drive circuit 20) Next, refer to Figures 4-7 The operation of the gate drive circuit 20 will be explained. Figure 7This is a timing diagram of the control signals input to the gate drive circuit 20.

[0047] <Operation of Shift Register Unit Circuit 21> like Figure 7 As shown, during the display period TD, the CLK1A, CLK2A, CLK1B, and CLK2B signals are sequentially input to the gate drive circuit 20. Figure 5 As shown, in the shift register unit circuit 21 constituting the m-th stage, at the time point before the CLK signal is input, transistor T12 becomes on according to the output signal Qm-2 (SET signal) from the (m-2)-th stage. Consequently, node N12 and capacitor C1 are charged to the on-level. Furthermore, with node N12 on, transistor T14 becomes on, and node N13 becomes off. Consequently, transistors T16 and T17 become off.

[0048] Then, when the CLK signal is input, node N11 becomes on via transistor T11. As a result, the output signal Qm (gate signal) is output to gate line 11 and subsequent stages. Then, when the output signal Qm+3 (RESET signal) from stage m+3 is input to the shift register unit circuit 21, transistor T13 turns on, and node N12 is turned off. Furthermore, with node N12 at the off level, transistor T15 becomes off, and node N13 becomes on. Consequently, transistors T16 and T17 become on, while nodes N12 and N11 remain off. By performing the above actions at each stage, output signals Q are sequentially output from the multiple stages of the shift register unit circuit 21 (performing the operation of the gate drive circuit 20).

[0049] Then, as Figure 7 As shown, at time point t1, when the touch detection period TP and the stop period TR begin, as Figure 4 As shown, the VTP signal is supplied to all shift register unit circuits 21. (As indicated...) Figure 5 As shown, when the VTP signal is supplied to the shift register unit circuit 21, transistor T18 becomes on, and the output signal Q is stopped. Additionally, during the period from time t1 to time t2, the TPC signal is input as a RESET signal to the shift register unit circuits 21 of stages n-3 to n-1. Consequently, transistor T13 becomes off, and node N12 becomes off.

[0050] <Operation of latch circuit 22> like Figure 7As shown, during the display period TD, the CLK signal is input to the shift register unit circuit 21, and the output signal Q is output sequentially (performing the operation of the gate drive circuit 20). Thus, as... Figure 6 As shown, the output signal Qn-1 (LSET signal) from the shift register unit circuit 21 constituting the (n-1)th stage is input to the latch circuit 22 constituting the nth stage. Consequently, transistor T22 becomes on, and node N23 becomes on-level. As a result, capacitor C3 is charged.

[0051] Furthermore, during the display period TD, the TRS signal is at the off level. Therefore, transistor T28 is not turned on, and nodes N23 and N22 are not connected. As a result, node N23 can be kept at the on level without applying a conduction-level voltage to the gate electrode T21g of transistor T21.

[0052] Furthermore, during the display period TD, the RSM signal is at the cutoff level. Therefore, the output signal Q (SET signal) is not output to subsequent stages of the latch circuit 22, and the operation of the gate drive circuit 20 stops.

[0053] Subsequently, at time t1, after the touch detection period TP and the stop period TR begin, in the latch circuit 22, the state in which the voltage at node N23 is maintained at the on level (the state in which capacitor element C3 is charging) and the state in which the voltage at the on level is not applied to the gate electrode T21g of transistor T21 is maintained. This prevents changes in the characteristics of transistor T21 in the latch circuit 22.

[0054] like Figure 7 As shown, at time point t3, the touch detection period TP ends, and at time point t4, the TRS signal is input to the latch circuit 22 (the TRS signal level is the on level). Therefore, as... Figure 6 As shown, transistor T28 is turned on, and nodes N23 and N22 are also turned on. Consequently, node N22 is at the on-state, and capacitor C2 is charged. Therefore, transistor T21 is turned on.

[0055] like Figure 7 As shown, at time point t5, the TRS signal level becomes the cutoff level, and the RSM signal level becomes the on level. Therefore, as... Figure 6 As shown, node N21 becomes on via transistor T21. Therefore, the output signal Qn is output to subsequent stages (e.g., shift register unit circuits 21 of stages n+1 and n+2). Then, at time t6, when the CLK signal is supplied again, the stop period TR ends, and the operation of the gate drive circuit 20 restarts.

[0056] Then, when the output signal Qn+3 (LRESET signal) from stage (n+3) is input to latch circuit 22, transistors T23a and T23b ​​are turned on, and nodes N23 and N22 are turned off to the cutoff level. Furthermore, with node N23 at the cutoff level, transistor T25 is turned off, and node N24 is turned on. Consequently, transistors T26 and T27 are turned on, while nodes N22 and N21 remain at the cutoff level. As described above, during the stop period TR until the TRS signal is input, since no on-level (high-level) voltage is applied to the gate electrode T21g of transistor T21, changes in the characteristics of transistor T21 in latch circuit 22 can be prevented.

[0057] [Second Implementation] Next, refer to Figure 8 and Figure 9 The configuration of the display device 200 according to the second embodiment will be described below. In the second embodiment, the VTP signal is input to the latch circuit 222. Furthermore, configurations identical to those in the first embodiment described above are labeled with the same reference numerals, and descriptions are omitted. Figure 8 This is a diagram showing the configuration of the gate drive circuit 220 of the display device 200 according to the second embodiment. Figure 9 This is a circuit diagram of the latch circuit 222 according to the second embodiment.

[0058] like Figure 8 As shown, the gate drive circuit 220 of the display device 200 includes a latch circuit 222. The VTP signal is input to the latch circuit 222. Figure 9 As shown, the source electrode of transistor T223a in latch circuit 222 is connected to node N221. The VTP signal is input to node N221. Furthermore, transistor T223a is an example of the "third transistor" of this disclosure. Additionally, the VTP signal is an example of the "third control signal" of this disclosure. Node N221 is an example of the "input node" of this disclosure. The drain electrode of transistor T223a is an example of the "fifth electrode" of this disclosure. The source electrode of transistor T223a is an example of the "sixth electrode" of this disclosure.

[0059] According to the configuration of the second embodiment, during touch detection TP, the potential difference between the drain electrode and the source electrode of transistor T223a can be reduced. As a result, cutoff leakage through transistor T223a can be suppressed, thus preventing the potential of node N23 from changing from the on-state during this period. Furthermore, the other configurations and effects of the second embodiment are the same as those of the first embodiment.

[0060] [Third Implementation Method] Next, refer to Figure 10The configuration of the gate drive circuit 320 according to the third embodiment will be described. In the third embodiment, the transistors in the stabilization circuit 322a of the latch circuit 322 are cascaded together. Furthermore, configurations identical to those in the first embodiment described above are labeled with the same reference numerals, and descriptions are omitted. Figure 10 This is a circuit diagram of the latch circuit 322 of the gate drive circuit 320 according to the second embodiment.

[0061] like Figure 10 As shown, the gate drive circuit 320 includes a latch circuit 322. A stabilizing circuit 322a is provided in the latch circuit 322. The stabilizing circuit 322a includes transistors T324a, T324b, T325a, T325b, and T326. Transistor T326 is an example of the "fourth transistor" of this disclosure. The drain, source, and gate electrodes of transistor T326 are examples of the "seventh electrode," "eighth electrode," and "fourth control electrode" of this disclosure. Transistor T325a is an example of the "fifth transistor" of this disclosure. The drain, source, and gate electrodes of transistor T325a are examples of the "ninth electrode," "tenth electrode," and "fifth control electrode" of this disclosure. Transistor T325b is an example of the "sixth transistor" of this disclosure. The drain, source, and gate electrodes of transistor T325b are examples of the "eleventh electrode," "twelfth electrode," and "sixth control electrode" of this disclosure. Transistor T324a is an example of the "seventh transistor" of this disclosure. The drain, source, and gate electrodes of transistor T324a are examples of the "thirteenth electrode," "fourteenth electrode," and "seventh control electrode" of this disclosure. Transistor T324b is an example of the "eighth transistor" of this disclosure. The drain, source, and gate electrodes of transistor T324b are examples of the "fifteenth electrode," "sixteenth electrode," and "eighth control electrode" of this disclosure.

[0062] Additionally, nodes N324a and N324b are provided in the stabilizing circuit 322a. Node N324a is an example of the "first intermediate node" of this disclosure. Node N324b is an example of the "second intermediate node" of this disclosure.

[0063] The drain electrode of transistor T326 is connected to node N22. A VSS signal is supplied to the source electrode of transistor T326. The gate electrode of transistor T326 is connected to node N324a. Furthermore, the potential of the VSS signal is an example of the "first reference potential" of this disclosure.

[0064] The drain electrode of transistor T325a is connected to node N324a. The VSS signal is supplied to the source electrode of transistor T325a. The gate electrode of transistor T325a is connected to node N23.

[0065] The drain electrode of transistor T325b is connected to node N324b. The VSS signal is supplied to the source electrode of transistor T325b. The gate electrode of transistor T325b is connected to node N23.

[0066] The VDD signal is supplied to the drain electrode of transistor T324a. The source electrode of transistor T324a is connected to node N324a. The gate electrode of transistor T324a is connected to node N324b. Furthermore, the potential of the VDD signal is an example of the "second reference potential" of this disclosure.

[0067] The VDD signal is supplied to the drain and gate electrodes of transistor T324b. The source electrode of transistor T324b is connected to node N324b.

[0068] According to the configuration of the third embodiment, a cascaded connection including node N324b is formed between node N23 and node N324a. Therefore, during the period when the voltage level of node N324a is off, it is possible to prevent the generation of through current (VDD signal intrusion) at node N324a, and to prevent noise from intruding into transistor T326 connected to node N324a. As a result, it is possible to prevent changes in the characteristics of transistor T326. Furthermore, the other configurations and effects of the third embodiment are the same as those of the first embodiment.

[0069] [Fourth Implementation Method] Next, refer to Figure 11 The configuration of the gate drive circuit 420 according to the fourth embodiment will be described. In the fourth embodiment, the latch circuit 422 is connected to the gate line 11. Furthermore, configurations identical to those in the first embodiment described above are labeled with the same reference numerals, and descriptions are omitted. Figure 11 This is a diagram showing the configuration of the gate drive circuit 420 according to the fourth embodiment.

[0070] like Figure 11 As shown, the gate drive circuit 420 includes a latch circuit 422. The latch circuit 422 is connected to the gate line 11. The latch circuit 422, which constitutes the nth stage, outputs the output signal Qn to the gate line 11, the (n+1)th stage, and the (n+2)th stage shift register unit circuit 21. According to the configuration of the fourth embodiment, since the latch circuit 422 also functions as the circuit driving the gate line 11, the gate drive circuit 420 can be miniaturized. Furthermore, the other configurations and effects of the fourth embodiment are the same as those of the first embodiment.

[0071] [Deformation, etc.] The above-described embodiments are merely illustrative examples for implementing this disclosure. Therefore, this disclosure is not limited to the above-described embodiments, and appropriate modifications and implementations can be made to the above-described embodiments without departing from its spirit.

[0072] (1) In the first to fourth embodiments described above, examples of providing a bootstrap capacitor element in a unit circuit are shown, but this disclosure is not limited thereto. Figure 12 In the first modified example shown, the latch circuit 522 does not have a capacitor connected to the transistor T521. In this case, the capacitive component of the transistor T521 can replace the function of the capacitor C2 in the first to fourth embodiments.

[0073] (2) In the first to fourth embodiments described above, an example is shown of supplying VDD to the drain electrode of a transistor constituting a unit circuit, but this disclosure is not limited thereto. Figure 13 In the second variation of the latch circuit 622 shown, the transistor T622 can also be connected to node N23 by diode by inputting the LSET signal (output signal Qn-1) to the gate electrode and drain electrode of the transistor T622.

[0074] (3) In the first to fourth embodiments described above, examples of providing a touch detection function on the display device were shown, but this disclosure is not limited thereto. That is, it is also possible not to provide a touch detection function on the display device.

[0075] (4) In the first to fourth embodiments described above, an example of supplying four CLK signals to the gate drive circuit is shown, but this disclosure is not limited thereto. That is, the number (number of phases) of CLK signals can be three or less, or five or more. In addition, the destination of the SET signal and RESET signal, which are input as output signals Q, can be designed to be any number of stages, depending on the number of CLK signals.

[0076] (5) In the first to fourth embodiments described above, examples of display devices constituted by liquid crystal display panels including liquid crystal layers were shown, but this disclosure is not limited thereto. For example, the display device may be constituted by an organic EL (Electro Luminescence) display panel.

[0077] (6) In the first to fourth embodiments described above, an example was shown in which the capacitance of capacitor element C3 was configured to be greater than that of capacitor element C2, but this disclosure is not limited thereto. It is also possible to configure capacitor element C3 to have a capacitance of capacitor element C2 or less.

[0078] The control methods for the aforementioned driving circuit, display device, and embedded touch panel device can also be described as follows.

[0079] The first configuration involves a driving circuit composed of multiple stages that supplies driving signals to a scan signal line group based on multiple input clock signals. It includes multiple unit circuits constituting each of the multiple stages, comprising: a shift register unit circuit connected to a scan signal line within the scan signal line group, supplying an output signal to the scan signal line and subsequent stages of the shift register unit circuit; a latch circuit that holds the output signal input from a previous stage during a stop period when the supply of the multiple clock signals is stopped and the operation of the driving circuit is stopped, and supplies an output signal to subsequent stages of the latch circuit at the end of the stop period; the latch circuit includes: a signal holding node; an on-circuit that changes the level of the signal holding node from a cutoff level to an on level based on the output signal input from the preceding stage; a first output node connected to the subsequent stage; and a first crystal. The first control electrode has a first electrode to which a first control signal is supplied at the end of the stop period, a second electrode connected to the first output node, and a first control electrode; a second output node connected to the first control electrode; a second transistor having a third electrode connected to the signal holding node; a fourth electrode connected to the second output node; and a second control electrode to which a second control signal is supplied, the second control signal being supplied after the start of the stop period and before the first control signal being supplied to the first electrode. The second transistor turns on the signal holding node and the second output node by supplying the second control signal to the second control electrode, and the first transistor turns on through the signal holding node and the second output node, changing the level of the second output node from a cutoff level to a turn-on level, thereby supplying the first control signal as an output signal to the first output node (first configuration).

[0080] According to the first configuration described above, during the stop period when the operation of the drive circuit stops, the first control electrode of the first transistor in the latch circuit is disconnected from the signal holding node that maintains the conduction level. This prevents the continuous application of a conduction level voltage to the first control electrode of the first transistor during the stop period. Consequently, it prevents changes in the characteristics of the first transistor in the latch circuit.

[0081] In the first configuration described above, the latching circuit may also include a first capacitor element connected to the signal holding node (second configuration).

[0082] According to the second configuration described above, when the signal holding node and the second output node are connected, the charge stored in the first capacitor element can be used to change the potential of the second output node.

[0083] In the second configuration described above, the latching circuit may also include a second capacitor element connected to the second output node. The capacitance of the first capacitor element may also be greater than the capacitance of the second capacitor element (third configuration).

[0084] According to the third configuration described above, since the amount of charge stored in the first capacitor element increases, the second capacitor element connected to the second output node can be fully charged.

[0085] In any of the first to third configurations described above, the latch circuit further includes: an input node supplied with a third control signal that is on for at least a portion of the stop period; and a third transistor having a fifth electrode connected to the signal holding node, a sixth electrode connected to the input node, and a third control electrode (fourth configuration) receiving an output signal from a stage following the latch circuit.

[0086] According to the fourth configuration described above, the potential difference between the fifth and sixth electrodes of the third transistor can be reduced during at least a portion of the stop period. As a result, since cutoff leakage through the third transistor can be suppressed, the potential of the signal holding node can be prevented from changing from the on-level during this period.

[0087] In any of the first to fourth configurations described above, the latching circuit may also include: a first intermediate node and a second intermediate node; a fourth transistor having a seventh electrode connected to the second output node, an eighth electrode connected to the first reference potential, and a fourth control electrode connected to the first intermediate node; a fifth transistor having a ninth electrode connected to the first intermediate node, a tenth electrode connected to the first reference potential, and a fifth control electrode connected to the signal holding node; a sixth transistor having an eleventh electrode connected to the second intermediate node, a twelfth electrode connected to the first reference potential, and a sixth control electrode connected to the signal holding node; a seventh transistor having a thirteenth electrode connected to the second reference potential, a fourteenth electrode connected to the second intermediate node, and a seventh control electrode connected to the second reference potential; and an eighth transistor having a fifteenth electrode connected to the second reference potential, a sixteenth electrode connected to the first intermediate node, and an eighth control electrode connected to the second intermediate node (fifth configuration).

[0088] According to the fifth configuration described above, a cascaded connection including a second intermediate node is formed between the signal holding node and the first intermediate node. This prevents through-current from the second reference potential to the first intermediate node and prevents noise from entering the fourth transistor connected to the first intermediate node. As a result, it prevents changes in the characteristics of the fourth transistor.

[0089] In any of the first to fifth configurations described above, the first output node may also be connected to any one of the scan signal lines in the scan signal line group and the subsequent stage (sixth configuration).

[0090] According to the sixth configuration described above, since the latch circuit also functions as the circuit that drives the scan signal line, the drive circuit can be miniaturized.

[0091] In any of the first to fifth configurations described above, the first output node may not be connected to the scan signal line group, but may be connected to the subsequent stage (seventh configuration).

[0092] According to the seventh configuration described above, since it is assumed that even if the characteristics of the first transistor in the latch circuit change, the latch circuit is not connected to the scan signal line group, the change in the characteristics of the first transistor will not affect the display.

[0093] The display device involved in the eighth configuration includes: the driving circuit of any one of the first to seventh configurations; and a display that is configured with the scanning signal line group (eighth configuration).

[0094] According to the eighth configuration described above, a display device is provided that can prevent changes in the characteristics of transistors in the latching circuit.

[0095] The embedded touch panel device involved in the ninth configuration includes: the driving circuit of any one of the first to seventh configurations; and an embedded touch panel, which is an embedded touch panel configured with the scanning signal line group, and detects the touch of the indicator during the stop period (ninth configuration).

[0096] According to the ninth configuration described above, an embedded touch panel device is provided that can prevent changes in the characteristics of transistors within the latching circuit. Explanation of reference numerals in the attached figures

[0097] 1: Touch panel; 2: Control circuit; 10: Display unit; 11: Gate line; 12: Source line; 13: Transistor; 13a: Gate electrode; 13b: Source electrode; 13c: Drain electrode; 14: Pixel electrode; 15: Common electrode; 16: Wiring; 20: Gate drive circuit; 21: Shift register unit circuit; 21a: Stabilizing circuit; 21b: Stabilizing circuit; 22: Latch circuit; 22a: Stabilizing circuit; 22b: Stabilizing circuit; 30: Source drive circuit; 40: Touch detection control circuit; 10 0: Display device; 200: Display device; 220: Gate drive circuit; 222: Latch circuit; 320: Gate drive circuit; 322: Latch circuit; 322a: Stabilizing circuit; 420: Gate drive circuit; 422: Latch circuit; 522: Latch circuit; 622: Latch circuit; C1: Capacitor; C2: Capacitor; C3: Capacitor; Lout: Output signal; N11: Node; N12: Node; N13: Node; N21: Node; N22: Node; N221: Node Point, N23: Node, N24: Node, N324a: Node, N324b: Node, Q: Output signal, Qm: Output signal, Qn: Output signal, Qn-1: Output signal, T11: Transistor, T12: Transistor, T13: Transistor, T14: Transistor, T15: Transistor, T16: Transistor, T17: Transistor, T18: Transistor, T21: Transistor, T21d: Drain electrode, T21g: Gate electrode, T21s: Source electrode, T22: Transistor, T223a T23: Transistor, T23a: Transistor, T23b: Transistor, T24: Transistor, T25: Transistor, T26: Transistor, T27: Transistor, T28: Transistor, T28d: Drain electrode, T28g: Gate electrode, T28s: Source electrode, T324a: Transistor, T324b: Transistor, T325a: Transistor, T326: Transistor, T521: Transistor, T622: Transistor, TD: Display period, TP: Touch detection period, TR: Stop period

Claims

1. A driving circuit comprising multiple stages, supplying driving signals to a scan signal line group according to multiple input clock signals, characterized in that, The plurality of unit circuits comprising each of the plurality of levels include: a shift register unit circuit, which is a shift register unit circuit connected to one of the scan signal lines in the scan signal line group, supplies an output signal to the scan signal line and a subsequent stage of the shift register unit circuit; as well as A latch circuit, which holds the output signal input from the previous stage of the shift register unit circuit during a stop period when the supply of the plurality of clock signals is stopped and the operation of the drive circuit is stopped, and supplies the output signal to the subsequent stage of the latch circuit at the end of the stop period. The latching circuit includes: a signal holding node; A conduction circuit that, based on the output signal input from the previous stage, causes the level of the signal holding node to change from a cutoff level to a conduction level; The first output node, which is connected to the subsequent stages; A first transistor having a first electrode to which a first control signal is supplied at the end of the stop period, a second electrode connected to the first output node, and a first control electrode; The second output node is connected to the first control electrode; as well as The second transistor has: a third electrode connected to the signal holding node; and a fourth electrode connected to the second output node; and a second control electrode to which a second control signal is supplied, the second control signal being supplied during a predetermined period before the end of the stop period, and the supply ending before the point at which the first control signal is supplied to the first electrode. The second transistor enables the signal holding node and the second output node to conduct by supplying the second control signal to the second control electrode. The first transistor is turned on through the signal holding node and the second output node, and the level of the second output node changes from the off level to the on level, thereby supplying the first control signal as an output signal to the first output node.

2. The driving circuit according to claim 1, characterized in that, The latching circuit includes a first capacitor element connected to the signal holding node.

3. The driving circuit according to claim 2, characterized in that, The latching circuit includes a second capacitor element connected to the second output node. The capacitance of the first capacitor element is greater than the capacitance of the second capacitor element.

4. The driving circuit according to any one of claims 1 to 3, characterized in that, The latching circuit further includes: An input node, which is supplied with a third control signal that is at an on level for at least a portion of the stop period; and The third transistor has a fifth electrode connected to the signal holding node, a sixth electrode connected to the input node, and a third control electrode that receives an output signal from a stage following the latch circuit.

5. The driving circuit according to any one of claims 1 to 3, characterized in that, The latching circuit includes: First intermediate node and second intermediate node; The fourth transistor has a seventh electrode connected to the second output node, an eighth electrode connected to the first reference potential, and a fourth control electrode connected to the first intermediate node. The fifth transistor has a ninth electrode connected to the first intermediate node, a tenth electrode connected to the first reference potential, and a fifth control electrode connected to the signal holding node; The sixth transistor has an eleventh electrode connected to the second intermediate node, a twelfth electrode connected to the first reference potential, and a sixth control electrode connected to the signal holding node; A seventh transistor having a thirteenth electrode connected to a second reference potential, a fourteenth electrode connected to the second intermediate node, and a seventh control electrode connected to the second reference potential; and The eighth transistor has a fifteenth electrode connected to the second reference potential, a sixteenth electrode connected to the first intermediate node, and an eighth control electrode connected to the second intermediate node.

6. The driving circuit according to any one of claims 1 to 3, characterized in that, The first output node is connected to any one of the scan signal lines in the scan signal line group and to the subsequent stages.

7. The driving circuit according to any one of claims 1 to 3, characterized in that, The first output node is not connected to the scan signal line group, but is connected to the subsequent stage.

8. A display device, characterized in that, include: The driving circuit as described in claim 1; as well as A display, which is equipped with the aforementioned scan signal line group.

9. An embedded touch panel device, characterized in that, include: The driving circuit as described in claim 1; as well as An embedded touch panel, which is an embedded touch panel configured with the scanning signal line group, and detects the touch of the indicator during the stop period.

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