一种基于存算单元中标准延时单元的时间数字转换器电路
By employing a time-to-digital converter circuit with a standard delay unit in the memory unit, combined with rising and falling edge signal quantization and advance carry mechanism, the contradiction between high resolution and low power consumption of TDC is resolved, achieving high-precision time-to-digital conversion, reducing energy consumption and improving quantization accuracy.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2024-12-19
- Publication Date
- 2026-07-17
AI Technical Summary
Existing time-to-digital converters (TDCs) face challenges in balancing high resolution and low power consumption, resulting in insufficient quantization accuracy or excessive conversion power consumption, which affects the practicality of delay unit chains in in-memory computing.
Quantization is performed using a standard delay unit consistent with the computing array, combining rising and falling edge signals, and introducing an advance carry mechanism to reduce errors. A fine counting module, a coarse counting module, an advance carry unit, a positive and negative edge switching module, and a decoder are designed to perform time-to-digital conversion by combining fine and coarse counting.
It effectively reduces energy consumption in the quantization process, reduces errors, improves quantization accuracy, and its structure is easy to expand, ensuring the reusability and scalability of the design.
Smart Images
Figure CN119834809B_ABST