Display panel and its manufacturing method, display device

Abstract

This application relates to a display panel and its manufacturing method, as well as a display device. The panel includes: a substrate; a pixel array including m pixel units, each pixel unit including a sub-pixels; in each pixel unit, the sub-pixels are arranged in a polygonal pattern, with each sub-pixel located at a vertex of the polygon; m sets of anode pads and m sets of cathode pads; m common pads located inside the polygons in each pixel unit; the common pads are common cathode pads electrically connected to the cathode pads; common pad connection lines electrically connecting the common pads of each row of pixel units, with the common pad connection lines of each row located on a straight line; electrode connection lines, each electrode connection line located on a straight line, electrically connecting the pads of the same seed pixel in a row or column of the pixel array. This invention simplifies circuit design, and the area occupied by pads, connection lines, and vias is smaller, thus increasing the number of pixels per unit area and improving the resolution of the display screen.

Description

Technical Field

[0001] This invention relates to the field of display device technology, and in particular to a display panel, a method for manufacturing the display panel, and a display device. Background Technology

[0002] With the development of display technology, improving resolution has become an important research topic in the field of LED (light-emitting diode) displays. Therefore, it is necessary to increase the number of pixels per unit area.

[0003] Traditional LED display panels have complex circuit designs, making it difficult to improve the resolution of the display screen. Summary of the Invention

[0004] Therefore, it is necessary to provide a display panel with a relatively simple circuit.

[0005] A display panel includes: a substrate; a pixel array located on a first main surface of the substrate, comprising m pixel units, each pixel unit comprising a sub-pixels, the pixel array comprising at most a sub-pixels, where a is an integer greater than 2 and m is a positive integer greater than 3; in each pixel unit, the sub-pixels are arranged in a polygonal pattern, each sub-pixel being located at a vertex of the polygon; m sets of anode pads and m sets of cathode pads located on the first main surface of the substrate, each set of anode pads comprising a anode pads corresponding one-to-one with the a sub-pixels, and each set of cathode pads comprising a cathode pads corresponding one-to-one with the a sub-pixels; and m common pads located on the first main surface and within the polygons in each pixel unit; the common pads... The pads are common cathode pads electrically connected to each cathode pad, or common anode pads electrically connected to each anode pad; common pad connection lines electrically connect the common pads of each row of pixel units, with the common pad connection lines of each row located on a straight line; or the common pad connection lines electrically connect the common pads of each column of pixel units, with the common pad connection lines of each column located on a straight line; electrode connection lines, each of the electrode connection lines located on a straight line, electrically connect the pads of the same seed pixel in a row or column of the pixel array, and the electrically connected pads are the anode pads and cathode pads that are not connected to the common pads, and the anode pads and cathode pads that are not connected to the common pads are located outside the polygon in each pixel unit.

[0006] The aforementioned display panel employs a special pad and connection line design, which simplifies the circuit design. The pads, connections, and vias occupy a smaller area, thus increasing the number of pixels per unit area and improving the display screen's resolution.

[0007] In one embodiment, the substrate is a glass substrate.

[0008] In one embodiment, the common pad of each pixel unit is located at the geometric center of each polygon.

[0009] In one embodiment, the polygons of each pixel unit have the same shape, size, and orientation.

[0010] In one embodiment, a=3, and each pixel unit includes sub-pixels of RGB colors.

[0011] In one embodiment, a first insulating layer is also included on the first main surface, through which the common pad connection lines are isolated from at least a portion of the electrode connection lines.

[0012] In one embodiment, a second insulating layer is further provided on the first insulating layer, wherein at least one sub-pixel electrically connected electrode connection line is isolated from other electrode connection lines through the second insulating layer, and / or at least one sub-pixel electrically connected electrode connection line is isolated from the common pad connection line through the second insulating layer.

[0013] In one embodiment, the substrate further includes electronic components and component pads located on a second main surface of the substrate, the electronic components being electrically connected to the component pads, the second main surface being opposite to the first main surface, and the substrate having through holes that electrically connect the pads on the second main surface to the pads on the first main surface.

[0014] A display device comprising the display panel described in any of the foregoing embodiments.

[0015] A method for manufacturing a display panel includes: obtaining a substrate; setting a pixel array and pads of the pixel array on a first main surface of the substrate; the pixel array includes m pixel units, each pixel unit includes a sub-pixels, the pixel array includes at most a seed pixels, a is an integer greater than 2, and m is a positive integer greater than 3; in each pixel unit, the sub-pixels are arranged in a polygon, and each sub-pixel is located at a vertex of the polygon; the pads of the pixel array include m sets of anode pads, m sets of cathode pads, and m common pads, each set of anode pads includes a anode pads corresponding one-to-one with the a sub-pixels, each set of cathode pads includes a cathode pads corresponding one-to-one with the a sub-pixels, and each common pad is located inside the polygon in each pixel unit; The common pad is a common cathode pad electrically connected to each cathode pad, or a common anode pad electrically connected to each anode pad; forming a common pad connection line; the common pad connection line electrically connects the common pad of each row of pixel units, and the common pad connection lines of each row are located on a straight line; or the common pad connection line electrically connects the common pad of each column of pixel units, and the common pad connection lines of each column are located on a straight line; forming an electrode connection line; each electrode connection line is located on a straight line and electrically connects the pads of the same seed pixel in a row or column of the pixel array, and the electrically connected pads are the anode pads and cathode pads that are not connected to the common pad, and the anode pads and cathode pads that are not connected to the common pad are located outside the polygon in each pixel unit.

[0016] The aforementioned manufacturing method for the display panel employs a special pad and connection line design, which simplifies the circuit design. The pads, connection lines, and vias occupy a smaller area, thus increasing the number of pixels per unit area and improving the resolution of the display screen.

[0017] In one embodiment, after the step of forming the common pad connection, the step of forming a first insulating layer on the first main surface is further included; the common pad connection and at least a portion of the electrode connection are isolated by the first insulating layer; in the step of forming the electrode connection, the at least a portion of the electrode connection is formed after the first insulating layer is formed.

[0018] In one embodiment, after forming the first insulating layer, the method further includes forming a second insulating layer on the first insulating layer, wherein at least one sub-pixel electrically connected electrode connection line is isolated from other electrode connection lines through the second insulating layer, and / or at least one sub-pixel electrically connected electrode connection line is isolated from the common pad connection line through the second insulating layer; in the step of forming electrode connection lines, the at least one pixel electrically connected electrode connection line is formed after forming the second insulating layer. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a portion of the structure of the display panel in one embodiment of this application.

[0020] Figure 2 This is a schematic diagram of the common pad connection line 132 extending along the column direction in one embodiment of this application.

[0021] Figure 3 This is a schematic diagram of the sub-pixel positions of a pixel unit in one embodiment of this application.

[0022] Figure 4 yes Figure 1 The diagram shown illustrates the structure after the LED chip has been installed.

[0023] Figure 5 This is a schematic diagram of a display panel using virtual pixels in one embodiment of this application.

[0024] Figure 6 This is a flowchart of a method for manufacturing a display panel according to one embodiment of this application.

[0025] Figure 7 This is a flowchart of a method for manufacturing a display panel according to another embodiment of this application.

[0026] Figure 8 This is a schematic diagram of the structure of a portion of the display panel after step S642 is completed in one embodiment of this application. Detailed Implementation

[0027] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0029] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0030] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0032] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0033] Figure 1 This is a schematic diagram of a portion of the structure of a display panel according to an embodiment of this application. The display panel includes a substrate 110 and a pixel array ( Figure 1 (Not shown), anode pad, cathode pad, common pad 121, common pad connection line 132, and electrode connection line 134. In one embodiment of this application, the display panel is an LED (light-emitting diode) display panel. The pixel array is located on the first main surface (i.e., the front surface of the substrate) of the substrate 110, including i rows and j columns, totaling i×j=m pixel units ( Figure 1 In this application, four squares on a substrate represent four pixel units. Each pixel unit includes *a* sub-pixels, and the pixel array includes at most *a* seed pixels, where *a* is an integer greater than 2 and *m* is a positive integer greater than 3. In one embodiment of this application, the *a* sub-pixels of each pixel unit are also *a* seed pixels. For example, each pixel unit includes three sub-pixels of RGB (red, green, blue), and the pixel array includes sub-pixels of RGB colors. In another embodiment of this application, each pixel unit includes four sub-pixels of RGBG, but only RGB sub-pixels, and the pixel array also includes sub-pixels of RGB colors. Figure 1 In the illustrated embodiment, a=3, and the pixel unit includes sub-pixels of RGB colors. Within each pixel unit, the sub-pixels are arranged in a polygon, denoted as polygon β. Each sub-pixel is located at a vertex of polygon β. Figure 1 In the illustrated embodiment, polygon β is a triangle, and the three RGB (red, green, blue) sub-pixels in each pixel unit serve as the three vertices of the triangle. In one embodiment of this application, the shape, size, and orientation of polygon β in each pixel unit are the same.

[0034] There are m sets of anode and cathode pads, meaning each pixel unit has a corresponding set of anode and cathode pads on the front side of the substrate. Each set of anode pads includes a anode pads corresponding to a sub-pixels, and each set of cathode pads includes a cathode pads corresponding to a sub-pixels. A common pad 121 is also corresponding to each pixel unit on the front side of the substrate and located inside polygon β within the corresponding pixel unit. In embodiments where the pixel array uses a common cathode connection, the common pad 121 is a common cathode pad electrically connecting all cathode pads; in embodiments where the pixel array uses a common anode connection, the common pad 121 is a common anode pad electrically connecting all anode pads. Figure 1 In the illustrated embodiment, the display panel employs a common cathode connection, with a common pad 121 in each pixel unit electrically connected to cathode pads 122a (cathode pad for the red sub-pixel), 122b (cathode pad for the blue sub-pixel), and 122c (cathode pad for the green sub-pixel). The substrate 110 has through-holes at the location of the common pad 121, electrically connecting the common pad 121 to the back of the substrate.

[0035] In one embodiment of this application, the common pad connection line 132 is electrically connected to the common pad 121 of each row of pixel units, and the common pad connection line 132 of each row is located on a straight line. Therefore, the common pads 121 of each row of pixel units need to be arranged on a straight line. To facilitate the identification of the various structures, Figure 1 Only the common pad connection line 132 of the first row of pixel units is shown (the common pad connection lines 132 of other rows are not shown). In another embodiment of this application, the common pad connection line 132 is electrically connected to the common pad 121 of each column of pixel units, and the common pad connection line 132 of each column of pixel units is located in a straight line, as shown in the reference. Figure 2 . Figure 2 The triangle of each pixel unit is Figure 2 In the illustrated embodiment, polygon β has each common pad 121 of each column of pixel units located on a straight line.

[0036] The pads in the anode and cathode pads that are not connected to the common pad 121 are located outside the polygon β in each pixel unit and are electrically connected to the electrode connection line 134. Figure 1In the illustrated embodiment, the common pad 121 is electrically connected to the cathode pad, therefore each anode pad (including anode pads 124a, 124b, and 124c) is located outside the polygon β and electrically connected via electrode connection lines 134. In the embodiment where the common pad 121 is electrically connected to the anode pad, the electrode connection lines 134 are electrically connected to each cathode pad, and each cathode pad is located outside the polygon β. Each electrode connection line 134 connects to the pads of the same seed pixel (whether they are the same type of pixel is determined by the a-seed pixel of the pixel array) in a row or column of the pixel array, and each electrode connection line 134 is located on a straight line. Therefore, the anode or cathode pads of the same seed pixel need to be arranged on a straight line. In one embodiment of this application, in each row of pixel units, the same seed pixel is located on a straight line in the row direction; and / or, in each column of pixel units, the same seed pixel is located on a straight line in the column direction.

[0037] The aforementioned display panel employs a special pad and connection line design, which simplifies the circuit design. The pads (including anode pads, cathode pads, and common pad 121), connection lines (including common pad connection lines 132 and electrode connection lines 134), and vias occupy a smaller area, thus increasing the number of pixels per unit area and improving the resolution of the display screen.

[0038] In one embodiment of this application, the substrate 110 may have one or more layers. In another embodiment, the substrate 110 is a glass substrate, which may be a single layer or multiple layers of glass. Using a glass substrate results in lower material costs and reduces usage costs. Furthermore, a glass substrate can support smaller LED chips.

[0039] In one embodiment of this application, the display panel further includes electronic components and component pads located on the second main surface (i.e., the back surface of the substrate) of the substrate 110. The electronic components may be electronic devices such as resistors, capacitors, and inductors, or other integrated circuits, and the electronic components are electrically connected to the component pads. The substrate 110 is provided with through holes that electrically connect the pads (component pads) on the back surface of the substrate to the pads (anode pads, cathode pads, and common pad 121) on the front surface of the substrate.

[0040] In one embodiment of this application, each common pad 121 is located at the geometric center of polygon β in the corresponding pixel unit, and the geometric centers of polygon β in each row or column are located on a straight line, so as to ensure that the common pad connection lines 132 in each row or column are located on a straight line. In one embodiment of this application, the geometric center of polygon β coincides with the geometric center of each pixel unit, see [link to relevant documentation]. Figure 3 .exist Figure 3 In the embodiment shown, the common pad 121 ( Figure 3 (Not shown in the image) is located at the incenter of a triangle formed by the three RGB sub-pixels.

[0041] In one embodiment of this application, the display panel further includes a first insulating layer located on the front side of the substrate. Figure 1 (Not shown in the image), the common pad connection line 132 and at least some of the electrode connection lines 134 are isolated by a first insulating layer. In one embodiment of this application, the common pad connection line 132, the first insulating layer, and some of the electrode connection lines 134 are a three-layer structure stacked sequentially from bottom to top. Figure 1 In the illustrated embodiment, the electrode connection line 134 connecting the anode pad 124b and the anode pad 124c is disposed on the first insulating layer. Since the electrode connection line 134 connecting the anode pad 124b and the anode pad 124c extends along the column direction, it will intersect with the common pad connection line 132 extending along the row direction. Therefore, the first insulating layer is provided to insulate and isolate them.

[0042] In one embodiment of this application, the first insulating layer may be formed only at the intersection of the common pad connection line 132 and the electrode connection line 134 (connecting anode pad 124b and anode pad 124c), i.e., an insulating layer with a "cap" structure is formed at the intersection. In other embodiments, a first insulating layer may be formed over a large area or covering the entire surface of the substrate 110. In one embodiment of this application, the electrode connection line 134 disposed on the first insulating layer passes through the through-holes of the first insulating layer and connects to each anode pad (in... Figure 1 In the illustrated embodiment, anode pads 124b and 124c are electrically connected.

[0043] In one embodiment of this application, the display panel further includes a second insulating layer located on the first insulating layer. Figure 1 (Not shown in the image), at least one sub-pixel electrically connected electrode connection line 134 is isolated from other electrode connection lines 134 by a second insulating layer, or at least one sub-pixel electrically connected electrode connection line 134 is isolated from the common pad connection line 132 by a second insulating layer. Figure 1 In the illustrated embodiment, the common pad connection line 132, the first insulating layer, a portion of the electrode connection lines 134, the second insulating layer, and another portion of the electrode connection lines 134 form a five-layer structure stacked sequentially from bottom to top. Figure 1In the illustrated embodiment, the electrode connection line 134 connecting the anode pad 124a is disposed on the second insulating layer and extends along the row direction. Since the electrode connection line 134 connecting the anode pad 124a extends along the row direction, it will intersect with the electrode connection lines 134 connecting the anode pads 124b and 124c extending along the column direction. Therefore, the second insulating layer is provided to insulate and isolate them.

[0044] In one embodiment of this application, the second insulating layer may be formed only at the intersection of the electrode connection line 134 (connecting anode pad 124a) and the electrode connection line 134 (connecting anode pad 124b and anode pad 124c), i.e., an insulating layer with a "cap" structure is formed at the intersection. In other embodiments, a large area or the entire surface of the substrate 110 may be formed as the second insulating layer. In one embodiment of this application, the electrode connection line 134 disposed on the second insulating layer passes through the through-holes of the second insulating layer and the through-holes of the first insulating layer, and connects with each anode pad (in Figure 1 In the embodiment shown, the anode pad 124a is electrically connected.

[0045] In one embodiment of this application, the display panel is an LED (light-emitting diode) display panel. Figure 4 yes Figure 1 The diagram shows the structure after the LED chips are installed. The LED chips can be substrate-free micro LED chips or mini LED chips. The pixel unit includes a red sub-pixel 120a, a blue sub-pixel 120b, and a green sub-pixel 120c. Red sub-pixel 120a is a red LED chip, blue sub-pixel 120b is a blue LED chip, and green sub-pixel 120c is a green LED chip. In one embodiment of this application, the long side dimension of the LED chip is 30 micrometers to 200 micrometers. With appropriate spacing between the LED chips, adjacent red, green, and blue LED chips can also be used to form virtual pixels. Figure 5 For the pixel design of the display panel using virtual pixels, each circle in the figure represents either a real pixel or a virtual pixel.

[0046] This application provides a display device including the display panel described in any of the foregoing embodiments. The display device may be an LED display screen, or a display screen of a terminal device such as a personal computer, mobile phone, or portable game console, or a display screen of a head-mounted display device (e.g., VR, AR, MR).

[0047] This application provides a method for manufacturing a display panel, which can be used to manufacture the display panel described in any of the foregoing embodiments. Figure 6 This is a flowchart of a method for manufacturing a display panel according to an embodiment of this application, including the following steps:

[0048] S610, Obtain the substrate.

[0049] In one embodiment of this application, the substrate 110 may have one or more layers. In one embodiment of this application, the substrate 110 is a glass substrate. Using a glass substrate results in lower material costs and reduces usage costs. Furthermore, a glass substrate can support smaller LED chips.

[0050] S620 has a pixel array and pixel array pads disposed on the first main surface of the substrate.

[0051] The first main surface is the front side of the substrate. The pixel array includes i rows and j columns, totaling i×j=m pixel units. Each pixel unit includes a sub-pixels, and the pixel array includes at most a sub-pixels, where a is an integer greater than 2 and m is a positive integer greater than 3. In one embodiment of this application, a=3, and the pixel unit includes sub-pixels of RGB colors. In each pixel unit, the sub-pixels are arranged in a polygon, denoted as polygon β. Each sub-pixel is located at a vertex of polygon β. In one embodiment of this application, polygon β is a triangle, and the three RGB (red, green, blue) sub-pixels in each pixel unit serve as the three vertices of the triangle. In one embodiment of this application, the shape, size, and orientation of polygon β in each pixel unit are the same.

[0052] The pixel array's pads include m sets of anode pads, m sets of cathode pads, and m common pads. There are a total of m sets of anode and cathode pads, meaning each pixel unit has one set corresponding to each anode pad on the front side of the substrate. Each set of anode pads includes a anode pads corresponding to a sub-pixels, and each set of cathode pads includes a cathode pads corresponding to a sub-pixels. The common pad 121 is also corresponding to each pixel unit on the front side of the substrate and is located inside polygon β in each pixel unit. In embodiments where the pixel array uses a common cathode connection, the common pad 121 is a common cathode pad electrically connecting all cathode pads; in embodiments where the pixel array uses a common anode connection, the common pad 121 is a common anode pad electrically connecting all anode pads. Figure 4 In the embodiment shown, the display panel adopts a common cathode connection, and the common pad 121 in each pixel unit is electrically connected to the cathode pad 122a (cathode pad of red sub-pixel), cathode pad 122b (cathode pad of blue sub-pixel) and cathode pad 122c (cathode pad of green sub-pixel).

[0053] In one embodiment of this application, before the common pad 121, a via is first opened at the location where the common pad 121 needs to be set on the substrate 110, and then the common pad 121 is deposited around the via.

[0054] S630 forms a common pad connection line.

[0055] In one embodiment of this application, the common pad connection line 132 is electrically connected to the common pad 121 of each row of pixel units, and the common pad connection line 132 of each row is located on a straight line. Therefore, the common pads 121 of each row need to be arranged on a straight line. To facilitate identification of the various structures, Figure 4 Only the common pad connection line 132 of the first row of pixel units is shown. In another embodiment of this application, the common pad connection line 132 is electrically connected to the common pad 121 of each column of pixel units, and the common pad connection line 132 of each column is located in a straight line, as shown in the reference. Figure 2 . Figure 2 The triangle of each pixel unit is Figure 2 In the illustrated embodiment, polygon β has each common pad 121 in each column located on a straight line.

[0056] S640 forms the electrode connection line.

[0057] The pads in the anode and cathode pads that are not connected to the common pad 121 are located outside the polygon β in each pixel unit and are electrically connected to the electrode connection line 134. Figure 4 In the illustrated embodiment, the common pad 121 is electrically connected to the cathode pad, therefore each anode pad (including anode pads 124a, 124b, and 124c) is electrically connected via electrode connection lines 134. In the embodiment where the common pad 121 is electrically connected to the anode pads, the electrode connection lines 134 are electrically connected to each cathode pad. Each electrode connection line 134 connects to the pads of the same seed pixel (i.e., the same seed pixel among the a seed pixels of the pixel array) in a row or column of the pixel array, and each electrode connection line 134 is located in a straight line. Therefore, the anode or cathode pads of the same seed pixel need to be aligned in a straight line.

[0058] The aforementioned manufacturing method for the display panel employs a special pad and connection line design, which simplifies the circuit design. The pads, connection lines, and vias occupy a smaller area, thus increasing the number of pixels per unit area and improving the resolution of the display screen.

[0059] Figure 7 This is a flowchart of a method for manufacturing a display panel according to another embodiment of this application, wherein steps S610 to S630 can be combined with... Figure 6 The illustrated embodiment is the same. After step S630, the method further includes:

[0060] S634, a first insulating layer is formed on the front side of the substrate.

[0061] The first insulation is used to insulate and isolate the common pad connection line 132 from at least a portion of the electrode connection line 134.

[0062] S642 forms part of the electrode connection line.

[0063] Reference Figure 8 In one embodiment of this application, step S642 includes forming an electrode connection line 134 connecting anode pads 124b and 124c. Since the electrode connection line 134 connecting anode pads 124b and 124c extends along the column direction, it will intersect with the common pad connection line 132 extending along the row direction; therefore, a first insulating layer is provided to insulate them. In one embodiment of this application, before step S642, a step of forming a through-hole in the first insulating layer is included. The electrode connection line 134 formed in step S642 passes through the through-hole in the first insulating layer and connects with each anode pad (in...). Figure 8 In the illustrated embodiment, anode pads 124b and 124c are electrically connected.

[0064] S644, a second insulating layer is formed on the first insulating layer.

[0065] The second insulating layer is used to insulate and isolate one part of the electrode connection line 134 from another part of the electrode connection line 134, or to insulate and isolate one part of the electrode connection line 134 from the common pad connection line 132.

[0066] S646 forms another part of the electrode connection line.

[0067] In one embodiment of this application, step S646 includes forming electrode connection lines 134 connecting anode pads 124a. Since the electrode connection lines 134 connecting anode pads 124a extend along the row direction, they will intersect with the electrode connection lines 134 connecting anode pads 124b and anode pads 124c extending along the column direction. Therefore, a second insulating layer is provided to insulate them. In one embodiment of this application, before performing step S646, a step of forming through-holes in the second insulating layer is included. The electrode connection lines 134 formed in step S646 pass through the through-holes in the second insulating layer and the through-holes in the first insulating layer, and connect with each anode pad (in...). Figure 1 In the embodiment shown, the anode pad 124a is electrically connected.

[0068] S650 forms electronic components and component pads on the back side of the substrate.

[0069] Electronic components can be resistors, capacitors, inductors, or other integrated circuits, and are electrically connected to the component pads.

[0070] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0071] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0072] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, include: substrate; A pixel array, located on the first main surface of the substrate, includes m pixel units, each pixel unit including a sub-pixels, the pixel array including at most a seed pixels, where a is an integer greater than 2 and m is a positive integer greater than 3; in each pixel unit, the sub-pixels are arranged in a polygon, and each sub-pixel is located at a vertex of the polygon; m groups of anode pads and m groups of cathode pads are located on the first main surface of the substrate. Each group of anode pads includes a anode pads that correspond one-to-one with the a sub-pixels, and each group of cathode pads includes a cathode pads that correspond one-to-one with the a sub-pixels. m common pads are located on the first main surface and inside the polygon in each pixel unit; the common pads are common cathode pads electrically connected to each cathode pad, or common anode pads electrically connected to each anode pad; A common pad connection line is electrically connected to the common pad of each row of pixel units, and the common pad connection lines of each row are located on a straight line; or the common pad connection line is electrically connected to the common pad of each column of pixel units, and the common pad connection lines of each column are located on a straight line. The electrode connection lines are all located on a straight line and electrically connect the pads of the same seed pixel in a row or column of the pixel array. The electrically connected pads are the anode pads and cathode pads that are not connected to the common pad. The anode pads and cathode pads that are not connected to the common pad are located outside the polygon in each pixel unit.

2. The display panel according to claim 1, characterized in that, The substrate is a glass substrate.

3. The display panel according to claim 1, characterized in that, The common pad of each pixel unit is located at the geometric center of each polygon; and / or The polygons in each pixel unit have the same shape, size, and orientation; and / or a=3, each pixel unit includes sub-pixels of three colors: RGB.

4. The display panel according to claim 1, characterized in that, It also includes a first insulating layer located on the first main surface, through which the common pad connection lines are isolated from at least a portion of the electrode connection lines.

5. The display panel according to claim 4, characterized in that, It also includes a second insulating layer located on the first insulating layer, wherein at least one electrode connection line electrically connected to a sub-pixel is isolated from other electrode connection lines or the common pad connection line through the second insulating layer.

6. The display panel according to any one of claims 1-5, characterized in that, It also includes electronic components and component pads located on the second main surface of the substrate, the electronic components being electrically connected to the component pads, the second main surface being opposite to the first main surface, and the substrate having through holes that electrically connect the pads on the second main surface to the pads on the first main surface.

7. A display device, characterized in that, Includes the display panel as described in any one of claims 1-6.

8. A method for manufacturing a display panel, comprising: Obtain the substrate; A pixel array and pads for the pixel array are disposed on a first main surface of the substrate. The pixel array comprises m pixel units, each pixel unit comprising a sub-pixels, and the pixel array comprises at most a seed pixels, where a is an integer greater than 2 and m is a positive integer greater than 3. In each pixel unit, the sub-pixels are arranged in a polygonal pattern, and each sub-pixel is located at a vertex of the polygon. The pads for the pixel array comprise m sets of anode pads, m sets of cathode pads, and m common pads. Each set of anode pads comprises a anode pads corresponding one-to-one with the a sub-pixels, and each set of cathode pads comprises a cathode pads corresponding one-to-one with the a sub-pixels. Each common pad is located inside the polygon in each pixel unit. The common pad is a common cathode pad electrically connected to each cathode pad, or a common anode pad electrically connected to each anode pad. A common pad connection line is formed; the common pad connection line is electrically connected to the common pad of each row of pixel units, and the common pad connection line of each row is located on a straight line; or the common pad connection line is electrically connected to the common pad of each column of pixel units, and the common pad connection line of each column is located on a straight line. Electrode connection lines are formed; each electrode connection line is located on a straight line and electrically connects the pads of the same seed pixel in a row or column of the pixel array, and the electrically connected pads are the anode pads and cathode pads that are not connected to the common pads, and the anode pads and cathode pads that are not connected to the common pads are located outside the polygon in each pixel unit.

9. The method for manufacturing a display panel according to claim 8, characterized in that, After the step of forming the common pad connection line, the method further includes the step of forming a first insulating layer on the first main surface; the common pad connection line is isolated from at least a portion of the electrode connection lines through the first insulating layer; In the step of forming electrode connection lines, at least a portion of the electrode connection lines are formed after the first insulating layer is formed.

10. The method for manufacturing a display panel according to claim 9, characterized in that, After forming the first insulating layer, the method further includes the step of forming a second insulating layer on the first insulating layer, wherein at least one electrode connection line electrically connected to a sub-pixel is isolated from other electrode connection lines or common pad connection lines through the second insulating layer. In the step of forming electrode connection lines, the electrode connection lines electrically connected to at least one sub-pixel are formed after the second insulating layer is formed.

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