Silicon wafer texturing pretreatment solution, silicon wafer texturing pretreatment method, silicon wafer texturing method and application thereof

Abstract

The application provides a silicon wafer etching pretreatment liquid, a silicon wafer etching pretreatment method and a silicon wafer etching method and application thereof. The silicon wafer etching pretreatment liquid comprises a first treatment liquid and a second treatment liquid. The first treatment liquid is a mixed solution of a first metal salt, hydrofluoric acid and nitric acid, and the second treatment liquid is a mixed solution of a second metal salt, hydrofluoric acid and nitric acid. In the first treatment liquid, the concentration of the first metal salt is 0.01-0.1 g / L, the concentration of the hydrofluoric acid is 3wt%-15wt%, and the concentration of the nitric acid is 5wt%-20wt%. In the second treatment liquid, the concentration of the second metal salt is 0.02-0.08 g / L, the mass concentration of the hydrofluoric acid is 5wt%-30wt%, and the mass concentration of the nitric acid is 10wt%-20wt%. The porous microstructure silicon wafer prepared by the application can not only provide many etching points for the subsequent alkaline etching, but also change the reaction kinetics. In a very short time and at a low temperature, the outer layer of the porous silicon gradually peels off, and finally grows into a uniform pyramid-shaped texture.

Description

Technical Field

[0001] This application relates to the field of silicon wafer texturing technology, and in particular to a silicon wafer texturing pretreatment liquid, a silicon wafer texturing pretreatment method, and a silicon wafer texturing method and their applications. Background Technology

[0002] With the increasing global demand for clean energy, solar cells, as a green and renewable clean energy source, have gradually become a research hotspot. Currently, the conversion efficiency of solar cells has made great breakthroughs, but there are still many challenges in the production process. For example, after the raw silicon wafer is cut, it will form several regions, including polycrystalline domains, fracture domains, elastic distortion domains, and substrate silicon, which are generally removed by pre-cleaning and texturing processes.

[0003] Texturing primarily utilizes the anisotropic etching characteristics of silicon wafers in low-concentration alkaline solutions, meaning the etching rate of silicon on the 110 and 100 crystal planes is much higher than that on the 111 crystal plane. The specific texturing process involves: a pre-cleaning process to remove organic contaminants and metallic impurities from the silicon wafer surface, as well as the mechanical damage layer generated during the wire cutting process, thereby reducing recombination centers; then, under the synergistic effect of alkali and additives, the wafer is immersed in a high-temperature environment of 82°C for approximately 7 minutes, forming an uneven, pyramidal texture on the silicon wafer surface. This process results in a long texturing time and high temperature, leading to low texturing efficiency and high texturing costs. Summary of the Invention

[0004] This application provides a silicon wafer texturing pretreatment solution, a silicon wafer texturing pretreatment method, and a silicon wafer texturing method and their applications, aiming to solve the problems of low texturing efficiency and high texturing cost in traditional texturing technology.

[0005] In a first aspect, embodiments of this application provide a silicon wafer texturing pretreatment solution, including a first treatment solution and a second treatment solution, wherein the first treatment solution is a mixed solution of a first metal salt, hydrofluoric acid and nitric acid, and the second treatment solution is a mixed solution of a second metal salt, hydrofluoric acid and nitric acid;

[0006] In the first treatment solution, the concentration of the first metal salt is 0.01-0.1 g / L, the concentration of hydrofluoric acid is 3 wt%-15 wt%, and the concentration of nitric acid is 5 wt%-20 wt%.

[0007] In the second treatment solution, the concentration of the second metal salt is 0.02-0.08 g / L, the mass concentration of hydrofluoric acid is 5wt%-30wt%, and the mass concentration of nitric acid is 10wt%-20wt%.

[0008] Optionally, the first metal salt includes one of silver nitrate and silver fluoride, and the second metal salt includes one of copper nitrate, copper chloride, and copper sulfate.

[0009] Secondly, embodiments of this application provide a method for texturing silicon wafers, the method comprising:

[0010] A first metal salt, hydrofluoric acid, and nitric acid are mixed to obtain a first treatment solution. In the first treatment solution, the concentration of the first metal salt is 0.01-0.1 g / L, the concentration of hydrofluoric acid is 3 wt%-15 wt%, and the concentration of nitric acid is 5 wt%-20 wt%.

[0011] A second metal salt, hydrofluoric acid, and nitric acid are mixed to obtain a second treatment solution. In the second treatment solution, the concentration of the second metal salt is 0.02-0.08 g / L, the mass concentration of hydrofluoric acid is 5wt%-30wt%, and the mass concentration of nitric acid is 10wt%-20wt%.

[0012] The silicon wafer is placed in the first processing solution for treatment;

[0013] The silicon wafers treated with the first processing solution are then washed with water.

[0014] The washed silicon wafer is placed in the second pretreatment solution for catalytic etching to obtain a silicon wafer with a porous microstructure.

[0015] Optionally, the step of placing the original silicon wafer in the first processing solution for treatment further includes:

[0016] The silicon wafers were cleaned in a mixed solution of 0.25wt%-0.5wt% NaOH and 1.5wt%-3.0wt% H2O2 at a temperature of 60-70℃ for 180-220 seconds.

[0017] Optionally, in the first treatment solution, the concentration of the first metal salt is 0.01-0.03 g / L, the concentration of hydrofluoric acid is 5wt%-10wt%, and the concentration of nitric acid is 10wt%-15wt%.

[0018] Optionally, in the second treatment solution, the concentration of the second metal salt is 0.04-0.06 g / L, the concentration of hydrofluoric acid is 10wt%-25wt%, and the concentration of nitric acid is 15wt%-16wt%.

[0019] Optionally, in the step of placing the silicon wafer in the first processing solution:

[0020] The processing temperature is 25-35℃, and the processing time is 50-70s.

[0021] Optionally, in the step of placing the water-washed silicon wafer in the second pretreatment solution for catalytic etching:

[0022] The catalytic etching temperature is 25-35℃, and the catalytic etching time is 110-130s.

[0023] Thirdly, embodiments of this application provide a silicon wafer texturing method, including the aforementioned silicon wafer texturing pretreatment method. Following the silicon wafer texturing pretreatment method, the silicon wafer texturing method further includes:

[0024] The catalytically etched silicon wafers were cleaned with NH3·H2O and H2O2 at a temperature of 60-70℃ for 160-200 seconds.

[0025] The cleaned silicon wafers are placed in a texturing bath containing 0.5wt%-1.5wt% NaOH and 5wt%-10wt% androstenedione for etching at a temperature of 50-70℃ for 200-280s.

[0026] Fourthly, embodiments of this application provide an application of a silicon wafer texturing product obtained according to the above-described silicon wafer texturing method in a solar cell.

[0027] The embodiments of this application employing the above-described technical solution may have the following advantages:

[0028] 1. By first treating the silicon wafer with a first processing solution containing a low concentration of a first metal salt, and then treating it with a second processing solution containing a high concentration of a second metal salt, a porous microstructure is formed in the silicon wafer under the metal catalysis of a mixed solution of AgNO3 / Cu(NO3)2, HF, and HNO3. The resulting porous silicon has an aspect ratio of approximately 5, a diameter of 100-200 nm, and a depth of 500-1000 nm, mainly due to Ag... + / Ag、Cu 2+ Cu has a stronger electronegativity than silicon, followed by Ag. + Cu 2+ They will be reduced and grown into Ag and Cu nanoparticles (Ag / Cu NPs). The potential difference between the upper and lower surfaces of Ag / Cu NPs, as well as the influence of the built-in electric field and the solution environment, lead to the oxidation of the single crystal of Ag / Cu NPs and the corrosion of a large number of porous structures, thus obtaining a porous silicon wafer. In addition, these Ag / Cu NPs are not always oriented vertically downward along the (100) crystal surface, which leads to the spiral etching and lateral etching of the silicon wafer, making the porous structure of the silicon wafer more dense and uniform.

[0029] 2. After passing through, a second treatment solution containing copper metal salt is used for treatment. Copper acts as a catalyst. During the process of electron transfer from silicon, the silicon in the parts that can come into contact with silver and copper will be oxidized. The oxidized silicon is dissolved and removed by HF, which is beneficial to further improve the chemical etching effect of metal catalysis.

[0030] 3. The porous microstructure silicon wafer prepared in the embodiments of this application not only provides many texturing points for alkaline etching in the subsequent texturing process, but also changes the reaction kinetics. In a very short time and at a low temperature, the outer layer of the porous silicon gradually peels off and eventually grows into a uniform pyramid-shaped texture.

[0031] 4. In this embodiment, the nucleation of the pyramid structure obtained after texturing begins with a porous structure catalytically etched by metal. The silicon wafer surface evolves from a porous structure into a partially inverted pyramid, and finally, with increasing alkaline etching time, a completely covered upright pyramid is formed. This is significantly different from the mechanism of pyramid nucleation and growth in current texturing processes, which mainly rely on nucleating agents in additives. This application achieves a high surface chemical state in the porous silicon structure, enabling rapid (200-280s) and low-temperature (50-70℃) alkaline texturing of the textured surface during subsequent texturing processes. The resulting pyramid structure is more independent and uniform, with less texturing debris. When matched with subsequent coating processes and LECO technology, this improves passivation and contact, thereby increasing open-circuit voltage and fill factor. Attached Figure Description

[0032] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0033] Figure 1 This is a flowchart of a silicon wafer texturing pretreatment method provided in an embodiment of this application;

[0034] Figure 2 This is an effect diagram of a silicon wafer texturing method provided in an embodiment of this application. Detailed Implementation

[0035] The embodiments of this application are described in detail below, examples of which are illustrated in the accompanying drawings. In the drawings, for clarity, the dimensions of layers, regions, and elements, as well as their relative dimensions, may be exaggerated. Throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0036] It should be understood that when an element or layer is referred to as "on," "below," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "below," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part. When a second element, component, region, layer, or portion is discussed, it does not imply that a first element, component, region, layer, or portion necessarily exists in this disclosure.

[0037] In this application, unless otherwise expressly specified and limited, the terms "set," "install," "connect," "link," and "fix" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0038] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0039] To facilitate understanding of the technical solutions provided in the embodiments of this application by those skilled in the art, the relevant technologies are described below:

[0040] The applicant discovered that texturing mainly utilizes the anisotropic corrosion characteristics of silicon wafers in low-concentration alkaline solutions, namely, the corrosion rate of silicon on the (110) and (100) crystal planes is much greater than that on the 111 crystal plane. The specific texturing process is as follows: the silicon wafer undergoes a pre-cleaning process to remove organic dirt and metallic impurities from the surface of the silicon wafer, while also removing the mechanical damage layer generated during the silicon wafer wire cutting process, thereby reducing the number of composite centers; then, under the synergistic effect of alkali and additives, it is immersed in a high temperature of 82°C for about 7 minutes, thereby forming an uneven textured surface, i.e., a pyramid, on the surface of the silicon wafer. This results in the current texturing tank process being time-consuming and at high temperatures, leading to low texturing efficiency and high texturing costs.

[0041] In view of the above problems, the texturing pretreatment solution proposed in this application utilizes a mixture of AgNO3 / Cu(NO3)2, HF, and HNO3 to form porous silicon. The main mechanism is Ag... + / Ag、Cu 2+ Cu has a stronger electronegativity than silicon, followed by Ag. + Cu 2+ The material will be reduced and grown into Ag and Cu nanoparticles (Ag / Cu NPs). The potential difference between the upper and lower surfaces of Ag / Cu NPs, as well as the influence of the built-in electric field and the solution environment, lead to the oxidation of the Ag / Cu NPs single crystal and the corrosion of a large number of porous structures. In addition, these Ag / Cu NPs are not always oriented vertically downward along the (100) crystal surface, resulting in spiral and lateral etching of the silicon wafer, which in turn makes the porous structure of the silicon wafer more compact and uniform. Furthermore, the resulting porous microstructure of the silicon wafer not only provides many texturing points for the alkaline etching in the subsequent texturing process, but also changes the reaction kinetics, thereby enabling the subsequent texturing process to form a uniform pyramidal texture in a very short time and at a low temperature.

[0042] Exemplary embodiments according to this application will now be described in more detail with reference to the accompanying drawings. It should be understood that these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0043] Please see Figure 1 This application provides a silicon wafer texturing pretreatment method, including steps S101 to S105, wherein:

[0044] Step 101: Mix the first metal salt, hydrofluoric acid, and nitric acid to obtain the first treatment solution;

[0045] It should be noted that in the prepared first treatment solution, the concentration of the first metal salt is 0.01-0.1 g / L, the concentration of hydrofluoric acid is 3 wt%-15 wt%, and the concentration of nitric acid is 5 wt%-20 wt%.

[0046] In some embodiments, the first metal salt includes at least one of silver nitrate and silver fluoride, and the concentration of the first metal salt needs to be lower than the concentration of the second metal salt. If the concentration of the first metal salt is too low, it will affect the metal catalytic etching effect of the first treatment solution; if the concentration of the first metal salt is too high, it will affect the metal catalytic etching effect of the second treatment solution. By controlling the concentration of the first metal salt within a suitable range of 0.01-0.1 g / L, Ag can be effectively catalytically etched. + They are reduced and grown into Ag nanoparticles (Ag NPs), thereby achieving the initial etching of the silicon wafer.

[0047] In some embodiments, the concentration of the first metal salt is preferably 0.01-0.03 g / L, the concentration of hydrofluoric acid is preferably 5wt%-10wt%, and the concentration of nitric acid is preferably 10wt%-15wt%.

[0048] Step 102: Mix the second metal salt, hydrofluoric acid, and nitric acid to obtain the second treatment solution;

[0049] It should be noted that in the prepared second treatment solution, the concentration of the second metal salt is 0.02-0.08 g / L, the mass concentration of hydrofluoric acid is 5wt%-30wt%, and the mass concentration of nitric acid is 10wt%-20wt%.

[0050] In some embodiments, the second metal salt includes one of copper nitrate, copper chloride, and copper sulfate. If the concentration of the second metal salt is too low, the reaction rate is slow, resulting in a small porous structure; if the concentration of the second metal salt is too high, the reaction rate is fast, but the porous structure may be uneven. By controlling the concentration of the second metal salt within a suitable range, i.e., 0.01-0.03 g / L, the Cu... 2+ It will be reduced and grown into Cu nanoparticles. Under the combined effect of the potential difference between the upper and lower surfaces of the Cu nanoparticles, the built-in electric field, and the solution environment, the Ag / Cu NPs single crystal undergoes oxidation and corrosion of a large number of porous structures, thereby ensuring the formation of porous silicon.

[0051] In some embodiments, the concentration of the second metal salt is preferably 0.04-0.06 g / L, the concentration of hydrofluoric acid is preferably 10wt%-25wt%, and the concentration of nitric acid is preferably 15wt%-16wt%.

[0052] Step 103: Place the silicon wafer in the first processing solution for treatment;

[0053] In some embodiments, the processing temperature of the first processing liquid is 25-35°C and the processing time is 50-70s. For example, the processing temperature of the first processing liquid for pretreatment can be 25°C, 30°C, 35°C, etc., and the processing time of the first processing liquid for pretreatment can be 50s, 60s, 70s, etc.

[0054] Step 104: Wash the silicon wafers after the first treatment with water;

[0055] It should be noted that, in order to avoid the excessive silver ions affecting the catalytic etching effect of subsequent copper ions, after the first treatment solution containing silver ions is used, the silicon wafer needs to be washed with deionized water to remove some or even all of the residual silver ions.

[0056] Step 105: Place the washed silicon wafer in the second pretreatment solution for catalytic etching to obtain a silicon wafer with a porous microstructure.

[0057] In some embodiments, the catalytic etching temperature of the second processing solution for catalytic etching is 25-35°C, and the catalytic etching time is 110-130s. For example, the catalytic etching temperature for pretreatment with the second processing solution can be 25°C, 30°C, 35°C, etc., and the catalytic etching time for pretreatment with the second processing solution can be 110s, 120s, 130s, etc.

[0058] In addition, in some embodiments, before placing the original silicon wafer in the first processing solution, it is necessary to clean the silicon wafer in a mixed solution of 0.25wt%-0.5wt% NaOH and 1.5wt%-3.0wt% H2O2 at a cleaning temperature of 60-70℃ for 180-220s to remove organic matter and some mechanical damage layers from the silicon surface. After that, the silicon wafer is washed with water, and then the washed silicon wafer is placed in the first processing solution for pretreatment.

[0059] In summary, the porous silicon prepared in this application not only provides numerous texturing points for alkaline etching but also alters the reaction kinetics. This allows the outer layer of the porous silicon to gradually peel off during the texturing process in a very short time and at a relatively low temperature, ultimately growing into a uniform pyramidal texture.

[0060] This application also provides a method for texturing silicon wafers, which includes the following steps after the silicon wafer texturing pretreatment method:

[0061] Step S201: The catalytically etched silicon wafer is cleaned in 11wt%-14wt% NH3·H2O and 15wt%-20wt% H2O2 at a temperature of 60-70℃ for 160-200s.

[0062] It should be noted that the purpose of this step is to remove metal residues from the surface of the silicon wafer. The cleaning temperature can be 60℃, 65℃, 70℃, etc., and the cleaning time can be 160s, 180s, 200s, etc.

[0063] Step S202: Place the cleaned silicon wafer in a texturing bath containing 0.5wt%-1.5wt% NaOH and 5wt%-10wt% androstenedione for etching. The etching temperature is 50-70℃ and the etching time is 200-280s.

[0064] After obtaining the pyramid-shaped textured surface structure, this step requires washing with water. In addition, the final pyramid dimensions are 1.65-1.70 μm wide, 1.0 ± 0.2 μm high, with a texture yield of over 200,000, a specific surface area of ​​about 1.25, and a reflectivity of 9%-10%.

[0065] Furthermore, by using the first and second processing solutions for pretreatment, the prepared porous silicon not only provides many texturing points for alkaline etching, but also changes the reaction kinetics, resulting in a lower etching temperature and shorter etching time during the actual texturing process in this step.

[0066] Step S203: Clean the silicon wafer by placing it in a mixed solution containing 0.25wt%-0.5wt% NaOH and 1.5wt%-3.0wt% H2O2;

[0067] The purpose of this alkaline washing step is to remove residual organic matter. After the alkaline washing, the silicon wafer also needs to be washed with water.

[0068] Step S204: Place the silicon wafer in a mixture of 10wt%-13wt%HF and 60wt%-65wt%HNO3, place it at 30°C for 3-7 seconds, and then wash it with water.

[0069] Treatment with a mixture of HF and [unspecified substance] can smooth the bottom of the pyramid structure.

[0070] Step S205: Immerse the silicon wafer in an acid bath containing a mixed solution of 2wt%-5wt% HF and HCl, and then wash it with water;

[0071] This step involves acid washing of the silicon wafer to remove the oxide layer and some metal ion impurities.

[0072] Step S206: Place the silicon wafer in a hot water bath at 70-75℃ for 15-25 seconds;

[0073] In practice, this step requires entering the slow lifting groove, where a robotic arm slowly lifts the basket to dehydrate the silicon wafer surface, preventing watermarks and wafer stacking.

[0074] Step S207: Dry the silicon wafer at a high temperature of 80-90℃ for 650-750 seconds.

[0075] In summary, compared with the prior art, this application has the following advantages:

[0076] 1. The pyramid structure prepared in the embodiments of this application is more independent, highly uniform and concentrated. When matched with the subsequent passivation process and LECO technology, it is conducive to improving passivation capability and contact, thereby improving open circuit voltage and fill factor, and the final cell has a gain of about 0.03-0.05%.

[0077] 2. The embodiments of this application obtain denser and smaller submicron pyramids, which slightly improves the short-wavelength absorption of the silicon wafer prepared by the new process, thereby increasing the possibility of short-wavelength photons being refracted into the silicon and improving the short-circuit current.

[0078] 3. The nucleation of the pyramids involved in this application starts from the porous structure of metal catalytic etching. The wafer surface evolves from a porous structure into a partially inverted pyramid, and finally becomes a fully covered upright pyramid as the alkaline etching time increases. The high surface chemical state of the porous silicon structure is the fundamental reason why this application embodiment can achieve fast and low-temperature alkaline texture.

[0079] The following specific embodiments provide a more detailed description of this application, but should not be construed as limiting the application. Any modifications or substitutions made to the methods, steps, or conditions of this application without departing from the spirit and substance of this application are within the scope of this application.

[0080]

Example 1

[0081] (1) Silver nitrate, hydrofluoric acid and nitric acid are mixed to obtain a first treatment solution. In the first treatment solution, the concentration of silver nitrate is 0.01 g / L, the concentration of hydrofluoric acid is 3 wt%, and the concentration of nitric acid is 5 wt%.

[0082] (2) Copper nitrate, hydrofluoric acid and nitric acid are mixed to obtain a second treatment solution. In the second treatment solution, the concentration of copper nitrate is 0.02 g / L, the mass concentration of hydrofluoric acid is 5 wt%, and the mass concentration of nitric acid is 10 wt%.

[0083] (3) The silicon wafer was cleaned in a mixed solution of 0.35wt% NaOH and 2.0wt% H2O2 at a temperature of 65℃ for 200s.

[0084] (4) The silicon wafer is placed in the first processing solution for 60 seconds and the processing temperature is 30°C.

[0085] (5) Wash the silicon wafers after they have been treated with the first treatment solution with water;

[0086] (6) The washed silicon wafer is placed in the second pretreatment solution for catalytic etching to obtain a silicon wafer with a porous microstructure. The catalytic etching time is 120s and the catalytic etching temperature is 30℃.

[0087] (7) The silicon wafer that has been catalytically etched is placed in 13wt% NH3·H2O and 18wt% H2O2 for cleaning. The cleaning temperature is 65℃ and the cleaning time is 180s.

[0088] (8) The cleaned silicon wafer was placed in a texturing tank containing 1wt% NaOH and 7.5wt% androstenedione for etching at a temperature of 60°C for 240s.

[0089] (9) The silicon wafer is cleaned in a mixed solution containing 0.35wt% NaOH and 2.0wt% H2O2, and then washed with water;

[0090] (10) Place the silicon wafer in a mixture of 12wt%HF and 62wt%HNO3, place it at 30°C for 3-7s, and then wash it with water;

[0091] (11) Immerse the silicon wafer in an acid bath containing a mixed solution of 3.5 wt% HF and HCl, and then wash it with water;

[0092] (12) Place the silicon wafer in a 75°C hot water bath for 20 seconds;

[0093] (13) Dry the silicon wafer at a high temperature of 85°C for 700 seconds.

[0094] Example 2 - Example 7

[0095] Examples 2-7 are basically the same as the scheme of Example 1, except that the following are the differences: the ratio of the first treatment liquid in step (1), the ratio of the second treatment liquid in step (2), the treatment temperature of the first treatment liquid in step (4), the treatment time of the first treatment liquid in step (6), the etching time in step (8), and the etching temperature in step (8), as detailed in Table 1 below:

[0096] Table 1

[0097]

[0098] To more clearly illustrate the technical effects of the embodiments of this application, this application also points out the silicon wafer texturing methods of [Comparative Examples 1]-[Comparative Examples 6].

[0099] Comparative Example 1 - Comparative Example 4

[0100] Comparative Examples 1-4 are basically the same as those in Example 1, except that the proportions of the first treatment solution in step (1), the proportions of the second treatment solution in step (2), the treatment temperature of the first treatment solution in step (4), the treatment time of the first treatment solution in step (6), the etching time in step (8), and the etching temperature in step (8) are adjusted as shown in Table 2 below:

[0101] Table 2

[0102]

[0103] Comparative Example 5

[0104] Comparative Example 5 is basically the same as Example 1, except that steps (1), (3), (4) and (5) are deleted, that is, only the second processing liquid is used to pre-treat the silicon wafer.

[0105] Comparative Example 6

[0106] Comparative Example 6 is basically the same as Example 1, except that steps (2), (3), (5) and (6) are deleted, that is, only the first processing liquid is used to pre-treat the silicon wafer.

[0107] The performance of the silicon wafer texturing products obtained by the silicon wafer texturing method in Examples 1-7 and Comparative Examples 1-6 of this application is tested below to obtain the pyramid height, pyramid width, texturing quantity, reflectivity, specific surface area, open-circuit voltage, fill factor, and short-circuit current of the silicon wafer texturing products. The test results are shown in Table 3 below:

[0108] Table 3 Performance test results of Examples 1-6 and Comparative Examples 1-6

[0109]

[0110] Data Results Analysis: According to the data recorded in Table 3, the pyramid-shaped textured structure prepared in this application has a pyramid width of 1.65-1.70 μm and a pyramid height of 1.0 ± 0.2 μm. The process is stable and can meet the production line requirements. In contrast, the textured structures obtained in the comparative examples either do not meet the requirements for pyramid width or pyramid height. Furthermore, the textured quantity of this application is above 20W, which is significantly higher than that of comparative examples 1-6, indicating that the embodiments of this application have a good textured effect. In addition, the reflectivity of the embodiments of this application is significantly lower than that of the comparative examples, reaching as low as 9.14. Moreover, the cells prepared in this application have improved open-circuit voltage, short-circuit current, and fill factor, indicating that the solar cells obtained in this application have good performance.

[0111] In summary, the porous microstructure silicon wafer prepared in this application not only provides numerous texturing points for alkaline etching in the subsequent texturing process, but also alters the reaction kinetics, allowing the outer layer of the porous silicon to gradually peel off in a very short time and at a low temperature, ultimately growing into a uniform pyramidal texture; furthermore, the porous microstructure... Figure 2 It can be seen that by achieving a high surface chemical state of porous silicon structure, alkaline texture of the texturing surface can be achieved quickly (200-280s) and at low temperature (50-70℃) in the subsequent texturing process. The resulting pyramid structure is more independent and neat, with less broken texturing. When matched with the subsequent coating process and LECO technology, it is beneficial to passivation ability and contact improvement, thereby increasing open circuit voltage and fill factor.

[0112] This application also provides an application of the silicon wafer texturing product obtained by the above-described silicon wafer texturing method in solar cells.

[0113] This application provides a photovoltaic module (not shown) with multiple solar cells connected in series and / or in parallel, wherein at least one solar cell is the perovskite solar cell described above, and adjacent perovskite solar cells can be connected together by string welding.

[0114] This application provides a photovoltaic system including the photovoltaic modules described in any of the above embodiments. The advantages of the aforementioned photovoltaic modules are also present in this photovoltaic system, and will not be repeated here. The application fields of the aforementioned photovoltaic system are wide, not limited to photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and floating power plants, but also including various devices and apparatuses that utilize solar energy for power generation, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of the photovoltaic system are not limited to these; that is, the photovoltaic system can be applied in all fields that require solar energy for power generation. Taking a photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic modules; for example, multiple photovoltaic modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can collect the current generated by the photovoltaic array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to achieve solar power supply.

[0115] It should be noted that the terms "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. The directional terms "inner" and "outer" refer to the inside or outside relative to the outline of the component itself. For example, if the device in the drawings is inverted, a device described as "above" or "on top of other devices or structures" will later be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein are interpreted accordingly.

[0116] It should also be noted that the terms "one embodiment," "another embodiment," and "embodiment" used in this application refer to specific features, structures, or characteristics described in connection with that embodiment, which are included in at least one embodiment described in the general description of this application. The appearance of the same expression in multiple places in the specification does not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure, or characteristic is described in connection with any embodiment, the intention is to suggest that implementing such a feature, structure, or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0117] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0118] It should also be noted that the above are merely preferred embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A method for texturing silicon wafers, characterized in that, The method includes: A first metal salt, hydrofluoric acid, and nitric acid are mixed to obtain a first treatment solution. In the first treatment solution, the concentration of the first metal salt is 0.01-0.1 g / L, the concentration of hydrofluoric acid is 3 wt%-15 wt%, and the concentration of nitric acid is 5 wt%-20 wt%. A second metal salt, hydrofluoric acid, and nitric acid are mixed to obtain a second treatment solution. In the second treatment solution, the concentration of the second metal salt is 0.02-0.08 g / L, the mass concentration of hydrofluoric acid is 5wt%-30wt%, and the mass concentration of nitric acid is 10wt%-20wt%. The first metal salt includes one of silver nitrate and silver fluoride, and the second metal salt includes one of copper nitrate, copper chloride, and copper sulfate. The silicon wafer is placed in the first processing solution for treatment; The silicon wafers that have been treated with the first processing solution are then washed with water. The washed silicon wafer is placed in the second processing solution for catalytic etching to obtain a silicon wafer with a porous microstructure.

2. The silicon wafer texturing pretreatment method according to claim 1, characterized in that, Prior to placing the silicon wafer in the first processing solution for treatment, the process further includes: The silicon wafers were cleaned in a mixed solution of 0.25wt%-0.5wt% NaOH and 1.5wt%-3.0wt% H2O2 at a temperature of 60-70℃ for 180-220 seconds.

3. The silicon wafer texturing pretreatment method according to claim 1, characterized in that, In the first treatment solution, the concentration of the first metal salt is 0.01-0.03 g / L, the concentration of hydrofluoric acid is 5 wt%-10 wt%, and the concentration of nitric acid is 10 wt%-15 wt%.

4. The silicon wafer texturing pretreatment method according to claim 1, characterized in that, In the second treatment solution, the concentration of the second metal salt is 0.04-0.06 g / L, the concentration of hydrofluoric acid is 10wt%-25wt%, and the concentration of nitric acid is 15wt%-16wt%.

5. The silicon wafer texturing pretreatment method according to claim 1, characterized in that, In the step of placing the silicon wafer in the first processing solution: The processing temperature is 25-35℃, and the processing time is 50-70s.

6. The silicon wafer texturing pretreatment method according to claim 1, characterized in that, In the step of placing the water-washed silicon wafer in the second processing solution for catalytic etching: The catalytic etching temperature is 25-35℃, and the catalytic etching time is 110-130s.

7. A method for texturing silicon wafers, characterized in that, The silicon wafer texturing pretreatment method according to any one of claims 1-4, wherein after the silicon wafer texturing pretreatment method, the silicon wafer texturing method further includes: The catalytically etched silicon wafers were cleaned with NH3·H2O and H2O2 at a temperature of 60-70℃ for 160-200 seconds. The cleaned silicon wafers are placed in a texturing bath containing 0.5wt%-1.5wt% NaOH and 5wt%-10wt% androstenedione for etching at a temperature of 50-70℃ for 200-280s.

8. The application of a silicon wafer texturing product obtained by the silicon wafer texturing method according to claim 7 in solar cells.

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