Chip high-voltage boosting test judgment method and device

Abstract

The invention relates to a chip high-voltage boosting test judgment method and device, and the method comprises the steps: introducing an oxide layer breakdown time model, precisely calculating a test condition based on a mathematical model, and employing the thickness consumption of an oxide layer and the quantitative analysis of a voltage factor, guaranteeing that the test condition meets the acceleration failure, remarkably reducing the test redundancy, and improving the test efficiency. And the test efficiency is improved. Compared with a traditional test method which mostly depends on experience or subjective judgment and is low in screening accuracy of bad chips after an HVS test, the scheme adopts a two-time current difference statistical analysis method of an IDDQ test and takes deviation from a statistical standard value (such as a value deviating from more than 2 sigma) as a judgment basis, so that the objectivity and repeatability of a judgment process are ensured. Through the standardized process, the misjudgment rate and the missed judgment rate are effectively reduced, so that the consistency and the reliability of the product quality are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of chip testing, and relates to a chip high voltage pressurization test determination method and device. Background Art

[0002] The chip production process involves multiple links from silicon crystal production to packaging, among which yield and reliability are important factors driving production and manufacturing. However, oxide defects have been considered one of the main reasons affecting the reliability of integrated circuits. Defects may come from particle contamination, substrate defects, or local point defects in the oxide. These problems can cause current to break through the oxide layer, causing chip damage, which in turn affects circuit performance and reliability.

[0003] In order to solve the problem of oxide layer defects, the chip is usually stress screened by high-voltage stress test (High-Voltage Stress Test, hereinafter referred to as HVS test). This accelerated test can effectively reduce the number of early defects in the chip, thereby improving the reliability of the product. However, this type of test method usually requires a lot of time and cost, accounting for about 5% - 40% of the total manufacturing cost, and increases production complexity. In addition, the existing HVS test process lacks a systematic and standardized method to determine the test conditions and determine whether the chip passes the test, which brings inconvenience to the implementation of the test and the analysis of the results. Therefore, it is necessary to develop a complete test process method to clarify the experimental conditions of the HVS test (for the digital circuit of the chip), and efficiently and accurately determine whether the chip passes the test, so as to optimize the test process and improve product quality. Summary of the invention

[0004] In response to the problems existing in the above-mentioned traditional testing methods, the present invention proposes a chip high-voltage pressure test judgment method and a chip high-voltage pressure test judgment device, which can provide a complete test process method to clarify the experimental conditions of the HVS test and efficiently and accurately determine whether the chip passes the test.

[0005] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a chip high voltage pressurization test determination method is provided, comprising the steps of: Obtain the current value measured by the chip manufacturing unit during the IDDQ test of the chip under test before the HVS test; According to the early failure period of the chip under test, the HVS test voltage and test time used in the HVS test of the chip under test are calculated using the oxide layer breakdown time model; Perform HVS test on the chip under test according to the HVS test voltage and test time; Obtain the current value measured by the chip manufacturing unit during the IDDQ test of the chip under test after the HVS test; In the chip manufacturing unit, the difference between the current values ​​measured by the IDDQ test before and after the HVS test is statistically analyzed; When the chip under test shows a difference that deviates from the statistical standard value within the chip manufacturing unit, the chip under test is determined to be a defective product.

[0006] In one embodiment, the above chip high voltage pressure test determination method further includes the steps of: When the chip under test does not show a difference that deviates from the statistical standard value within the chip manufacturing unit, the chip under test is determined to be a good product.

[0007] In one of the embodiments, in the process of determining whether the difference deviates from the statistical standard value, the chip under test is determined to be defective when the deviation from the statistical standard value reaches 3σ or more; σ represents the standard deviation.

[0008] On the other hand, a chip high voltage pressurization test determination device is also provided, comprising: The pre-test current module is used to obtain the current value measured by the chip manufacturing unit when performing an IDDQ test on the chip under test before the HVS test. A condition calculation module is used to calculate the HVS test voltage and test time used by the chip under test in the HVS test using an oxide layer breakdown time model according to the early failure period of the chip under test; A test execution module, used for performing HVS test on the chip under test according to HVS test voltage and test time; The post-test current module is used to obtain the current value measured by the chip manufacturing unit during the IDDQ test of the chip under test after the HVS test; The difference statistics module is used to perform difference statistics on the current values ​​measured by the IDDQ tests twice before and after the HVS test in the chip manufacturing unit; The result determination module is used to determine that the chip under test is a defective product when the chip under test shows a difference value deviating from the statistical standard value in the chip manufacturing unit.

[0009] In one of the embodiments, the result determination module is further configured to determine that the chip under test is a good product when the chip under test does not show a difference value deviating from a statistical standard value in a chip manufacturing unit.

[0010] In one embodiment, in the process of determining whether the difference deviates from the statistical standard value, the result determination module determines that the chip under test is defective when the deviation from the statistical standard value reaches 3σ or more; σ represents the standard deviation.

[0011] One of the above technical solutions has the following advantages and beneficial effects: The above-mentioned chip high voltage pressure test judgment method and device, by introducing the oxide layer breakdown time model, accurately calculates the test conditions based on the mathematical model, and uses the quantitative analysis of the oxide layer thickness consumption and voltage factor to ensure that the test conditions meet the accelerated failure while significantly reducing the redundancy of the test and improving the test efficiency. Compared with traditional test methods that rely more on experience or subjective judgment, the screening accuracy of defective chips after HVS testing is low. This solution adopts the statistical analysis method of the two current differences of the IDDQ test, and uses the deviation from the statistical standard value (such as the deviation from the value above 2σ) as the judgment basis to ensure the objectivity and repeatability of the judgment process. Through this standardized process, the false judgment rate and missed judgment rate are effectively reduced, thereby improving the consistency and reliability of product quality.

[0012] The traditional HVS test process leads to a waste of test time and equipment resources due to unreasonable condition settings. This solution avoids excessive testing and waste of resources by optimizing the calculation of test voltage and duration. In addition, the statistical-based qualification judgment method further simplifies the data analysis process and reduces reliance on manual intervention, thereby reducing testing and production costs. By optimizing the HVS test conditions, early failure problems related to the chip oxide layer can be fully exposed in the production stage. Combined with the standardized qualification judgment process, the failure rate of the chip during the user use stage is effectively reduced, especially the screening of oxide layer defects is more accurate, significantly enhancing the reliability and service life of the chip. This solution only needs to be executed according to the process in the existing test to complete the determination of the test conditions and the qualification judgment. Its testing method is simple and applicable, and can be widely used in the production test process of various chips. BRIEF DESCRIPTION OF THE DRAWINGS In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A schematic diagram of a process flow of a chip high voltage pressurization test determination method in one embodiment; Figure 2 A schematic diagram of a bathtub curve in one embodiment; Figure 3 A schematic flow chart of a chip high voltage pressurization test determination method in another embodiment; Figure 4 The module framework diagram of a chip high voltage pressurization test determination device in one embodiment. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0015] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification and appended claims of the present invention refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0016] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0017] In one embodiment, Figure 1 As shown, a chip high voltage pressure test determination method is provided, which may include the following steps S10 to S20: S10, obtaining a current value measured by a chip manufacturing unit during an IDDQ test of the chip under test before the HVS test; S12, according to the early failure period of the chip under test, using the oxide layer breakdown time model to calculate the HVS test voltage and test time used by the chip under test in the HVS test; S14, performing HVS test on the chip under test according to the HVS test voltage and test time; S16, obtaining a current value measured by a chip manufacturing unit performing an IDDQ test on the chip under test after the chip under test is subjected to an HVS test; S18, performing difference statistics on current values ​​measured by two IDDQ tests before and after the HVS test in the chip manufacturing unit; S20, when the chip under test shows a difference value that deviates from the statistical standard value in the chip manufacturing unit, the chip under test is determined to be a defective product.

[0018] It can be understood that the first step is to clarify the test conditions (test time and test voltage) of the HVS test. First, we need to understand the following oxide layer breakdown time model. The time it takes for the current to break through the oxide layer in the chip is related to the voltage and the thickness of the oxide layer. The time it takes for the oxide layer to break through (denoted as ) can be described by the following oxide breakdown time model:

[0019] in is the oxide breakdown time (in seconds), is the oxide layer thickness (in nm), is the applied voltage (in V), is a temperature-dependent coefficient, and G is also a temperature-dependent coefficient. Usually, G=350 MV / cm and = 10 ps (picoseconds). In the above oxide breakdown time model, the optimum temperature range is 25°C - 125°C.

[0020] In the second step, the problem caused by the oxide layer in the chip usually occurs in the early use stage of the product (i.e., the early failure period). The early failure period of the integrated circuit in the chip is about 6 months. For the convenience of discussion and for safety considerations, this embodiment assumes that this early failure period is 1 year (the calculation under other early failure periods is the same). Figure 2 As shown in the figure, the purpose of HVS test is to force early failure to be exposed in the production stage through stress testing, so as to reduce the failure rate of products during use. Among them, the A1 interval is the early failure period, the A2 interval is the accidental failure period, and the A3 interval is the loss failure period.

[0021] Substituting the time of 1 year and the voltage of the chip under normal working conditions into the oxide layer breakdown time model in the first step, the oxide layer thickness consumed by the chip during the early failure period can be calculated. The voltage used in the HVS test needs to be higher than the voltage of the chip under normal working conditions, which is usually 0.6 times the oxide layer thickness (in nm) in the chip (i.e., HVS test voltage (V) = oxide layer thickness (nm) x 0.6 (V / nm)). Substituting the oxide layer thickness consumed during the early failure period and the HVS test voltage used in the HVS test into the oxide layer breakdown time model again, the time for which the HVS test voltage needs to be applied to the chip can be calculated.

[0022] The third step is to determine whether the chip has passed the HVS test. The chip needs to be tested for IDDQ before and after the HVS test. The difference between the current values ​​measured by the two IDDQ tests is statistically analyzed within the chip manufacturing unit (such as a group or wafer unit). Chips that show a difference that deviates from the statistical standard value (such as but not limited to a deviation of σ or a value greater than 2σ) within the manufacturing unit are judged as defective.

[0023] Among them, IDDQ test is a test method for CMOS integrated circuits, which is used to detect physical defects in the circuit, such as bridging, open and short circuits, etc. The test principle is: when the CMOS circuit is static, the leakage current is normally very small, and the total power supply current IDDQ is in the microampere level. However, when the circuit has a fault such as bridging or gate-source short circuit, a low-resistance path from the positive power supply VDD to the ground (VSS) will be formed in the static CMOS circuit, causing the total power supply current IDDQ to increase significantly and exceed the milliampere level. By detecting whether the current IDDQ obtained from the power supply when the CMOS circuit is static has a significant change, the collected static power supply current is compared with the preset fault limit. If it exceeds the limit, it can be judged as a faulty chip. The test methods can be: (1) On-chip test: Design an on-chip current sensor inside the chip, connect it in series between the power supply and the circuit under test or between the circuit under test and the ground, process the power supply current flowing through the circuit under test, and output a signal (such as pass / fail) to indicate whether the circuit under test is defective. It is usually combined with built-in self-test. (2) Off-chip testing: Design an additional circuit off-chip, use series resistors for sampling and amplification, realize current-to-voltage conversion, and then measure and analyze through related equipment. External testing needs to be controlled with the help of ATE (automatic test equipment). Bypass capacitors are usually added at the power supply end to suppress the large switching current of CMOS and the inrush current caused by the package. Because the inrush current may overwhelm the static current, the current test must be performed after the transient process is completed.

[0024] The IDDQ test steps can be as follows: Generate a specific IDDQ vector using the ATPG (Automatic Test Pattern Generation) tool. Perform a vector test and apply the test vector to the input of the circuit under test; wait for the transient process to disappear, when the circuit reaches a stable state, and then measure the power supply current IDDQ; repeat the above steps to complete the application and measurement of all test vectors to cover various possible states of the circuit; compare the read static current with the set threshold to determine whether the circuit under test passes the test.

[0025] "σ" is the symbol for standard deviation in statistics. Standard deviation is the square root of variance, which describes the dispersion of data around the mean. The larger its value, the more dispersed the data is; the smaller its value, the more concentrated the data is around the mean. 2σ refers to the range of three standard deviations from the mean. In a normal distribution, the probability that the data falls within one standard deviation (μ±σ) around the mean is about 68.27%; the probability that it falls within two standard deviations (μ±2σ) around the mean is about 95.45%; and the probability that it falls within three standard deviations (μ±3σ) around the mean is about 99.73%. This means that only about 0.27% of the data will fall outside this range.

[0026] In chip manufacturing units, a large number of measurements and statistical analyses are performed on various chip performance indicators (such as current, voltage, and frequency) to obtain the mean and standard deviation of these indicators. When the performance indicators of a chip show a deviation of more than 2σ from the statistical standard value, it means that the performance indicators of the chip are in a low probability area in the normal distribution. In many production processes, the distribution of data often approximates normal distribution (also called Gaussian distribution). Normal distribution is a common continuous probability distribution whose probability density function presents a bell-shaped curve shape with the following characteristics: the curve is symmetrical about the mean (μ), that is, the distribution of data on both sides of the mean is symmetrical; most of the data is concentrated near the mean, and the farther away from the mean, the smaller the probability of the data appearing. Normal distribution can be fully determined by two parameters: mean (μ) and standard deviation (σ). The mean indicates the center position of the data, while the standard deviation measures the degree of dispersion of the data relative to the mean.

[0027] The above-mentioned chip high voltage pressure test judgment method, by introducing the oxide layer breakdown time model, accurately calculates the test conditions based on the mathematical model, and uses the quantitative analysis of the oxide layer thickness consumption and voltage factor to ensure that the test conditions meet the accelerated failure while significantly reducing the redundancy of the test and improving the test efficiency. Compared with traditional test methods that rely more on experience or subjective judgment, the screening accuracy of defective chips after HVS testing is low. This solution adopts the statistical analysis method of the two current differences of the IDDQ test, and uses the deviation from the statistical standard value (such as the deviation from the value above 2σ) as the judgment basis to ensure the objectivity and repeatability of the judgment process. Through this standardized process, the false judgment rate and missed judgment rate are effectively reduced, thereby improving the consistency and reliability of product quality.

[0028] The traditional HVS test process leads to a waste of test time and equipment resources due to unreasonable condition settings. This solution avoids excessive testing and waste of resources by optimizing the calculation of test voltage and duration. In addition, the statistical-based qualification judgment method further simplifies the data analysis process, reduces reliance on manual intervention, and thus reduces testing and production costs. By optimizing the HVS test conditions, early failure problems related to the chip oxide layer can be fully exposed in the production stage. Combined with the standardized qualification judgment process, the failure rate of the chip during the user use stage is effectively reduced, especially the screening of oxide layer defects is more accurate, significantly enhancing the reliability and service life of the chip. This solution only needs to be executed according to the process in the existing test to complete the determination of test conditions and qualification judgment. Its test method is simple and applicable, and can be widely used in the production test process of various chips.

[0029] In one embodiment, Figure 3 As shown, the above chip high voltage pressure test determination method may further include the steps of: S19, when the chip under test does not show a difference that deviates from the statistical standard value within the chip manufacturing unit, the chip under test is determined to be a good product.

[0030] It can be understood that in the process of judging whether the difference deviates from the statistical standard value, if the chip under test does not show a difference that deviates from the statistical standard value (for example, a value that deviates by more than 2σ) within the chip manufacturing unit, then the chip under test can be basically accurately judged as a good product.

[0031] In one embodiment, in the process of determining whether the difference deviates from the statistical standard value, the chip under test is determined to be defective when the deviation from the statistical standard value reaches 3σ or more; σ represents the standard deviation.

[0032] It is understandable that in the field of chip manufacturing and many other fields, 3σ is a concept proposed based on the principle of statistical normal distribution, which is used to measure the degree of data dispersion and set the limits of quality control. When the performance indicators of a chip show a deviation of more than 3σ from the statistical standard value, it means that the performance indicators of the chip are in an extremely low probability area in the normal distribution (only 0.27%), which is very likely caused by defects or abnormalities in the manufacturing process. Therefore, judging such tested chips as defective products can more effectively screen out products that may have quality problems, thereby further improving the overall quality and reliability of the products.

[0033] It should be understood that although Figure 1 and Figure 3The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 1 and Figure 3 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0034] In one embodiment, Figure 4 As shown, a chip high voltage pressurization test determination device 100 is provided, which may include a pre-test current module 11, a condition calculation module 13, a test execution module 15, a post-test current module 17, a difference statistics module 19 and a result determination module 21. Among them, the pre-test current module 11 is used to obtain the current value measured by the chip manufacturing unit for the IDDQ test of the tested chip before the HVS test. The condition calculation module 13 is used to calculate the HVS test voltage and test time used by the tested chip in the HVS test according to the early failure period of the tested chip using the oxide layer breakdown time model. The test execution module 15 is used to perform HVS test on the tested chip according to the HVS test voltage and test time. The post-test current module 17 is used to obtain the current value measured by the chip manufacturing unit for the IDDQ test of the tested chip after the HVS test. The difference statistics module 19 is used to perform difference statistics on the current values ​​measured by the IDDQ tests twice before and after the HVS test in the chip manufacturing unit. The result determination module 21 is used to determine that the chip under test is a defective product when the chip under test shows a difference value deviating from a statistical standard value in the chip manufacturing unit.

[0035] The above-mentioned chip high voltage pressure test judgment device 100, by introducing the oxide layer breakdown time model, accurately calculates the test conditions based on the mathematical model, and uses the quantitative analysis of the oxide layer thickness consumption and voltage factor to ensure that the test conditions meet the accelerated failure while significantly reducing the redundancy of the test and improving the test efficiency. Compared with traditional test methods that rely more on experience or subjective judgment, the screening accuracy of defective chips after HVS testing is low. This solution adopts the statistical analysis method of the two current differences of the IDDQ test, and uses the deviation from the statistical standard value (such as the deviation from the value above 2σ) as the judgment basis to ensure the objectivity and repeatability of the judgment process. Through this standardized process, the false judgment rate and missed judgment rate are effectively reduced, thereby improving the consistency and reliability of product quality.

[0036] The traditional HVS test process leads to a waste of test time and equipment resources due to unreasonable condition settings. This solution avoids excessive testing and waste of resources by optimizing the calculation of test voltage and duration. In addition, the statistical-based qualification judgment method further simplifies the data analysis process, reduces reliance on manual intervention, and thus reduces testing and production costs. By optimizing the HVS test conditions, early failure problems related to the chip oxide layer can be fully exposed in the production stage. Combined with the standardized qualification judgment process, the failure rate of the chip during the user use stage is effectively reduced, especially the screening of oxide layer defects is more accurate, significantly enhancing the reliability and service life of the chip. This solution only needs to be executed according to the process in the existing test to complete the determination of test conditions and qualification judgment. Its test method is simple and applicable, and can be widely used in the production test process of various chips.

[0037] In one embodiment, the result determination module 21 may also be used to determine that the chip under test is a good product when the chip under test does not show a difference value deviating from a statistical standard value within a chip manufacturing unit.

[0038] In one embodiment, in the process of determining whether the difference deviates from the statistical standard value, the result determination module 21 may also determine that the chip under test is defective when the deviation from the statistical standard value reaches 3σ or more; σ represents the standard deviation.

[0039] It can be understood that the explanation of each feature in the above-mentioned chip high voltage pressure test determination device 100 can be understood in the same way as the corresponding explanation in each embodiment of the above-mentioned chip high voltage pressure test determination method. Each module in the above-mentioned chip high voltage pressure test determination device 100 can be fully or partially implemented by software, hardware and a combination thereof. The above-mentioned components can be embedded in or independent of a device with data processing functions in the form of hardware, or can be stored in the memory of the aforementioned device in the form of software, so that the processor can call and execute the operations corresponding to the above modules. The aforementioned device can be but not limited to various types of chip test computers already available in the art.

[0040] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0041] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0042] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A chip high voltage pressure test determination method, characterized in that: Includes steps: Obtaining a current value measured by a chip manufacturing unit performing an IDDQ test on the chip under test before the HVS test; According to the early failure period of the chip under test, the HVS test voltage and test time used by the chip under test in the HVS test are calculated using an oxide layer breakdown time model; Performing HVS test on the chip under test according to the HVS test voltage and test time; Obtaining a current value measured by the chip manufacturing unit performing an IDDQ test on the chip under test after the chip under test performs the HVS test; In the chip manufacturing unit, performing difference statistics on current values ​​measured by two IDDQ tests before and after the HVS test; When the chip under test shows a difference value deviating from a statistical standard value in the chip manufacturing unit, the chip under test is determined to be a defective product.

2. The chip high voltage pressure test determination method according to claim 1, characterized in that: Also includes the steps: When the chip under test does not show a difference that deviates from a statistical standard value in the chip manufacturing unit, the chip under test is determined to be a good product.

3. The chip high voltage pressurization test determination method according to claim 1 or 2, characterized in that: In the process of determining whether the difference deviates from the statistical standard value, when the deviation from the statistical standard value reaches 3σ or more, the chip under test is determined to be a defective product; σ represents the standard deviation.

4. A chip high voltage pressure test determination device, characterized in that: include: A pre-test current module is used to obtain the current value measured by the chip manufacturing unit when the chip under test performs an IDDQ test on the chip under test before the HVS test; A condition calculation module, used to calculate the HVS test voltage and test time used by the chip under test in the HVS test using an oxide layer breakdown time model according to the early failure period of the chip under test; A test execution module, used for performing HVS test on the chip under test according to the HVS test voltage and test time; A post-test current module, used for obtaining a current value measured by the chip manufacturing unit performing an IDDQ test on the chip under test after the chip under test is subjected to the HVS test; A difference statistics module, used for performing difference statistics on current values ​​measured by two IDDQ tests before and after the HVS test in the chip manufacturing unit; The result determination module is used to determine that the chip under test is a defective product when the chip under test shows a difference value deviating from a statistical standard value in the chip manufacturing unit.

5. The chip high voltage pressurization test determination device according to claim 4, characterized in that: The result determination module is further configured to determine that the chip under test is a good product when the chip under test does not show a difference value deviating from a statistical standard value in the chip manufacturing unit.

6. The chip high voltage pressurization test determination device according to claim 4 or 5, characterized in that: In the process of judging whether the difference deviates from the statistical standard value, the result judging module judges the chip under test as defective when the deviation from the statistical standard value reaches 3σ or more; σ represents the standard deviation.

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