Stt-mram memory bit, memory device, and write and read methods thereof

Abstract

This invention relates to the field of magnetic storage technology, and in particular to an STT-MRAM storage bit, a storage device, and a method for writing and reading the same. The STT-MRAM storage bit comprises, from bottom to top, a first reference layer, a barrier layer, a free layer, a spacer layer, a second reference layer, and a heavy metal layer. The first reference layer, barrier layer, and free layer form a tunnel junction, which generates tunneling resistance. The larger the tunneling resistance ratio, the larger the read window of the storage bit. Furthermore, the magnetic anisotropy of the free layer determines the thermal stability of the storage bit, i.e., the non-volatile data retention characteristic. The spacer layer, second reference layer, and heavy metal layer form a spin current control layer. By controlling the relative direction of the magnetization of the first and second reference layers, the spin polarization current can be enhanced or weakened, thereby changing the critical write current of the storage bit.

Description

Technical Field

[0001] This invention relates to the field of magnetic storage technology, and in particular to an STT-MRAM storage bit, a storage device, and methods for writing and reading the same. Background Technology

[0002] With the rapid development of information technology, memory, as a core component of information processing systems, plays a crucial role in the overall system's operational efficiency and stability through its performance and reliability. In recent years, magnetoresistive random access memory (MRAM), as a novel type of non-volatile memory, has attracted widespread attention from the international academic and industrial communities due to its unique advantages, such as high compatibility with 28nm and below CMOS logic processes, fast access speed, high reliability, and low power consumption. In particular, spin-transfer torque magnetoresistive random access memory (STT-MRAM), as an important type of MRAM, has become the preferred solution to replace embedded flash memory (eFlash) with processes below 22nm.

[0003] STT-MRAM utilizes the spin-transfer torque effect to write data, and its core storage cell—the magnetic tunnel junction (MTJ)—determines its working mechanism. The MTJ consists of two magnetic layers (a free layer and a reference layer) and an insulating layer. Switching between high and low resistance states is achieved by controlling the flipping of the magnetization of the free layer, thus representing binary data "0" and "1". However, STT-MRAM faces a series of challenges in practical applications.

[0004] First, because STT-MRAM shares the same current loop for data writing and reading, frequent write operations can gradually degrade the oxide layer performance in the memory bits, and may even cause breakdown due to excessive current, severely affecting the durability of STT-MRAM. To address this issue, researchers have focused on reducing the critical write current by optimizing the device materials and structure of MTJs, thereby mitigating damage to the oxide layer. However, this strategy introduces new problems: reducing the critical write current increases the bit error rate during readout, because small current differences may make it difficult to accurately distinguish between high and low impedance states.

[0005] Furthermore, the critical write current density of a microlayer junction device (MTJ) is closely related to its material properties (such as the magnetic anisotropy of the free layer, saturation magnetic moment, damping coefficient, and spin polarizability) and size. Once the material of the MTJ is selected, its critical write current mainly depends on the volume of the MTJ; therefore, reducing the size of the MTJ becomes the primary means of lowering the critical write current. However, these material parameters cannot be dynamically adjusted after device fabrication, limiting the possibility of flexibly controlling the critical write current through external means.

[0006] In summary, STT-MRAM must balance endurance and bit error rate while pursuing low write power consumption. How to achieve highly reliable reading with extremely low write power consumption without sacrificing endurance and bit error rate has become a critical issue that urgently needs to be addressed in the current development of STT-MRAM technology.

[0007] In view of this, the present invention is proposed. Summary of the Invention

[0008] The purpose of this invention is to provide an STT-MRAM storage bit, a storage device, and a method for writing and reading the same, which can simultaneously achieve extremely low power writing and high reliability reading, and increase the durability of the storage bit writing process.

[0009] In a first aspect, the present invention provides an STT-MRAM memory bit, comprising, from bottom to top, a first reference layer, a barrier layer, a free layer, a spacer layer, a second reference layer, and a heavy metal layer. By controlling the relative direction of the magnetization intensities of the first reference layer and the second reference layer, the spin polarization current can be enhanced or weakened, thereby changing the critical write current of the memory bit.

[0010] The storage bits of this invention, combined with external control circuitry, can achieve dynamic switching between critical write current and read operations, thereby enabling both extremely low-power writing and high-reliability reading within the chip simultaneously, and increasing the chip's durability during the writing process. This solves the problem that traditional STT-MRAM storage bits struggle to simultaneously achieve both extremely low-power writing and high-reliability reading.

[0011] As a preferred embodiment of this technical solution, it further includes a substrate, a bottom metal electrode, a pinning layer, and a protective layer. The substrate, the bottom metal electrode, and the pinning layer are disposed sequentially from bottom to top below the first reference layer, and the protective layer is disposed above the heavy metal layer.

[0012] Specifically, the STT-MRAM memory bit of the present invention includes, from bottom to top, a substrate, a bottom metal electrode, a pinned layer, a first reference layer, a barrier layer, a free layer, a spacer layer, a second reference layer, a heavy metal layer, and a protective layer. The first reference layer, the barrier layer, and the free layer form a tunnel junction (MTJ), which can generate tunneling resistance. The larger the tunneling resistance ratio, the larger the read window of the memory bit. In addition, the magnetic anisotropy intensity of the free layer determines the thermal stability of the memory bit, i.e., the non-volatile data retention characteristic. The spacer layer, the second reference layer, and the heavy metal layer form a spin current control layer. By controlling the relative direction of the magnetization intensity of the first reference layer and the second reference layer, the spin polarization current can be enhanced or weakened, thereby changing the critical write current of the memory bit.

[0013] In a preferred embodiment of this technical solution, the first reference layer, the free layer, and the second reference layer are all ferromagnetic alloys with in-plane magnetic anisotropy, and the thickness of the second reference layer is greater than the thickness of the first reference layer.

[0014] More preferably, the first reference layer, the free layer, and the second reference layer are all CoFeB ferromagnetic alloys with in-plane magnetic anisotropy, and their thicknesses are all arbitrary values ​​between 1.5nm and 3nm. However, the thickness of the second reference layer is greater than that of the first reference layer, so that the second reference layer has stronger in-plane magnetic anisotropy.

[0015] During write operations, the magnetization direction of the second reference layer needs to be configured antiparallel to the first reference layer to achieve extremely low-power data writing. A thicker second reference layer can more stably maintain its magnetization direction, thereby ensuring the accuracy and reliability of the write operation. During read operations, the magnetization direction of the second reference layer is configured parallel to the first reference layer to increase the critical write current and reduce the probability of false writes. A thicker second reference layer also helps to achieve this goal because it is more effective at resisting external interference and maintaining the stability of the magnetization direction.

[0016] In addition, the stability and performance of the second reference layer also make an important contribution to the thermal stability of the storage bit. By increasing the thickness of the second reference layer, the data retention capability of the storage bit in high-temperature environments can be further improved.

[0017] As a preferred embodiment of this technical solution, the barrier layer is a metal oxide with a body-centered cubic lattice structure, so as to effectively generate tunneling resistance in the MTJ.

[0018] More preferably, the barrier layer is MgO with a body-centered cubic lattice structure, and its thickness is any value between 1 nm and 2 nm.

[0019] As a preferred embodiment of this technical solution, the spacer layer is a non-magnetic metallic element with a large spin diffusion length, in order to meet the functional requirements of the spin flow control layer.

[0020] More preferably, the spacer layer is elemental Cu, and its thickness is any value between 1 nm and 3 nm.

[0021] As a preferred embodiment of this technical solution, the heavy metal layer is a metallic material with a large spin Hall angle, so as to endow the heavy metal layer with the key characteristic of spin flow control.

[0022] More preferably, the material of the heavy metal layer includes any one of metal W, Ta / W alloy and topological insulator, and its thickness is any value between 3nm and 5nm. The present invention does not strictly limit it.

[0023] As a preferred embodiment of this technical solution, the pinning layer is an antimagnetic alloy with in-plane magnetic anisotropy, such as IrMn alloy, and its thickness is any value between 15nm and 20nm.

[0024] The protective layer is a conductive material with antioxidant properties, such as TiN and TaN.

[0025] As a preferred embodiment of this technical solution, the bottom metal electrode is generally made of 20nm Ta or Ru, which has relatively low resistivity and can serve as a transition material for lattice matching between the substrate and the magnetic layer.

[0026] In a preferred embodiment of this technical solution, the pinning layer, the first reference layer, the barrier layer, the free layer, the spacer layer, and the second reference layer are arranged in an elliptical cylindrical structure. The bottom metal electrode and the heavy metal layer are arranged perpendicularly to each other. The collinear current of the heavy metal layer and the short axis of the elliptical cylindrical structure is used to control the direction of the magnetization intensity of the second reference layer.

[0027] In a preferred embodiment of this technical solution, one end of the heavy metal layer is connected to a first transistor, the other end is connected to a third transistor, and the bottom metal electrode is connected to a second transistor.

[0028] When the first and second transistors are turned on and the third transistor is turned off, data can be written and read; when the second transistor is turned off and the first and third transistors are turned on, the magnetization of the second reference layer can be initialized.

[0029] Secondly, the present invention also provides a method for writing and reading the above-mentioned STT-MRAM storage bits. Specifically, by utilizing the spin orbital moment effect, a bipolar current is dynamically provided in the heavy metal layer through an external circuit to dynamically adjust the critical flip current of the storage bit.

[0030] When performing a write operation, extremely low-power data writing is achieved by configuring the magnetization direction of the second reference layer to be antiparallel to the first reference layer.

[0031] When performing a read operation, the probability of erroneous writes during the read operation is reduced by configuring the magnetization direction of the second reference layer to be parallel to that of the first reference layer.

[0032] Thirdly, the present invention also provides a storage device including the above-mentioned STT-MRAM storage bits, which should also fall within the protection scope of the present invention.

[0033] The STT-MRAM storage bits of the present invention have at least the following beneficial effects:

[0034] The STT-MRAM memory bit of this invention comprises, from bottom to top, a first reference layer, a barrier layer, a free layer, a spacer layer, a second reference layer, and a heavy metal layer. The first reference layer, barrier layer, and free layer form a tunnel junction, which generates tunneling resistance. A higher tunneling resistance ratio results in a larger read window for the memory bit. Furthermore, the magnetic anisotropy of the free layer determines the thermal stability of the memory bit, i.e., its non-volatile data retention characteristic. The spacer layer, second reference layer, and heavy metal layer form a spin current control layer. By controlling the relative direction of the magnetization of the first and second reference layers, the spin polarization current can be enhanced or weakened, thereby changing the critical write current of the memory bit. For example, during a write operation, by pre-configuring the magnetization direction of the second reference layer to be antiparallel to the first reference layer using external circuitry, extremely low-power data writing can be achieved. During a read operation, by configuring the magnetization direction of the second reference layer to be parallel to the first reference layer using external circuitry, the critical write current is increased, thus greatly reducing the probability of erroneous writes during reading. Attached Figure Description

[0035] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the structure of the STT-MRAM storage bit of the present invention;

[0037] Figure 2 This is a schematic diagram illustrating the working principle of the STT-MRAM storage bits of the present invention. Figure 1 ;

[0038] Figure 3 This is a schematic diagram illustrating the working principle of the STT-MRAM storage bits of the present invention. Figure 2 ;

[0039] Figure 4 This is a schematic diagram illustrating the working principle of the STT-MRAM storage bits of the present invention. Figure 3 ;

[0040] Figure 5 This is a schematic diagram illustrating the working principle of the STT-MRAM storage bits of the present invention. Figure 4 ;

[0041] Figure 6 This is a three-dimensional structural diagram of the STT-MRAM storage bit of the present invention;

[0042] Figure 7 This is a schematic diagram of the integrated structure of the STT-MRAM storage bits of the present invention. Detailed Implementation

[0043] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0045] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Furthermore, the terms "installed," "connected," and "linked" should be interpreted broadly; for example, they may refer to a fixed connection, a detachable connection, or an integral connection; they may refer to a mechanical connection or an electrical connection; they may refer to a direct connection or an indirect connection through an intermediate medium; and they may refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0046] Example 1

[0047] like Figure 1-2As shown, this embodiment provides an STT-MRAM memory bit, comprising, from bottom to top, a first reference layer, a barrier layer, a free layer, a spacer layer, a second reference layer, and a heavy metal layer. The first reference layer, barrier layer, and free layer form a tunnel junction, which generates tunneling resistance. The larger the tunneling resistance ratio, the larger the read window of the memory bit. In addition, the magnetic anisotropy of the free layer determines the thermal stability of the memory bit, i.e., the non-volatile data retention characteristic. The spacer layer, second reference layer, and heavy metal layer form a spin current control layer. By controlling the relative direction of the magnetization of the first reference layer and the second reference layer, the spin polarization current can be enhanced or weakened, thereby changing the critical write current of the memory bit.

[0048] Specifically, such as Figure 3-4 As shown, the relative directions of the magnetization in the first and second reference layers are different (the direction of the arrow indicates the direction of the magnetization in the magnetic layer). It is assumed that the electrons move from the substrate to the protective layer. After passing through the first reference layer, the electron's spin direction is polarized to the same direction as the magnetization in the first reference layer. When it enters the free layer, the spin-transfer torque effect induces the magnetization in the free layer to flip to the direction of the electron's spin polarization.

[0049] for Figure 3 When current passes through the spacer layer into the second reference layer, electrons with spin directions opposite to the magnetization of the second reference layer are reflected back, pass through the spacer layer again, and enter the free layer. In this free layer, the effective spin polarization of the electrons weakens, thus increasing the critical flip current; conversely, for Figure 4 The critical reversal current decreases.

[0050] It can be seen that the relative direction of the magnetization of the first reference layer and the second reference layer determines the magnitude of the critical reversal current. Therefore, if the direction of the magnetization of the second reference layer can be dynamically adjusted, the critical reversal current can be dynamically adjusted.

[0051] like Figure 5 As shown, this invention utilizes the spin-orbit moment effect to control the magnetization of the second reference layer. It is known that the magnetization of the second reference layer is in-plane. When a current is passed vertically inward or outward through the heavy metal layer, spin-polarized electrons accumulate at the interface between the second reference layer and the heavy metal layer. When a current is passed vertically inward through the heavy metal, the spin polarization direction of the accumulated electrons at the interface is horizontally to the left; when a current is passed vertically outward through the heavy metal, the spin polarization direction of the accumulated electrons at the interface is horizontally to the right. When the spin-polarized electrons accumulate to a certain extent, they can induce the magnetization of the second reference layer to flip in the corresponding direction.

[0052] Therefore, by utilizing the spin-orbit moment effect, a properly designed external circuit can dynamically provide bipolar current in the heavy metal layer, thereby dynamically adjusting the critical flip current of the memory bit. For example, during a write operation, by pre-configuring the magnetization direction of the second reference layer to be antiparallel to the first reference layer, extremely low-power data writing can be achieved; during a read operation, configuring the magnetization direction of the second reference layer to be parallel to the first reference layer increases the critical write current, thus greatly reducing the probability of erroneous writes during reading.

[0053] Example 2

[0054] This embodiment provides an STT-MRAM storage bit, which includes, from bottom to top, a substrate, a bottom metal electrode, a pinned layer, a first reference layer, a barrier layer, a free layer, a spacer layer, a second reference layer, a heavy metal layer, and a protective layer.

[0055] Among them, the bottom metal electrode is generally made of 20nm Ta or Ru, which has relatively low resistivity and can serve as a transition material for lattice matching between the substrate and the magnetic layer.

[0056] The pinning layer is an antimagnetic alloy with in-plane magnetic anisotropy, such as IrMn alloy, with a thickness of any value between 15nm and 20nm;

[0057] The first reference layer is a CoFeB ferromagnetic alloy with in-plane magnetic anisotropy and a thickness of any value between 1.5 nm and 3 nm.

[0058] Besides CoFeB ferromagnetic alloys, FeGa alloys have the characteristics of large saturation magnetostriction coefficient, small coercivity, low saturation magnetic field, fast response speed, high Curie temperature and excellent mechanical properties, and can also be used as important candidate materials for ferromagnetic phases in magnetoelectric coupling thin films.

[0059] Besides CoFeB and FeGa, NiFe (Permalloy) also has good magnetic properties and in-plane magnetic anisotropy, and can also be used as a material for the first reference layer.

[0060] The barrier layer is a metal oxide with a body-centered cubic lattice structure, such as MgO with a body-centered cubic lattice structure, and its thickness is any value between 1 nm and 2 nm.

[0061] Besides MgO, other metal oxides such as aluminum oxide (Al₂O₃) or barium oxide (BaO) may also possess properties suitable for MTJ barrier layers. However, the specific applicability of these materials depends on their crystal structure, electronic properties, and compatibility with adjacent magnetic layers.

[0062] Besides metal oxides, other types of crystalline materials, such as certain nitrides or carbides, can be considered as barrier layers. These materials may have similar crystal structures and electronic properties to MgO, but further research and verification are needed to determine their applicability.

[0063] The free layer is a CoFeB ferromagnetic alloy with in-plane magnetic anisotropy and a thickness of any value between 1.5 nm and 3 nm.

[0064] Similarly, in addition to CoFeB ferromagnetic alloys, FeGa and NiFe, which have good magnetic properties and in-plane magnetic anisotropy, can also be selected.

[0065] The spacer layer is a non-magnetic metallic element with a long spin diffusion length, such as Cu, with a thickness of any value between 1 nm and 3 nm.

[0066] Besides Cu, other metallic elements such as Ag (silver) and Au (gold) may also have properties suitable for spacer layers. These metals usually have good electrical conductivity and spin diffusion properties, but their specific applicability depends on their electronic structure and compatibility with adjacent layers.

[0067] In addition, certain alloy materials, especially those with low magnetic properties and high spin diffusion lengths, may also be suitable as spacer layers, but these alloys may require special processing and optimization to meet the performance requirements of STT-MRAM.

[0068] The second reference layer is a CoFeB ferromagnetic alloy with in-plane magnetic anisotropy and a thickness of any value between 1.5 nm and 3 nm.

[0069] Similarly, in addition to CoFeB ferromagnetic alloys, FeGa and NiFe, which have good magnetic properties and in-plane magnetic anisotropy, can also be selected.

[0070] The heavy metal layer is a metallic material with a large spin Hall angle, such as any one of metal W, Ta / W alloy and topological insulator, and its thickness is any value between 3nm and 5nm. This invention does not strictly limit it.

[0071] Besides W and Ta, other heavy metals such as Pt (platinum) and Pd (palladium) also have large spin Hall angles. These materials have wide applications in the field of spintronics and may be suitable for heavy metal layers in STT-MRAM.

[0072] In addition, certain heavy metal alloys, such as PtAu and PtPd, can have their spin Hall angle and other related properties further optimized through alloying effects. These alloy materials may have superior performance compared to single heavy metals.

[0073] The protective layer is made of conductive materials with oxidation resistance, such as TiN and TaN;

[0074] The second reference layer is thicker than the first reference layer to give it stronger in-plane magnetic anisotropy. This enhances the in-plane magnetic anisotropy of the second reference layer, optimizes write and read operations, and improves the thermal stability of the memory bits, thereby improving the overall performance and reliability of the STT-MRAM memory bits.

[0075] Example 3

[0076] This embodiment provides a method for preparing the above-mentioned STT-MRAM storage bits, including the following steps:

[0077] Substrate preparation: Select a suitable substrate material and perform necessary cleaning and pretreatment to ensure that its surface is clean and suitable for subsequent film growth;

[0078] Bottom metal electrode deposition: Using methods such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), a 20 nm thick layer of Ta or Ru is deposited on the substrate as a bottom metal electrode. This bottom metal electrode not only has low resistivity, but can also serve as a transition material for lattice matching between the substrate and the magnetic layer.

[0079] Pinning layer preparation: A layer of antimagnetic alloy with in-plane magnetic anisotropy, such as IrMn alloy, is deposited on the bottom metal electrode with an arbitrary thickness between 15nm and 20nm to fix the magnetization direction of adjacent magnetic layers.

[0080] Preparation of the first reference layer: A CoFeB ferromagnetic alloy with in-plane magnetic anisotropy is deposited on the pinned layer, with a thickness of any value between 1.5 nm and 3 nm;

[0081] Barrier layer preparation: Deposit a metal oxide, such as MgO, with a body-centered cubic lattice structure on the first reference layer, with a thickness of any value between 1 nm and 2 nm;

[0082] Free layer preparation: A CoFeB ferromagnetic alloy with in-plane magnetic anisotropy is deposited on the barrier layer, with a thickness of any value between 1.5 nm and 3 nm;

[0083] Spacer layer preparation: Deposit a non-magnetic metallic element with a long spin diffusion length, such as Cu, on the free layer, with a thickness of any value between 1 nm and 3 nm;

[0084] Preparation of the second reference layer: A CoFeB ferromagnetic alloy with in-plane magnetic anisotropy is deposited on the spacer layer, with a thickness of any value between 1.5 nm and 3 nm;

[0085] Preparation of heavy metal layer: Deposit a layer of metal material with a large spin Hall angle, such as W, Ta / W alloy or topological insulator, on the second reference layer, with a thickness of any value between 3nm and 5nm;

[0086] Protective layer preparation: A conductive material with oxidation resistance, such as TiN or TaN, is deposited on the heavy metal layer to protect the entire memory bit from external environmental corrosion.

[0087] Subsequent processing: Annealing, etching, patterning, and other subsequent process steps are performed as needed to complete the fabrication of STT-MRAM memory bits.

[0088] Throughout the fabrication process, the deposition conditions of each layer (such as temperature, pressure, and gas flow rate) must be strictly controlled to ensure that the quality and performance of each layer meet the design requirements. Simultaneously, necessary characterization and testing are required to verify the performance and reliability of the storage bits.

[0089] Example 4

[0090] like Figure 6 As shown, this embodiment provides a three-dimensional structure of the above-mentioned STT-MRAM storage bit. Specifically, in this storage device, the pinning layer, the first reference layer, the barrier layer, the free layer, the spacer layer, and the second reference layer are in the form of an elliptical cylinder structure, with an aspect ratio preferably greater than 2:1. The bottom metal electrode and the heavy metal layer are arranged perpendicularly to each other. The collinear current of the heavy metal layer and the short axis of the elliptical cylinder structure is used to control the direction of the magnetization intensity of the second reference layer.

[0091] Example 5

[0092] like Figure 7 As shown, this embodiment provides the integrated structure of the above-mentioned STT-MRAM storage bits. Specifically, when WL1 and WL2 are open and WL3 is closed, data can be written and read; when WL2 is closed and WL1 and WL3 are open, the magnetization intensity of the second reference layer can be initialized.

[0093] Therefore, the methods for writing and reading this storage bit are as follows:

[0094] Before writing data, WL2 is turned off and WL1 and WL3 are turned on to initialize the magnetization of the second reference layer and configure it to low critical current mode.

[0095] By further opening WL1 and WL2 and closing WL3, extremely low-power data writing can be achieved;

[0096] Similarly, before reading the data, WL2 is turned off and WL1 and WL3 are turned on to initialize the magnetization of the second reference layer and configure it to high critical current mode.

[0097] By further enabling WL1 and WL2 and disabling WL3, the probability of accidental writes during reading can be greatly reduced.

[0098] The above description does not provide detailed explanations of the technical aspects of each layer's patterning and etching. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to create the same structure, those skilled in the art can design methods that are not entirely identical to those described above.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An STT-MRAM storage bit, characterized in that, The structure includes, from bottom to top, a substrate, a bottom metal electrode, a pinned layer, a first reference layer, a barrier layer, a free layer, a spacer layer, a second reference layer, a heavy metal layer, and a protective layer. By controlling the relative direction of the magnetization intensity of the first reference layer and the second reference layer, the spin polarization current can be enhanced or weakened, thereby changing the critical write current of the memory bit. The first reference layer, the free layer, and the second reference layer are all ferromagnetic alloys with in-plane magnetic anisotropy, and the thickness of the second reference layer is greater than the thickness of the first reference layer; The collinear current in the direction of the short axis of the heavy metal layer and the elliptical cylindrical structure is used to control the direction of the magnetization intensity of the second reference layer.

2. The STT-MRAM storage bit according to claim 1, characterized in that, The barrier layer is a metal oxide with a body-centered cubic lattice structure.

3. The STT-MRAM storage bit according to claim 1, characterized in that, The spacer layer is a non-magnetic metallic element with a large spin diffusion length.

4. The STT-MRAM storage bit according to claim 1, characterized in that, The heavy metal layer is a metallic material with a large spin Hall angle; The pinning layer is an antimagnetic alloy with in-plane magnetic anisotropy; The protective layer is a conductive material with antioxidant properties.

5. The STT-MRAM storage bit according to claim 1, characterized in that, The pinning layer, the first reference layer, the barrier layer, the free layer, the spacer layer, and the second reference layer have an elliptical cylindrical structure, and the bottom metal electrode and the heavy metal layer are arranged perpendicular to each other.

6. The STT-MRAM storage bit according to claim 1, characterized in that, One end of the heavy metal layer is connected to a first transistor, and the other end is connected to a third transistor. The bottom metal electrode is connected to a second transistor.

7. The method for writing and reading STT-MRAM storage bits according to any one of claims 1-6, characterized in that, By utilizing the spin orbital moment effect, a bipolar current is dynamically provided in the heavy metal layer through an external circuit, thereby dynamically adjusting the critical flip current of the storage bit. When performing a write operation, extremely low-power data writing is achieved by configuring the magnetization direction of the second reference layer to be antiparallel to the first reference layer. When performing a read operation, the probability of erroneous writes during the read operation is reduced by configuring the magnetization direction of the second reference layer to be parallel to that of the first reference layer.

8. A storage device, characterized in that, Includes the STT-MRAM storage bits as described in any one of claims 1-6.

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