Plasma processing device and wafer processing method thereof

Abstract

The embodiment of the invention discloses a plasma processing device and a wafer processing method thereof. The plasma processing device comprises a reaction chamber; the carrying table is positioned at the bottom of the reaction cavity and is used for carrying a wafer; the focusing ring is positioned in the reaction cavity and is arranged around the carrying table; and the variable resistance layer covers the lower surface of the focusing ring, and the resistance of the variable resistance layer is adjustable.

Description

Technical Field

[0001] The present disclosure relates to the field of plasma processing devices, and in particular to a plasma processing device and a method for processing a wafer thereof. Background Art

[0002] Plasma processing equipment, such as plasma etching equipment, generates plasma by means of radio frequency coupled discharge, and then uses plasma to process the wafer. Plasma usually includes a carrier for carrying the wafer, and a focusing ring surrounding the wafer is also arranged around the carrier. The focusing ring is used to adjust the electric field distribution around the wafer to ensure the uniformity of wafer etching.

[0003] However, the upper surface of the focusing ring is exposed to the plasma environment and will be consumed as the etching process proceeds, which will cause changes in the electric field around the wafer, resulting in changes in the etching direction and rate at the edge of the wafer, affecting the uniformity of wafer processing. Summary of the invention

[0004] The present disclosure provides a plasma processing device, comprising:

[0005] Reaction chamber;

[0006] A carrier, located at the bottom of the reaction chamber, for carrying a wafer;

[0007] A focusing ring, located in the reaction chamber and arranged around the stage;

[0008] A variable resistance layer covers the lower surface of the focusing ring, and the resistance of the variable resistance layer is adjustable.

[0009] In some embodiments, the variable resistance layer includes a photoresistance layer.

[0010] In some embodiments, the photoresistor layer includes a doped semiconductor layer.

[0011] In some embodiments, the material of the photoresistor layer includes one or a combination of metal sulfide, selenide, and telluride.

[0012] In some embodiments, the plasma processing device further includes: at least one light source disposed below the photoresistor layer, the light source being used to provide illumination for the photoresistor layer, and the illumination intensity of the light source being adjustable.

[0013] In some embodiments, the light source includes an LED cold light source.

[0014] In some embodiments, the plasma processing device also includes: a protective cover located below the photoresistor layer, the protective cover including a first sub-portion, and a second sub-portion extending in a vertical direction below the first sub-portion and connected to the first sub-portion, the second sub-portion is arranged around the light source, and the light source is located in the space formed by the protective cover.

[0015] The present disclosure also provides a method for processing a wafer using a plasma processing device, using any of the plasma processing devices described above, the method comprising:

[0016] placing the wafer on the stage;

[0017] A processing process is performed on the wafer.

[0018] In some embodiments, during the process of performing a treatment process on the wafer, the method further includes:

[0019] The resistance of the variable resistance layer is adjusted.

[0020] In some embodiments, the variable resistance layer includes a photoresistance layer; the plasma processing device further includes: at least one light source disposed below the variable resistance layer, the light source is used to provide light for the photoresistance layer, and the light intensity of the light source is adjustable;

[0021] Adjusting the resistance of the variable resistance layer comprises:

[0022] Adjust the light intensity of at least one of the light sources.

[0023] The plasma processing device and the method for processing a wafer provided by the embodiment of the present disclosure include: a reaction chamber; a carrier, located at the bottom of the reaction chamber, for carrying a wafer; a focusing ring, located in the reaction chamber and arranged around the carrier; a variable resistance layer, covering the lower surface of the focusing ring, and the resistance of the variable resistance layer is adjustable. The lower surface of the focusing ring provided by the embodiment of the present disclosure is provided with a variable resistance layer, and the resistance of the variable resistance layer is adjustable. In this way, the overall impedance of the focusing ring and the variable resistance layer can be adjusted by adjusting the resistance of the variable resistance layer, and then the thickness of the sheath layer located above the focusing ring can be adjusted, so that the edge area of ​​the wafer and the upper surface of the sheath layer above the focusing ring are flush or substantially flush, thereby adjusting the incident direction and incident rate of the plasma in the edge area of ​​the wafer, and improving the processing uniformity of the edge area and the center area of ​​the wafer, such as etching uniformity.

[0024] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A schematic diagram of a plasma processing device provided in an embodiment of the present disclosure;

[0027] Figure 2 for Figure 1 A bottom view of the protective cover and the light source shown in FIG.

[0028] Figure 3a to Figure 3c Different examples of schematic diagrams of the structure of the sheath during wafer processing;

[0029] Figure 4 A schematic top view of a wafer provided in an embodiment of the present disclosure;

[0030] Figure 5 A flowchart of a method for processing a wafer provided in an embodiment of the present disclosure;

[0031] Figure 6 A process flow chart of a method for processing a wafer provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0033] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0034] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0035] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0036] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0037] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] Plasma processing equipment, such as plasma etching equipment, generally includes a reaction chamber and a carrier located in the reaction chamber for carrying the wafer to be processed, and the carrier also serves as the lower electrode of the reaction chamber. The reaction gas is input into the reaction chamber, and one or more radio frequency power supplies can be applied to the lower electrode separately to transmit radio frequency power to the lower electrode, thereby generating a radio frequency electric field inside the reaction chamber. The reaction gas introduced into the reaction chamber generates plasma (including active particles such as electrons, cations, and electrically neutral free radicals) under the excitation of the radio frequency electric field, and chemical reactions and / or physical effects (such as etching) occur between the plasma and the wafer to form various characteristic structures.

[0039] In the process, since electrons have a smaller mass than cations, they are more easily accelerated by the radio frequency electric field, so electrons have a greater moving speed than cations. Electrons gradually accumulate on the surface of the wafer and the focusing ring, forming a negative electric field (i.e., sheath) on the surface of the wafer and the focusing ring. The wafer and the focusing ring are gradually biased to a negative voltage. Under the traction of the negative electric field, the cations are incident on the surface of the wafer to be processed, thereby performing a processing process on the wafer. Among them, the thickness of the sheath determines the energy and direction of the cations in the plasma incident on the wafer to be processed. The focusing ring is used to control the thickness of the sheath in the edge area of ​​the wafer to be processed, thereby ensuring the uniformity of wafer etching. However, the upper surface of the focusing ring is exposed to the plasma environment, and will be consumed as the etching process proceeds, which will cause changes in the electric field around the wafer, resulting in changes in the etching direction and rate of the wafer edge, affecting the uniformity of wafer processing.

[0040] Based on this, the following technical solutions of the embodiments of the present disclosure are proposed:

[0041] The disclosed embodiment provides a plasma processing device, comprising: a reaction chamber; a carrier, located at the bottom of the reaction chamber and used to carry a wafer; a focusing ring, located in the reaction chamber and arranged around the carrier; a variable resistance layer, covering the lower surface of the focusing ring, and the resistance of the variable resistance layer is adjustable.

[0042] The lower surface of the focusing ring provided in the embodiment of the present disclosure is provided with a variable resistance layer, and the resistance of the variable resistance layer is adjustable. In this way, the overall impedance of the focusing ring and the variable resistance layer can be adjusted by adjusting the resistance of the variable resistance layer, and then the thickness of the sheath layer above the focusing ring can be adjusted, so that the edge area of ​​the wafer and the upper surface of the sheath layer above the focusing ring are flush or substantially flush, thereby adjusting the incident direction and incident rate of the plasma in the edge area of ​​the wafer, and improving the processing uniformity of the edge area and the center area of ​​the wafer, such as etching uniformity.

[0043] It should be noted that the plasma processing device provided in the embodiment of the present disclosure can be applied to plasma etching processes, such as ion beam etching (IBE) process, reactive ion etching (RIE) process, etc. However, it is not limited thereto, and the plasma processing device can also be applied to other plasma processes.

[0044] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure in detail, for the sake of convenience, the schematic diagram will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the scope of protection of the present disclosure.

[0045] like Figure 1 As shown, the plasma processing device includes: a reaction chamber 10; a carrier 12, located at the bottom of the reaction chamber 10, for carrying a wafer; a focusing ring 16, located in the reaction chamber 10 and arranged around the carrier 12; a variable resistance layer 17, covering the lower surface of the focusing ring 16, and the resistance of the variable resistance layer 17 is adjustable.

[0046] like Figure 1 As shown, the plasma processing device further includes a reaction chamber wall 101, which surrounds the reaction chamber 10, and a wafer inlet 102 is disposed on the side of the reaction chamber wall 101. In an actual process, a wafer to be processed can be placed on the carrier 12 through the wafer inlet 102.

[0047] In some embodiments, the plasma processing apparatus further includes: a vacuum pump 11 in communication with the reaction chamber 10. In actual operation, the vacuum pump 11 can be used to exhaust the processing gas in the reaction chamber 10 to adjust the pressure in the reaction chamber 10.

[0048] In some embodiments, the carrier 12 can be an electrostatic chuck, which can include a dielectric layer 121 and a base 122 located below the dielectric layer. An electrostatic electrode can be set in the dielectric layer 121. When processing the chip, a voltage can be applied to the electrostatic electrode in the electrostatic chuck through a DC power supply, so that the surface of the electrostatic chuck and the back of the chip generate polarized charges with opposite polarities, so that an electrostatic suction force is generated between the electrostatic chuck and the chip, thereby fixing the chip on the electrostatic chuck.

[0049] In some embodiments, the plasma processing apparatus further includes: a gas shower head 14 disposed opposite to the carrier 12, and a gas supply device 15 connected to the gas shower head 14, wherein the gas shower head 14 is used to serve as an upper electrode of the plasma processing apparatus and to introduce the gas required for processing the wafer from the gas supply device 15 into the reaction chamber 10.

[0050] In some embodiments, the material of the base 122 in the carrier 12 can be metal or metal alloy, and the base 122 in the carrier 12 can serve as the lower electrode of the plasma processing device; the plasma processing device also includes: a radio frequency power supply 13 connected to the base 122. The radio frequency power supply 13 is used to generate a radio frequency electric field between the upper electrode and the lower electrode. Most of the radio frequency electric field is contained in the processing area above the carrier 12. This radio frequency electric field accelerates a small amount of electrons existing inside the reaction chamber, causing them to collide with gas molecules of the reaction gas input into the reaction chamber 10. These collisions lead to ionization of the reaction gas and excitation of plasma, thereby generating plasma (including active particles such as electrons, cations, and electrically neutral free radicals) in the reaction chamber 10. The plasma can be used to perform plasma etching and other processes on the wafer.

[0051] In the process of performing a processing on the wafer, since the mass of electrons is smaller than that of cations, they are more easily accelerated by the radio frequency electric field, and thus the electrons have a greater moving speed than the cations. The electrons gradually accumulate on the surface of the wafer and the focusing ring 16, forming a negative electric field, i.e., a sheath, on the surface of the wafer and the focusing ring 16. The wafer and the focusing ring 16 are gradually biased to a negative voltage. Under the pulling effect of the negative electric field, the cations are incident on the surface of the wafer to be processed, thereby performing a processing on the wafer. Among them, the thickness of the sheath 21 determines the energy and direction of the cations in the plasma incident on the wafer to be processed, and the focusing ring 16 is used to control the sheath thickness in the edge area of ​​the wafer to be processed, thereby ensuring the uniformity of wafer etching.

[0052] Figure 3a to Figure 3c 2 are different examples of schematic structural diagrams of the sheath 21 during processing of the wafer 20 , wherein arrow A indicates the incident direction of the cations. Figure 4 2 is a schematic top view of a wafer 20 . The wafer 20 includes a central region 201 and an edge region 202 surrounding the central region 201 .

[0053] like Figure 3a to Figure 3c As shown, in some embodiments, the upper surface of the focus ring 16 is higher than the upper surface of the stage 12, so that after the wafer 20 is placed on the stage 12, the focus ring 16 can surround the wafer 20, so that the sheath thickness of the edge region 202 of the wafer 20 can be controlled by the focus ring 16.

[0054] like Figure 3aAs shown, the applicant found that during the processing of the wafer 20, the focus ring 16 is also exposed to the plasma. As the processing proceeds, its material will be lost, which will cause the height of the upper surface of the focus ring 16 to decrease, and then cause the height of the sheath 21 located on the surface of the focus ring 16 to decrease. The upper surface of the sheath 21 located above the wafer 20 is higher than the upper surface of the sheath 21 located above the focus ring 16, and the sheath 21 located at the junction of the wafer 20 and the focus ring 16 is tilted. During the processing of the wafer 20, the incident direction of the cations located in the central area 201 of the wafer 20 is perpendicular to the plane of the wafer 20, and the incident direction of the cations located in the edge area 202 of the wafer 20 is tilted toward the inside of the wafer 20, resulting in differences in parameters such as the processing rate of the edge area 202 of the wafer 20 and the central area 201 of the wafer 20. For example, when performing an etching process on the wafer 20, the etching direction of the edge region 202 of the wafer 20 is tilted toward the inside of the wafer 20, and the etching rate of the edge region 202 of the wafer 20 is greater than the etching rate of the central region 201 of the wafer 20, thereby reducing the uniformity of processing the wafer 20.

[0055] In addition, the applicant has also discovered that, in the process of performing a processing on the wafer 20, there may be some situations that cause the impedance of the focusing ring 16 to increase, thereby causing the thickness of the sheath 21 located above the wafer 20 to be greater than the thickness of the sheath 21 located above the focusing ring 16, and the upper surface of the sheath 21 located above the wafer 20 to be higher than the upper surface of the sheath 21 located above the focusing ring 16, causing the sheath 21 located at the junction of the wafer 20 and the focusing ring 16 to tilt, causing the incident direction of the cations located in the edge region 202 of the wafer 20 to tilt toward the inside of the wafer 20, thereby causing parameters such as the processing rate in the edge region 202 of the wafer 20 to differ from those in the central region 201 of the wafer 20.

[0056] like Figure 3bAs shown, the applicant has also found that in the process of etching the wafer 20, there may be some situations that cause the impedance of the focus ring 16 to decrease, thereby causing the thickness of the sheath 21 located above the wafer 20 to be less than the thickness of the sheath 21 located above the focus ring 16, and the upper surface of the sheath 21 located above the wafer 20 is lower than the upper surface of the sheath 21 located above the focus ring 16, so that the sheath 21 located at the junction of the wafer 20 and the focus ring 16 is tilted. In the process of performing a processing process on the wafer 20, the sheath 21 pulls the cations located in the edge area 202 of the wafer 20 toward the outside of the wafer 20, which will cause the processing rate of the edge area 202 of the wafer 20 to be different from that of the central area 201 of the wafer 20. For example, when performing an etching process on the wafer 20, the etching direction of the edge area 202 of the wafer 20 will be tilted toward the outside of the wafer 20, and the etching rate of the edge area 202 of the wafer 20 will be lower than the etching rate of the central area 201 of the wafer 20, which reduces the uniformity of processing the wafer 20.

[0057] Specifically, in actual operation, a variety of situations may cause the impedance of the focus ring to change, such as: (1) After long-term use, the aging of the focus ring material may cause the impedance of the focus ring to increase; (2) Mechanical damage such as scratches or wear may occur on the surface of the focus ring. The presence of damage may cause the local resistance of the focus ring to increase, resulting in an increase in the overall impedance of the focus ring; (3) When pollutants such as reaction by-products, dust, and ions accumulate on the surface of the focus ring, the pollutants may form additional conductive paths, resulting in a decrease in the impedance of the focus ring; (4) Water can act as an electrolyte. When the ambient humidity increases, the impedance of the focus ring may decrease; (5) The focus ring has poor contact with other components or the connection points between the focus ring and other components are oxidized, which will increase the contact resistance and increase the impedance of the focus ring; (6) The material of the focus ring may react with chemicals in the environment, resulting in an increase or decrease in the impedance of the focus ring; in addition, electrostatic effects will cause charges to accumulate on the surface of the focus ring, which usually does not cause the impedance of the focus ring to change, but may affect the potential distribution on the surface of the focus ring and indirectly affect the overall electrical performance.

[0058] It should be noted that the impedance changes of the focusing ring in the above cases are not absolute. They depend on the specific materials and conditions. In practical applications, it may be necessary to determine the specific changes in the focusing ring impedance through experiments or detailed analysis.

[0059] like Figure 3cAs shown, in the embodiment of the present disclosure, a variable resistance layer 17 is provided on the lower surface of the focusing ring 16, and the resistance of the variable resistance layer 17 is adjustable. Thus, the overall impedance of the focusing ring 16 and the variable resistance layer 17 can be adjusted by adjusting the resistance of the variable resistance layer 17, and then the thickness of the sheath 21 located above the focusing ring 16 can be adjusted, so that the sheath 21 located on the surface of the wafer 20 and the upper surface of the sheath 21 located on the surface of the focusing ring 16 are flush or substantially flush, thereby adjusting the incident direction and incident rate of cations in the edge region 202 of the wafer 20, and improving the processing uniformity of the edge region 202 and the center region 201 of the wafer 20. For example, when the upper surface of the sheath 21 above the focus ring 16 is lower than the upper surface of the sheath 21 above the wafer 20, the resistance of the variable resistance layer 17 can be adjusted to be lowered, thereby increasing the thickness of the sheath 21 above the focus ring 16; when the upper surface of the sheath 21 above the focus ring 16 is higher than the upper surface of the sheath 21 above the wafer 20, the resistance of the variable resistance layer 17 can be adjusted to be higher, thereby reducing the thickness of the sheath 21 above the focus ring 16. In this way, by adjusting the impedance of the focus ring 16 and the variable resistance layer 17, the upper surfaces of the sheath 21 above the wafer 20 and the sheath 21 above the focus ring 16 are flush or substantially flush.

[0060] In actual operation, the thickness of the sheath 21 located above the focusing ring 16 and the sheath 21 located above the chip 20 can be determined by monitoring parameters such as the etching rate and etching direction of the central area 201 and the edge area 202 of the chip 20, and the resistance value of the variable resistor layer 17 can be adjusted according to the judgment result.

[0061] In some embodiments, the material of the focus ring 16 is at least one of the following materials: quartz, aluminum oxide, aluminum nitride, single crystal silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxide, for example, silicon.

[0062] In actual operation, the variable resistance layer 17 can be formed on the lower surface of the focusing ring 16 by one or more thin film processes, such as one or more of chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0063] In some embodiments, the variable resistance layer 17 includes a photoresistor layer 171. In actual operation, under dark conditions, most of the electrons in the photoresistor layer 171 are valence band electrons that cannot move freely, and the resistance of the photoresistor layer 171 is very high at this time; when there is light of a suitable wavelength, the valence band electrons in the photoresistor layer 171 absorb photon energy and transition to the conduction band, becoming free electrons that can conduct electricity, and leave a hole in the valence band, and the resistance of the photoresistor layer 171 decreases. The greater the light intensity, the more electron-hole pairs are excited in the photoresistor layer 171, and the lower the resistance of the photoresistor layer 171. In this way, the resistance of the photoresistor layer 171 can be adjusted by adjusting the light intensity of the photoresistor layer 171, and then the thickness of the sheath layer 21 located above the focusing ring 16 can be adjusted.

[0064] In some embodiments, the photoresistor layer 171 includes a doped semiconductor layer. By doping the semiconductor layer, the adjustable resistance range of the photoresistor layer 171 can be increased.

[0065] In some embodiments, the material of the photoresistor layer 171 includes one or a combination of metal sulfide, selenide, and telluride, such as cadmium sulfide, cadmium telluride, gallium arsenide, etc. However, it is not limited thereto, and the material of the photoresistor layer 171 may also be other materials whose resistance changes with light intensity, such as organic dye light-absorbing materials, etc., and the present disclosure does not make specific restrictions on this. In some embodiments, the thickness of the photoresistor layer 171 may be flexibly adjusted according to the actual process.

[0066] In some embodiments, the plasma processing device further includes: at least one light source 18 disposed below the photoresistor layer 171, the light source 18 is used to provide light for the photoresistor layer 171, and the light intensity of the light source 18 is adjustable. Thus, in actual operation, the resistance of the photoresistor layer 171 can be adjusted by adjusting the light intensity of the light source 18, thereby adjusting the thickness of the sheath layer 21 located above the focusing ring 16. Here, the wavelength of the light emitted by the light source 18 is related to the material of the photoresistor layer 171, and it should be ensured that the light emitted by the light source 18 is sufficient to excite the electron-hole pairs in the photoresistor layer 171.

[0067] In some embodiments, the light source 18 includes an LED cold light source. The LED cold light source is used to adjust the resistance of the photoresistor layer 171, so as to avoid introducing an additional heat source into the reaction chamber 10 to affect the processing of the wafer.

[0068] like Figure 2As shown, in some embodiments, the number of light sources 18 can be multiple, and the multiple light sources 18 can be evenly distributed under the focus ring 16. In this way, when it is necessary to adjust the overall thickness of the sheath 21 above the focus ring 16, the illumination intensity of the multiple light sources 18 can be adjusted simultaneously to improve the uniformity of illumination in different regions, thereby improving the uniformity of the thickness of the sheath 21 above the focus ring 16. In addition, due to process differences or other reasons, such as different consumption conditions in different regions of the focus ring 16, or different aggregation conditions of etching byproducts in different regions of the focus ring 16, the thickness of the sheath 21 above the different regions may be different. In this way, the illumination intensity of the light sources 18 below the different regions of the focus ring 16 can be flexibly adjusted according to the thickness difference of the sheath 21 above the different regions of the focus ring 16, so as to flexibly adjust the resistance of the photoresistor layer 171 below the different regions of the focus ring 16, and accurately adjust the thickness of the sheath 21 above the focus ring 16 according to the different regions of the focus ring 16, thereby improving the uniformity of wafer processing.

[0069] It should be noted that Figure 2 The number and arrangement of the light sources 18 is only one possible example. In fact, the number of light sources 18 can be more or less, and the multiple light sources 18 can also have other uniform or non-uniform arrangements, which can be flexibly set according to actual needs.

[0070] In some embodiments, the plasma processing device further includes: a protective cover 19 located below the photoresistor layer 171, the protective cover 19 includes a first sub-portion 191, and a second sub-portion 192 extending vertically below the first sub-portion 191 and connected to the first sub-portion 191, the second sub-portion 192 surrounds the light source 18, and the light source 18 is located in the space formed by the protective cover 19. In actual operation, when the wafer is subjected to a processing process, the protective cover 19 is used to protect the light source 18 from being damaged by plasma. The material of the protective cover 19 includes a transparent material, such as quartz.

[0071] like Figure 2 As shown, in some embodiments, the second sub-portion 192 of the protective cover 19 includes a first annular side wall 1921 and a second annular side wall 1922 that are relatively arranged and surround the carrier 12, and a plurality of light sources 18 are located in the space between the first annular side wall 1921 and the second annular side wall 1922. The arrangement of the first annular side wall 1921 and the second annular side wall 1922 can provide better protection for the light sources 18.

[0072] The embodiment of the present disclosure also provides a method for processing a wafer using a plasma processing device, wherein the plasma processing device comprises: a reaction chamber; a carrier, located at the bottom of the reaction chamber, for carrying the wafer; a focusing ring, located in the reaction chamber and arranged around the carrier; a variable resistance layer, covering the lower surface of the focusing ring, wherein the resistance of the variable resistance layer is adjustable; Figure 5 As shown, the method for processing a wafer comprises the following steps:

[0073] Step S101, placing a wafer on a stage;

[0074] Step S102: performing a processing process on the wafer.

[0075] Next, the method for processing a wafer using a plasma processing device provided by an embodiment of the present disclosure is further described in detail with reference to the accompanying drawings.

[0076] like Figure 6 As shown, the plasma processing device includes: a reaction chamber 10; a carrier 12, located at the bottom of the reaction chamber 10, for carrying a wafer; a focusing ring 16, located in the reaction chamber 10 and arranged around the carrier 12; a variable resistance layer 17, covering the lower surface of the focusing ring 16, and the resistance of the variable resistance layer 17 is adjustable; execute step S101 to place the wafer 20 on the carrier 12.

[0077] like Figure 6 As shown, the plasma processing device further includes a reaction chamber wall 101, which surrounds the reaction chamber 10, and a wafer inlet 102 is disposed on the side of the reaction chamber wall 101. In an actual process, the wafer 20 to be processed can be placed on the carrier 12 through the wafer inlet 102.

[0078] In some embodiments, the plasma processing apparatus further includes: a vacuum pump 11 in communication with the reaction chamber 10. In actual operation, the vacuum pump 11 can be used to exhaust the processing gas in the reaction chamber 10 to adjust the pressure in the reaction chamber 10.

[0079] In some embodiments, the carrier 12 may be an electrostatic chuck, which may include a dielectric layer 121 and a base 122 located below the dielectric layer, and an electrostatic electrode may be disposed in the dielectric layer 121. In some embodiments, after placing the wafer 20 on the carrier 12, the method further includes: applying a voltage to the electrostatic electrode in the electrostatic chuck through a DC power supply, so that a polarized charge with opposite polarity is generated between the surface of the electrostatic chuck and the back of the wafer 20, so that an electrostatic suction force is generated between the electrostatic chuck and the wafer 20, thereby fixing the wafer 20 on the electrostatic chuck.

[0080] In some embodiments, the plasma processing apparatus further includes: a gas shower head 14 disposed opposite to the carrier 12 , and a gas supply device 15 connected to the gas shower head 14 . The gas shower head 14 is used to serve as an upper electrode of the plasma processing apparatus and is also used to introduce the gas required for processing the wafer 20 from the gas supply device 15 into the reaction chamber 10 .

[0081] In some embodiments, the material of the base 122 in the carrier 12 can be metal or metal alloy, and the base 122 can serve as the lower electrode of the plasma processing device; the plasma processing device also includes: a radio frequency power supply 13 connected to the base 122.

[0082] In some embodiments, the material of the focus ring 16 is at least one of the following materials: quartz, aluminum oxide, aluminum nitride, single crystal silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxide, for example, silicon.

[0083] In actual operation, the variable resistance layer 17 can be formed on the lower surface of the focusing ring 16 by one or more thin film processes, such as one or more of chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0084] In some embodiments, the variable resistance layer 17 includes a photoresistor layer 171, and the resistance of the photoresistor layer 171 can change with the intensity of light. The plasma processing device also includes: at least one light source 18 arranged under the photoresistor layer 171, the light source 18 is used to provide light for the photoresistor layer 171, and the light intensity of the light source 18 is adjustable.

[0085] In some embodiments, the photoresistor layer 171 includes a doped semiconductor layer. By doping the semiconductor layer, the adjustable resistance range of the variable resistance layer 17 can be increased.

[0086] In some embodiments, the material of the photoresistor layer 171 includes one or a combination of metal sulfide, selenide, and telluride, such as cadmium sulfide, cadmium telluride, gallium arsenide, etc. However, it is not limited thereto, and the material of the photoresistor layer 171 may also be other materials whose resistance changes with light intensity, such as organic dye light-absorbing materials, etc., and the present disclosure does not make specific restrictions on this. In some embodiments, the thickness of the photoresistor layer 171 may be flexibly adjusted according to the actual process.

[0087] In some embodiments, the light source 18 includes an LED (Light Emitting Diode) cold light source, so that it is possible to avoid introducing an additional heat source into the reaction chamber 10 to affect the processing of the wafer 20 .

[0088] like Figure 2As shown, in some embodiments, the number of light sources 18 can be multiple, and the multiple light sources 18 can be evenly distributed below the focusing ring 16. It should be noted that, Figure 2 The number and arrangement of the light sources 18 is only one possible example. In fact, the number of light sources 18 can be more or less, and the multiple light sources 18 can also have other uniform or non-uniform arrangements, which can be flexibly set according to actual needs.

[0089] In some embodiments, the plasma processing device further includes: a protective cover 19 located below the photoresistor layer 171, the protective cover 19 includes a first sub-portion 191, and a second sub-portion 192 extending vertically below the first sub-portion 191 and connected to the first sub-portion 191, the second sub-portion 192 surrounds the light source 18, and the light source 18 is located in the space formed by the protective cover 19. When the wafer 20 is subsequently subjected to a processing process, the protective cover 19 is used to protect the light source 18 from being damaged by plasma. The material of the protective cover 19 includes a transparent material, such as quartz.

[0090] like Figure 2 As shown, in some embodiments, the second sub-portion 192 of the protective cover 19 includes a first annular side wall 1921 and a second annular side wall 1922 that are relatively arranged and surround the carrier 12, and a plurality of light sources 18 are located in the space between the first annular side wall 1921 and the second annular side wall 1922. The arrangement of the first annular side wall 1921 and the second annular side wall 1922 can provide better protection for the light sources 18.

[0091] Next, step S102 is executed to perform a treatment process on the wafer 20 .

[0092] The processing performed on the wafer 20 may include performing a plasma etching process on the wafer 20 , such as an ion beam etching (IBE) process, a reactive ion etching (RIE) process, etc.

[0093] In some embodiments, the processing of the wafer 20 further includes: introducing the reaction gas from the gas supply device 15 into the reaction chamber 10 through the gas shower head 14; generating a radio frequency electric field between the upper electrode and the lower electrode through the radio frequency power supply 13, most of the radio frequency electric field is contained in the processing area above the carrier 12, and the radio frequency electric field accelerates a small amount of electrons existing inside the reaction chamber, causing them to collide with gas molecules of the reaction gas input into the reaction chamber 10, and these collisions lead to ionization of the reaction gas and excitation of plasma, thereby generating plasma (including active particles such as electrons, cations, and electrically neutral free radicals) in the reaction chamber 10, and the plasma can be used to perform processes such as plasma etching on the wafer 20.

[0094] In the process of performing the treatment process on the wafer 20, since the mass of electrons is smaller than that of cations, they are more easily accelerated by the radio frequency electric field, and thus the electrons have a greater moving speed than the cations, and the electrons gradually accumulate on the surface of the wafer 20 and the focusing ring 16, forming a negative electric field, i.e., a sheath, on the surface of the wafer 20 and the focusing ring 16, and the wafer 20 and the focusing ring 16 are gradually biased to a negative voltage. Under the pulling effect of the negative electric field, the cations are incident on the surface of the wafer 20 to be processed, thereby performing the treatment process on the wafer 20. Among them, the thickness of the sheath 21 determines the energy and direction of the cations in the plasma incident on the wafer 20 to be processed, and the focusing ring 16 is used to control the sheath thickness of the edge area of ​​the wafer 20 to be processed, thereby ensuring the uniformity of etching of the wafer 20.

[0095] like Figure 6 As shown, in some embodiments, the upper surface of the focus ring 16 is higher than the upper surface of the stage 12, so that after the wafer 20 is placed on the stage 12, the focus ring 16 can surround the wafer 20, so that the sheath thickness of the edge region 202 of the wafer 20 can be controlled by the focus ring 16. Figure 4 As shown, in some embodiments, the wafer 20 includes a central region 201 and an edge region 202 surrounding the central region 201 .

[0096] like Figure 3a As shown, the applicant found that during the processing of the wafer 20, the focus ring 16 is also exposed to the plasma. As the processing proceeds, its material will be lost, which will cause the height of the upper surface of the focus ring 16 to decrease, and then cause the height of the sheath 21 located on the surface of the focus ring 16 to decrease. The upper surface of the sheath 21 located above the wafer 20 is higher than the upper surface of the sheath 21 located above the focus ring 16, and the sheath 21 located at the junction of the wafer 20 and the focus ring 16 is tilted. During the processing of the wafer 20, the incident direction of the cations located in the central area 201 of the wafer 20 is perpendicular to the plane of the wafer 20, and the incident direction of the cations located in the edge area 202 of the wafer 20 is tilted toward the inside of the wafer 20, resulting in differences in parameters such as the processing rate of the edge area 202 of the wafer 20 and the central area 201 of the wafer 20. For example, when performing an etching process on the wafer 20, the etching direction of the edge region 202 of the wafer 20 is tilted toward the inside of the wafer 20, and the etching rate of the edge region 202 of the wafer 20 is greater than the etching rate of the central region 201 of the wafer 20, thereby reducing the uniformity of processing the wafer 20.

[0097] In addition, the applicant has also discovered that, in the process of performing a processing on the wafer 20, there may be some situations that cause the impedance of the focusing ring 16 to increase, thereby causing the thickness of the sheath 21 located above the wafer 20 to be greater than the thickness of the sheath 21 located above the focusing ring 16, and the upper surface of the sheath 21 located above the wafer 20 to be higher than the upper surface of the sheath 21 located above the focusing ring 16, causing the sheath 21 located at the junction of the wafer 20 and the focusing ring 16 to tilt, causing the incident direction of the cations located in the edge region 202 of the wafer 20 to tilt toward the inside of the wafer 20, thereby causing parameters such as the processing rate in the edge region 202 of the wafer 20 to differ from those in the central region 201 of the wafer 20.

[0098] like Figure 3b As shown, the applicant has also found that in the process of etching the wafer 20, there may be some situations that cause the impedance of the focus ring 16 to decrease, thereby causing the thickness of the sheath 21 located above the wafer 20 to be less than the thickness of the sheath 21 located above the focus ring 16, and the upper surface of the sheath 21 located above the wafer 20 is lower than the upper surface of the sheath 21 located above the focus ring 16, so that the sheath 21 located at the junction of the wafer 20 and the focus ring 16 is tilted. In the process of performing a processing process on the wafer 20, the sheath 21 pulls the cations located in the edge area 202 of the wafer 20 toward the outside of the wafer 20, which will cause the processing rate of the edge area 202 of the wafer 20 to be different from that of the central area 201 of the wafer 20. For example, when performing an etching process on the wafer 20, the etching direction of the edge area 202 of the wafer 20 will be tilted toward the outside of the wafer 20, and the etching rate of the edge area 202 of the wafer 20 will be lower than the etching rate of the central area 201 of the wafer 20, which reduces the uniformity of processing the wafer 20.

[0099] In some embodiments, during the process of performing the processing on the wafer 20, the method further includes: adjusting the resistance of the variable resistance layer 17, such that Figure 3cAs shown, the embodiment of the present disclosure adjusts the resistance of the variable resistance layer 17, adjusts the overall impedance of the focus ring 16 and the variable resistance layer 17, and then adjusts the thickness of the sheath layer 21 located above the focus ring 16, so that the sheath layer 21 located on the surface of the wafer 20 and the upper surface of the sheath layer 21 located on the surface of the focus ring 16 are flush or substantially flush, thereby adjusting the incident direction and incident rate of the cations in the edge area 202 of the wafer 20, and improving the processing uniformity of the edge area 202 and the central area 201 of the wafer 20. For example: when the upper surface of the sheath layer 21 located above the focus ring 16 is lower than the upper surface of the sheath layer 21 located above the wafer 20, the resistance of the variable resistance layer 17 can be reduced, thereby increasing the thickness of the sheath layer 21 located above the focus ring 16; when the upper surface of the sheath layer 21 located above the focus ring 16 is higher than the upper surface of the sheath layer 21 located above the wafer 20, the resistance of the variable resistance layer 17 can be increased, thereby reducing the thickness of the sheath layer 21 located above the focus ring 16. In this way, by adjusting the impedance of the focus ring 16 and the variable resistance layer 17 , the upper surface of the sheath layer 21 located above the wafer 20 and the upper surface of the sheath layer 21 located above the focus ring 16 are flush or substantially flush.

[0100] In actual operation, the thickness of the sheath 21 located above the focusing ring 16 and the sheath 21 located above the chip 20 can be determined by monitoring parameters such as the etching rate and etching direction of the central area 201 and the edge area 202 of the chip 20, and the resistance value of the variable resistor layer 17 can be adjusted according to the judgment result.

[0101] In some embodiments, the variable resistance layer 17 includes a photoresistance layer 171 ; adjusting the resistance of the variable resistance layer 17 includes: adjusting the light intensity of at least one light source 18 .

[0102] In actual operation, under dark conditions, most of the electrons in the photoresistor layer 171 are valence band electrons that cannot move freely, and the resistance of the photoresistor layer 171 is very high at this time; when there is light of appropriate wavelength, the valence band electrons in the photoresistor layer 171 will absorb photon energy and transition to the conduction band, becoming free electrons that can conduct electricity, and leave a hole in the valence band, and the resistance of the photoresistor layer 171 is reduced. The greater the light intensity, the more electron-hole pairs are excited in the photoresistor layer 171, and the lower the resistance of the photoresistor layer 171. In this way, the resistance of the photoresistor layer 171 can be adjusted by adjusting the light intensity of the light source 18 to adjust its resistance, and then adjust the thickness of the sheath layer 21 located above the focusing ring 16.

[0103] Here, the wavelength of the light emitted by the light source 18 is related to the material of the photoresistor layer 171 , and it should be ensured that the light emitted by the light source 18 is sufficient to excite the electron-hole pairs in the photoresistor layer 171 .

[0104] In some embodiments of the present disclosure, the number of light sources 18 may be multiple. When it is necessary to adjust the overall thickness of the sheath 21 above the focus ring 16, the illumination intensity of multiple light sources 18 may be adjusted simultaneously to improve the uniformity of illumination in different regions, thereby improving the uniformity of the thickness of the sheath 21 above the focus ring 16. In addition, due to process differences or other reasons, such as different consumption conditions in different regions of the focus ring 16, or different aggregation conditions of etching byproducts in different regions of the focus ring 16, the thickness of the sheath 21 above the different regions may be different. In this way, the illumination intensity of the light sources 18 below the different regions of the focus ring 16 may be flexibly adjusted according to the thickness difference of the sheath 21 above the different regions of the focus ring 16, so as to flexibly adjust the resistance of the photoresistor layer 171 below the different regions of the focus ring 16, and accurately adjust the thickness of the sheath 21 above the focus ring 16 according to the different regions of the focus ring 16, thereby improving the uniformity of the processing of the wafer 20.

[0105] It should be noted that those skilled in the art can change the order of the above steps without departing from the protection scope of the present disclosure. The above is only an optional embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A plasma processing device, characterized in that: include: Reaction chamber; A carrier, located at the bottom of the reaction chamber, for carrying a wafer; A focusing ring, located in the reaction chamber and arranged around the stage; A variable resistance layer covers the lower surface of the focusing ring, and the resistance of the variable resistance layer is adjustable.

2. The plasma processing device according to claim 1, characterized in that: The variable resistance layer includes a photoresistance layer.

3. The plasma processing device according to claim 2, characterized in that: The photoresistor layer includes a doped semiconductor layer.

4. The plasma processing device according to claim 2, characterized in that: The material of the photoresistor layer includes one or a combination of metal sulfide, selenide and telluride.

5. The plasma processing device according to claim 2, characterized in that: The plasma processing device further includes: at least one light source disposed below the photoresistor layer, the light source being used to provide illumination for the photoresistor layer, and the illumination intensity of the light source being adjustable.

6. The plasma processing device according to claim 5, characterized in that: The light source includes an LED cold light source.

7. The plasma processing device according to claim 5, characterized in that: The plasma processing device also includes: a protective cover located below the photoresistor layer, the protective cover includes a first sub-section, and a second sub-section extending vertically below the first sub-section and connected to the first sub-section, the second sub-section is arranged around the light source, and the light source is located in the space formed by the protective cover.

8. A method for processing a wafer, using the plasma processing device according to any one of claims 1 to 7, characterized in that: The method comprises: placing the wafer on the stage; A processing process is performed on the wafer.

9. The method according to claim 8, characterized in that In the process of performing a processing process on the wafer, the method further comprises: The resistance of the variable resistance layer is adjusted.

10. The method according to claim 9, characterized in that The variable resistance layer includes a photoresistance layer; the plasma processing device further includes: at least one light source disposed below the variable resistance layer, the light source is used to provide light for the photoresistance layer, and the light intensity of the light source is adjustable; Adjusting the resistance of the variable resistance layer comprises: Adjust the light intensity of at least one of the light sources.

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