Pixel arrangement on two substrates and method for manufacturing an image sensor

Abstract

A pixel arrangement includes a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate includes a photodiode, a circuit node, a pass transistor coupled with the photodiode and the circuit node, an amplifier having an input coupled with the circuit node, and a terminal coupled with an output of the amplifier. The second semiconductor substrate includes a second capacitor coupled with the terminal, another amplifier having an input coupled with the second capacitor, a column line, and a select transistor coupled with the column line and an output of the another amplifier. The first semiconductor substrate or the second semiconductor substrate includes a first capacitor coupled with the terminal. In addition, a method for manufacturing a plurality of image sensors is described.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of priority from U.S. Provisional Patent Application No. 63 / 404,637, filed on September 8, 2022, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention provides a pixel arrangement, an image sensor having the pixel arrangement, and a method for manufacturing a plurality of image sensors. Background Art

[0004] An image sensor typically includes a pixel arrangement having a photodiode array, a plurality of transistors and one or more capacitors. Capacitors with high capacitance reduce the effects of noise. Capacitors occupy a large area on a semiconductor substrate. However, the small size of the pixel arrangement is advantageous.

[0005] Therefore, there is a need for a pixel arrangement, an image sensor having a pixel arrangement, and a method for manufacturing a plurality of image sensors. Summary of the invention

[0006] In one embodiment, a pixel arrangement comprises a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate comprises a photodiode, a circuit node, a transfer transistor coupled to the photodiode and the circuit node, an amplifier having an input coupled to the circuit node, and a terminal coupled to an output of the amplifier. The second semiconductor substrate comprises a second capacitor coupled to the terminal, another amplifier having an input coupled to the second capacitor, a column line, and a selection transistor coupled to the column line and an output of the another amplifier. The first semiconductor substrate or the second semiconductor substrate comprises a first capacitor coupled to the terminal.

[0007] In one embodiment, in a cross section of the pixel arrangement, the first capacitor and the second capacitor are placed on top of each other. For example, the second semiconductor substrate comprises the first capacitor, and the first capacitor and the second capacitor are placed on top of each other.

[0008] For example, the first capacitor and the second capacitor are placed on top of each other by using different metal layouts. For example, the first capacitor is implemented by two metallization layers in a metallization layer stack, and the second capacitor is implemented by another two metallization layers in the metallization layer stack. For example, the first capacitor uses metal 4 and metal 5, and the second capacitor uses metal 6 and metal 7 of the same semiconductor substrate.

[0009] In one example, the photodiode, the circuit node, the transfer transistor, and the amplifier are integrated in the first semiconductor substrate.

[0010] In one example, the second capacitor, the further amplifier, the column line, and the selection transistor are integrated in the second semiconductor substrate.

[0011] In one example, the first capacitor is integrated in the first semiconductor substrate or the second semiconductor substrate. In an embodiment of the pixel arrangement, the first semiconductor substrate has a first face and a second face. The second semiconductor substrate has a first face and a second face.

[0012] In an embodiment of the pixel arrangement, the first side of the first semiconductor substrate is attached to the first side of the second semiconductor substrate. Thus, the transistor, the capacitor and the terminal are located at the first side of the first semiconductor substrate and the first side of the second semiconductor substrate.

[0013] In one embodiment of the pixel arrangement, the second side of the first semiconductor substrate is configured to receive electromagnetic radiation. The photodiode is located on the second side of the first semiconductor substrate.

[0014] In an embodiment of the pixel arrangement, the first capacitor is one of the group consisting of: a metal-insulator-metal capacitor, an interdigital capacitor and a metal-oxide-semiconductor capacitor.

[0015] In an embodiment of the pixel arrangement, the second capacitor is one of the group consisting of: a metal-insulator-metal capacitor, an interdigital capacitor and a metal-oxide-semiconductor capacitor.

[0016] In one embodiment of the pixel arrangement, the metal-insulator-metal capacitor is a high density capacitor. The insulator of the metal-insulator-metal capacitor is a high density material or a high-k material.

[0017] In an embodiment of the pixel arrangement, the capacitance of the first capacitor is in the range between 10 fF and 100 fF, or in the range between 20 fF and 80 fF, or in the range between 30 fF and 50 fF.

[0018] In an embodiment of the pixel arrangement, the capacitance of the second capacitor is in the range between 10 fF and 100 fF, or in the range between 20 fF and 80 fF, or in the range between 30 fF and 50 fF.

[0019] In one embodiment of the pixel arrangement, the first semiconductor substrate comprises a first transistor coupled to an output of the amplifier, the terminal and the first capacitor.

[0020] In an embodiment of the pixel arrangement, the first capacitor is connected or directly connected to the terminal.

[0021] In an alternative embodiment of the pixel arrangement, the first capacitor is coupled to the terminal via the first transistor.

[0022] In one embodiment of the pixel arrangement, the first capacitor comprises a first electrode coupled to a node between the first transistor and the terminal.A second electrode of the first capacitor is coupled to a further reference potential terminal.

[0023] In an embodiment of the pixel arrangement, the second semiconductor substrate comprises a second transistor coupled to the input of the further amplifier and the second capacitance.

[0024] In a further extension of the pixel arrangement, the second transistor is also coupled to the terminal.

[0025] In an embodiment of the pixel arrangement, the second capacitor is coupled to the terminal via the second transistor and is connected to an input of the further amplifier.

[0026] In an alternative embodiment of the pixel arrangement, the second capacitor is connected to the terminal, the second transistor and an input of the further amplifier.

[0027] In an embodiment of the pixel arrangement, the second capacitor comprises a first electrode coupled or connected to a node between the second transistor and the input of the further amplifier.A second electrode of the second capacitor is coupled or connected to a further reference potential terminal.

[0028] In an alternative embodiment of the pixel arrangement, the second capacitor comprises a first electrode coupled or connected to the terminal, and a second electrode coupled or connected to a node between the second transistor and the input of the further amplifier.

[0029] In an alternative embodiment of the pixel arrangement, the second capacitor comprises a first electrode coupled or connected to the second transistor, and a second electrode coupled or connected to the further reference potential terminal.

[0030] In one embodiment of the pixel arrangement, the first semiconductor substrate comprises a reset transistor coupled to a power supply terminal and the circuit node.

[0031] In one embodiment of the pixel arrangement, the first semiconductor substrate comprises a coupling transistor coupled to the circuit node and the reset transistor.

[0032] In one embodiment of the pixel arrangement, the first semiconductor substrate comprises a third capacitor coupled or connected to a node between the reset transistor and the coupling transistor.

[0033] In one embodiment of the pixel arrangement, the second semiconductor substrate comprises a reset transistor coupled or connected to the supply terminal and the terminal.

[0034] In one embodiment of the pixel arrangement, the first semiconductor substrate comprises a coupling transistor coupled or connected to the circuit node and the terminal.

[0035] In one embodiment of the pixel arrangement, the first semiconductor substrate comprises a bias transistor. The bias transistor is coupled to the output of the amplifier and the reference potential terminal.

[0036] In an alternative embodiment of the pixel arrangement, the second semiconductor substrate comprises the bias transistor.The bias transistor is coupled to the terminal and the reference potential terminal.

[0037] In one embodiment, an image sensor includes a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate includes a photodiode array, a circuit node, a transfer transistor, an amplifier, a terminal, and a first capacitor. The second semiconductor substrate includes a column line, a second capacitor array, another amplifier, and a selection transistor. In one embodiment, the image sensor includes a pixel array, such as an n by m pixel array. In one example, the image sensor includes an evaluation circuit and a row driver, both of which are coupled to the pixel arrangement.

[0038] In one example, the number of transistors in one pixel of the pixel arrangement is 8 or 9. The number is at least 8. The number is less than 12 or less than 10.

[0039] In one embodiment, a method for manufacturing a plurality of image sensors includes:

[0040] manufacturing a first wafer having a first semiconductor substrate,

[0041] manufacturing a second wafer having a second semiconductor substrate,

[0042] Wafer stacking of the first wafer and the second wafer is achieved by wafer bonding,

[0043] A plurality of image sensors are singulating from the wafer stack.

[0044] The first semiconductor substrate includes a photodiode, a circuit node, a transfer transistor coupled to the photodiode and the circuit node, an amplifier having an input terminal connected to the circuit node, and a terminal connected to an output terminal of the amplifier. The second semiconductor substrate includes a second capacitor coupled to the terminal, another amplifier having an input terminal coupled to the second capacitor, a column line, and a selection transistor coupled to the column line and an output terminal of the another amplifier. The first semiconductor substrate or the second semiconductor substrate includes a first capacitor coupled to the terminal.

[0045] Each of the plurality of image sensors includes the first semiconductor substrate and the second semiconductor substrate.

[0046] The above described pixel arrangement and image sensor are particularly suitable for use in a method of manufacturing a plurality of image sensors. Thus, features described in relation to the pixel arrangement and image sensor can be used in the method and vice versa.

[0047] In one embodiment, the transfer transistor, the coupling transistor, the reset transistor, the bias transistor, the first transistor, the second transistor, and the selection transistor are implemented as metal oxide semiconductor field effect transistors, referred to as MOSFETs. For example, each of these transistors can be implemented as an N-channel MOSFET. Alternatively, each of these transistors can also be implemented as a P-channel MOSFET.

[0048] In one example, the pixel arrangement implements a small pixel pitch voltage-domain global-shutter pixel. The image sensor is, for example, a global shutter image sensor. The image sensor can be applied to, for example, consumer, industrial, household and / or automotive markets. The image sensor is configured for, for example, augmented reality / virtual reality devices (AR / VR devices for short), mobile three-domain authentication (mobile 3D authentication for short), drones, barcode scanners, robots, machine vision, security, health monitoring, industrial applications, etc.

[0049] In one example, the image sensor is implemented as a CMOS image sensor (CIS for short) or an image sensor module. The advantage is a smaller pixel pitch, thereby reducing the cost and size of the camera. The pixel arrangement enables a reduction in the pixel pitch of a global shutter image sensor.

[0050] In one example, the pixel is split into two silicon layers or silicon substrates, with the storage capacitors on different silicon layers. Splitting the storage capacitors into two silicon layers allows for a reduction in pixel pitch when capacitor size is limited. In one example, the pixel arrangement allows for a splitting of the pixel capacitors into two semiconductor substrates (e.g., implemented as silicon layers), optionally allowing for a reduction in pixel pitch from, e.g., 2 µm to, e.g., 1.4 µm and below.

[0051] In one example, splitting the storage capacitor into a pixel circuit in two silicon layers results in a smaller pixel pitch. The pixel arrangement is manufactured as a CMOS image sensor, implementing a global shutter or a rolling shutter. The pixel arrangement operates in a voltage domain. The pixel arrangement is sensitive to, for example, near infrared radiation (NIR for short).

[0052] With the alternative method of having two capacitors in one wafer, it is almost impossible to reduce the pixel pitch after downsizing. With the above method, the pixel pitch can be further reduced compared to the alternative method of placing the individual capacitors on the same semiconductor substrate, while maintaining the manufacturing design rules (which is necessary for mass production) and keeping the capacitor value relatively high (good for reducing read noise).

[0053] In one example, the pixel arrangement allows for a reduction in voltage domain global shutter pixel pitch while maintaining a higher capacitor value which is important for reducing read noise. The pixel arrangement includes, for example:

[0054] - Eight or nine transistor voltage domain global shutter pixels.

[0055] - Two high-density metal-to-metal capacitors, or HDMIM for short: one on the first wafer, which is the sensor wafer, and the other on the second wafer.

[0056] - Backside-illuminated image sensor process, referred to as BSI process, which achieves good optical performance (especially NIR responsivity).

[0057] - In-pixel stacking process for stacking the backbone transistors in a second wafer.

[0058] - The second wafer may contain the ASIC circuitry, or the ASIC may be located in a third wafer.

[0059] - The pixel arrangement can operate in rolling shutter (RS) mode, voltage domain global shutter mode or charge domain global shutter mode.

[0060] In one example, the circuit node has a capacitive characteristic. The circuit node has a capacitance such as a diffusion capacitance or a floating diffusion capacitance. Therefore, the charge provided by the photodiode can be applied to the capacitance of the circuit node and the third capacitor through a transfer transistor and a coupling transistor, for example, in a first storage stage. Therefore, by the charge provided by the photodiode stored not only by the capacitance of the circuit node but also by the third capacitor, this charge can be detected with low sensitivity. This reduces the capacitive voltage at the capacitance of the circuit node. This voltage is amplified and stored in, for example, the first capacitor and the second capacitor.

[0061] In one example, in the second storage phase, the charge at the capacitance of the circuit node is not provided to the third capacitor through the coupling transistor. Therefore, by storing the charge provided by the photodiode only by the capacitance of the circuit node and not by the third capacitor, this charge can be detected with high sensitivity. This keeps the voltage fluctuation at the capacitance large. This voltage is amplified and stored in, for example, the first capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The following description of the drawings of examples and embodiments may further illustrate and explain various aspects of pixel arrangements, image sensors, and methods for manufacturing multiple image sensors. Arrangements, devices, circuit blocks, and layers having the same structure and effect are shown using equivalent reference symbols, respectively. Where arrangements, devices, circuit blocks, and layers in different drawings correspond to each other in function, their descriptions are not repeated for each of the following drawings.

[0063] Figures 1A to 1I An exemplary embodiment of a pixel arrangement is shown;

[0064] Figures 2A to 2F An exemplary embodiment of an image sensor having a pixel arrangement is shown in cross section, top view and details thereof; and

[0065] Figure 3 An exemplary embodiment of a method for manufacturing a plurality of image sensors is shown. DETAILED DESCRIPTION

[0066] Figure 1AAn exemplary embodiment of a pixel arrangement 10 is shown. The pixel arrangement 10 includes a first semiconductor substrate 11 and a second semiconductor substrate 12. The first semiconductor substrate 11 includes a first part of the pixel circuit and the second semiconductor substrate 12 includes a second part of the pixel circuit. The first and second semiconductor substrates 11, 12 are made of, for example, silicon. The first semiconductor substrate 11 includes a photodiode 20 and a first capacitor 70. In addition, the first semiconductor substrate 11 includes a circuit node 35, a transfer transistor 30 coupled to the photodiode 20 and the circuit node 35, and an amplifier 60 having an input terminal 62 coupled to the circuit node 35. The transfer transistor 30 may also be referred to as a transfer gate. A first terminal of a controlled path of the transfer transistor 30 is coupled or connected to the photodiode 20 (e.g., a cathode of the photodiode 20). An anode of the photodiode 20 is connected to a ground terminal 19. A second terminal of a controlled path of the transfer transistor 30 is coupled or connected to the circuit node 35.

[0067] Furthermore, the first semiconductor substrate 11 includes a terminal 13. The first capacitor 70 is coupled to the output terminal 64 of the amplifier 60 and the terminal 13. Furthermore, the first semiconductor substrate 11 includes a first transistor 90 coupled to the output terminal 64 of the amplifier 60, the terminal 13, and the first capacitor 70. The first semiconductor substrate 11 includes a reset transistor 50, which is coupled to the power supply terminal 17 and the circuit node 35. The first semiconductor substrate 11 includes a coupling transistor 105, which is coupled to the circuit node 35 and the reset transistor 50. The first semiconductor substrate 11 includes a third capacitor 85, which has a first electrode coupled or connected to a node between the reset transistor 50 and the coupling transistor 105. A second electrode of the third capacitor 85 is connected to the ground terminal 19.

[0068] The first semiconductor substrate 11 includes a bias transistor 65, which is coupled to the output 64 of the amplifier 60 and the reference potential terminal 18. A first terminal of a controlled path of the bias transistor 65 is coupled or connected to the output 64 of the amplifier 60. A second terminal of a controlled path of the bias transistor 65 is coupled or connected to the reference potential terminal 18.

[0069] The first capacitor 70 is connected to the terminal 13. Therefore, the first capacitor 70 includes a first electrode, which is coupled or connected to the node between the first transistor 90 and the terminal 13. A second electrode of the first capacitor 70 is coupled or connected to the further reference potential terminal 14. A first terminal of the controlled path of the first transistor 90 is coupled or connected to the output 64 of the amplifier 60. A second terminal of the controlled path of the first transistor 90 is coupled or connected to the terminal 13 and the first electrode of the first capacitor 70.

[0070] The amplifier 60 comprises an amplifier transistor 61 having a control terminal coupled or connected to an input 62 of the amplifier 60. A first terminal of a controlled path of the amplifier transistor 61 is coupled to the voltage terminal 16. A second terminal of the controlled path of the amplifier transistor 61 is coupled to an output 64 of the amplifier 60. The amplifier 60 is implemented as a source follower.

[0071] The second semiconductor substrate 12 includes a second capacitor 80. The second capacitor 80 is coupled to the terminal 13. The second semiconductor substrate 12 includes another amplifier 110, which has an input terminal 112 coupled to the second capacitor 80. Additionally, the second semiconductor substrate 12 includes a column line 130 and a selection transistor 120, which is coupled to the column line 130 and an output terminal 114 of the other amplifier 110. A first terminal of a controlled path of the selection transistor 120 is coupled or connected to the output terminal 114 of the other amplifier 110. A second terminal of a controlled path of the selection transistor 120 is coupled or connected to the column line 130.

[0072] At least the photodiode 20, the circuit node 35, the transfer transistor 30, the amplifier 60 and the first capacitor 70 are integrated in the first semiconductor substrate 11. At least the second capacitor 80, the further amplifier 110, the column line 130 and the selection transistor 120 are integrated in the second semiconductor substrate 12.

[0073] For example, the capacitance of the first capacitor 70 and the capacitance of the second capacitor 80 are equal or different. The capacitance of the first capacitor 70 is, for example, higher than the value of the capacitance 40 of the circuit node 35. The capacitance of the second capacitor 80 is, for example, higher than the value of the capacitance 40 of the circuit node 35. The capacitance of the third capacitor 85 is, for example, higher than the value of the capacitance 40 of the circuit node 35.

[0074] The capacitance of the first capacitor 70 is in the range of 10 fF to 100 fF, or in the range of 20 fF to 80 fF, or in the range of 30 fF to 50 fF. The capacitance of the second capacitor 80 is in the range of 10 fF to 100 fF, or in the range of 20 fF to 80 fF, or in the range of 30 fF to 50 fF.

[0075] Circuit node 35 has capacitance 40. Capacitor 40 is, for example, a floating diffusion capacitor. Circuit node 35 is, for example, connected to a first terminal of capacitor 40, or is identical to a first terminal of capacitor 40. Capacitor 40 of circuit node 35 includes, for example, the capacitance of a control terminal of amplifier transistor 61, the capacitance of a PN junction of a terminal of transfer transistor 30, and the capacitance of a PN junction of a first terminal of coupling transistor 105. Therefore, parasitic capacitance of transistors connected to circuit node 35 may result in capacitance 40 of circuit node 35. The value of capacitance 40 of circuit node 35 may be the sum of the values ​​of parasitic capacitances of transistors connected to circuit node 35. Optionally, pixel array 10 includes, for example, a capacitor connected to circuit node 35; the capacitor may constitute capacitor 40.

[0076] A second terminal of the capacitor 40 is connected to the ground terminal 19. The reference potential terminal 18 is connected to the ground terminal 19 or is not connected to the ground terminal 19. The other reference potential terminal 14 is connected to the ground terminal 19 or is not connected to the ground terminal 19. The other reference potential terminal 14 is connected to the reference potential terminal 18 or is not connected to the reference potential terminal 18.

[0077] The second semiconductor substrate 12 includes a second transistor 100, and the second transistor 100 is coupled to an input terminal 112 of another amplifier 110 and a second capacitor 80. The second transistor 100 is coupled to the terminal 13. The second capacitor 80 is coupled to the terminal 13 through the second transistor 100. The second capacitor 80 is connected to the input terminal 112 of another amplifier 110. The first transistor and the second transistor 90, 100 may be referred to as a first switch and a second switch.

[0078] The second capacitor 80 comprises a first electrode coupled to a node between the second transistor 100 and an input 112 of the further amplifier 110. A second electrode of the second capacitor 80 is coupled to the further reference potential terminal 14. The further amplifier 110 comprises a further amplifier transistor 111 having a control terminal coupled or connected to the input 112 of the further amplifier 110. A first terminal of a controlled path of the further amplifier transistor 111 is connected to the voltage terminal 16. A second terminal of a controlled path of the further amplifier transistor 111 is coupled or connected to an output 114 of the further amplifier 110. The further amplifier 110 is implemented as a source follower.

[0079] The terminal 13 is implemented as a pixel-level hybrid bonding, PLHB for short, and a metal component or a metal plug configured to provide an electrical connection between the first semiconductor substrate 11 and the second semiconductor substrate 12 .

[0080] The supply voltage VDD is connected to the supply terminal 17. The other supply voltage VDD1 is connected to the voltage terminal 16. The reference potential VSS_PC is connected to the reference potential terminal 18. The other reference potential VSS1 is connected to the other reference potential terminal 14. The supply voltage VDD and the other supply voltage VDD1 are positive relative to the reference potential VSS_PC. The supply voltage VDD and the other supply voltage VDD1 have, for example, different values. The ground potential VSS is connected to the ground terminal 19. The reference potential VSS_PC, the other reference potential VSS1 and the ground potential VSS have, for example, three different values ​​or two different values ​​or equal values.

[0081] The row driver (as shown in FIG. 2 ) is coupled to the control terminal of the transmission transistor 30, the control terminal of the coupling transistor 105, the control terminal of the reset transistor 50, the control terminal of the bias transistor 65, the control terminal of the first transistor 90, the control terminal of the second transistor 100, and the control terminal of the selection transistor 120. The row driver provides a transmission signal TG to the transmission transistor 30, a coupling signal DS to the coupling transistor 105, a reset signal RST to the reset transistor 50, a bias transistor signal PC to the bias transistor 65, a first control signal S1 to the first transistor 90, a second control signal S2 to the second transistor 100, and a selection signal SEL to the selection transistor 120. If the reset signal RST sets the bias transistor 65 to a conductive state, the bias transistor 65 will deliver a bias current to the amplifier 60.

[0082] The pixel arrangement 10 implements a voltage domain global shutter, VGS for short, with a pitch that can be minimized by placing the first and second capacitors 70, 80 in two different wafers and stacking them together to form a pixel. The first and second capacitors 70, 80 are implemented as high density capacitors, for example.

[0083] The implementation of the voltage domain global shutter provides at least two capacitors 70, 80 for sampling the reset level and the signal level. Therefore, the pixel arrangement 10 reduces the pixel pitch and still accommodates two capacitors 70, 80. By this method of two capacitors 70, 80 in two wafers, the pixel pitch can be reduced, so that the total grain size can be reduced. Therefore, the grain size will be suitable for AR / VR applications where the occupied size is very important. The first capacitor 70 is located in the first wafer which is the sensor wafer. The second capacitor 80 is located in the second wafer in which a certain trunk transistor exists. The first capacitor and the second capacitor 70, 80 are metal-insulator-metal capacitors, referred to as MIM capacitors. Since high-density MIM capacitors 70, 80 may consume a large area, placing them in two different wafers allows the pixel pitch to be reduced.

[0084] In the storage phase, charge is stored in the first and second capacitors 70, 80. The capacitor voltage VC of the capacitor 40 connected to the circuit node 35 is amplified by the amplifier 60 and provided to the first and second capacitors 70, 80 through the first and second transistors 90, 100.

[0085] Therefore, the first capacitor 70 stores a voltage obtained by a high conversion gain, and the second capacitor 80 stores an output voltage VO obtained by a low conversion gain. In other words, a low sensitivity signal is stored on the second capacitor 80, and a high sensitivity signal is stored on the first capacitor 70. This achieves good low light performance at a small size pixel arrangement 10 by utilizing dual conversion gains and only three capacitors.

[0086] Alternatively, a voltage with a low conversion gain is stored on the first capacitor 70 , and a voltage with a high conversion gain is stored on the second capacitor 80 .

[0087] The pixel arrangement 10 is used, for example, as a voltage domain global shutter pixel (VGS pixel for short) or a rolling shutter pixel. The two capacitors 70, 80 are used for double conversion gain.

[0088] In an alternative embodiment not shown, the supply terminal 17 is connected to the voltage terminal 16. The supply voltage VDD and the further supply voltage VDD1 are equal.

[0089] In an alternative embodiment not shown, the reference potential terminal 18 is connected to the further reference potential terminal 14. The reference potential VSS_PC and the further reference potential VSS1 are equal.

[0090] Figure 1B An exemplary embodiment of a pixel arrangement 10 is shown. Figure 1A A further extension of the embodiment shown. The second semiconductor substrate 12 comprises a bias transistor 65. The bias transistor 65 is coupled to the terminal 13 and the reference potential terminal 18. A first terminal of the controlled path of the bias transistor 65 is coupled or connected to a node between the terminal 13 and the second transistor 100. A second terminal of the controlled path of the bias transistor 65 is coupled or connected to the reference potential terminal 18.

[0091] Therefore, the number of transistors in the second semiconductor substrate 12 is 4 per pixel and Figure 1A and the number of transistors in the first semiconductor substrate 11 is 5 for each pixel, and Figure 1A Compared to reduced.

[0092] Figure 1C An exemplary embodiment of a pixel arrangement 10 is shown. Figure 1A and Figure 1B Further development of the illustrated embodiment. The second semiconductor substrate 12 comprises a reset transistor 50, which is coupled to the supply terminal 17 and the terminal 13. The first semiconductor substrate 11 comprises a coupling transistor 105, which is coupled to the circuit node 35 and the terminal 13. A first terminal of the controlled path of the coupling transistor 30 is connected to the circuit node 35. A second terminal of the controlled path of the coupling transistor 30 is connected to the terminal 13. The second semiconductor substrate 12 comprises a bias transistor 65, which is coupled to the terminal 13 and the reference potential terminal 18.

[0093] By using the first capacitor 70 as a low gain capacitor and moving the reset transistor 50 to the second wafer, there are now even fewer transistors in the first wafer, potentially further reducing the pixel pitch.

[0094] Figure 1D An exemplary embodiment of a pixel arrangement 10 is shown. Figure 1A to Figure 1C Further extension of the illustrated embodiment. The terminal 13 is coupled to the node between the output 64 of the amplifier 60 and the first transistor 90. Thus, the first capacitor 70 is coupled to the terminal 13 via the first transistor 90. Thus, the first electrode of the first capacitor 70 is coupled or connected to the second terminal of the controlled path of the first transistor 90.

[0095] The first semiconductor substrate 11 comprises an additional amplifier 110' having an input terminal 112' coupled to the first capacitor 70. The first semiconductor substrate 11 comprises an additional selection transistor 120' coupled to an additional column line 130' and an output terminal 114' of the additional amplifier 10'. The first semiconductor substrate 11 comprises an additional column line 130'.

[0096] Hence, the pixel arrangement 10 comprises two column lines 130, 130' for each column. The further amplifier 110 and the additional amplifier 110' implement two output buffers. The pixel arrangement 10 implements a sample-and-hold circuit on the first wafer and the second wafer.

[0097] Figure 1E An exemplary embodiment of a pixel arrangement 10 is shown. Figures 1A to 1D Further development of the illustrated embodiment. The second semiconductor substrate 12 further comprises an additional amplifier 110' having an input 112' coupled or connected to the terminal 13. Thus, the input 112' of the additional amplifier 110' is coupled to the first electrode of the first capacitor 70 via the terminal 13.

[0098] The second semiconductor substrate 12 further comprises an additional selection transistor 120', which is coupled to an additional column line 130' and to an output terminal 114' of the additional amplifier 110'. Optionally, the additional column line 130' is connected to the column line 130. The pixel arrangement 10 implements two output buffers on the second wafer, one sample-and-hold capacitor 70 on the first wafer and another sample-and-hold capacitor 80 on the second wafer.

[0099] Figure 1F An exemplary embodiment of a pixel arrangement 10 is shown. Figures 1A to 1E A further extension of the illustrated embodiment. The second semiconductor substrate 12 comprises a bias transistor 65, which is coupled to the terminal 13 and the reference potential terminal 18. Thus, the bias transistor 65 couples the node between the terminal 13 and the second transistor 100 to the reference potential terminal 18. The pixel arrangement 10 implements the bias transistor 65 on the second wafer.

[0100] Figure 1G An exemplary embodiment of a pixel arrangement 10 is shown. Figures 1A to 1F A further extension of the illustrated embodiment. The second capacitor 80 is connected to the terminal 13, the second transistor 100 and the input 112 of the further amplifier 110. The terminal 13 is coupled to the second transistor 100 and the input 112 of the further amplifier 110 via the second capacitor 80. The second capacitor 80 comprises a first electrode coupled to the terminal 13, and a second electrode coupled to a node between the second transistor 100 and the input 112 of the further amplifier 110. The pixel arrangement 10 implements the output buffer 110 and the second capacitor 80 on a second wafer. The second transistor 100 is connected to a reference voltage VREF.

[0101] Figure 1H An exemplary embodiment of a pixel arrangement 10 is shown. Figures 1A to 1G Further development of the illustrated embodiment. The second semiconductor substrate 12 comprises a first capacitor 70. The second semiconductor substrate 12 further comprises, for example, a first transistor 90. The first capacitor 70 is coupled to the terminal 13 via the first transistor 90. The first capacitor 70 is connected to the first transistor 90, and the first transistor 90 is connected to the terminal 13 and to an input 112 of a further amplifier 110. In other words, a first electrode of the first capacitor 70 is coupled or connected to the first transistor 90. A second electrode of the first capacitor 70 is coupled or connected to a further reference potential terminal 14.

[0102] The first semiconductor substrate 11 comprises a further selection transistor 120 ″ which couples the output 64 of the amplifier 60 to the terminal 13 . The first semiconductor substrate 11 comprises a bias transistor 65 which couples the terminal 13 to the reference potential terminal 18 .

[0103] The second capacitor 80 is connected to the second transistor 100, and the second transistor 100 is connected to the terminal 13 and the input 112 of the further amplifier 110. Therefore, the second capacitor 80 is coupled to the terminal 13 via the second transistor 100. In other words, the first electrode of the second capacitor 80 is coupled or connected to the second transistor 100. The second electrode of the second capacitor 80 is coupled or connected to the further reference potential terminal 14. The terminal 13 is directly connected to the input 112 of the further amplifier 110.

[0104] exist Figures 1A to 1C , Figure 1E to Figure 1G or Fig. 1I In the example of the embodiment shown, the second semiconductor substrate 12 comprises a first capacitor 70. The second semiconductor substrate 12 also comprises, for example, a first transistor 90. The first capacitor and the second capacitor 80 are arranged on top of each other; in other words, they are located in a stacked configuration.

[0105] Fig. 1I An exemplary embodiment of a pixel arrangement 10 is shown. Figures 1A to 1H A further extension of the illustrated embodiment. The first semiconductor substrate 11 comprises a first capacitor 70 and a first transistor 90. The first capacitor 70 is coupled to the terminal 13 via the first transistor 90. Optionally, the first semiconductor substrate 11 comprises another first capacitor 71 and another first transistor 91. The other first capacitor 71 is coupled to the terminal 13 via the other first transistor 91. Therefore, the first semiconductor substrate 11 comprises a first number of series circuits. Each series circuit comprises a capacitor and a transistor. The capacitor is implemented, for example, as a first capacitor and another first capacitor 70, 71. The transistor is implemented, for example, as a first transistor and another first transistor 90, 91. Each of the first number of series circuits couples the terminal 13 to another reference potential terminal 14. As Figure 1H As shown, the first number is, for example, 0. Fig. 1I As shown, the first number is, for example, 2. The first number may be 0, 1, 2, or 3, or at least 0, at least 1, or at least 2. The capacitance values ​​of the capacitors 70, 71 of the first number of series circuits are equal or have at least two different values.

[0106] Optionally, the second semiconductor substrate 12 includes another second capacitor 81 and another second transistor 101. The other second capacitor 81 is coupled to the terminal 13 via the other second transistor 101. Therefore, the second semiconductor substrate 12 includes a second number of series circuits. Each series circuit includes a capacitor and a transistor. The capacitor is implemented as, for example, a second capacitor and another second capacitor 80, 81. The transistor is implemented as, for example, a second transistor and another second transistor 100, 101. Each of the second number of series circuits couples the terminal 13 to another reference potential terminal 14. Figure 1H and Fig. 1I As shown, the second number is, for example, 2. The second number may be 1 or 2 or 3 or at least 1 or at least 2. The capacitance values ​​of the capacitors 80, 81 of the second number of series circuits are equal or have at least two different values. The first number and the second number are equal or different.

[0107] FIG. 1A to FIG. 1I The transistors 30, 50, 61, 65, 90, 100, 105, 111, 120, etc. shown are field effect transistors, or FETs for short. These transistors are, for example, metal-oxide-semiconductor FETs, or MOSFETs for short. The MOSFETs are, for example, N-channel MOSFETs.

[0108] Figure 2A An exemplary embodiment of an image sensor 200 having a pixel arrangement 10 is shown in cross section. FIG. 1A to FIG. 1I Further extension of the illustrated embodiment. The first semiconductor substrate 11 has a first face 181 and a second face 182. The second semiconductor substrate 12 has a first face 183 and a second face 184. The first face 181 of the first semiconductor substrate 11 is attached to the first face 183 of the second semiconductor substrate 12. The second face 182 of the first semiconductor substrate 11 is configured for receiving electromagnetic radiation IL.

[0109] The first semiconductor substrate 11 of the image sensor 200 includes an array of photodiodes 20, a circuit node 35, a transfer transistor 30, an amplifier 60, a terminal 13, a first capacitor 70, etc. The second semiconductor substrate 12 of the image sensor 200 includes a column line 130 and an array of second capacitors 80, another amplifier 110, a selection transistor 120, etc. Figure 2A In the example shown, the image sensor 200 includes three pixels 201 to 203. The three pixels 201 to 203 are implemented identically, for example.

[0110] The first semiconductor substrate 11 is part of a sensor wafer (referred to as the first wafer) containing the first capacitor 70. The second semiconductor substrate 12 is part of a main transistor wafer with the second capacitor 80 and with or without an application specific integrated circuit (referred to as ASIC). The terminal 13 implements pixel-level hybrid bonding, referred to as PLHB.

[0111] In an alternative embodiment not shown, the pixel arrangement 10 (and thus the image sensor 200) comprises a third semiconductor substrate. The third semiconductor substrate is implemented as an ASIC. The third semiconductor substrate comprises, for example, a row driver (e.g. Figure 2B as shown).

[0112] Figure 2B An exemplary embodiment of an image sensor 200 having a pixel arrangement 10 is shown in a top view. FIG. 1A to FIG. 1I and Figure 2A A further extension of the embodiment shown. Figure 2B , a view of the first face 183 of the second semiconductor substrate 12 is shown.

[0113] The image sensor 200 further comprises a row driver 204 which provides a transmission signal TG, a coupling signal DS, a reset signal RST, a bias transistor signal PC, a first control signal S1, a second control signal S2 and a selection signal SEL to the pixel arrangement 10. The row driver 204 provides these signals for each row. The image sensor 200 comprises an evaluation circuit 205 for digitizing the signals at the column lines 130. The pixel arrangement 10 comprises n×m pixels 201 to 203 arranged in an array configuration.

[0114] Figure 2C An exemplary embodiment of a capacitor is shown, which is a further extension of the first and second capacitors 70, 80 shown above. The capacitor is implemented as a metal-insulator-metal capacitor 185, referred to as a MIM capacitor. The MIM capacitor 185 is a flat plate capacitor. The MIM capacitor 185 has a first electrode 188 and a second electrode 189, which are implemented as, for example, conductive plates. An insulating layer 190 separates the first electrode 188 from the second electrode 189. The first electrode 188 is made of, for example, metal, polysilicon or silicide. The second electrode 189 is made of, for example, metal, polysilicon or silicide. The insulating layer 190 is made of, for example, silicon dioxide, silicon nitride, aluminum oxide or aluminum nitride.

[0115] Metal-insulator-metal capacitor 185 is, for example, a high-density capacitor. Insulating layer 190 of metal-insulator-metal capacitor 185 is a high-density material or a high-k material. Aluminum oxide or aluminum nitride are examples of high-density materials with a high dielectric constant.

[0116] In one example, the first capacitor 70 includes or is implemented as a MIM capacitor 185. In one example, the second capacitor 80 includes or is implemented as a MIM capacitor 185.

[0117] Figure 2D An exemplary embodiment of a capacitor is shown, which is a further extension of the first capacitor and the second capacitor 70, 80 shown above. The capacitor is implemented as an interdigital capacitor 186, referred to as IDC. The capacitor is, for example, a planar capacitor. The IDC 186 capacitor 185 has a first electrode 188 including interconnected parallel stripes. The IDC 186 has a second electrode 189 including interconnected parallel stripes. The stripes of the first electrode 188 and the stripes of the second electrode 189 have gaps. The first electrode and the second electrode 188, 189 are arranged between two insulating layers. Therefore, the gap is filled with insulating material. Sometimes, the IDC 186 is called a metal-oxide-metal capacitor, referred to as MOM.

[0118] The first and second electrodes 188, 189 are made of, for example, metal, polysilicon, or silicide. The insulating layer is made of, for example, silicon dioxide, silicon nitride, aluminum oxide, or aluminum nitride.

[0119] In one example, the first capacitor 70 includes or is implemented as an IDC 186. In one example, the second capacitor 80 includes or is implemented as an IDC 186.

[0120] Figure 2E An exemplary embodiment of a capacitor is shown, which is a further development of the first and second capacitors 70, 80. The capacitor is implemented as a metal-oxide-semiconductor capacitor 187, or MOS capacitor for short. The MOS capacitor 187 has a first electrode 188 implemented, for example, as a conductive plate. The first electrode 188 is made of, for example, metal, polysilicon or silicide. The second electrode 189 is implemented as a semiconductor portion or semiconductor layer. An insulating layer 190 separates the first electrode 188 from the second electrode 189. The insulating layer 190 is made of, for example, silicon dioxide, silicon nitride, aluminum oxide or aluminum nitride. The MOS capacitor 187 has a high capacitance value that depends on the voltage between the first and second electrodes 188, 189.

[0121] In one example, the first capacitor 70 includes or is implemented as a MOS capacitor 187. In one example, the second capacitor 80 includes or is implemented as a MOS capacitor 187.

[0122] The first capacitor 70 and the second capacitor 80 may both be implemented as MIM capacitors 185, both be implemented as IDCs 187, or both be implemented as MOS capacitors 186. Alternatively, the first capacitor 70 and the second capacitor 80 are implemented differently.

[0123] Figure 2F An exemplary embodiment of a cross section of the second semiconductor substrate 12 is shown, which is an exemplary embodiment of the above-described embodiment (particularly Figure 1H ). The second semiconductor substrate 12 includes a metallization layer stack 191, which includes a plurality of metallization layers 193-197. The metallization layer stack 191 is arranged on top of a semiconductor layer 192 (such as a single crystal silicon layer) of the second semiconductor substrate 12. The second capacitor 80 is implemented by the first and second metallization layers 193, 194 of the metallization layer stack 191 and a first insulating layer 198. The first and second metallization layers 193, 194 are directly adjacent to each other. The first insulating layer 198 separates the first and second metallization layers 193, 194.

[0124] Accordingly, the first capacitor 70 is realized by the third and fourth metallization layers 195, 196 of the metallization layer stack 191 and the second insulating layer 199. The third and fourth metallization layers 195, 196 are directly adjacent to each other. The second insulating layer 199 separates the third and fourth metallization layers 195, 196.

[0125] Alternatively, the first capacitor 70 can be implemented by the second and third metallization layers 194, 195 of the metallization layer stack 191 and the second insulating layer 199. The second and third metallization layers 194, 195 are directly adjacent to each other. The second insulating layer 199 separates the second and third metallization layers 194, 195. Therefore, the first capacitor and the second capacitor 70, 80 have a common electrode, which is connected to the other reference potential terminal 14 in one example.

[0126] The first and second capacitors 70, 80 are configured as metal-insulator-metal capacitors 185, such as Figure 2C The first and second insulating layers 198 and 199 are implemented as, for example, interlayer dielectric layers.

[0127] The first capacitor 70 and the second capacitor 80 are placed on top of each other in the cross section of the pixel arrangement 10. Thus, the area of ​​the second semiconductor substrate 12 (eg as shown in the top view) is used very efficiently.

[0128] Optionally, the metallization layer stack 191 includes at least a fifth metallization layer 197 , which is arranged between the fourth metallization layer 196 and the first surface 183 of the second semiconductor substrate 12 , and / or between the first metallization layer 193 and the semiconductor layer 192 , and / or between the second metallization layer 193 and the third metallization layer 194 .

[0129] In alternative embodiments, one of the first capacitor 70 and the second capacitor 80 is implemented as a metal-insulator-metal capacitor 185 or an interdigital capacitor 186, and the other of the first capacitor 70 and the second capacitor 80 is implemented as a metal-insulator-metal capacitor 185, an interdigital capacitor 186, or a metal-oxide-semiconductor capacitor 187. Therefore, different implementations of the first capacitor 70 and the second capacitor 80 inside the second semiconductor substrate 12 are possible.

[0130] Figure 3 An exemplary embodiment for manufacturing a plurality of image sensors 200 is shown, which is a further extension of the above-mentioned embodiment. The method for manufacturing a plurality of image sensors 200 includes:

[0131] - manufacturing a first wafer having a first semiconductor substrate 11 by means of steps 221 to 225 of the first series 210 ;

[0132] - manufacturing a second wafer with a second semiconductor substrate 12 by means of steps 226 to 229 of the second series 211 ;

[0133] - realizing a wafer stack of the first wafer and the second wafer by wafer bonding and singulating a plurality of image sensors 200 from the wafer stack by steps 230 to 233 of the third series 212 .

[0134] Steps 221 to 225 of the first series 210 include manufacturing a sensor wafer having photodiodes 20. The following steps are examples of steps of the first series 210:

[0135] Step 221: Perform shallow trench isolation, or STI for short.

[0136] Step 222 : forming a photodiode 20 .

[0137] Step 223: Fabricate a transistor having a source, a drain and a gate.

[0138] Step 224: Implementing contacts.

[0139] Step 225: Back-end of the line (BEOL) circuit elements such as transistors, first capacitor 70, a portion of terminal 13, photodiode 20, etc. are interconnected through one or more metallization layers.

[0140] Steps 226 to 229 of the second series 211 comprise manufacturing a transistor wafer with or without row drivers 204 and with or without evaluation circuits 205. The following steps are examples of steps of the second series 211:

[0141] Step 226: Perform shallow trench isolation, or STI for short.

[0142] Step 227: Fabricate a transistor having a source, a drain and a gate.

[0143] Step 228: Implementing contacts.

[0144] Step 229: Back-end of the line (BEOL) circuit elements such as transistors, the second capacitor 80, another portion of the terminal 13, the photodiode 20, etc. are interconnected through one or more metallization layers.

[0145] Steps 230 to 233 of the third series 212 include fabricating two wafers together. The following steps are examples of steps of the third series 212:

[0146] Step 230 : Flip the first wafer (ie, the sensor wafer) and bond it to the second wafer (ie, the ASIC wafer).

[0147] Step 231: Wafer thinning of the first wafer.

[0148] Step 232: Etching of deep trenches on the back side and formation of near infrared (NIR) structures (optionally implementing contacts).

[0149] Step 233: Forming a pad (eg, a bonding pad).

[0150] The pixel arrangement 10 is used for example as a voltage domain global shutter pixel, VGS pixel for short. Alternatively, the pixel arrangement 10 is implemented as for example a rolling shutter pixel. The two capacitors 70, 80 are used for double conversion gain.

[0151] The invention is not limited to the description of the exemplary embodiments. On the contrary, the invention comprises every new feature and every combination of features, in particular every combination of features of the claims, even if this feature or combination of features itself is not explicitly mentioned in the claims or exemplary embodiments.

[0152] Reference Number

[0153] 10 pixel layout

[0154] 11First semiconductor substrate

[0155] 12 second semiconductor substrate

[0156] 13 terminals

[0157] 14 Another reference potential terminal

[0158] 16 Voltage terminals

[0159] 17 Power supply terminal

[0160] 18 Reference potential terminal

[0161] 19 Ground terminal

[0162] 20, 20' Photodiode

[0163] 30, 30' transfer transistor

[0164] 35 circuit nodes

[0165] 40 Capacitor

[0166] 50 Reset transistor

[0167] 60 Amplifier

[0168] 61 Amplifier Transistor

[0169] 62 Input

[0170] 64 output ports

[0171] 65 Bias transistor

[0172] 70, 71 first capacitor

[0173] 80, 81 second capacitor

[0174] 85 The third capacitor

[0175] 90, 91 first resistor

[0176] 100, 101 second resistor

[0177] 105 coupling transistor

[0178] 110, 110' Another amplifier

[0179] 111, 111' another amplifier transistor

[0180] 112, 112' input terminal

[0181] 114, 114' output

[0182] 120, 120', 120'' selection transistor

[0183] 130, 130' line

[0184] 181, 183 Page 1

[0185] 182, 184 Page 2

[0186] 185 Metal-Insulator-Metal Capacitor

[0187] 186 Interdigital Capacitor

[0188] 187 Metal-Oxide-Semiconductor Capacitor

[0189] 188, 189 electrodes

[0190] 190 Insulation Layer

[0191] 191 Metallization layer stack

[0192] 192Semiconductor layer

[0193] 193-197 metallization layer

[0194] 198, 199 insulation layer

[0195] 200 Image Sensor

[0196] 201, 202, 203 pixels

[0197] 204 line drivers

[0198] 205 Evaluation Circuit

[0199] Series 210 to 212

[0200] Steps 221 to 233

[0201] DS coupled signal

[0202] IL Electromagnetic Radiation

[0203] PC bias transistor signal

[0204] Q, Q' charge

[0205] RST reset signal

[0206] SEL, SEL' selection signal

[0207] S1 first control signal

[0208] S2 second control signal

[0209] TG, TG' transmission signal

[0210] VC capacitor voltage

[0211] VDD supply voltage

[0212] VDD1 Another supply voltage

[0213] VO output voltage

[0214] VREF reference voltage

[0215] VSS ground potential

[0216] VSS1 Another reference potential

[0217] VSS_PC reference potential

Claims

1. A pixel arrangement (10), comprising: a first semiconductor substrate (11), and a second semiconductor substrate (12), The first semiconductor substrate (11) comprises: Photodiode (20), Circuit Node (35), a transfer transistor (30) coupled to the photodiode (20) and the circuit node (35), an amplifier (60) having an input terminal (62) coupled to the circuit node (35), a terminal (13) coupled to an output terminal (64) of the amplifier (60), The second semiconductor substrate (12) comprises: a second capacitor (80) coupled to the terminal (13), another amplifier (110) having an input terminal (112) coupled to the second capacitor (80), Column lines (130), and a selection transistor (120) coupled to the column line (130) and the output terminal (114) of the further amplifier (110), The first semiconductor substrate or the second semiconductor substrate (11, 12) comprises a first capacitor (70) coupled to the terminal (13).

2. The pixel arrangement (10) according to claim 1, Wherein in a cross section of the pixel arrangement (10), the first capacitor (70) and the second capacitor (80) are placed on top of each other.

3. The pixel arrangement (10) according to claim 1 or 2, The first semiconductor substrate (11) has a first surface (181) and a second surface (182), The second semiconductor substrate (12) has a first surface (183) and a second surface (184), wherein the first side (181) of the first semiconductor substrate (11) is attached to the first side (183) of the second semiconductor substrate (12), and The second side (182) of the first semiconductor substrate (11) is configured to receive electromagnetic radiation (IL).

4. The pixel arrangement (10) according to claim 1, The first capacitor (70) comprises one of the group consisting of: a metal-insulator-metal capacitor (185), an interdigital capacitor (186), and a metal-oxide-semiconductor capacitor (187).

5. The pixel arrangement (10) according to claim 1, The second capacitor (80) comprises one of the group consisting of: a metal-insulator-metal capacitor (185), an interdigital capacitor (186) and a metal-oxide-semiconductor capacitor (187).

6. The pixel arrangement (10) according to claim 1, The capacitance of the first capacitor (70) is in the range of 10 fF to 100 fF.

7. The pixel arrangement (10) according to claim 1, The capacitance of the second capacitor (80) is in the range of 10 fF to 100 fF.

8. The pixel arrangement (10) according to claim 1, The first semiconductor substrate (11) includes a first transistor (90) coupled to an output end (64) of the amplifier (60), the terminal (13) and the first capacitor (70).

9. The pixel arrangement (10) according to claim 8, wherein the first capacitor (70) is connected to the terminal (13), or The first capacitor (70) is coupled to the terminal (13) via the first transistor (90).

10. The pixel arrangement (10) according to claim 1, The second semiconductor substrate (12) includes a second transistor (100) coupled to an input terminal (112) of the other amplifier (110) and the second capacitor (80).

11. The pixel arrangement (10) according to claim 10, wherein the second capacitor (80) is coupled to the terminal (13) via the second transistor (100) and is connected to the input terminal (112) of the further amplifier (110), or wherein the second capacitor (80) is connected to the terminal (13), the second transistor (100) and the input (112) of the further amplifier (110), or The second capacitor (80) is connected to the second transistor (100), and the second transistor (100) is connected to the terminal (13) and the input (112) of the further amplifier (110).

12. The pixel arrangement (10) according to claim 1, The first semiconductor substrate (11) includes a reset transistor (50) coupled to a power supply terminal (17) and the circuit node (35).

13. The pixel arrangement (10) according to claim 12, The first semiconductor substrate (11) includes a coupling transistor (105) coupled to the circuit node (35) and the reset transistor (50).

14. The pixel arrangement (10) according to claim 13, The first semiconductor substrate (11) includes a third capacitor (85) coupled to a node between the reset transistor (50) and the coupling transistor (105).

15. The pixel arrangement (10) according to claim 1, The second semiconductor substrate (12) includes a reset transistor (50) coupled to a power supply terminal (17) and the terminal (13).

16. The pixel arrangement (10) according to claim 1, The first semiconductor substrate (11) includes a coupling transistor (105) coupled to the circuit node (35) and the terminal (13).

17. The pixel arrangement (10) according to one of claims 1 to 16, The first semiconductor substrate (11) includes a bias transistor (65) coupled to an output terminal (64) of the amplifier (60) and a reference potential terminal (18).

18. The pixel arrangement (10) according to one of claims 1 to 16, The second semiconductor substrate (12) includes a bias transistor (65) coupled to the terminal (13) and a reference potential terminal (18).

19. The image sensor (200) according to any one of claims 1 to 18, wherein the first semiconductor substrate (11) comprises an array of photodiodes (20), a circuit node (35), a transfer transistor (30), an amplifier (60), a terminal (13) and a first capacitor (70), and The second semiconductor substrate (12) includes a column line (130) and an array of second capacitors (80), another amplifier (110) and a selection transistor (120).

20. A method for manufacturing a plurality of image sensors (200), comprising: manufacturing a first wafer having a first semiconductor substrate (11), manufacturing a second wafer having a second semiconductor substrate (12), realizing wafer stacking of the first wafer and the second wafer by wafer bonding, and singulating a plurality of image sensors (200) from the wafer stack, The first semiconductor substrate (11) comprises: Photodiode (20), Circuit Node (35), a transfer transistor (30) coupled to the photodiode (20) and the circuit node (35), an amplifier (60) having an input terminal (62) coupled to the circuit node (35), and A terminal (13) coupled to an output terminal (64) of the amplifier (60), and The second semiconductor substrate (12) comprises: a second capacitor (80), coupled to the terminal (13), another amplifier (110) having an input terminal (112) coupled to the second capacitor (80), Column lines (130), and a select transistor (120) coupled to the column line (130) and the output terminal (114) of the further amplifier (110), The first semiconductor substrate or the second semiconductor substrate (11, 12) comprises a first capacitor (70) coupled to the terminal (13).

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