Phase shifter construction method and apparatus, electronic device, and storage medium

Abstract

The present disclosure provides a phase shifter construction method and device, electronic equipment and storage medium, and relates to the technical field of test circuit. The method comprises the following steps: constructing a virtual LFSR which is dual to an actual LFSR, the virtual LFSR comprising a plurality of register units connected in sequence, and the plurality of register units being divided into a plurality of register groups. The following steps are repeatedly executed until the corresponding relationship between each XOR unit and the register unit is obtained. The virtual LFSR is controlled to run continuously for a preset number of clock cycles; the number of target register groups in which the register unit with a unique unit value of 1 exists in the virtual LFSR is obtained; in the case that the number of target register groups is within a preset number range, any XOR unit which has not established a corresponding relationship with the register unit is selected, and a corresponding relationship is established between the XOR unit and the register unit with a unit value of 1 in each target register group. The present disclosure can improve the construction speed of the phase shifter, and to a certain extent, improve the fault coverage of the test circuit.

Description

Technical Field

[0001] This disclosure relates to the field of test circuit technology, and in particular to a phase shifter construction method, apparatus, electronic device and storage medium. Background Technology

[0002] Phase shifters are a commonly used test circuit structure in the built-in self-test of large-scale integrated circuits. They enable the test stimulus generation circuit to drive more scan chains simultaneously and reduce the correlation between the output data of adjacent register cells, thereby improving the fault coverage of the test.

[0003] In related technologies, the construction of phase shifters is relatively complex and requires a lot of time. Summary of the Invention

[0004] To overcome the problems existing in related technologies, this disclosure provides a phase shifter construction method, apparatus, electronic device and storage medium.

[0005] According to a first aspect of the present disclosure, a method for constructing a phase shifter is provided, the method being used to construct a phase shifter in a test excitation generation circuit, the test excitation generation circuit including an actual LFSR and a plurality of XOR units;

[0006] The method includes:

[0007] A virtual LFSR is constructed that is dual to the actual LFSR. The virtual LFSR includes multiple register units connected in sequence. The multiple register units are divided into multiple register groups, and the register units in each register group are connected in series.

[0008] Repeat the following steps until the correspondence between each XOR unit and register unit is obtained, so that the XOR units in the test stimulus generation circuit can be constructed as phase shifters:

[0009] The virtual LFSR is controlled to run continuously for a preset number of clock cycles;

[0010] Obtain the number of target register groups in the virtual LFSR; wherein, a target register group is a register group that has a unique register cell with a value of 1;

[0011] If the number of target register groups in the virtual LFSR is within a preset range, select any XOR unit that has not established a correspondence with a register unit, and establish a correspondence between the XOR unit and the register units in each target register group whose unit value is 1.

[0012] In some embodiments, constructing a virtual LFSR that is dual to the actual LFSR includes:

[0013] The number of register units and the number of register groups in the virtual LFSR are determined based on the number of objects to be driven; wherein, the objects to be driven include: the scan chain and / or the first-level input port in the circuit under test, and the circuit under test is the circuit used for testing by the test stimulus generation circuit;

[0014] Based on the number of register units and the number of register groups in the virtual LFSR, the register units in the virtual LFSR are divided into multiple register groups;

[0015] Based on the number of register units and the grouping method, the target primitive polynomial is selected from the primitive polynomial library;

[0016] Based on the target primitive polynomial, a virtual LFSR that is dual to the actual LFSR is constructed.

[0017] In some embodiments, the number of register units in the virtual LFSR is calculated as follows:

[0018] Calculate the first combination number of randomly selected m different register units from n register units, where m is the upper limit of the preset number range, and n and m are both positive integers;

[0019] The minimum value of n when the first combination number is greater than or equal to the first combination number threshold is taken as the number of register units in the virtual LFSR;

[0020] Wherein, the first combination number threshold is the product of the order-limited scaling factor α and the number of the objects to be driven, and α≥5.

[0021] In some embodiments, the number of register groups in the virtual LFSR is calculated as follows:

[0022] Calculate the second combination number from g register groups, randomly selecting m different register groups, where m is the upper limit of the preset number range, and g and m are both positive integers;

[0023] When the second combination number is greater than or equal to the second combination number threshold, the minimum value of g is taken as the number of register groups in the virtual LFSR;

[0024] Wherein, the second combination number threshold is the product of the group number limitation ratio factor β and the number of objects to be driven, 0<β≤1.

[0025] In some embodiments, selecting a target primitive polynomial from the primitive polynomial library based on the number and grouping method of register units includes:

[0026] Select any candidate primitive polynomial from the primitive polynomial library. The order of the candidate primitive polynomial is n, where n is the number of register units in the virtual LFSR.

[0027] If the candidate primitive polynomial satisfies the preferred condition, then the candidate primitive polynomial is taken as the target primitive polynomial.

[0028] The preferred condition is that for each register group in the virtual LFSR, there are multiple terms with a coefficient of 1 in the candidate primitive polynomial.

[0029] In some embodiments, the method further includes:

[0030] If none of the candidate primitive polynomials in the primitive polynomial library satisfy the preferred condition, then the candidate primitive polynomial in the primitive polynomial library with the most terms that satisfy the alternative condition and have a coefficient of 1 is taken as the target primitive polynomial.

[0031] The candidate condition is that for each register group in the virtual LFSR, there is at least one term with a coefficient of 1 in the candidate primitive polynomial.

[0032] In some embodiments, the preset quantity range is the range of the number of input ports for each XOR unit, and the method further includes:

[0033] The range of the number of input ports is determined based on the number of scan chains in the circuit under test;

[0034] The circuit under test is the circuit used for testing by the test stimulus generation circuit, and a mapping relationship is pre-established between the number of scan chains and the range of the number of input ports.

[0035] According to a second aspect of the present disclosure, a phase shifter construction apparatus is provided, the apparatus being used to construct a phase shifter in a test excitation generation circuit, the test excitation generation circuit including an actual LFSR and a plurality of XOR units;

[0036] The device includes:

[0037] The construction module is used to construct a virtual LFSR that is the counterpart of the actual LFSR. The virtual LFSR includes multiple register units connected in sequence. The multiple register units are divided into multiple register groups, and the register units in each register group are connected in series.

[0038] An execution module is used to repeatedly execute the following steps until the correspondence between each XOR unit and register unit is obtained, so as to construct the XOR units in the test stimulus generation circuit as phase shifters:

[0039] The virtual LFSR is controlled to run continuously for a preset number of clock cycles;

[0040] Obtain the number of target register groups in the virtual LFSR; wherein, a target register group is a register group that has a unique register cell with a value of 1;

[0041] If the number of target register groups in the virtual LFSR is within a preset range, select any XOR unit that has not established a correspondence with a register unit, and establish a correspondence between the XOR unit and the register units in each target register group whose unit value is 1.

[0042] According to a third aspect of the present disclosure, an electronic device is provided, comprising:

[0043] Processor; and

[0044] Memory for storing the executable instructions of the processor;

[0045] The processor is configured to execute the method described in the first aspect by executing the executable instructions.

[0046] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method described in the first aspect.

[0047] The solution provided in this disclosure allows for the grouping of register cells in a virtual LFSR during the construction of a phase shifter, with each input of the same XOR cell corresponding to a register cell from a different register group. This method reduces the computational load during phase shifter construction, increases construction speed, and improves fault coverage of the test circuit to some extent. Attached Figure Description

[0048] Figure 1 A schematic diagram of a built-in self-test circuit is shown in an embodiment of this disclosure.

[0049] Figure 2 A schematic diagram of the structure of an XOR unit in an embodiment of this disclosure is shown.

[0050] Figure 3 A schematic flowchart of a phase shifter construction method according to an embodiment of the present disclosure is shown.

[0051] Figure 4 The diagram shows the structural schematics of two types of LFSRs in the embodiments of this disclosure.

[0052] Figure 5 A schematic diagram of the constructed phase shifter in an embodiment of this disclosure is shown.

[0053] Figure 6 The diagram shows a flowchart of a virtual LFSR construction method according to an embodiment of the present disclosure.

[0054] Figure 7 A schematic diagram showing the correspondence between primitive polynomials and LFSRs in an embodiment of this disclosure is provided.

[0055] Figure 8 A flowchart illustrating a method for selecting primitive polynomials in an embodiment of this disclosure is shown.

[0056] Figure 9 A flowchart illustrating a method for determining the number of register units in an embodiment of this disclosure is shown.

[0057] Figure 10 A logical schematic diagram of the method for determining the number of register units in an embodiment of this disclosure is shown.

[0058] Figure 11 This diagram illustrates a flowchart of a method for determining the number of register groups according to an embodiment of the present disclosure.

[0059] Figure 12 A logical schematic diagram of the method for determining the number of register groups in an embodiment of this disclosure is shown.

[0060] Figure 13 A schematic diagram of a phase shifter construction device according to an embodiment of the present disclosure is shown.

[0061] Figure 14 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0062] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0063] Built-in Self-Test (BIST) refers to the use of internal self-test circuitry within integrated circuit design to perform fault testing on the circuit itself without the need for external test equipment. Scan-based BIST schemes are common in BIST technology. However, single-scan chain test schemes have long testing times. To reduce testing time, multi-scan chain BIST schemes combining serial and parallel methods can be used.

[0064] In built-in self-test circuits based on multi-scan chains, test vectors can be generated using a linear feedback shift register (LFSR). Due to the inherent structural dependence of the LFSR, the generated test vectors can be correlated; that is, the value of each register cell in the LFSR is adjusted by simply left- or right-shifting the value of its adjacent register cell from the previous clock cycle. To address this and achieve higher fault coverage in the built-in self-test circuit, a phase shifter can be added to reduce the correlation between test vectors shifted into the scan chain.

[0065] For example, Figure 1 A schematic diagram of a built-in self-test circuit according to an embodiment of this disclosure is shown. Figure 1 As shown, in the built-in self-test circuit, the phase shifter is located between the LFSR and the scan chain, and it can be composed of XOR units. Figure 1 In this process, the pseudo-random numbers generated by the LFSR are input into the phase shifter, which further reduces the correlation between the outputs of adjacent register cells in the LFSR. This allows the test data output to the scan chain via the phase shifter to cover more fault test types. The outputs of each scan chain are finally aggregated into a multi-input feature register (MIR). The MIR compresses the test responses of each scan chain output, and the obtained feature values ​​are compared to determine whether the circuit under test passes the test.

[0066] It is worth noting that, despite Figure 1 In the phase shifter shown, each XOR unit is an XOR gate with two inputs. However, in practical applications, the number of inputs to the XOR unit can be arbitrary.

[0067] For example, Figure 2 A schematic diagram of an XOR unit with multiple inputs is shown. It can be understood that a single XOR gate has two inputs. By cascading multiple XOR gates, an XOR unit with multiple inputs can be obtained. For example, in... Figure 2 In this context, by cascading seven XOR gates, each with two inputs, a single XOR unit with eight inputs can be obtained.

[0068] For example, when it is desired to use an XOR unit with an odd number of inputs, an XOR unit with an even number of inputs, containing more inputs than desired, can be constructed first, and one or more inputs can be fixed to 0. For instance, when it is desired to obtain an XOR unit with seven inputs, any one of the inputs can be fixed to 0 based on the aforementioned XOR unit with eight inputs.

[0069] The application scenarios and basic concepts involved in this disclosure have been introduced above. The specific implementation methods of this disclosure will be described in detail below.

[0070] First, this disclosure provides a method for constructing a phase shifter, which can be executed by any electronic device to construct a phase shifter in a test stimulus generation circuit. Specifically, the test stimulus generation circuit is a circuit built into a self-test circuit used to generate test stimuli, and it can consist of an LFSR and an XOR unit (used to construct a phase shifter). By executing the method of this disclosure, the correspondence between the XOR unit in the test stimulus generation circuit and the register unit (in the LFSR) can be obtained. Subsequently, in the test stimulus generation circuit, the XOR unit and the register unit are connected according to this correspondence, thereby constructing the XOR unit as a phase shifter to improve the randomness of the test vector output by the LFSR.

[0071] Figure 3 This diagram illustrates a flow chart of a phase shifter construction method according to an embodiment of the present disclosure, as shown below. Figure 3 As shown, the method includes the following steps.

[0072] S310 constructs a virtual LFSR that is dual to the actual LFSR. The virtual LFSR includes multiple register units connected in sequence. The multiple register units are divided into multiple register groups, and the register units in each register group are connected in series.

[0073] It should be noted that an actual LFSR can be understood as an LFSR actually used in a test circuit, while a virtual LFSR is an LFSR simulated by a computer program.

[0074] It is understood that the method provided in this disclosure is essentially a program instruction executed by an electronic device. The virtual LFSR is also constructed through computer program instructions and can be implemented by a circuit simulation program running in a computer. The constructed virtual LFSR can be shown to the user in a visual manner or it can be represented as program code that describes the structure of the LFSR; this disclosure does not limit this aspect.

[0075] For example, LFSRs can be divided into two types: Type I LFSRs and Type II LFSRs, which are dual to each other. Please refer to... Figure 4 The difference between Type I LFSR and Type II LFSR lies in their feedback register units ( Figure 4The XOR operation methods for the register units (numbered 1, 5, and 6) differ. In a Type I LFSR, there is only one XOR unit, and all feedback register units are connected to the input of this XOR unit. In a Type II LFSR, each feedback register unit is followed by an independent XOR unit, and each feedback register unit is connected to the input of its respective XOR unit.

[0076] The following theorem applies to the transformation matrices M and D of the two types of LFSRs: Assume m = 2 n -1-q, then [M q ] T =D m Where n is the LFSR order, m and q are the simulation cycles of the two types of LFSRs respectively, and T represents the matrix transpose operation. This theorem is the basis of the phase shifter construction method of this disclosure, characterizing the symmetry between dual LFSRs in state switching. By using a virtual LFSR that is dual to the actual LFSR to perform simulation in a computer, the computational load of the method provided in this disclosure can be reduced and the simulation efficiency can be improved.

[0077] Therefore, when the actual LFSR is a Type I LFSR, the virtual LFSR constructed through computer program instructions is a Type II LFSR. Conversely, when the actual LFSR is a Type II LFSR, the virtual LFSR constructed through computer program instructions is a Type I LFSR.

[0078] For example, in the constructed virtual LFSR, register cells are divided into multiple register groups. By dividing the register groups, inter-group isolation can be achieved to a certain extent for register cells with high correlation, thereby improving the randomness of the test vectors generated by the LFSR.

[0079] S320, Repeat steps S321 to S323 until the correspondence between each XOR unit and register unit is obtained, so as to construct the XOR unit in the test stimulus generation circuit as a phase shifter.

[0080] Those skilled in the art will understand that, after obtaining the correspondence between the XOR unit and the register unit, in the actual test stimulus generation circuit, the different input terminals of the XOR unit can be connected to their respective register units, thereby constructing the XOR unit as a phase shifter.

[0081] S321 controls the virtual LFSR to run continuously for a preset number of clock cycles.

[0082] For example, a virtual LFSR can be controlled to run continuously in a computer. Within one clock cycle, the value stored in each register cell of the virtual LFSR is shifted once.

[0083] For example, the preset quantity can be greater than or equal to 3.

[0084] In other words, after the virtual LFSR "idles" for at least 3 clock cycles each time, the following steps S322 and S323 are executed to establish the correspondence between the XOR unit and the register unit, so as to further reduce the correlation between adjacent output ports (i.e., the output ports of the XOR unit) in the constructed phase shifter.

[0085] For example, the virtual LFSR operates as follows within each clock cycle:

[0086] Step 1: Based on the specific structure of the feedback register units in the virtual LFSR, calculate and temporarily store the XOR output results of each feedback register unit. If the virtual LFSR is a Type I LFSR, temporarily store the XOR output result of the external feedback register unit. If the virtual LFSR is a Type II LFSR, temporarily store the XOR output result of each internal feedback register unit, and also temporarily store the value of the penultimate register unit.

[0087] Step 2: Starting from the second-to-last register cell of the virtual LFSR, shift the current register cell value to the next register cell (overwriting the value of the next register cell). If the virtual LFSR is a Type I LFSR, the data in the feedback register cell participating in the shift is the original register value. If the virtual LFSR is a Type II LFSR, the data in the feedback register cell participating in the shift is the XOR output result of the feedback register cell temporarily stored in Step 1.

[0088] Step 3: Repeat step 2, looping forward until the shift of the first register unit is completed.

[0089] Step 4: If the virtual LFSR is a Type I LFSR, then write the XOR output result of the external feedback register unit temporarily stored in Step 1 into the first register unit of the LFSR. If the virtual LFSR is a Type II LFSR, then write the value of the last register unit of the LFSR temporarily stored in Step 1 into the first register unit of the LFSR.

[0090] S322, Get the number of target register groups in the virtual LFSR, where the target register group is a register group with a unique unit value of 1.

[0091] S323, when the number of target register groups in the virtual LFSR is within a preset range, select any XOR unit that has not established a correspondence with a register unit, and establish a correspondence between the XOR unit and the register units in each target register group whose unit value is 1.

[0092] It's understandable that a phase shifter is essentially an XOR network composed of a set of XOR units, where each XOR unit can be understood as an "XOR tree." The "root node" of each "XOR tree" drives a scan chain, and the construction process of the phase shifter is the process of connecting the "leaf nodes" of the "XOR tree" to register units. The "root node" can be understood as the output of the XOR unit, and the "leaf nodes" can be understood as the input of the XOR unit.

[0093] Based on the aforementioned theorems related to the transformation matrices of the two types of LFSRs, taking the unit with a register value of 1 in each simulation cycle of the dual LFSR as the input of the XOR unit can achieve higher traversal efficiency for state switching, where "simulation cycle" is the aforementioned "preset number of clock cycles". Furthermore, this disclosure further makes the input of a single XOR unit correspond to register units within different register groups, thereby improving the randomness of the XOR unit output.

[0094] In some embodiments, the preset quantity range can be the range of the number of input ports for each XOR unit. When the number of target register groups in the virtual LFSR is within the preset quantity range, the sum of the number of register units with a value of 1 in all target register groups falls exactly within the range of the number of input ports for the XOR unit. In this case, a correspondence can be established between these register units and the same XOR unit, thereby constructing the XOR unit in the test stimulus generation circuit as a phase shifter, and enabling the output of the phase shifter to provide high fault coverage.

[0095] For example, the range of input ports of the XOR unit can be determined based on the number of scan chains in the circuit under test. Here, the circuit under test is the circuit used for testing by the test stimulus generation circuit, and a mapping relationship is pre-established between the number of scan chains and the range of input ports.

[0096] Understandably, the more XOR gate input ports a phase shifter has, the stronger the randomness of the test values ​​output to the scan chain. Furthermore, given a fixed LFSR order, the more input ports the XOR units have in the phase shifter, the more combinations of XOR units there are, and the greater the probability that different scan chains will obtain different test values ​​during testing. However, a higher number of XOR unit input ports also requires a greater number of cascaded basic XOR gates, resulting in a larger area overhead for the test circuit. Therefore, the selection of the range of XOR unit input ports must balance the randomness of the test values ​​with the area overhead of the test circuit.

[0097] For example, in this embodiment of the present disclosure, the mapping relationship between the number of scan chains t and the range of the number of input ports can be as follows:

[0098] If t≤30, then the lower limit of the range of the number of input ports is l=1 and the upper limit is m=3;

[0099] If 30 < t ≤ 300, then the lower limit of the range of the number of input ports is l = 3 and the upper limit is m = 5.

[0100] If 300 < t ≤ 1000, then the lower limit of the range of the number of input ports is l = 4 and the upper limit is m = 6.

[0101] If t > 1000, then the lower limit of the range of the number of input ports is l = 5 and the upper limit is m = 7.

[0102] In some embodiments, after obtaining the correspondence between each XOR unit and register unit based on the method provided in the embodiments of this disclosure, a phase shifter can be constructed in the test stimulus generation circuit of a practical application in the following manner.

[0103] First, construct an actual LFSR with the same order as the virtual LFSR and which is the dual of the virtual LFSR.

[0104] Specifically, assuming the virtual LFSR is a Type I LFSR, the external loops in the virtual LFSR, namely the loops used to generate the input values ​​of the first-stage register unit through XOR operations for each feedback register unit, can be removed. Then, a two-input XOR unit is inserted at the output of each feedback register, with one input being the output of the feedback register unit and the other being the output of the final-stage register. This yields the Type II LFSR structure in the actual test stimulus generation circuit.

[0105] Assuming the virtual LFSR is a Type II LFSR, the XOR units connected to the outputs of each feedback register in the virtual LFSR can be removed and directly connected to the inputs of the next-stage register unit. Then, a multi-input XOR unit is added outside the shift path, with its inputs being the outputs of each feedback shift register and the output of the final stage register of the LFSR. Thus, the Type I LFSR structure in the actual test stimulus generation circuit can be obtained.

[0106] It is understandable that LFSRs that are dual to each other have the same order, meaning they contain the same number of register units. Therefore, register units at the same position on their shift paths can be matched one-to-one.

[0107] Therefore, the correspondence between the XOR units and register units obtained through virtual LFSR simulation can be equivalent to the correspondence between the XOR units in the actual test circuit and the register units in the actual LFSR. Based on this correspondence, by connecting the input terminal of each XOR unit to the output terminal of the corresponding register unit in the actual test stimulus generation circuit, the phase shifter in the actual test stimulus generation circuit can be constructed.

[0108] It is worth noting that this disclosure does not limit the order in which the correspondence between each XOR unit is determined. That is, in S323, any XOR unit that has not yet established a correspondence can be selected and a correspondence can be established between it and a register unit that meets the conditions.

[0109] However, when connecting the constructed phase shifter to the scan chain, the order of the scan chain needs to correspond to the order in which the XOR units are determined. That is, the first scan chain in the circuit under test is connected to the output of the first XOR unit whose correspondence (with register units) has been determined, the second scan chain is connected to the output of the second XOR unit whose correspondence has been determined, the third scan chain is connected to the output of the third XOR unit whose correspondence has been determined, and so on.

[0110] The number of scan chains is the same as the number of XOR units. By connecting the scan chains sequentially to the XOR units in the phase shifter in this way, the correlation between the test vectors input to adjacent scan chains can be reduced.

[0111] Therefore, the phase shifter construction method provided in this embodiment can quickly construct the XOR unit in the test excitation generation circuit into a phase shifter, while improving the randomness of the output data of each port of the phase shifter, thereby improving the fault coverage of the test circuit.

[0112] Exemplary, based on the methods provided in the embodiments of this disclosure, a system can be constructed as follows: Figure 5 The phase shifter shown. In Figure 5 In the diagram, solid circles indicate crossover connections of signal lines. A register set refers to a grouping of all register cells in a linear shift register into a fixed number of groups; each register cell associated with a single scan chain input of the phase shifter comes from a different register set.

[0113] For example, for the register unit corresponding to scan chain 1, its input register units come from three different groups: register group 1, register group g-1, and register group g. Similarly, for the register unit corresponding to scan chain t, its input register units come from three different groups: register group 2, register group g-1, and register group g. This significantly reduces the simulation and search configuration time for register units during phase shifter construction, while also improving the randomness of the output data at each port of the phase shifter and increasing the fault coverage of the test.

[0114] Below, we will combine Figures 6 to 8 This document details the method for constructing a virtual LFSR in the embodiments of this disclosure.

[0115] First, please refer to Figure 6 , Figure 6 This diagram illustrates a flowchart of a virtual LFSR construction method according to an embodiment of the present disclosure, as shown below. Figure 6 As shown, the method includes the following steps.

[0116] S610 determines the number of register units and register groups in the virtual LFSR based on the number of objects to be driven.

[0117] The objects to be driven include: the scan chain and / or the first-level input port in the circuit under test, and the circuit under test is the circuit used for testing by the test excitation generation circuit.

[0118] For example, when a phase shifter in a practical LFSR is used to drive the scan chain, the scan chain can be considered the object to be driven. However, when a phase shifter in a practical LFSR is used for both the scan chain and the primary inputs (PI), both the scan chain and the primary inputs (PI) can be considered as objects to be driven simultaneously.

[0119] Understandably, the more register cells a LFSR has, the more combinations of selecting a fixed number of register cells to drive the object being driven. However, increasing the number of register cells increases the area overhead of the test circuit and reduces the operating efficiency of the LFSR. Therefore, the number of register cells in the LFSR can be determined based on the number of objects to be driven, in order to achieve a relative balance among the above-mentioned effects and make the number of register cells relatively reasonable.

[0120] Furthermore, since the number of register groups in an LFSR is closely related to the number of register units, a similar approach can be used to determine the number of register groups in the LFSR based on the number of objects to be driven.

[0121] S620 divides the register units in the virtual LFSR into multiple register groups based on the number of register units and register groups in the virtual LFSR.

[0122] For example, the number of register units within each register group Where n is the total number of register units in the virtual LFSR, and g is the total number of register groups in the virtual LFSR. This indicates that the result of the division is rounded up.

[0123] After calculating sz, the interconnected register units can be grouped sequentially according to their numbers in the virtual LFSR, where the register unit numbers are consistent with the serial order of the register units.

[0124] For example, register units numbered 1 to sz can be divided into register group 1, register units numbered sz+1 to sz×2 can be divided into register group 2, and so on, until the number of remaining register units is less than or equal to sz, at which point all remaining register units are divided into the last register group.

[0125] S630 selects the target primitive polynomial from the primitive polynomial library based on the number of register units and the grouping method.

[0126] It should be noted that a primitive polynomial refers to a polynomial that possesses certain special properties in a finite field. Specifically, in the finite field GF(2) (i.e., the binary field), a primitive polynomial is an irreducible polynomial whose minimal roots are generators of the field. The primitive polynomial can serve as the characteristic polynomial of an LFSR, thereby enabling the LFSR to generate polynomials of length 2. n A pseudo-random sequence of -1, where n is the number of register units in the LFSR, i.e., the order of the LFSR.

[0127] For example, the correspondence between primitive polynomials and LFSRs can be found by referring to Figure 7 , Figure 7 An example is shown where the primitive polynomial is h(x) = x 5 +x 2 The structural diagrams of the corresponding Type I and Type II LFSRs are shown in the case of +1 (5th order primitive polynomial). It can generate a length of 31 (2... 5 A pseudo-random sequence of -1).

[0128] It is understandable that the primitive polynomial determines the location of the feedback register unit in the LFSR. The embodiments of this disclosure expect that there are as many feedback register units as possible in each register group in order to enhance the switching frequency of the register unit data in each group.

[0129] For example, embodiments of this disclosure can pre-generate and construct a library of primitive polynomials of different orders using the M-sequence sampling method. After determining the order of the LFSR, candidate primitive polynomials that satisfy the order requirement of the LFSR can be searched in the primitive polynomial library first. Then, based on this, the primitive polynomials that maximize the number of polynomial coefficients of each register group that are "1" are selected as the target primitive polynomials.

[0130] S640, based on the objective primitive polynomial, constructs a virtual LFSR that is dual to the actual LFSR.

[0131] As mentioned above, LFSRs can be divided into two types: Type I LFSRs and Type II LFSRs, and Type I LFSRs and Type II LFSRs are dual to each other.

[0132] If the test stimulus generation circuit used in the actual application contains a Type I LFSR, then the virtual LFSR used for simulation when constructing the phase shifter is a Type II LFSR. Conversely, if the test stimulus generation circuit used in the actual application contains a Type II LFSR, then the virtual LFSR used for simulation when constructing the phase shifter is a Type I LFSR.

[0133] Whether the virtual LFSR is a Type I LFSR or a Type II LFSR, it can be constructed by selecting the target primitive polynomial. The difference lies in whether the XOR operation of the feedback unit is performed on the shift path (corresponding to Type II LFSR) or outside the shift path (corresponding to Type I LFSR) when constructing the LFSR.

[0134] Next, we will combine Figure 8 The method for selecting primitive polynomials in the embodiments of this disclosure is described in detail. Figure 8 This invention discloses a method for selecting a primitive polynomial in an embodiment of the present invention, such as... Figure 8 As shown, the method includes the following steps.

[0135] S810 selects any candidate primitive polynomial from the primitive polynomial library. The order of the candidate primitive polynomial is n, where n is the number of register units in the virtual LFSR.

[0136] S820, if the candidate primitive polynomial satisfies the preferred condition, then the candidate primitive polynomial is taken as the target primitive polynomial.

[0137] The preferred condition is that for each register group in the virtual LFSR, there are multiple terms with a coefficient of 1 in the candidate primitive polynomials.

[0138] In some embodiments, if none of the candidate primitive polynomials in the primitive polynomial library meet the preferred condition, then the candidate primitive polynomial in the primitive polynomial library with the most terms that meet the alternative condition and have a coefficient of 1 is taken as the target primitive polynomial.

[0139] The candidate condition is that for each register group in the virtual LFSR, there is at least one term with a coefficient of 1 in the candidate primitive polynomial.

[0140] In other words, after determining the order of the virtual LFSR, the preferred target primitive polynomial can ensure that the number of terms with a coefficient of 1 in the primitive polynomial corresponding to each register group (register unit within the group) is no less than two.

[0141] The candidate target primitive polynomial can ensure that the number of terms with coefficients of 1 in the primitive polynomial corresponding to each register group is not less than one, and that the total number of terms with coefficients of 1 in the target primitive polynomial is the largest among all candidate primitive polynomials.

[0142] Below, we will combine Figures 9 to 12 This describes the method for determining the number of register units and the number of register groups in the embodiments of this disclosure.

[0143] As mentioned earlier, the order of an LFSR refers to the number of LFSR register cells. The more register cells it has, the more combinations are possible to select a fixed number of register cells to drive the object being driven. However, the higher the order of the LFSR, the greater its area overhead and the longer the simulation execution time.

[0144] In some embodiments, to balance the impact of the number of register units on the LFSR, the number of combinations can be calculated. The total number of different combinations of the XOR gate inputs of the phase shifter is obtained, and this number of combinations, combined with the order-limited scaling factor α, is used to determine whether the currently selected LFSR order is appropriate. Here, n is the currently selected LFSR order; m is the upper limit of the preset number range in S323, which can also be understood as the maximum number of input ports of the pre-configured XOR unit; the order-limited scaling factor α is used to balance the effect of the number of register units on the LFSR.

[0145] For example, Figure 9 This disclosure illustrates a method for determining the number of register units in an embodiment, such as... Figure 9 As shown, the method includes the following steps.

[0146] S910, calculate the first combination number of randomly selecting m different register units from n register units.

[0147] Where m is the upper limit of the preset quantity range, and n and m are both positive integers.

[0148] S920, the minimum value of n when the first combination number is greater than or equal to the first combination number threshold is used as the number of register units in the virtual LFSR.

[0149] The first combination threshold is the product of the order-limited scaling factor α and the number of objects to be driven, where α ≥ 5.

[0150] For example, please refer to Figure 10 , Figure 10 This example illustrates the specific process for determining the number of register units in a practical application. Figure 10 In order to improve the running speed of the algorithm, the order n of LFSR is given an initial value of a certain size.

[0151] Specifically, Figure 10 The following steps are shown:

[0152] Step 1: Initialize the order of the LFSR n = 10, and set the order-limited scaling factor α = 8 (in this example, n and α are empirical values).

[0153] Step 2: Calculate the first combination number

[0154] Step 3: If the first combination number fi ≥ α × (t + p), then the order of the LFSR takes the value of n at this time. Otherwise, let n = n + 1.

[0155] Where t is the number of scan chains in the circuit under test, p is the number of first-stage input ports in the circuit under test, that is, in this example, the scan chains and first-stage input ports are used together as the objects to be driven in the test excitation generation circuit, and t+p is used to represent the number of objects to be driven in the circuit under test.

[0156] Step 4: Repeat step 3 above until the order n of the LFSR that satisfies the conditions is obtained.

[0157] In some embodiments, Figure 11 This invention illustrates a method for determining the number of register groups in an embodiment of the present disclosure. The core idea of ​​this invention is to group the register units in the virtual LFSR and select one register unit from each group to drive the scan chain.

[0158] Therefore, the number of combinations can be calculated. This process yields the total number of possible configurations for the LFSR register groups, and uses this number of combinations to determine whether the currently selected number of LFSR groups is appropriate. Since different register units can be selected within the same group to drive the XOR unit, a group number limitation factor β is also set during the judgment process to increase the rationality of the judgment and avoid an excessive number of register unit groups.

[0159] Specifically, please refer to Figure 11 The method includes the following steps.

[0160] S1111, calculate the second combination number of randomly selected m different register groups from g register groups.

[0161] Where m is the upper limit of the preset quantity range, and both g and m are positive integers.

[0162] S1120, when the second combination number is greater than or equal to the second combination number threshold, the minimum value of g is taken as the number of register groups in the virtual LFSR.

[0163] The second combination threshold is the product of the group number limitation ratio factor β and the number of objects to be driven, where 0 < β ≤ 1.

[0164] For example, please refer to Figure 12 , Figure 12 This example illustrates the specific process for determining the number of register groups in a practical application.

[0165] Specifically, Figure 12 The following steps are shown:

[0166] Step 1: Initialize the number of LFSR packets g = m (m is the upper limit of the preset number range in S323, which can also be understood as the maximum number of input ports of the pre-configured XOR unit), and set the packet number limitation ratio factor β = 0.1 (in this example, β is an empirical value).

[0167] Step 2: Calculate the second combination number

[0168] Step 3: If the second combination number fo ≥ β × (t + p), then the number of groups in the LFSR is taken as the value of g at this time. Otherwise, g = g + 1, and the second combination number fo is recalculated.

[0169] Step 4: Repeat step 3 above until the number of LFSR groups that meet the conditions is obtained, g.

[0170] Based on the same inventive concept, this disclosure also provides a phase shifter construction device, as shown in the following embodiment. Since the principle of this phase shifter construction device embodiment in solving the problem is the same as that described above... Figure 3 The method embodiments shown are similar, therefore, the implementation of this phase shifter construction device embodiment can be found in the above description. Figure 3 The implementation of the method embodiments shown will not be repeated here.

[0171] Figure 13 A schematic diagram of a phase shifter construction apparatus according to an embodiment of the present disclosure is shown. This apparatus is used to construct a phase shifter in a test excitation generation circuit, which includes an actual LFSR and multiple XOR units.

[0172] Specifically, such as Figure 13 As shown, the phase shifter construction device 1300 includes:

[0173] Module 1310 is used to construct a virtual LFSR that is dual to the actual LFSR. The virtual LFSR includes multiple register units connected in sequence. The multiple register units are divided into multiple register groups, and the register units in each register group are connected in series.

[0174] Execution module 1320 is used to repeatedly perform the following steps until the correspondence between each XOR unit and register unit is obtained, so as to construct the XOR units in the test stimulus generation circuit as phase shifters:

[0175] Control the virtual LFSR to run continuously for a preset number of clock cycles;

[0176] Get the number of target register groups in the virtual LFSR; where the target register group is the register group with a unique register cell value of 1;

[0177] In the virtual LFSR, if the number of target register groups is within a preset range, select any XOR unit that has not yet established a correspondence with a register unit, and establish a correspondence between the XOR unit and the register units in each target register group whose unit value is 1.

[0178] In some embodiments, the construction module 1310 is specifically used to determine the number of register units and the number of register groups in the virtual LFSR based on the number of objects to be driven; wherein, the objects to be driven include: the scan chain and / or the first-level input port in the circuit under test, and the circuit under test is a circuit used for testing by the test stimulus generation circuit;

[0179] Based on the number of register units and register groups in the virtual LFSR, the register units in the virtual LFSR are divided into multiple register groups;

[0180] Based on the number of register units and the grouping method, the target primitive polynomial is selected from the primitive polynomial library;

[0181] Based on the objective primitive polynomial, a virtual LFSR that is dual to the actual LFSR is constructed.

[0182] In some embodiments, the construction module 1310 is specifically used to calculate the first combination number of randomly selected m different register units from n register units, where m is the upper limit of a preset number range, and n and m are both positive integers;

[0183] The minimum value of n when the first combination number is greater than or equal to the first combination number threshold is taken as the number of register units in the virtual LFSR;

[0184] The first combination threshold is the product of the order-limited scaling factor α and the number of objects to be driven, where α ≥ 5.

[0185] In some embodiments, the construction module 1310 is specifically used to calculate a second combination number from g register groups, in which m different register groups are randomly selected, where m is the upper limit of a preset range, and both g and m are positive integers;

[0186] When the second combination number is greater than or equal to the second combination number threshold, the minimum value of g is taken as the number of register groups in the virtual LFSR;

[0187] The second combination threshold is the product of the group number limitation ratio factor β and the number of objects to be driven, where 0 < β ≤ 1.

[0188] In some embodiments, the construction module 1310 is specifically used to select any candidate primitive polynomial from the primitive polynomial library, wherein the order of the candidate primitive polynomial is n, and n is the number of register units in the virtual LFSR.

[0189] If the candidate primitive polynomial satisfies the preferred condition, then the candidate primitive polynomial is taken as the target primitive polynomial.

[0190] The preferred condition is that for each register group in the virtual LFSR, there are multiple terms with a coefficient of 1 in the candidate primitive polynomials.

[0191] In some embodiments, the construction module 1310 is specifically used to, if none of the candidate primitive polynomials in the primitive polynomial library meet the preferred condition, then take the candidate primitive polynomial in the primitive polynomial library that meets the alternative condition and has the most terms with a coefficient of 1 as the target primitive polynomial.

[0192] The candidate condition is that for each register group in the virtual LFSR, there is at least one term with a coefficient of 1 in the candidate primitive polynomial.

[0193] In some embodiments, the preset quantity range is the range of the number of input ports for each XOR unit. The construction module 1310 is specifically used to determine the range of the number of input ports based on the number of scan chains in the circuit under test.

[0194] Among them, the circuit under test is the circuit used for testing by the test excitation generation circuit, and a mapping relationship is pre-established between the number of scan chains and the range of the number of input ports.

[0195] The following reference Figure 14 To describe an electronic device 1400 capable of implementing embodiments of the present disclosure. Figure 14 The electronic device 1400 shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0196] like Figure 14 As shown, the electronic device 1400 is presented in the form of a general-purpose computing device. The components of the electronic device 1400 may include, but are not limited to: at least one processor 1410, at least one memory 1420, and a bus 1430 connecting different system components (including memory 1420 and processor 1410).

[0197] The memory stores program code that can be executed by the processor 1410, causing the processor 1410 to perform the steps described in the "Exemplary Methods" section of this disclosure according to various exemplary embodiments of this disclosure.

[0198] In some embodiments, the processor 1410 may also perform the following steps of the above method embodiments:

[0199] Construct a virtual LFSR that is the dual to the actual LFSR. The virtual LFSR consists of multiple register units connected in sequence. The multiple register units are divided into multiple register groups, and the register units in each register group are connected in series.

[0200] Repeat the following steps until the correspondence between each XOR cell and register cell is obtained, so that the XOR cells in the test stimulus generation circuit can be constructed as phase shifters:

[0201] Control the virtual LFSR to run continuously for a preset number of clock cycles;

[0202] Get the number of target register groups in the virtual LFSR; where the target register group is the register group with a unique register cell value of 1;

[0203] In the virtual LFSR, if the number of target register groups is within a preset range, select any XOR unit that has not yet established a correspondence with a register unit, and establish a correspondence between the XOR unit and the register units in each target register group whose unit value is 1.

[0204] The memory 1420 may include a readable medium in the form of volatile memory, such as random access memory (RAM) 14201 and / or cache memory 14202, and may further include read-only memory (ROM) 14203.

[0205] The memory 1420 may also include a program / utility 14204 having a set (at least one) of program modules 14205, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0206] Bus 1430 can represent one or more of several types of bus structures, including a memory bus or memory controller, peripheral bus, graphics acceleration port, processor, or a local bus using any of the various bus structures.

[0207] Electronic device 1400 can also communicate with one or more external devices 1440 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with the electronic device 1400, and / or with any device that enables the electronic device 1400 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 1450. Furthermore, electronic device 1400 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 1460. Figure 14 As shown, network adapter 1460 communicates with other modules of electronic device 1400 via bus 1430. It should be understood that, although not shown in the figures, other hardware and / or software modules may be used in conjunction with electronic device 1400, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0208] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0209] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, which may be a readable signal medium or a readable storage medium. A program product capable of implementing the methods described above is stored thereon. In some possible implementations, various aspects of this disclosure may also be implemented as a program product including program code, which, when run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this disclosure according to various exemplary embodiments of this disclosure.

[0210] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for constructing a phase shifter, characterized in that, The method is used to construct a phase shifter in a test stimulus generation circuit, which includes an actual LFSR and multiple XOR units; The method includes: A virtual LFSR is constructed that is dual to the actual LFSR. The virtual LFSR includes multiple register units connected in sequence. The multiple register units are divided into multiple register groups, and the register units in each register group are connected in series. Repeat the following steps until the correspondence between each XOR unit and register unit is obtained, so that the XOR units in the test stimulus generation circuit can be constructed as phase shifters: The virtual LFSR is controlled to run continuously for a preset number of clock cycles; Obtain the number of target register groups in the virtual LFSR; wherein, a target register group is a register group that has a unique register cell with a value of 1; When the number of target register groups in the virtual LFSR is within a preset range, any XOR unit that has not been established with a register unit is selected, and a correspondence is established between the XOR unit and the register units in each target register group whose unit value is 1. The method further includes: The number of register units in the virtual LFSR is calculated as follows: Calculate the first combination number of randomly selected m different register units from n register units, where m is the upper limit of the preset number range, and n and m are both positive integers; The minimum value of n when the first combination number is greater than or equal to the first combination number threshold is taken as the number of register units in the virtual LFSR; Wherein, the first combination number threshold is the product of the order-limited scaling factor α and the number of objects to be driven, α is greater than or equal to 5, and the objects to be driven include the scan chain and / or the first-level input port in the circuit under test.

2. The method according to claim 1, characterized in that, The construction of the virtual LFSR that is dual to the actual LFSR includes: The number of register units and the number of register groups in the virtual LFSR are determined based on the number of objects to be driven; wherein, the objects to be driven include: the scan chain and / or the first-level input port in the circuit under test, and the circuit under test is the circuit used for testing by the test stimulus generation circuit; Based on the number of register units and the number of register groups in the virtual LFSR, the register units in the virtual LFSR are divided into multiple register groups; Based on the number of register units and the grouping method, the target primitive polynomial is selected from the primitive polynomial library; Based on the target primitive polynomial, a virtual LFSR that is dual to the actual LFSR is constructed.

3. The method according to claim 2, characterized in that, The number of register groups in the virtual LFSR is calculated as follows: Calculate the second combination number from g register groups, randomly selecting m different register groups, where m is the upper limit of the preset number range, and g and m are both positive integers; When the second combination number is greater than or equal to the second combination number threshold, the minimum value of g is taken as the number of register groups in the virtual LFSR; Wherein, the second combination number threshold is a group number-limited ratio factor. The product of the number of objects to be driven, .

4. The method according to claim 2, characterized in that, The selection of target primitive polynomials from the primitive polynomial library based on the number and grouping method of register units includes: Select any candidate primitive polynomial from the primitive polynomial library. The order of the candidate primitive polynomial is n, where n is the number of register units in the virtual LFSR. If the candidate primitive polynomial satisfies the preferred condition, then the candidate primitive polynomial is taken as the target primitive polynomial. The preferred condition is that for each register group in the virtual LFSR, there are multiple terms with a coefficient of 1 in the candidate primitive polynomial.

5. The method according to claim 4, characterized in that, The method further includes: If none of the candidate primitive polynomials in the primitive polynomial library satisfy the preferred condition, then the candidate primitive polynomial in the primitive polynomial library with the most terms that satisfy the alternative condition and have a coefficient of 1 is taken as the target primitive polynomial. The candidate condition is that for each register group in the virtual LFSR, there is at least one term with a coefficient of 1 in the candidate primitive polynomial.

6. The method according to any one of claims 1 to 3, characterized in that, The preset quantity range is the range of the number of input ports for each XOR unit, and the method further includes: The range of the number of input ports is determined based on the number of scan chains in the circuit under test; The circuit under test is the circuit used for testing by the test stimulus generation circuit, and a mapping relationship is pre-established between the number of scan chains and the range of the number of input ports.

7. A phase shifter construction device, characterized in that, The device is used to construct a phase shifter in a test excitation generation circuit, the test excitation generation circuit including an actual LFSR and multiple XOR units; The device includes: The construction module is used to construct a virtual LFSR that is the counterpart of the actual LFSR. The virtual LFSR includes multiple register units connected in sequence. The multiple register units are divided into multiple register groups, and the register units in each register group are connected in series. An execution module is used to repeatedly execute the following steps until the correspondence between each XOR unit and register unit is obtained, so as to construct the XOR units in the test stimulus generation circuit as phase shifters: The virtual LFSR is controlled to run continuously for a preset number of clock cycles; Obtain the number of target register groups in the virtual LFSR; wherein, a target register group is a register group that has a unique register cell with a value of 1; When the number of target register groups in the virtual LFSR is within a preset range, any XOR unit that has not been established with a register unit is selected, and a correspondence is established between the XOR unit and the register units in each target register group whose unit value is 1. The building module is also used for: The number of register units in the virtual LFSR is calculated as follows: Calculate the first combination number of randomly selected m different register units from n register units, where m is the upper limit of the preset number range, and n and m are both positive integers; The minimum value of n when the first combination number is greater than or equal to the first combination number threshold is taken as the number of register units in the virtual LFSR; Wherein, the first combination number threshold is the product of the order-limited scaling factor α and the number of objects to be driven, α is greater than or equal to 5, and the objects to be driven include the scan chain and / or the first-level input port in the circuit under test.

8. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the method of any one of claims 1 to 6 by executing the executable instructions.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1 to 6.

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