Flash quantizer for delta-sigma modulator and control method thereof

Abstract

The application provides a flash quantizer for a delta-sigma modulator and a control method thereof. The quantizer comprises: a reference voltage scrambling module configured to output a target reference voltage pair by sequentially scrambling a plurality of pairs of differential reference voltages output by resistance array voltage division; a plurality of comparators, each of which receives a differential input voltage and the target reference voltage pair to obtain a comparison result, and controls a connected DAC circuit to output to a loop filter in the delta-sigma modulator according to the comparison result, wherein the differential input voltage is an output voltage of the loop filter, and the number of pairs of differential reference voltages corresponds to the number of comparators; and a plurality of chopping modules configured to input the signals at the input ends of the comparators into corresponding comparators after exchanging the signals, so as to eliminate the offset voltage of the comparators, wherein the chopping modules are arranged one by one corresponding to the comparators. The application can effectively reduce power consumption and improve the overall performance of the circuit.

Description

Technical Field

[0001] This invention relates to the field of mixed-signal integrated circuit design, and more particularly to a Flash-type quantizer for Delta-Sigma modulators and its control method. Background Technology

[0002] Delta-Sigma analog-to-digital converters (ADCs) are widely used in high-precision applications. In Delta-Sigma ADC circuit design, the quantizer is a crucial component; its speed and accuracy determine the effective bandwidth and effective conversion bit depth of the ADC. A Flash quantizer is a high-speed quantization circuit based on a comparator, and its key lies in the comparator design. However, existing quantizers typically improve DAC mismatch by adjusting the process or using calibration circuits, which suffers from circuit complexity and high power consumption. Summary of the Invention

[0003] In view of the problems existing in the prior art, the present invention proposes a Flash-type quantizer and its control method for Delta-Sigma modulators, which mainly solves the problems that existing quantizer DAC mismatch improvement methods rely on complex circuit structures, have high power consumption, and affect the overall circuit performance.

[0004] To achieve the above and other objectives, the technical solution adopted by the present invention is as follows.

[0005] This application provides a Flash-type quantizer for a Delta-Sigma modulator, comprising: a reference voltage scrambling module, which sequentially scrambles multiple pairs of differential reference voltage outputs obtained by voltage division by a resistor array and outputs a target reference voltage pair; multiple comparators, each of which receives a differential input voltage and the target reference voltage pair to obtain a comparison result, and controls a connected DAC circuit to output to a loop filter in the Delta-Sigma modulator according to the comparison result, wherein the differential input voltage is the output voltage of the loop filter, and the number of differential reference voltage pairs corresponds to the number of comparators; and multiple chopper modules, which swap the input signals of the comparators and input them to the corresponding comparators to eliminate the offset voltage of the comparators, wherein the chopper modules are configured one-to-one with the comparators.

[0006] In one embodiment of this application, the reference voltage scrambling module includes: multiple delay elimination units, each receiving a multi-bit input control signal and generating corresponding output control signal pairs; the delay elimination units eliminate the delay between the output control signal pairs through a cross-coupling structure; wherein the number of bits in the input control signal corresponds to the number of the output control signal pairs and the number of comparators; and a switch array, which receives the output control signal pairs to control the transmission relationship between the multiple pairs of differential reference voltages obtained by the resistor array voltage division and the target reference voltage pair, and polls the multi-bit input control signals at intervals to adjust the output order of the target reference voltage pairs.

[0007] In one embodiment of this application, the delay cancellation unit includes: a delay unit, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor. The input terminal of the delay unit is connected to the gate of the second NMOS transistor as the input terminal of the delay cancellation unit and is connected to the input control signal. The output terminal of the delay unit is connected to the gate of the first NMOS transistor, and the sources of the first NMOS transistor and the second NMOS transistor are grounded. The drain of the first NMOS transistor is connected to the source of the first PMOS transistor as the first output terminal of the delay cancellation unit. The drain of the second NMOS transistor is connected to the source of the second PMOS transistor as the second output terminal of the delay cancellation unit. The gate of the first PMOS transistor is connected to the source of the second PMOS transistor, and the gate of the second PMOS transistor is connected to the source of the first PMOS transistor to form the cross-coupling structure. The drains of the first PMOS transistor and the second PMOS transistor are respectively connected to the power supply voltage. The output control signal of the second output terminal is the inverted signal of the output control signal of the first output terminal.

[0008] In one embodiment of this application, the switch array includes a plurality of switch units, wherein the number of switch units is the square of the number of delay elimination units; each switch unit includes a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The source of the third NMOS transistor is connected to the source of the third PMOS transistor as a first input terminal of the switch unit, and the drain of the third NMOS transistor is connected to the drain of the third PMOS transistor as a first output terminal of the switch unit; the source of the fourth NMOS transistor is connected to the source of the fourth PMOS transistor as a second input terminal of the switch unit, and the drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor as a second output terminal of the switch unit; the gate of the third NMOS transistor is connected to the first control terminal of the switch unit and to the first output terminal of the delay elimination unit; the gate of the fourth NMOS transistor is connected to the second control terminal of the switch unit and to the first output terminal of the delay elimination unit; the gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor as a fifth control terminal of the switch unit and to the second output terminal of the delay elimination unit.

[0009] In one embodiment of this application, the chopper module includes a first chopper unit, a second chopper unit, a third chopper unit, a fourth chopper unit, and a fifth chopper unit; the first input terminal of the first chopper unit is connected to a first input voltage, the second input terminal is connected to a first reference voltage, the first output terminal is connected to the first input terminal of the second chopper unit, and the second output terminal is connected to the first input terminal of the fourth chopper unit; the first input terminal of the third chopper unit is connected to a second reference voltage, the second input terminal is connected to a second input voltage, the first output terminal is connected to the second input terminal of the second chopper unit, and the second output terminal is connected to the second input terminal of the fourth chopper unit; the second chopper unit... The two output terminals of the first chopper unit and the two output terminals of the fourth chopper unit are respectively connected to the corresponding input terminals of the comparator; the first and second input terminals of the fifth chopper unit are connected to the corresponding output terminals of the comparator, and the two output terminals of the fifth chopper unit output the comparison result. The first chopper unit and the third chopper unit are controlled by the first clock signal, and the second chopper unit, the fourth chopper unit, and the fifth chopper unit are all controlled by the second clock signal. The first input voltage and the second input voltage form a pair of differential input voltages, and the first reference voltage and the second reference voltage form a pair of target reference voltages.

[0010] In one embodiment of this application, the first chopper unit, the second chopper unit, the third chopper unit, the fourth chopper unit, and the fifth chopper unit have the same circuit structure. The first chopper unit includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor. The drain of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor as the first input terminal of the first chopper unit, and the drain of the sixth NMOS transistor is connected to the drain of the seventh NMOS transistor as the first output terminal of the first chopper unit. The gates of the fifth NMOS transistor and the seventh NMOS transistor are connected to the inverted clock signal of the first clock signal. The drain of the eighth NMOS transistor is connected to the source of the seventh NMOS transistor as the second input terminal of the first chopper unit, and the source of the eighth NMOS transistor is connected to the source of the fifth NMOS transistor as the second output terminal of the first chopper unit. The gate of the eighth NMOS transistor is connected to the first clock signal.

[0011] In one embodiment of this application, the comparator includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor; the source of the first transistor, the source of the third transistor, the drain of the fifth transistor, the drain of the seventh transistor, the gate of the sixth transistor, the source of the ninth transistor, and the eleventh transistor. The gates of the transistors are connected together. The drains of the first transistor, the third transistor, the second transistor, the fourth transistor, and the tenth transistor are connected together. The gates of the first transistor and the second transistor are connected to the differential input voltage pair. The gates of the third transistor and the fourth transistor are connected to the target reference voltage pair. The sources of the second transistor, the fourth transistor, the sixth transistor, the eighth transistor, the fifth transistor, the ninth transistor, and the twelfth transistor are connected together. The gate of the tenth transistor... The gates of the seventh, eighth, and ninth transistors are connected to a clock signal; the drain of the tenth transistor is connected to the power supply voltage; the sources of the eleventh and twelfth transistors are grounded; the drain of the eleventh transistor, the source of the thirteenth transistor, and the source of the nineteenth transistor are connected together; the drain of the twelfth transistor, the source of the fourteenth transistor, and the source of the twentieth transistor are connected together; the drain of the thirteenth transistor is connected to the source of the fifteenth transistor, the source of the seventeenth transistor, the gate of the sixteenth transistor, and the gate of the fourteenth transistor, as the ratio The first output terminal of the comparator; the drain of the fourteenth transistor is connected to the source of the sixteenth transistor, the source of the eighteenth transistor, the gate of the fifteenth transistor, and the gate of the thirteenth transistor, serving as the second output terminal of the comparator; the drains of the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, and the twentieth transistor are connected to the power supply voltage; the gates of the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, and the twentieth transistor are connected to the inverted signal of the clock signal.

[0012] This application also provides a control method for a Flash-type quantizer in a Delta-Sigma modulator, comprising: sequentially scrambling multiple pairs of differential reference voltage outputs obtained by voltage division by a resistor array through a reference voltage scrambling module, and outputting a target reference voltage pair; receiving a differential input voltage and the target reference voltage pair through multiple comparators to obtain a comparison result, and controlling a connected DAC circuit to output to a loop filter in the Delta-Sigma modulator according to the comparison result, wherein the differential input voltage is the output voltage of the loop filter, and the number of differential reference voltage pairs corresponds to the number of comparators; and exchanging the input signals of the comparators through multiple chopper modules and inputting them to the corresponding comparators to eliminate the offset voltage of the comparators, wherein the chopper modules are configured one-to-one with the comparators.

[0013] As described above, the present invention provides a Flash-type quantizer for Delta-Sigma modulators and its control method, which has the following beneficial effects.

[0014] This application eliminates offset voltage by introducing a chopper circuit into the quantizer; adding a reference voltage scrambling module to the quantizer reduces circuit overhead, effectively lowers power consumption, and improves the overall performance of the circuit. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the overall architecture of a Flash-type quantizer used in a Delta-Sigma modulator according to one embodiment of this application.

[0016] Figure 2 This is a chopper circuit diagram of a four-input dynamic comparator in one embodiment of this application.

[0017] Figure 3 This is a schematic diagram of the circuit structure of a four-input dynamic comparator in one embodiment of this application.

[0018] Figure 4 This is a schematic diagram of the circuit structure of the chopper module in one embodiment of this application.

[0019] Figure 5 This is a schematic diagram of the circuit structure of the delay elimination unit in one embodiment of this application.

[0020] Figure 6 This is a schematic diagram of the circuit structure of the switch array in one embodiment of this application.

[0021] Figure 7 This is a schematic diagram of a scrambling method in one embodiment of this application.

[0022] Figure 8A flowchart illustrating the control method of a Flash-type quantizer for a Delta-Sigma modulator in one embodiment of this application. Detailed Implementation

[0023] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0024] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0025] Please see Figure 1 , Figure 1 This is a schematic diagram of the overall architecture of a Flash-type quantizer for a Delta-Sigma modulator according to an embodiment of this application. The Flash-type quantizer for a Delta-Sigma modulator provided in this embodiment includes: a reference voltage scrambling module, which sequentially scrambles multiple pairs of differential reference voltage outputs obtained through resistor array voltage division and outputs a target reference voltage pair; multiple comparators, each comparator receiving a differential input voltage and the target reference voltage pair to obtain a comparison result, and controlling a connected DAC circuit to output to a loop filter in the Delta-Sigma modulator based on the comparison result, wherein the differential input voltage is the output voltage of the loop filter, and the number of differential reference voltage pairs corresponds to the number of comparators; and multiple chopper modules, which swap the input signals of the comparators and input them to the corresponding comparators to eliminate the offset voltage of the comparators, wherein the chopper modules are configured one-to-one with the comparators. The specific number of comparators and chopper modules can be set and adjusted according to actual application requirements, and is not limited here.

[0026] Specifically, please refer to Figure 2 , Figure 2This is a chopper circuit diagram of a four-input dynamic comparator in one embodiment of this application. The comparators in this embodiment all employ a four-input dynamic comparator, which includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, and a twentieth transistor M20; the source of the first transistor M1, the third transistor... The source of transistor M3, the drain of the fifth transistor M5, the drain of the seventh transistor M7, the gate of the sixth transistor M6, the source of the ninth transistor M9, and the gate of the eleventh transistor M11 are connected. The drain of the first transistor M1, the drain of the third transistor M3, the drain of the second transistor M2, the drain of the fourth transistor M4, and the source of the tenth transistor M10 are connected. The gates of the first transistor M1 and the second transistor M2 are connected to the differential input voltage pair. The gates of the third transistor M3 and the fourth transistor M4 are connected to the target reference voltage pair. The source of the second transistor M2, the drain of the fifth transistor M5, the drain of the seventh transistor M7, the gate of the sixth transistor M6, the source of the ninth transistor M9, and the gate of the eleventh transistor M11 are connected. The source of the fourth transistor M4, the drain of the sixth transistor M6, the drain of the eighth transistor M8, the gate of the fifth transistor M5, the drain of the ninth transistor M9, and the gate of the twelfth transistor M12 are connected together; the gate of the tenth transistor M10, the gate of the seventh transistor M7, the gate of the eighth transistor M8, and the gate of the ninth transistor M9 are connected to a clock signal; the drain of the tenth transistor M10 is connected to the power supply voltage; the sources of the eleventh transistor M11 and the twelfth transistor M12 are grounded; the drain of the eleventh transistor M11, the source of the thirteenth transistor M13, and the gate of the nineteenth transistor M19 are connected together. The sources of the 12th transistor M12, the source of the 14th transistor M14, and the source of the 20th transistor M20 are connected together; the drain of the 13th transistor M13 is connected to the source of the 15th transistor M15, the source of the 17th transistor M17, the gate of the 16th transistor M16, and the gate of the 14th transistor M14, serving as the first output terminal of the comparator; the drain of the 14th transistor M14 is connected to the source of the 16th transistor M16, the source of the 18th transistor M18, the gate of the 15th transistor M15, and the gate of the 13th transistor M13, serving as the second output terminal of the comparator;The drains of the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, and the twentieth transistor M20 are connected to the power supply voltage; the gates of the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, and the twentieth transistor M20 are connected to the inverted signal of the clock signal.

[0027] In one embodiment, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, and the twentieth transistor M20 can all be PMOS transistors. The fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 can all be NMOS transistors.

[0028] In one embodiment, the specific design of the four-input dynamic comparator is as follows: Figure 3As shown, the circuit includes a preamplifier and a latch. The preamplifier uses differential transistors to implement the function of inputs VREFN-VIN and VIP-VREFP, and amplifies and adds these two signals separately. The preamplifier uses a cross-coupling structure to ensure common-mode stability, high gain, and high bandwidth. The output of the preamplifier is connected to the latch for further comparison. The working principle of the highly dynamic comparator is as follows: When CLK is high, the comparator is in the reset phase, M7, M8, and M9 are turned on, M10 is turned off, there is no static power consumption in the circuit, and the output of the preamplifier is pulled down to GND. M17, M18, M19, and M20 are turned on, and the output voltages VOUTP and VOUTN are raised to VDD. The drain voltages of M19 and M20 are also raised to VDD to prevent incomplete discharge during the comparison phase from causing mismatch and resulting in an error in the comparator result. When CLK is low, the comparator is in the comparison phase, M10 is turned on, and M7, M8, and M9 are turned off. Assuming VIN-VREFN>VIP-VREFP, the current flowing through M4 is greater than the current flowing through M3. The gate voltage of M11 rises more slowly than the gate voltage of M12. M6 turns on, quickly pulling the gate voltage of M12 down to GND. M5 turns off, and M14 turns on. When the gate voltage of M11 reaches its threshold voltage, M11 turns on before M12. VOP discharges through M13 and M11 faster than VON, causing M16 to turn on before M15. The output voltage VON is pulled up to VDD, M15 remains off, and the output VOP is discharged to GND, yielding the comparison result.

[0029] In one embodiment, each comparator is provided with five chopper units, which together form a chopper module. The chopper module includes a first chopper unit, a second chopper unit, a third chopper unit, a fourth chopper unit, and a fifth chopper unit. The first chopper unit has a first input terminal connected to a first input voltage VIP, a second input terminal connected to a first reference voltage VREFN, a first output terminal connected to the first input terminal of the second chopper unit, and a second output terminal connected to the first input terminal of the fourth chopper unit. The third chopper unit has a first input terminal connected to a second reference voltage VREFP, a second input terminal connected to a second input voltage VIN, a first output terminal connected to the second input terminal of the second chopper unit, and a second output terminal connected to the second input terminal of the fourth chopper unit. The second chopper unit has two output terminals... The two output terminals of the fourth chopper unit are respectively connected to the corresponding input terminals of the comparator; the first and second input terminals of the fifth chopper unit are connected to the corresponding output terminals of the comparator, and the two output terminals of the fifth chopper unit output the comparison result. The first chopper unit and the third chopper unit are controlled by the first clock signal CLK1, and the second, fourth, and fifth chopper units are all controlled by the second clock signal CLK2. The first input voltage VIP and the second input voltage VIN form a pair of differential input voltages, and the first reference voltage VREFN and the second reference voltage VREFP form a pair of target reference voltages.

[0030] Please see Figure 4 , Figure 4This is a schematic diagram of the circuit structure of a chopper module in one embodiment of this application. The first chopper unit, the second chopper unit, the third chopper unit, the fourth chopper unit, and the fifth chopper unit have the same circuit structure. The first chopper unit includes: a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, and an eighth NMOS transistor N8. The drain of the fifth NMOS transistor N5 is connected to the source of the sixth NMOS transistor N6 as the first input terminal of the first chopper unit, and the drain of the sixth NMOS transistor N6 is connected to the drain of the seventh NMOS transistor N7 as the first output terminal of the first chopper unit. The gates of the fifth NMOS transistor N5 and the seventh NMOS transistor N7 are connected to the inverted clock signal of the first clock signal. The drain of the eighth NMOS transistor N8 is connected to the source of the seventh NMOS transistor N7 as the second input terminal of the first chopper unit, and the source of the eighth NMOS transistor N8 is connected to the source of the fifth NMOS transistor N5 as the second output terminal of the first chopper unit. The gate of the eighth NMOS transistor N8 is connected to the first clock signal. Specifically, the chopper module is controlled by CLK1 and CLK2 signals. Each chopper unit consists of four NMOS transistors, realizing the function of exchanging input signals under clock drive. The input signals are VIN and VIP, and the reference voltages are VREFN and VREFP. CLK2 mainly controls the exchange of VREFN / VIN and VREFP / VIP, eliminating the offset voltages of VIP and VREFP, VIN and VREFN at the comparator input ports. At the same time, since the output of the differential comparator changes with the exchange of input signals, the chopper module at the output end is controlled by CLK2 to ensure that the output result does not change with the chopper operation. CLK1 mainly controls the exchange of VIP / VREFN and VIN / VREFP, eliminating the offset voltages of the differential input pairs in the four-input comparator. The exchange process controlled by CLK1 does not affect the output result, so there is no need to add a chopper module controlled by CLK1 at the output end.

[0031] In one embodiment, the reference voltage scrambling module includes: multiple delay elimination units, each receiving a multi-bit input control signal and generating corresponding output control signal pairs; the delay elimination units eliminate the delay between the output control signal pairs through a cross-coupling structure; wherein the number of bits in the input control signal corresponds to the number of the output control signal pairs and the number of comparators; and a switch array, which receives the output control signal pairs to control the transmission relationship between the multiple pairs of differential reference voltages obtained by the resistor array voltage division and the target reference voltage pairs, and polls the multi-bit input control signals at intervals to adjust the output order of the target reference voltage pairs.

[0032] Please see Figure 5 , Figure 5This is a schematic diagram of the circuit structure of a delay cancellation unit in one embodiment of this application. The delay cancellation unit includes: a delay unit INV1, a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, and a second PMOS transistor P2. The input terminal of the delay unit INV1 is connected to the gate of the second NMOS transistor N2 as the input terminal of the delay cancellation unit, and is connected to the input control signal. The output terminal of the delay unit INV1 is connected to the gate of the first NMOS transistor N1, and the sources of the first NMOS transistor N1 and the second NMOS transistor N2 are grounded. The drain of the first NMOS transistor N1 is connected to the source of the first PMOS transistor P1 as the delay cancellation unit. The delay cancellation unit has a first output terminal; the drain of the second NMOS transistor N2 is connected to the source of the second PMOS transistor P2 as the second output terminal of the delay cancellation unit; the gate of the first PMOS transistor is connected to the source of the second PMOS transistor P2, and the gate of the second PMOS transistor P2 is connected to the source of the first PMOS transistor P1 to form the cross-coupling structure; the drains of the first PMOS transistor P1 and the drains of the second PMOS transistor P2 are respectively connected to the power supply voltage; wherein the output control signal of the second output terminal is the inverted signal of the output control signal of the first output terminal.

[0033] Please see Figure 6 , Figure 6 This is a schematic diagram of the circuit structure of a switch array according to an embodiment of this application. The switch array includes multiple switch units, wherein the number of switch units is the square of the number of delay elimination units; each switch unit includes a third NMOS transistor N3, a fourth NMOS transistor N4, a third PMOS transistor P3, and a fourth PMOS transistor P4. The source of the third NMOS transistor N3 is connected to the source of the third PMOS transistor P3 as the first input terminal of the switch unit, and the drain of the third NMOS transistor N3 is connected to the drain of the third PMOS transistor P3 as the first output terminal of the switch unit; the source of the fourth NMOS transistor N4 is connected to the source of the fourth PMOS transistor P4 as the first output terminal of the switch unit. The second input terminal of the switching unit is the drain of the fourth NMOS transistor N4, which is connected to the drain of the fourth PMOS transistor P4 to serve as the second output terminal of the switching unit; the gate of the third NMOS transistor N3 serves as the first control terminal of the switching unit and is connected to the first output terminal of the delay elimination unit; the gate of the fourth NMOS transistor N4 serves as the second control terminal of the switching unit and is connected to the first output terminal of the delay elimination unit; the gate of the third PMOS transistor P3 is connected to the gate of the fourth PMOS transistor P4 to serve as the fifth control terminal of the switching unit and is connected to the second output terminal of the delay elimination unit.

[0034] Please see Figure 7 , Figure 7This is a schematic diagram of the scrambling method in one embodiment of this application. Taking eight reference voltages and one differential input voltage as an example, the quantizer input signal is the differential output signal of the loop filter in the Delta-Sigma modulator. The reference voltages are different voltages obtained by voltage division of the reference voltage under resistors. There are a total of 8 reference voltages and one differential input signal. The reference voltage is defined as REF[7:0]. The quantizer is mainly composed of 8 comparators and a reference voltage scrambling module. The comparators are four-input comparators, where VIP and VIN are connected to the differential input signal. The VREFN and VREFP of the 8 comparators can be written as VREFN[7:0] and VREFP[7:0]. The inputs of VREFN[n] and VREFP[n] are the reference voltages after scrambling by the reference voltage scrambling module. The control signal IN is an 8-bit strobe signal, with a total of 8 groups. The OUT signal is the same as the IN signal, and OUTN is the inverted signal of the OUT signal. In the first clock cycle, the reference voltage scrambling module is equivalent to IN1=00000001, IN2=00000010, IN3=00000100 up to IN8=10000000. Here, the IN input is represented as IN1=1, IN2=2 up to IN8=8. This group of signals makes REF[n]=VREFP[n], REF[7-n]=VREFN[n]. The reference voltage is connected to the comparator in order of magnitude. When the scrambling process begins, according to... Figure 4 As shown, after the second clock cycle arrives, IN1=2, IN2=4, IN3=1, IN4=6, IN5=3, IN6=8, IN7=5, IN8=7. This makes REF[1]=VREFP[0], REF[3]=VREFP[1], REF[0]=VREFP[2], REF[5]=VREFP[3], REF[2]=VREFP[4], REF[7]=VREFP[5], REF[4]=VREFP[6], REF[6]=VREFP[7], thus realizing the first scrambling of the reference voltage. After the subsequent clock cycle arrives, the 8 groups of input signals IN are arranged according to... Figure 4 The scrambling strategy shown continues to change, causing the connection order of the reference voltage and the comparator to be regularly scrambled over time.

[0035] After receiving four input signals, power supply voltage, and control clock signal, the comparator starts working. When the control clock is high, the comparator resets and outputs a high level. When the control clock is low, the comparator performs a comparison, comparing the magnitudes of the VIN-VREFN and VIP-VREFP signals and outputting the result. Since the outputs of the eight comparators are eight-bit thermometer codes, the order of the thermometer codes does not affect their magnitude, so it does not affect the quantization output result; only the thermometer codes are scrambled. However, different thermometer codes representing the same result control different equally weighted DACs. Therefore, the scrambled thermometer codes control different DACs when representing the same digital quantity. This causes subsequent DACs to be scrambled according to the scrambling method of the thermometer codes, reducing the nonlinear distortion of the DACs.

[0036] Based on the technical solutions of the embodiments of this application above, the offset voltage of the comparator is reduced by chopping technology, thereby improving the accuracy of the quantizer; the improved four-input comparator improves the speed and accuracy of the traditional comparator while reducing threshold voltage loss, making it easier to implement under advanced low power supply voltage processes; the reference voltage scrambling module scrambles the input reference voltages of each comparator, so that the output 8-bit thermometer code has a scrambling effect, and controlling the operation of the subsequent equally weighted DAC circuit can effectively reduce the nonlinear distortion problem of the DAC.

[0037] Please see Figure 8 , Figure 8 A flowchart illustrating a control method for a Flash-type quantizer used in a Delta-Sigma modulator according to one embodiment of this application is shown. The method includes:

[0038] Step S800: The target reference voltage pair is output after the multiple pairs of differential reference voltage outputs obtained by voltage division by the resistor array are sequentially scrambled by the reference voltage scrambling module.

[0039] Step S810: Each of the multiple comparators receives a differential input voltage and a target reference voltage pair to obtain a comparison result, and controls the connected DAC circuit to output to the loop filter in the Delta-Sigma modulator according to the comparison result, wherein the differential input voltage is the output voltage of the loop filter, and the number of differential reference voltages corresponds to the number of comparators;

[0040] Step S820: The input signals of the comparators are swapped by multiple chopper modules and then input to the corresponding comparators to eliminate the offset voltage of the comparators. The chopper modules are configured in a one-to-one correspondence with the comparators.

[0041] The specific execution process has been described in detail in the aforementioned circuit embodiments, and will not be repeated here.

[0042] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A Flash-type quantizer for a Delta-Sigma modulator, characterized in that, include: The reference voltage scrambling module is used to sequentially scramble multiple pairs of differential reference voltage outputs obtained by voltage division through a resistor array and then output the target reference voltage pair. Multiple comparators, each of which receives a differential input voltage and a target reference voltage pair to obtain a comparison result, and controls a connected DAC circuit to output to a loop filter in the Delta-Sigma modulator based on the comparison result, wherein the differential input voltage is the output voltage of the loop filter, and the number of logarithmic differential reference voltages corresponds to the number of comparators; Multiple chopper modules are used to swap the input signals of the comparators and input them to the corresponding comparators to eliminate the offset voltage of the comparators, wherein the chopper modules are configured in a one-to-one correspondence with the comparators; The reference voltage scrambling module includes: multiple delay elimination units, which are connected to multiple input control signals and generate corresponding output control signal pairs. The delay elimination units eliminate the delay between the output control signal pairs through a cross-coupling structure. The number of bits in the input control signals corresponds to the number of output control signal pairs and the number of comparators. A switch array is connected to the output control signal pairs to control the transmission relationship between the multiple pairs of differential reference voltages obtained by the resistor array voltage division and the target reference voltage pairs. The switch array also polls the multiple input control signals at intervals to adjust the output order of the target reference voltage pairs.

2. The Flash-type quantizer for a Delta-Sigma modulator according to claim 1, characterized in that, The delay cancellation unit includes: a delay unit, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor. The input terminal of the delay unit is connected to the gate of the second NMOS transistor as the input terminal of the delay cancellation unit and is connected to the input control signal. The output terminal of the delay unit is connected to the gate of the first NMOS transistor, and the sources of the first NMOS transistor and the second NMOS transistor are grounded. The drain of the first NMOS transistor is connected to the source of the first PMOS transistor as the first output terminal of the delay cancellation unit. The drain of the second NMOS transistor is connected to the source of the second PMOS transistor as the second output terminal of the delay cancellation unit. The gate of the first PMOS transistor is connected to the source of the second PMOS transistor, and the gate of the second PMOS transistor is connected to the source of the first PMOS transistor to form the cross-coupling structure. The drains of the first PMOS transistor and the second PMOS transistor are respectively connected to the power supply voltage. The output control signal of the second output terminal is the inverted signal of the output control signal of the first output terminal.

3. The Flash-type quantizer for a Delta-Sigma modulator according to claim 2, characterized in that, The switch array includes multiple switch units, wherein the number of switch units is the square of the number of delay elimination units. Each switch unit includes a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The source and source of the third NMOS transistor are connected to each other as the first input terminal of the switch unit, and the drain and drain of the third NMOS transistor are connected to each other as the first output terminal of the switch unit. The source and source of the fourth NMOS transistor are connected to each other as the second input terminal of the switch unit, and the drain and drain of the fourth NMOS transistor are connected to each other as the second output terminal of the switch unit. The gate of the third NMOS transistor is connected to the first control terminal of the switch unit and the first output terminal of the delay elimination unit. The gate of the fourth NMOS transistor is connected to the second control terminal of the switch unit and the first output terminal of the delay elimination unit. The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor as the fifth control terminal of the switch unit and the second output terminal of the delay elimination unit.

4. The Flash-type quantizer for a Delta-Sigma modulator according to claim 1, characterized in that, The chopper module includes a first chopper unit, a second chopper unit, a third chopper unit, a fourth chopper unit, and a fifth chopper unit. The first chopper unit has a first input terminal connected to a first input voltage, a second input terminal connected to a first reference voltage, a first output terminal connected to the first input terminal of the second chopper unit, and a second output terminal connected to the first input terminal of the fourth chopper unit. The third chopper unit has a first input terminal connected to a second reference voltage, a second input terminal connected to a second input voltage, a first output terminal connected to the second input terminal of the second chopper unit, and a second output terminal connected to the second input terminal of the fourth chopper unit. The two output terminals of the second chopper unit and the two output terminals of the fourth chopper unit are respectively connected to the corresponding input terminals of the comparator. The first and second input terminals of the fifth chopper unit are connected to the corresponding output terminals of the comparator, and the two output terminals of the fifth chopper unit output the comparison result. The first and third chopper units are controlled by a first clock signal, while the second, fourth, and fifth chopper units are all controlled by a second clock signal. The first input voltage and the second input voltage form a differential input voltage pair, and the first reference voltage and the second reference voltage form a target reference voltage pair.

5. The Flash-type quantizer for a Delta-Sigma modulator according to claim 4, characterized in that, The first chopper unit, second chopper unit, third chopper unit, fourth chopper unit, and fifth chopper unit have the same circuit structure. The first chopper unit includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor. The drain of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor as the first input terminal of the first chopper unit, and the drain of the sixth NMOS transistor is connected to the drain of the seventh NMOS transistor as the first output terminal of the first chopper unit. The gates of the fifth NMOS transistor and the seventh NMOS transistor are connected to the inverted clock signal of the first clock signal. The drain of the eighth NMOS transistor is connected to the source of the seventh NMOS transistor as the second input terminal of the first chopper unit, and the source of the eighth NMOS transistor is connected to the source of the fifth NMOS transistor as the second output terminal of the first chopper unit. The gate of the eighth NMOS transistor is connected to the first clock signal.

6. The Flash-type quantizer for a Delta-Sigma modulator according to claim 3, characterized in that, The comparator includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor; The source of the first transistor, the source of the third transistor, the drain of the fifth transistor, the drain of the seventh transistor, the gate of the sixth transistor, the source of the ninth transistor, and the gate of the eleventh transistor are connected together. The drain of the first transistor, the drain of the third transistor, the drain of the second transistor, the drain of the fourth transistor, and the source of the tenth transistor are connected together. The gates of the first transistor and the second transistor are connected to the differential input voltage pair. The gates of the third transistor and the fourth transistor are connected to the target reference voltage pair. The sources of the second transistor, the fourth transistor, the sixth transistor, the eighth transistor, the gate of the fifth transistor, the drain of the ninth transistor, and the gate of the twelfth transistor are connected together. The gates of the tenth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are connected to a clock signal. The drain of the tenth transistor is connected to the power supply voltage. The eleventh transistor and the twelfth transistor... The source is grounded; the drain of the eleventh transistor, the source of the thirteenth transistor, and the source of the nineteenth transistor are connected together; the drain of the twelfth transistor, the source of the fourteenth transistor, and the source of the twentieth transistor are connected together; the drain of the thirteenth transistor is connected to the source of the fifteenth transistor, the source of the seventeenth transistor, the gate of the sixteenth transistor, and the gate of the fourteenth transistor, serving as the first output terminal of the comparator; the drain of the fourteenth transistor is connected to the source of the sixteenth transistor, the source of the eighteenth transistor, the gate of the fifteenth transistor, and the gate of the thirteenth transistor, serving as the second output terminal of the comparator; the drains of the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, and the twentieth transistor are connected to the power supply voltage; the gates of the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, and the twentieth transistor are connected to the inverted signal of the clock signal.

7. A control method for a Flash-type quantizer used in a Delta-Sigma modulator, characterized in that, include: The target reference voltage pair is output after the multiple pairs of differential reference voltages obtained by voltage division by the resistor array are sequentially scrambled by the reference voltage scrambling module. Each of the multiple comparators receives a differential input voltage and a target reference voltage pair to obtain a comparison result, and controls the output of the connected DAC circuit to the loop filter in the Delta-Sigma modulator based on the comparison result, wherein the differential input voltage is the output voltage of the loop filter, and the number of differential reference voltages corresponds to the number of comparators; The input signals of the comparator are swapped by multiple chopper modules and then input to the corresponding comparator to eliminate the offset voltage of the comparator. The chopper modules are configured in a one-to-one correspondence with the comparators. The reference voltage scrambling module includes: multiple delay elimination units, which are connected to multiple input control signals and generate corresponding output control signal pairs. The delay elimination units eliminate the delay between the output control signal pairs through a cross-coupling structure. The number of bits in the input control signals corresponds to the number of output control signal pairs and the number of comparators. A switch array is connected to the output control signal pairs to control the transmission relationship between the multiple pairs of differential reference voltages obtained by the resistor array voltage division and the target reference voltage pairs. The switch array also polls the multiple input control signals at intervals to adjust the output order of the target reference voltage pairs.

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