Preparation method of thin-film resistor and semiconductor device
Patent Information
- Application Number
- CN202411865928.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-17
- Publication Date
- 2025-04-22
Smart Images
Figure CN119866177A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for preparing a thin film resistor and a semiconductor device. Background Art
[0002] The use of thin film resistors as integrated passive components significantly reduces the surface parasitic effects of semiconductor devices at high frequencies, increases packaging density, and improves device reliability. With the advancement of integrated circuit technology and the reduction of device size, higher requirements are placed on thin film resistors in integrated circuits, and high-precision thin film resistors have entered people's field of vision. High-precision thin film resistors have higher square resistance and stronger radiation resistance, and have shown excellent performance in high and low temperature and humid environments. Therefore, they are widely used in aviation, communications, automotive electronics, medical equipment, smart phones, navigation systems and other fields. The temperature coefficient of resistance TCR (Temperature Coefficient of Resistance) is a parameter used to indicate the degree to which the resistance of a thin film resistor changes with temperature. It is a key parameter to measure the sensitivity of resistance to temperature changes. The more stable the resistance of a thin film resistor is during temperature changes, the smaller the absolute value of TCR, which is expressed in ppm / ℃. Since the stability of TCR is crucial to precision electronic equipment, how to further optimize the temperature coefficient of resistance (TCR) of thin film resistors has become a technical problem that needs to be solved in this field. Summary of the invention
[0003] In view of the above shortcomings of the prior art, an object of the present invention is to provide a method for preparing a thin film resistor and a semiconductor device to improve the temperature coefficient of resistance of the thin film resistor, improve production efficiency and reduce production costs.
[0004] In order to achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a thin film resistor, comprising:
[0005] Providing a semiconductor substrate, on which an interlayer dielectric layer is formed;
[0006] A thin film resistor layer is formed on the interlayer dielectric layer, and the material forming the thin film resistor layer includes metal components and non-metal components. When forming the thin film resistor layer, the weight ratio of the metal component to the non-metal component in the target material for depositing the thin film resistor layer is controlled so that the weight ratio of the metal component in the target material is between 20% and 50%.
[0007] Optionally, the metal component comprises chromium or nickel.
[0008] Optionally, the non-metal component in the material of the thin film resistor layer includes one or more of silicon, oxygen or nitrogen, and the non-metal component in the target material of the thin film resistor layer includes silicon.
[0009] Optionally, the step of forming a thin film resistor layer on the interlayer dielectric layer further includes:
[0010] When forming the thin film resistor layer, nitrogen or oxygen is introduced into the reaction chamber.
[0011] Optionally, the step of forming a thin film resistor layer on the interlayer dielectric layer further includes:
[0012] The sputtering power is controlled to be between 900 W and 1800 W, and the nitrogen flow rate is controlled to be between 5 sccm and 15 sccm.
[0013] Optionally, the formed thin film resistor layer is a chromium silicon nitrogen thin film layer, and the resistance temperature coefficient of the formed thin film resistor layer is between -5ppm / °C and 5ppm / °C.
[0014] Optionally, the step of forming a thin film resistor layer on the interlayer dielectric layer further includes:
[0015] The sputtering power is controlled between 300W and 900W.
[0016] Optionally, the formed thin film resistor layer is a chromium silicon thin film layer, and the resistance temperature coefficient of the formed thin film resistor layer is between -15 ppm / °C and 15 ppm / °C.
[0017] Optionally, the step of forming a thin film resistor layer on the interlayer dielectric layer includes:
[0018] The thickness of the thin film resistor layer is controlled to be between
[0019] Optionally, when forming the thin film resistor layer, the process temperature is controlled to be room temperature.
[0020] Optionally, the step of forming a thin film resistor layer on the interlayer dielectric layer further includes:
[0021] The argon gas flow rate is controlled between 30 sccm and 70 sccm.
[0022] According to one aspect of the present invention, the present invention further provides a semiconductor device, the semiconductor device comprising:
[0023] A semiconductor substrate, wherein the semiconductor substrate includes at least one transistor and an interlayer dielectric layer is formed on the semiconductor substrate;
[0024] The thin film resistor is formed on the interlayer dielectric layer, and the thin film resistor is formed by using the above-mentioned thin film resistor preparation method.
[0025] Compared with the prior art, the method for preparing the thin film resistor and the semiconductor device of the present invention have at least the following beneficial effects:
[0026] The preparation method of the thin film resistor of the present invention includes providing a semiconductor substrate, on which an interlayer dielectric layer is formed. A thin film resistor layer is formed on the interlayer dielectric layer, and the material forming the thin film resistor layer includes metal components and non-metal components; when forming the thin film resistor layer, the weight ratio of the metal component to the non-metal component in the target material for depositing the thin film resistor layer is controlled so that the weight ratio of the metal component in the target material is between 20% and 50%. Furthermore, the present invention sputters and deposits the thin film resistor layer by changing the weight ratio of the metal component to the non-metal component in the target material, increasing the weight ratio of the non-metal component in the target material, and reducing the weight ratio of the metal component to reduce the temperature coefficient of resistance and improve the temperature stability of the resistor. Among them, increasing the non-metal component in the thin film resistor layer can, on the one hand, introduce more impurities into the thin film resistor, increase electron scattering, and reduce the temperature coefficient of resistance. On the other hand, the lattice constant of the thin film resistor layer can be changed, lattice distortion is generated, electron scattering is increased, and the temperature coefficient of resistance is reduced. Furthermore, increasing the proportion of non-metal components in the present invention helps to adjust the temperature coefficient of resistance in the negative direction, effectively improves the temperature coefficient of resistance (TCR) of the resistor, and improves the temperature stability of the resistor. Furthermore, since the temperature coefficient of resistance is more easily adjusted in a negative direction, the sputtering power when forming thin film resistors can be further increased and the process temperature can be further reduced, thereby improving production efficiency and reducing production costs.
[0027] Furthermore, the present invention also includes the step of introducing nitrogen or oxygen during the deposition process when depositing the thin film resistor layer. The addition of nitrogen makes the temperature coefficient of resistance more controllable, which allows the use of higher sputtering power to deposit the thin film resistor. Higher sputtering power can increase the deposition rate and reduce the required deposition time under a certain film thickness range, thereby improving production efficiency.
[0028] The thin film resistor in the semiconductor device of the present invention is formed by adopting the above-mentioned method for preparing the thin film resistor, and also has the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 is a flow chart of the steps of the method for preparing a thin film resistor in Example 1 of the present invention;
[0030] Figure 2 Schematic diagram of the structure of the semiconductor device in Example 2 of the present invention.
[0031] List of reference numerals:
[0032] 100 Semiconductor Substrate
[0033] 200 First interlayer dielectric layer / interlayer dielectric layer
[0034] 300 Thin Film Resistor
[0035] 400 Barrier layer
[0036] 500 Second interlayer dielectric layer
[0037] 600 Conductive Vias DETAILED DESCRIPTION
[0038] The following specific embodiments illustrate the embodiments of the present invention, and those familiar with the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.
[0039] It should be noted that the diagrams provided in the embodiments of the present invention are only used to illustrate the basic concept of the present invention in a schematic manner. Although the diagrams only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of each component can be changed at will during actual implementation, and the layout of the components may also be more complex. The structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions that can be implemented in this application, so they have no technical substantive significance. Any structural modification, change in proportional relationship or adjustment of size should still fall within the scope of the technical content disclosed in this application without affecting the effects and purposes that can be achieved by the present invention.
[0040] The temperature coefficient of resistance (TCR) is a parameter used to indicate the degree to which the resistance of a thin film resistor changes with temperature. It is a key parameter to measure the sensitivity of resistance to temperature changes. The more stable the resistance of a thin film resistor is during temperature changes, the smaller the absolute value of the TCR is, and the unit is ppm / ℃. The calculation formula for the temperature coefficient of resistance (TCR) is as follows:
[0041]
[0042] Where: T0: initial temperature before temperature change; T: final temperature after temperature change; R T0 : Initial resistance value before temperature change; R T : Final resistance value after temperature change.
[0043] The preparation process of thin film resistors will affect the size of their resistance temperature coefficient. In the traditional process, magnetron sputtering is generally used to form thin film resistors. In this process, a target material with a weight ratio of chromium to silicon of 60:40 is used to deposit at a process temperature of 200°C and a power of 400W. The chromium silicon thin film resistor layer is deposited, and the resistor temperature coefficient is optimized by adjusting the sputtering power, annealing temperature and time. However, when the inventors used the deposition method of the thin film resistor to prepare the thin film resistor, they found that the scheme had the following disadvantages:
[0044] 1) The temperature coefficient of resistance is positive: The temperature coefficient of resistance of the entire thin film resistor prepared by the existing process is positive, which cannot approach the ideal value of the temperature coefficient of resistance (TCR) approaching 0, and is limited in application scenarios with high TCR requirements.
[0045] 2) Low adjustability of the temperature coefficient of resistance: Controlling the temperature coefficient of resistance only by adjusting the sputtering power, annealing temperature, and annealing time of the chromium silicon film deposition may limit the adjustment range, resulting in low adjustability and unable to meet the precise control requirements of the TCR value for certain specific applications.
[0046] 3) High process temperature and machine requirements: The process temperature for depositing sputtered chromium silicon resistor film is 200°C, which places high demands on the machine structure and increases costs. At the same time, high temperature may have an adverse effect on film stress.
[0047] 4) Long process time: Using 400W deposition sputtering power is low, the process time is long, affecting production efficiency.
[0048] In order to solve the background technology and the above technical problems, the present embodiment provides a method for preparing a thin film resistor and a semiconductor device, so that the temperature coefficient of resistance of the thin film resistor can be adjusted in the negative direction, and the temperature coefficient of resistance (TCR) of the resistor is improved. At the same time, the requirements for process temperature and machine platform are reduced, the process time is reduced, and the production efficiency is improved.
[0049] The present invention is described in detail below with reference to specific examples.
[0050] Example 1
[0051] This embodiment provides a method for preparing a thin film resistor. Figure 1 , the preparation method of the thin film resistor comprises:
[0052] S1: providing a semiconductor substrate, on which an interlayer dielectric layer is formed;
[0053] Specifically, a semiconductor substrate is provided, which includes at least one of materials such as Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, etc., or a multilayer structure composed of the above semiconductor materials. Alternatively, the semiconductor substrate is silicon on insulator (SOI) or germanium on insulator (GOI), etc. In addition, at least one transistor is formed inside the semiconductor substrate, and the transistor can be a CMOS device, a logic device, etc.
[0054] The interlayer dielectric layer is formed on the semiconductor substrate, and its material can be silicon oxide, silicon nitride and other materials well known to those skilled in the art. The method for forming the interlayer dielectric layer includes: performing a deposition process to cover a layer of dielectric material layer on the semiconductor substrate, and performing a planarization process on the dielectric material layer to form the interlayer dielectric layer. It should be noted that other dielectric layers or metal layers may be included between the interlayer dielectric layer and the semiconductor substrate, and this embodiment does not limit this.
[0055] S2: forming a thin film resistor layer on the interlayer dielectric layer, wherein the material forming the thin film resistor layer includes a metal component and a non-metal component. When forming the thin film resistor layer, the weight ratio of the metal component to the non-metal component in the target material for depositing the thin film resistor layer is controlled so that the weight ratio of the metal component in the target material is between 20% and 50%.
[0056] The resistance temperature coefficient of the existing thin film resistor layer is positive. The reason is that the existing process uses a chromium-silicon 60:40 weight ratio target to sputter and deposit chromium-silicon thin film. Since the chromium metal component in the target material accounts for a large weight ratio, the metal characteristics of the deposited thin film chromium dominate. Since the resistivity of the metal increases with the increase of temperature, the resistance temperature coefficient of the entire film is positive, which cannot approach the ideal value of TCR approaching 0.
[0057] In order to solve the technical problem of the positive bias of the resistivity of the existing thin film resistor layer, this embodiment adopts the method of changing the weight ratio of the metal component to the non-metal component in the target material, increasing the weight ratio of the non-metal component in the target material, and sputtering and depositing the thin film resistor layer, which helps to adjust the temperature coefficient of resistance to the negative direction, effectively improve the temperature coefficient of resistance (TCR) of the resistor, and improve the temperature stability of the resistor. Among them, the technical principle that increasing the proportion of non-metallic elements in the target material can reduce the temperature coefficient of the thin film resistor is as follows: 1) Increasing the proportion of non-metallic elements in the target material so that the thin film resistor has a doping effect. Specifically, the increase of non-metallic elements will introduce more impurities into the thin film resistor, and these impurities can act as additional defect points, increase the scattering of electrons, and reduce the temperature coefficient of resistance of the thin film resistor. 2) Increasing the proportion of non-metallic elements in the target material can improve the lattice constant of the thin film resistor. Specifically, increasing the proportion of non-metallic elements in the target material, the addition of non-metallic elements will change the lattice constant of the chromium silicon film, resulting in lattice distortion, thereby increasing electron scattering and reducing the temperature coefficient of resistance of the thin film resistor.
[0058] Based on the above principles, this embodiment forms a thin film resistor layer on the interlayer dielectric layer formed in step S1. When forming the thin film resistor layer, the weight ratio of the metal component to the non-metal component in the target material for depositing the thin film resistor layer is controlled so that the weight ratio of the metal component in the target material is between 20% and 50%, and the weight ratio of the non-metal component is between 50% and 80%. Among them, the sum of the weight ratio of the metal component and the weight ratio of the non-metal component is 100%. For example, the weight ratio of the metal component to the non-metal component in the target material is 20:80, 25:75, 30:70, 40:60 or 50:50. Among them, the metal component in the target material may include chromium, nickel or titanium, and the non-metal component may include silicon. The non-metal component in the thin film resistor layer finally formed may also include nitrogen or oxygen.
[0059] In a specific example of this embodiment, the metal component in the target material is chromium, and the non-metal component is silicon. In the process step of forming the thin film resistor layer, the thin film resistor layer is deposited by a magnetron sputtering method. During the deposition process, in a high vacuum process chamber, the weight ratio of chromium to silicon in the target material for depositing the thin film resistor layer is controlled to be 20:80, and the sputtering frequency is controlled to be between 300W and 900W. A chromium silicon thin film layer is formed at room temperature, and the thickness of the chromium silicon thin film layer is between The resistance temperature coefficient of the formed chromium silicon thin film layer is between -15ppm / ℃ and 15ppm / ℃. Due to the increase of non-metallic components in the target material in the deposited thin film resistor layer, the existing process parameters are no longer suitable for preparing thin film resistors. This embodiment further optimizes the process parameters while increasing the non-metallic components in the target material: the sputtering frequency in this example is further increased by adjusting the sputtering frequency, for example, the sputtering frequency can be increased to 500W, 600W, 800W or 900W. Due to the increase of non-metallic components in the thin film resistor, the resistance temperature coefficient can be adjusted in a negative direction. Increasing the sputtering frequency will not have a significant impact on the resistance temperature coefficient in this example. At the same time, the sputtering process can also be carried out in a room temperature chamber environment, without the need to control the high temperature sputtering temperature. Furthermore, this example helps to reduce the machine construction cost caused by the process temperature, while also reducing the impact of high temperature on film stress, which is beneficial to improving device performance.
[0060] In an optional embodiment, when preparing the thin film resistor layer, nitrogen or oxygen may be introduced into the reaction chamber to further improve the temperature coefficient of resistance and increase the sputtering power during the process. Due to the introduction of nitrogen or oxygen, a non-metallic component is introduced into the thin film resistor, which can further increase electron scattering and reduce the temperature coefficient of resistance.
[0061] In a specific example of this optional embodiment, the metal component in the target material is chromium, and the non-metal component is silicon. In the process step of forming the thin film resistor layer, the thin film resistor layer is deposited by a magnetron sputtering method. During the deposition process, in a high vacuum process chamber, the weight ratio of chromium to silicon in the target material for depositing the thin film resistor layer is controlled to be 30:70. The sputtering power is controlled to be between 900W and 1800W, and the nitrogen flow rate is between 5sccm and 15sccm. A chromium silicon nitrogen thin film layer is formed at room temperature, and the thickness of the chromium silicon nitrogen thin film layer is between The resistance temperature coefficient of the formed chromium silicon nitrogen thin film layer is between -5ppm / ℃ and 5ppm / ℃. In this example, the resistance temperature coefficient is more controllable due to the addition of nitrogen, which allows the use of higher sputtering powers to deposit thin film resistors. For example, the sputtering power can be increased to 900W, 1000W, 1500W or 1800W. Higher sputtering power can increase the deposition rate and reduce the required deposition time under a certain film thickness range, thereby improving production efficiency. Similarly, this example allows the sputtering process to be performed in a room temperature chamber environment without the need to control the high temperature sputtering temperature, which helps to reduce the cost of machine construction and also reduces the impact of high temperature on film stress. Furthermore, this example increases the non-metal content in the film by increasing the weight ratio of silicon in the target material and introducing nitrogen as a reactive gas, which helps to adjust the resistance temperature coefficient in a negative direction, effectively improving the resistance temperature coefficient (TCR) of the resistor and improving the temperature stability of the resistor.
[0062] In other examples, oxygen can be introduced instead of nitrogen during the process to form a chromium silicon oxide thin film layer, and the process parameters are similar to those for forming a chromium silicon nitrogen thin film layer, and the sputtering power can be further increased, and the process can be performed at room temperature. In addition, the production efficiency can be improved, the cost can be reduced, and a thin film resistor with a resistance temperature coefficient of -5ppm / ℃ to 5ppm / ℃ can be obtained, and the formation quality is good.
[0063] In the above example, argon gas is also introduced during the deposition of the thin film resistor layer. The argon gas, as a working gas for physical vapor deposition, provides the necessary atmosphere for the sputtering process. During sputtering coating, high-energy ions of argon gas are used to bombard the surface of the target material, thereby releasing atoms or molecules, which are deposited on the surface of the substrate to form a thin film. In this embodiment, the flow rate of the introduced argon gas is controlled to be between 30sccm and 70sccm. The use of this argon flow rate range in conjunction with the above process parameters can increase the sputtering rate. When high-energy argon ions bombard the surface of the target material, not only can the atoms or molecules of the target material be knocked out, but more secondary electrons can also be generated on the surface of the target material. These secondary electrons will accelerate more argon ions to bombard the target material, thereby forming a positive sputtering cycle. Under the above process parameter conditions, the argon flow rate setting is conducive to increasing the sputtering rate.
[0064] Optionally, the formed thin film resistor layer is directly formed into the shape of a thin film resistor, or after the thin film resistor layer is formed, the thin film resistor layer is further etched to form the thin film resistor layer, which is not limited in this embodiment.
[0065] In summary, by adjusting the target material composition and increasing the weight ratio of silicon in the target material, the resistance-temperature characteristics of the deposited thin film resistor are significantly optimized, while improving production efficiency and reducing costs. By optimizing the process parameters, a thin film resistor with good resistance-temperature performance can be obtained to meet the needs of different application fields, and can be carried out at room temperature, thereby reducing thermal stress and improving the stability and reliability of the material.
[0066] Example 2
[0067] This embodiment provides a semiconductor device, referring to Figure 2 The semiconductor device includes a semiconductor substrate 100, an interlayer dielectric layer 200 and a thin film resistor 300. The semiconductor substrate 100 includes at least one transistor. The interlayer dielectric layer 200 is formed above the semiconductor substrate 100. The thin film resistor 300 is formed on the interlayer dielectric layer 200, and the thin film resistor 300 is formed by the thin film resistor preparation method in the above-mentioned embodiment 1.
[0068] In a specific example of this embodiment, Figure 2As shown, the semiconductor device includes a semiconductor substrate 100, a first interlayer dielectric layer 200, a thin film resistor 300, a barrier layer 400, a conductive via 600 and a second interlayer dielectric layer 500. Among them, the semiconductor substrate 100 contains at least one transistor, and the transistor can be a CMOS device, a logic device, etc. The first interlayer dielectric layer 200 is formed on the semiconductor substrate 100. The thin film resistor 300 is formed on the first interlayer dielectric layer 200. The thin film resistor 300 is also covered with a second interlayer dielectric layer 500, and a conductive via 600 is formed in the second interlayer dielectric layer 500, and a barrier layer 400 is formed between the conductive via 600 and the thin film resistor 300. The conductive via 600 is filled with a conductive material, and the conductive material in the conductive via 600 is connected to the thin film resistor 400 through the barrier layer 400. Optionally, the barrier layer 400 is TiN. Since the thin film resistor is often connected to the conductive material in the conductive via to connect the thin film resistor layer to an external circuit, but the conductive material and the material of the thin film resistor 300 are easily miscible at high temperatures, the addition of the barrier layer 400 in this embodiment can effectively prevent the conductive material in the conductive via and the thin film resistor 300 from miscible, thereby improving the reliability of the device.
[0069] The semiconductor device in this embodiment includes a thin film resistor, which is formed by the thin film resistor preparation method in the embodiment, which helps to improve the temperature stability and formation quality of the thin film resistor and improve the device performance. In addition, the semiconductor device also has higher production efficiency and lower production cost.
[0070] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for preparing a thin film resistor, characterized in that: include: Providing a semiconductor substrate, on which an interlayer dielectric layer is formed; A thin film resistor layer is formed on the interlayer dielectric layer, and the material forming the thin film resistor layer includes metal components and non-metal components. When forming the thin film resistor layer, the weight ratio of the metal component to the non-metal component in the target material for depositing the thin film resistor layer is controlled so that the weight proportion of the metal component in the target material is between 20% and 50%.
2. The method for preparing a thin film resistor according to claim 1, characterized in that: The metal component includes chromium or nickel.
3. The method for preparing a thin film resistor according to claim 1, characterized in that: The non-metal component in the material of the thin film resistor layer includes one or more of silicon, oxygen or nitrogen, and the non-metal component in the target material of the thin film resistor layer includes silicon.
4. The method for preparing a thin film resistor according to claim 1, characterized in that: The step of forming a thin film resistor layer on the interlayer dielectric layer further includes: When forming the thin film resistor layer, nitrogen or oxygen is introduced into the reaction chamber.
5. The method for preparing a thin film resistor according to claim 4, characterized in that: The step of forming a thin film resistor layer on the interlayer dielectric layer further includes: The sputtering power is controlled to be between 900 W and 1800 W, and the nitrogen flow rate is controlled to be between 5 sccm and 15 sccm.
6. The method for preparing a thin film resistor according to claim 4, characterized in that: The formed thin film resistor layer is a chromium silicon nitrogen thin film layer, and the resistance temperature coefficient of the formed thin film resistor layer is between -5ppm / °C and 5ppm / °C.
7. The method for preparing a thin film resistor according to claim 1, characterized in that: The step of forming a thin film resistor layer on the interlayer dielectric layer further includes: The sputtering power is controlled between 300W and 900W.
8. The method for preparing a thin film resistor according to claim 7, characterized in that: The formed thin film resistor layer is a chromium silicon thin film layer, and the resistance temperature coefficient of the formed thin film resistor layer is between -15ppm / °C and 15ppm / °C.
9. The method for preparing a thin film resistor according to claim 6 or 8, characterized in that: The step of forming a thin film resistor layer on the interlayer dielectric layer includes: The thickness of the thin film resistor layer is controlled to be between 10. The method for preparing a thin film resistor according to claim 5 or 7, characterized in that: When forming the thin film resistor layer, the process temperature is controlled to be room temperature.
11. The method for preparing a thin film resistor according to claim 5 or 7, characterized in that: The step of forming a thin film resistor layer on the interlayer dielectric layer further includes: The argon gas flow rate is controlled between 30 sccm and 70 sccm.
12. A semiconductor device, characterized in that: include: A semiconductor substrate, wherein at least one transistor is included in the semiconductor substrate and an interlayer dielectric layer is formed on the semiconductor substrate; A thin film resistor is formed on the interlayer dielectric layer, and the thin film resistor is formed by the method for preparing a thin film resistor according to any one of claims 1 to 11.