Pixel driving circuit and driving method thereof, display device

Abstract

A pixel driving circuit and its driving method, and a display device, the pixel driving circuit includes: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a storage sub-circuit, wherein the third control sub-circuit is electrically connected to a first reset signal line (Reset1), an auxiliary signal line (VX), and a third node (N3), and is configured to control the signal of the third node (N3) under the control of the signal of the first reset signal line (Reset1) and driven by the signal of the auxiliary signal line (VX); the storage sub-circuit is configured to store the voltage difference between the signals of the first node (N1) and the third node (N3).

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, specifically to a pixel driving circuit and its driving method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this application. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, this disclosure provides a pixel driving circuit, including: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a storage sub-circuit;

[0005] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide driving current to the third node under the control of the signals of the first node and the second node;

[0006] The first control sub-circuit is electrically connected to the first scan signal line, the second scan signal line, the data signal line, the reference signal line, and the first node, respectively, and is configured to provide the data signal line or the reference signal line to the first node under the control of the signals of the first scan signal line and the second scan signal line;

[0007] The second control sub-circuit is electrically connected to the first light-emitting signal line, the second light-emitting signal line, the first power supply line, the second node, the third node, and the fourth node, respectively. It is configured to provide the first power supply line signal to the second node and the third node signal to the fourth node under the control of the signals of the first light-emitting signal line and the second light-emitting signal line.

[0008] The third control sub-circuit is electrically connected to the first reset signal line, the auxiliary signal line and the third node respectively, and is configured to control the signal of the third node under the control of the signal of the first reset signal line and the drive of the signal of the auxiliary signal line.

[0009] The storage sub-circuit, which is electrically connected to the first node and the third node respectively, is configured to store the voltage difference of the signal between the first node and the third node.

[0010] In an exemplary embodiment, the third control sub-circuit includes: a sixth transistor and a second capacitor;

[0011] The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the auxiliary signal line, and the second electrode of the sixth transistor is electrically connected to the fifth node.

[0012] The first terminal of the second capacitor is electrically connected to the fifth node, and the second terminal of the second capacitor is electrically connected to the third node.

[0013] In an exemplary embodiment, the third control sub-circuit is also electrically connected to the third reset signal line and the initial signal line, respectively, and is configured to provide the initial signal line signal to the fourth node under the control of the signal of the third reset signal line.

[0014] In an exemplary embodiment, the third control sub-circuit further includes: an eighth transistor, the control electrode of the eighth transistor being electrically connected to the third reset signal line, the first electrode of the eighth transistor being electrically connected to the initial signal line, and the second electrode of the eighth transistor being electrically connected to the fourth node;

[0015] The signal on the auxiliary signal line is a non-DC signal and is electrically connected to the fourth node.

[0016] In an exemplary embodiment, the third control sub-circuit is also electrically connected to the second reset signal line and is configured to provide the signal of the fifth node to the third node under the control of the signal of the second reset signal line.

[0017] In an exemplary embodiment, the third control sub-circuit includes: a sixth transistor, a seventh transistor, and a second capacitor;

[0018] The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the auxiliary signal line, and the second electrode of the sixth transistor is electrically connected to the fifth node.

[0019] The control electrode of the seventh transistor is electrically connected to the second reset signal line, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the third node.

[0020] The first terminal of the second capacitor is electrically connected to the fifth node, and the second terminal of the second capacitor is electrically connected to the third node.

[0021] In an exemplary embodiment, the signal of the auxiliary signal line is a DC signal and is the same as the signal of any one of the initial signal line, the reference signal line, and the first power supply line.

[0022] In an exemplary embodiment, the third control sub-circuit includes: a sixth transistor and a second capacitor;

[0023] The first terminal of the second capacitor is electrically connected to the auxiliary signal line, and the second terminal of the second capacitor is electrically connected to the fifth node.

[0024] The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the fifth node, and the second electrode of the sixth transistor is electrically connected to the third node.

[0025] In an exemplary embodiment, the third control sub-circuit is also electrically connected to the third reset signal line and the initial signal line, respectively, and is configured to provide the initial signal line signal to the fourth node under the control of the signal of the third reset signal line.

[0026] In an exemplary embodiment, the third control sub-circuit further includes: an eighth transistor, the control electrode of the eighth transistor being electrically connected to the third reset signal line, the first electrode of the eighth transistor being electrically connected to the initial signal line, and the second electrode of the eighth transistor being electrically connected to the fourth node;

[0027] The signal of the auxiliary signal line is a DC signal, and the signal of the auxiliary signal line is the same as the signal of any one of the initial signal line, the reference signal line, and the first power supply line.

[0028] Alternatively, the signal of the auxiliary signal line is a non-DC signal, and the signal of the auxiliary signal line is electrically connected to the fourth node.

[0029] In an exemplary embodiment, the first control sub-circuit includes a first transistor and a second transistor, the driving sub-circuit includes a third transistor, the second control sub-circuit includes a fourth transistor and a fifth transistor, and the storage sub-circuit includes a first capacitor;

[0030] The control electrode of the first transistor is electrically connected to the first scan signal line, the first electrode of the first transistor is electrically connected to the data signal line, and the second electrode of the first transistor is electrically connected to the first node.

[0031] The control electrode of the second transistor is electrically connected to the second scan signal line, the first electrode of the second transistor is electrically connected to the reference signal line, and the second electrode of the second transistor is electrically connected to the first node.

[0032] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0033] The control electrode of the fourth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fourth transistor is electrically connected to the first power supply line, and the second electrode of the fourth transistor is electrically connected to the second node.

[0034] The control electrode of the fifth transistor is electrically connected to the second light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the fourth node.

[0035] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node.

[0036] In an exemplary embodiment, the first control sub-circuit includes a first transistor and a second transistor, the driving sub-circuit includes a third transistor, the second control sub-circuit includes a fourth transistor and a fifth transistor, the storage sub-circuit includes a first capacitor, the third control sub-circuit includes a second capacitor and a sixth transistor, and the third control sub-circuit further includes at least one of a seventh transistor and an eighth transistor.

[0037] The control electrode of the first transistor is electrically connected to the first scan signal line, the first electrode of the first transistor is electrically connected to the data signal line, and the second electrode of the first transistor is electrically connected to the first node.

[0038] The control electrode of the second transistor is electrically connected to the second scan signal line, the first electrode of the second transistor is electrically connected to the reference signal line, and the second electrode of the second transistor is electrically connected to the first node.

[0039] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0040] The control electrode of the fourth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fourth transistor is electrically connected to the first power supply line, and the second electrode of the fourth transistor is electrically connected to the second node.

[0041] The control electrode of the fifth transistor is electrically connected to the second light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the fourth node.

[0042] The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the auxiliary signal line, and the second electrode of the sixth transistor is electrically connected to the fifth node.

[0043] The control electrode of the seventh transistor is electrically connected to the second reset signal line, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the third node.

[0044] The control electrode of the eighth transistor is electrically connected to the third reset signal line, the first electrode of the eighth transistor is electrically connected to the initial signal line, and the second electrode of the eighth transistor is electrically connected to the fourth node.

[0045] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node.

[0046] The first terminal of the second capacitor is electrically connected to the fifth node, and the second terminal of the second capacitor is electrically connected to the third node.

[0047] Any one of the first to the eighth transistors is an N-type transistor.

[0048] In an exemplary embodiment, the third control sub-circuit includes: a sixth transistor, a seventh transistor, and a second capacitor.

[0049] During a portion of the time period when the signal of the first reset signal line is an effective level signal, the signals of the second reset signal line and the second light emission signal line are effective level signals. The signal of the second reset signal line is an effective level signal for at least a portion of the time period after the writing time period, wherein the writing time period is the time period during which the first scan signal line is an effective level signal.

[0050] In an exemplary embodiment, the third control sub-circuit includes: a sixth transistor, an eighth transistor, and a second capacitor.

[0051] During a portion of the time period when the signal of the third reset signal line is at an effective level, the signal of the second light emission signal line is at an effective level. The signals of the first reset signal line and the second light emission signal line are at least at an effective level for a portion of the time period after the writing time period, wherein the writing time period is the time period during which the first scan signal line is at an effective level.

[0052] In an exemplary embodiment, the third control sub-circuit includes: a sixth transistor, a seventh transistor, an eighth transistor, and a second capacitor.

[0053] When the signal of the first reset signal line is a valid level signal, the signal of the third reset signal line is a valid level signal, and the signal of the second reset signal line is an invalid level signal. When the signal of the second reset signal line is a valid level signal, the signal of the first reset signal line is an invalid level signal. During a certain period of time when the signal of the third reset signal line is a valid level signal, the signal of the second light emission signal line is a valid level signal. The signal of the second reset signal line is a valid level signal for at least a certain period of time after the writing period, wherein the writing period is the period during which the first scan signal line is a valid level signal.

[0054] In an exemplary embodiment, the first control sub-circuit includes a first transistor and a second transistor, the driving sub-circuit includes a third transistor, the second control sub-circuit includes a fourth transistor and a fifth transistor, the storage sub-circuit includes a first capacitor, and the third control sub-circuit includes a second capacitor, a sixth transistor, and an eighth transistor.

[0055] The control electrode of the first transistor is electrically connected to the first scan signal line, the first electrode of the first transistor is electrically connected to the data signal line, and the second electrode of the first transistor is electrically connected to the first node.

[0056] The control electrode of the second transistor is electrically connected to the second scan signal line, the first electrode of the second transistor is electrically connected to the reference signal line, and the second electrode of the second transistor is electrically connected to the first node.

[0057] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0058] The control electrode of the fourth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fourth transistor is electrically connected to the first power supply line, and the second electrode of the fourth transistor is electrically connected to the second node.

[0059] The control electrode of the fifth transistor is electrically connected to the second light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the fourth node.

[0060] The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the fifth node, and the second electrode of the sixth transistor is electrically connected to the third node.

[0061] The control electrode of the eighth transistor is electrically connected to the third reset signal line, the first electrode of the eighth transistor is electrically connected to the initial signal line, and the second electrode of the eighth transistor is electrically connected to the fourth node.

[0062] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node.

[0063] The first terminal of the second capacitor is electrically connected to the auxiliary signal line, and the second terminal of the second capacitor is electrically connected to the fifth node.

[0064] Any one of the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the eighth transistor is an N-type transistor.

[0065] In an exemplary embodiment, during a certain period of time when the signal of the third reset signal line is an effective level signal, the signal of the second light emission signal line is an effective level signal, and the signal of the first reset signal line is an invalid level signal during a period of time after the writing period. The writing period is the period during which the first scan signal line is an effective level signal.

[0066] Secondly, this disclosure also provides a display device having a display area, wherein the display area is provided with a plurality of the above-described pixel driving circuits.

[0067] Thirdly, this disclosure also provides a method for driving a pixel driving circuit, configured to drive the aforementioned pixel driving circuit, the method comprising:

[0068] The driving sub-circuit provides driving current to the third node under the control of the signals from the first and second nodes;

[0069] The first control sub-circuit provides data signal line or reference signal line signals to the first node under the control of the signals of the first scan signal line and the second scan signal line;

[0070] Under the control of the signals from the first and second light-emitting signal lines, the second control sub-circuit provides the signal from the first power line to the second node and the signal from the third node to the fourth node.

[0071] The third control sub-circuit controls the signal of the third node under the control of the signal of the first reset signal line and the signal of the auxiliary signal line;

[0072] The storage sub-circuit stores the voltage difference between the signals of the first node and the third node.

[0073] Fourthly, this disclosure also provides a method for driving a pixel driving circuit, configured to drive the aforementioned pixel driving circuit. The operation of the pixel driving circuit includes: a first stage to a fifth stage, and the method includes:

[0074] In the first stage, valid level signals are provided to the signals of the second scan signal line, the second light emission signal line, the first reset signal line and the second reset signal line. The first control sub-circuit provides the reference signal line signal to the first node. The third control sub-circuit provides the auxiliary signal line signal to the fifth node and provides the signal of the fifth node to the third node. The second control sub-circuit provides the signal of the fourth node to the third node.

[0075] In the second stage, effective level signals are provided to the first reset signal line, the second scan signal line and the first light emission signal line. The first control sub-circuit provides the reference signal line signal to the first node. The third control sub-circuit provides the auxiliary signal line signal to the fifth node. The second control sub-circuit provides the first power line signal to the second node to charge the first node. The storage sub-circuit stores the voltage difference between the signals of the first node and the third node.

[0076] In the third stage, the signals to the first reset signal line and the first scan signal line are high-level signals, the first control sub-circuit provides the data signal line signal to the first node, and the third control sub-circuit provides the auxiliary signal line signal to the fifth node;

[0077] In the fourth stage, an effective level signal is provided to the second reset signal line and the second light emission signal line, the third control sub-circuit provides the signal of the third node to the fifth node, and the second control sub-circuit provides the signal of the fourth node to the third node;

[0078] In the fifth stage, valid level signals are provided to the second reset signal line, the first light-emitting signal line, and the second light-emitting signal line. The second control sub-circuit provides the first power line signal to the second node and the third node signal to the fourth node. Under the control of the signals from the first and second nodes, the drive sub-circuit provides the drive current to the third node. The third control sub-circuit provides the third node signal to the fifth node.

[0079] Fifthly, this disclosure also provides a driving method for a pixel driving circuit, configured to drive the aforementioned pixel driving circuit. The operation of the pixel driving circuit includes: a first stage to a fifth stage, and the method includes:

[0080] In the first stage, valid level signals are provided to the signals of the second scan signal line, the second light emission signal line, the first reset signal line and the third reset signal line. The first control sub-circuit provides the reference signal line signal to the first node. The third control sub-circuit provides the auxiliary signal line signal to the fifth node and the initial signal line signal to the fourth node. The second control sub-circuit provides the signal of the fourth node to the third node.

[0081] In the second stage, effective level signals are provided to the first reset signal line, the third reset signal line, the second scan signal line, and the first light emission signal line. The first control sub-circuit provides a reference signal line signal to the first node. The third control sub-circuit provides an auxiliary signal line signal to the fifth node and an initial signal line signal to the fourth node. The second control sub-circuit provides a first power line signal to the second node to charge the first node. The storage sub-circuit stores the voltage difference between the signals of the first node and the third node.

[0082] In the third stage, the signals to the first reset signal line, the third reset signal line, and the first scan signal line are high-level signals. The first control sub-circuit provides the data signal line to the first node, the third control sub-circuit provides the auxiliary signal line to the fifth node, and provides the initial signal line to the fourth node.

[0083] In the fourth stage, effective level signals are provided to the first reset signal line, the third reset signal line, and the second light emission signal line. The third control sub-circuit provides the initial signal line signal to the fourth node and the auxiliary signal line signal to the fifth node. The second control sub-circuit provides the fourth node signal to the third node.

[0084] In the fifth stage, valid level signals are provided to the first reset signal line, the first light-emitting signal line, and the second light-emitting signal line. The second control sub-circuit provides the first power line signal to the second node and the third node signal to the fourth node. Under the control of the signals from the first and second nodes, the drive sub-circuit provides the drive current to the third node. The third control sub-circuit provides the auxiliary signal line signal to the fifth node.

[0085] Sixthly, this disclosure also provides a driving method for a pixel driving circuit, configured to drive the aforementioned pixel driving circuit. The operation of the pixel driving circuit includes: a first stage to a fifth stage, the method comprising:

[0086] In the first stage, valid level signals are provided to the signals of the second scan signal line, the second light emission signal line, the first reset signal line and the third reset signal line. The first control sub-circuit provides the reference signal line signal to the first node. The third control sub-circuit provides the auxiliary signal line signal to the fifth node and the initial signal line signal to the fourth node. The second control sub-circuit provides the signal of the fourth node to the third node.

[0087] In the second stage, effective level signals are provided to the first reset signal line, the third reset signal line, the second scan signal line, and the first light emission signal line. The first control sub-circuit provides a reference signal line signal to the first node. The third control sub-circuit provides an auxiliary signal line signal to the fifth node and an initial signal line signal to the fourth node. The second control sub-circuit provides a first power line signal to the second node to charge the first node. The storage sub-circuit stores the voltage difference between the signals of the first node and the third node.

[0088] In the third stage, the signals to the first reset signal line, the third reset signal line, and the first scan signal line are high-level signals. The first control sub-circuit provides the data signal line to the first node, the third control sub-circuit provides the auxiliary signal line to the fifth node, and provides the initial signal line to the fourth node.

[0089] In the fourth stage, valid level signals are provided to the second reset signal line, the third reset signal line, and the second light emission signal line. The third control sub-circuit provides the initial signal line signal to the fourth node, provides the third node signal to the fifth node, and the second control sub-circuit provides the fourth node signal to the third node.

[0090] In the fifth stage, valid level signals are provided to the second reset signal line, the first light-emitting signal line, and the second light-emitting signal line. The second control sub-circuit provides the first power line signal to the second node and the third node signal to the fourth node. Under the control of the signals from the first and second nodes, the drive sub-circuit provides the drive current to the third node. The third control sub-circuit provides the third node signal to the fifth node.

[0091] In a seventh aspect, this disclosure also provides a method for driving a pixel driving circuit, configured to drive the aforementioned pixel driving circuit. The operation of the pixel driving circuit includes: a first stage to a fifth stage, the method comprising:

[0092] In the first stage, valid level signals are provided to the signals of the second scan signal line, the second light emission signal line, the first reset signal line and the third reset signal line. The first control sub-circuit provides the reference signal line signal to the first node. The third control sub-circuit provides the signal of the third node to the fifth node and provides the signal of the initial signal line to the fourth node. The second control sub-circuit provides the signal of the fourth node to the third node.

[0093] In the second stage, effective level signals are provided to the first reset signal line, the third reset signal line, the second scan signal line, and the first light emission signal line. The first control sub-circuit provides the reference signal line signal to the first node. The third control sub-circuit provides the signal of the third node to the fifth node and the initial signal line signal to the fourth node. The second control sub-circuit provides the first power line signal to the second node to charge the first node. The storage sub-circuit stores the voltage difference between the signals of the first node and the third node.

[0094] In the third stage, the signals to the first reset signal line, the third reset signal line, and the first scan signal line are high-level signals. The first control sub-circuit provides the data signal line signal to the first node, and the third control sub-circuit provides the initial signal line signal to the fourth node and the signal of the third node to the fifth node.

[0095] In the fourth stage, an effective level signal is provided to the third reset signal line and the second light emission signal line. The third control sub-circuit provides the initial signal line signal to the fourth node, and the second control sub-circuit provides the signal of the fourth node to the third node.

[0096] In the fifth stage, effective level signals are provided to the first and second light-emitting signal lines. The second control sub-circuit provides the first power line signal to the second node and the third node signal to the fourth node. Under the control of the signals from the first and second nodes, the drive sub-circuit provides drive current to the third node.

[0097] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0098] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0099] Figure 1 This is a schematic diagram of the pixel driving circuit provided in an embodiment of the present disclosure;

[0100] Figure 2 Equivalent circuit of the third control sub-circuit Figure 1 ;

[0101] Figure 3 Equivalent circuit of the third control sub-circuit Figure 2 ;

[0102] Figure 4 Equivalent circuit of the third control sub-circuit Figure 3 ;

[0103] Figure 5 Equivalent circuit of the third control sub-circuit Figure 4 ;

[0104] Figure 6 Equivalent circuit of the third control sub-circuit Figure 5 ;

[0105] Figure 7 Equivalent circuit of the third control sub-circuit Figure 6 ;

[0106] Figure 8 This is a partial equivalent circuit diagram of the pixel driving circuit;

[0107] Figure 9 Equivalent circuit of pixel driving circuit Figure 1 ;

[0108] Figure 10 Equivalent circuit of pixel driving circuit Figure 2 ;

[0109] Figure 11 Equivalent circuit of pixel driving circuit Figure 3 ;

[0110] Figure 12 Equivalent circuit of pixel driving circuit Figure 4 ;

[0111] Figure 13 Equivalent circuit of pixel driving circuit Figure 5 ;

[0112] Figure 14 Equivalent circuit of pixel driving circuit Figure 6 ;

[0113] Figure 15 for Figure 9 and Figure 10 The provided timing diagram of the pixel driving circuit;

[0114] Figure 16 for Figure 11 The provided timing diagram of the pixel driving circuit;

[0115] Figure 17 for Figure 12 The provided timing diagram of the pixel driving circuit;

[0116] Figure 18 for Figure 13 and Figure 14 The provided timing diagram for the pixel driving circuit. Detailed Implementation

[0117] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0118] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0119] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0120] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0121] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0122] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0123] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0124] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0125] With the development of OLED display technology, oxide processes are frequently used in OLED display products due to their high uniformity. However, the coupling effect of partial capacitance in the pixel driving circuit fabricated using oxide processes can introduce noise during the display process, causing instability in the drive current output by the pixel driving circuit and affecting its reliability.

[0126] Figure 1 This is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure. Figure 1 As shown, the pixel driving circuit provided in this embodiment may include: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a storage sub-circuit.

[0127] like Figure 1 As shown, the driving sub-circuit is electrically connected to the first node N1, the second node N2, and the third node N3, respectively, and is configured to provide driving current to the third node N3 under the control of the signals from the first node N1 and the second node N2; the first control sub-circuit is electrically connected to the first scan signal line G1, the second scan signal line G2, the data signal line Data, the reference signal line REF, and the first node N1, respectively, and is configured to provide the data signal line Data or the reference signal line REF to the first node N1 under the control of the signals from the first scan signal line G1 and the second scan signal line G2; the second control sub-circuit is electrically connected to the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first power supply line VDD, and the second node N3, respectively. Point N2, the third node N3, and the fourth node N4 are electrically connected and configured to provide the first power line VDD signal to the second node N2 and the third node N3 signal to the fourth node N4 under the control of the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2. The third control sub-circuit is electrically connected to the first reset signal line Reset1, the auxiliary signal line VX, and the third node N3, and is configured to control the signal of the third node N3 under the control of the signal of the first reset signal line Reset1 and the drive of the signal of the auxiliary signal line VX. The storage sub-circuit is electrically connected to the first node N1 and the third node N3, and is configured to store the voltage difference between the signals of the first node N1 and the third node N3.

[0128] In an exemplary implementation, such as Figure 1 As shown, the pixel driving circuit is electrically connected to the light-emitting device L through the fourth node N4.

[0129] In an exemplary embodiment, the light-emitting device L may include a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together. Exemplarily, the anode of the light-emitting device L is electrically connected to a fourth node N4, and the cathode of the light-emitting device L is electrically connected to a second power line VSS.

[0130] In an exemplary embodiment, the light-emitting device L may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). The typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0131] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0132] In an exemplary embodiment, the first power line VDD continuously provides a high-level signal, and the signal of the first power line VDD is a DC signal.

[0133] In an exemplary embodiment, the second power line VSS continuously provides a low-level signal, and the signal of the second power line VSS is a DC signal.

[0134] In an exemplary embodiment, the reference signal line REF continuously provides a low-level signal. The signal of the reference signal line REF is a DC signal. For example, the voltage of the signal of the reference signal line REF can be 0V.

[0135] In an exemplary embodiment, the pixel driving circuit is located in the display substrate, and the content displayed by the display substrate includes multiple display frames. In any display frame, the signal of the first scan signal line G1 is a pulse signal, the signal of the second scan signal line G2 is a pulse signal, and the time period during which the second scan signal line G2 is an effective level signal occurs before the time period during which the first scan signal line G1 is an effective level signal.

[0136] This disclosure provides a pixel driving circuit, including: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a storage sub-circuit; the driving sub-circuit is electrically connected to a first node, a second node, and a third node, and is configured to provide a driving current to the third node under the control of signals from the first node and the second node; the first control sub-circuit is electrically connected to a first scan signal line, a second scan signal line, a data signal line, a reference signal line, and a first node, and is configured to provide a signal from the data signal line or the reference signal line to the first node under the control of signals from the first scan signal line and the second scan signal line; the second control sub-circuit... A circuit, electrically connected to a first light-emitting signal line, a second light-emitting signal line, a first power supply line, a second node, a third node, and a fourth node, is configured to provide the first power supply line signal to the second node and the third node signal to the fourth node under the control of the signals from the first and second light-emitting signal lines. A third control sub-circuit, electrically connected to a first reset signal line, an auxiliary signal line, and the third node, is configured to control the signal of the third node under the control of the signal from the first reset signal line and the signal from the auxiliary signal line. A storage sub-circuit, electrically connected to the first and third nodes, is configured to store the voltage difference between the signals from the first and third nodes. This disclosure, by setting the third control sub-circuit to control the signal of the third node through the signals from the first reset signal line and the auxiliary signal line, avoids introducing noise during the display stage, maintains the stability of the drive current output by the pixel driving circuit, and improves the reliability of the pixel driving circuit.

[0137] In an exemplary embodiment, the operation of the pixel driving circuit includes a display phase, which comprises a writing phase and a light-emitting phase. The light-emitting phase occurs after the writing phase, and the signal of the first scan signal line G1 is an active level signal during the writing phase. The signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are both active level signals during the light-emitting phase, and the writing phase occurs during a writing time period.

[0138] Figure 2 Equivalent circuit of the third control sub-circuit Figure 1 .like Figure 2 As shown, in an exemplary embodiment, the third control sub-circuit can also be electrically connected to the third reset signal line Reset3 and the initial signal line INIT, respectively, and is configured to provide the initial signal line signal to the fourth node N4 under the control of the signal of the third reset signal line Reset3. Exemplarily, the third control sub-circuit may include: a sixth transistor T6, an eighth transistor T8, and a second capacitor C2. The control terminal of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, the first terminal of the sixth transistor T6 is electrically connected to the auxiliary signal line VX, and the second terminal of the sixth transistor T6 is electrically connected to the fifth node N5; the first terminal of the second capacitor C2 is electrically connected to the fifth node N5, and the second terminal of the second capacitor C2 is electrically connected to the third node N3; the first terminal of the eighth transistor T8 is electrically connected to the initial signal line INIT, and the second terminal of the eighth transistor T8 is electrically connected to the fourth node N4.

[0139] In an exemplary implementation, such as Figure 2 As shown, the signal of the auxiliary signal line VX is a non-DC signal and is electrically connected to the fourth node N4.

[0140] In an exemplary implementation, such as Figure 2 As shown, this disclosure enables the third node N3 and the fourth node N4 to be reset before the writing period by having the signal of the third reset signal line Reset3 be an effective level signal for a certain period of time, and the signal of the second light-emitting signal line EM2 be an effective level signal. This ensures the uniformity of the pixel driving circuit display. Furthermore, by ensuring that the signals of the first reset signal line Reset1 and the second light-emitting signal line EM2 are effective level signals for at least a certain period of time after the writing period, this disclosure ensures that the voltage values ​​of the signals across the second capacitor C2 are the same during the light-emitting phase. This avoids the influence of the second capacitor C2 on the third node N3 during the light-emitting phase, prevents the introduction of noise into the third node N3, maintains the stability of the driving current output by the pixel driving circuit, and improves the reliability of the pixel driving circuit.

[0141] Figure 3 Equivalent circuit of the third control sub-circuit Figure 2 .like Figure 3As shown, in an exemplary embodiment, the third control sub-circuit can also be electrically connected to the second reset signal line Reset2, and is further configured to provide the signal of the fifth node N5 to the third node N3 under the control of the signal of the second reset signal line Reset2. Exemplarily, the third control sub-circuit may include: a sixth transistor T6, a seventh transistor T7, and a second capacitor C2. The first terminal of the sixth transistor T6 is electrically connected to the auxiliary signal line VX, and the second terminal of the sixth transistor T6 is electrically connected to the fifth node N5; the control terminal of the seventh transistor T7 is electrically connected to the second reset signal line Reset3, the first terminal of the seventh transistor T7 is electrically connected to the fifth node N5, and the second terminal of the seventh transistor T7 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fifth node N5, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0142] In an exemplary implementation, such as Figure 3 As shown, the signal of the auxiliary signal line VX can be a DC signal, and it is the same as the signal of any one of the initial signal line INIT, the reference signal line REF, and the first power supply line VDD.

[0143] In an exemplary implementation, such as Figure 3 As shown, this disclosure allows the second reset signal line Reset2 and the second light emission signal line EM2 to be active during a portion of the time the first reset signal line Reset1 is active, enabling the third node N3 and the fourth node N4 to be reset before the writing time period, thus ensuring the display uniformity of the pixel driving circuit. Furthermore, by ensuring that the second reset signal line Reset2 is active for at least a portion of the time period after the writing time period, this disclosure ensures that the voltage values ​​across the second capacitor C2 are the same during the light emission phase, preventing the second capacitor C2 from affecting the third node N3 during the light emission phase, avoiding the introduction of noise during the display phase, maintaining the stability of the drive current output by the pixel driving circuit, and improving the reliability of the pixel driving circuit.

[0144] Figure 4 Equivalent circuit of the third control sub-circuit Figure 3 , Figure 5 Equivalent circuit of the third control sub-circuit Figure 4 In an exemplary implementation, such as Figure 4 and Figure 5As shown, the third control sub-circuit can also be electrically connected to the third reset signal line Reset3 and the initial signal line INIT, respectively, and is configured to provide the initial signal line signal to the fourth node N4 under the control of the signal from the third reset signal line Reset3. Exemplarily, the third control sub-circuit can also include an eighth transistor T8, the control electrode of which is electrically connected to the third reset signal line Reset3, the first electrode of which is electrically connected to the initial signal line, and the second electrode of which is electrically connected to the fourth node N4.

[0145] In an exemplary embodiment, the signal of the auxiliary signal line VX is a DC signal, and the signal of the auxiliary signal line VX is the same as the signal of any one of the initial signal line, the reference signal line REF, and the first power supply line VDD; or, the signal of the auxiliary signal line VX is a non-DC signal, and the signal of the auxiliary signal line VX is electrically connected to the fourth node N4. Figure 4 This explanation uses the auxiliary signal line VX as an example, where the signal is a DC signal. Figure 5 This explanation is based on the example of the auxiliary signal line VX having a non-DC signal.

[0146] In an exemplary implementation, such as Figure 4 and Figure 5 As shown, when the signal of the first reset signal line Reset1 is at a valid level, the signal of the third reset signal line is at a valid level, and the signal of the second reset signal line is at an invalid level. Conversely, when the signal of the second reset signal line is at a valid level, the signal of the first reset signal line is at an invalid level. This disclosure allows the second light-emitting signal line EM2 to be at a valid level for a portion of the time period after the third reset signal line Reset3 is at a valid level. This enables the third node N3 and the fourth node N4 to be reset before the writing time period, ensuring the display uniformity of the pixel driving circuit. Furthermore, by ensuring that the second reset signal line Reset2 is at a valid level for at least a portion of the time period after the writing time period, this disclosure ensures that the voltage values ​​of the signals across the second capacitor C2 are the same during the light-emitting phase. This avoids the influence of the second capacitor C2 on the third node N3 during the light-emitting phase, prevents the introduction of noise during the display phase, maintains the stability of the driving current output by the pixel driving circuit, and improves the reliability of the pixel driving circuit.

[0147] Figure 6 Equivalent circuit of the third control sub-circuit Figure 5 , Figure 7 Equivalent circuit of the third control sub-circuit Figure 6 In an exemplary implementation, such as Figure 6 and Figure 7As shown, the third control sub-circuit can also be electrically connected to the third reset signal line Reset3 and the initial signal line INIT, respectively, and is configured to provide the initial signal line signal to the fourth node N4 under the control of the signal of the third reset signal line Reset3. Exemplarily, the third control sub-circuit can also include: a sixth transistor T6, an eighth transistor T8, and a second capacitor C2. The control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, the first electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and the second electrode of the sixth transistor T6 is electrically connected to the third node N3; the control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, the first electrode of the eighth transistor T8 is electrically connected to the initial signal line INIT, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the first terminal of the second capacitor C2 is electrically connected to the auxiliary signal line VX, and the second terminal of the second capacitor C2 is electrically connected to the fifth node N5.

[0148] In an exemplary embodiment, the signal of the auxiliary signal line VX is a DC signal, and the signal of the auxiliary signal line VX is the same as the signal of any one of the initial signal line, the reference signal line REF, and the first power supply line VDD; or, the signal of the auxiliary signal line VX is a non-DC signal, and the signal of the auxiliary signal line VX is electrically connected to the fourth node N4. Figure 6 This explanation uses the auxiliary signal line VX as an example, where the signal is a DC signal. Figure 7 This explanation is based on the example of the auxiliary signal line VX having a non-DC signal.

[0149] In an exemplary implementation, such as Figure 6 and Figure 7 As shown, this disclosure allows the second light-emitting signal line EM2 to be active during a certain period of time, when the signal of the third reset signal line Reset3 is active. This enables the third node N3 and the fourth node N4 to be reset before the writing period, ensuring the display uniformity of the pixel driving circuit. Furthermore, by making the first reset signal line Reset1 inactive for a period after the writing period, this disclosure prevents the second capacitor C2 from affecting the third node N3, avoiding noise introduction during the display stage, maintaining the stability of the drive current output by the pixel driving circuit, and improving the reliability of the pixel driving circuit.

[0150] In an exemplary embodiment, the initial signal line INIT continuously provides a low-level signal, and the signal of the initial signal line INIT is a DC signal.

[0151] In an exemplary embodiment, the voltage value of the initial signal line INIT can be less than the voltage value of the second power line VSS, which can prevent the light-emitting device L from emitting light erroneously and improve the reliability of the pixel driving circuit.

[0152] Figures 2 to 7 Only six exemplary structures of the third control sub-circuit are shown in the illustration. It will be readily understood by those skilled in the art that the implementation of the third control sub-circuit is not limited to these.

[0153] Figure 8 This is a partial equivalent circuit diagram of the pixel driving circuit. (Example:) Figure 8 As shown, in an exemplary embodiment, the first control sub-circuit may include: a first transistor T1 and a second transistor T2; the driving sub-circuit may include: a third transistor T3; the second control sub-circuit may include: a fourth transistor T4 and a fifth transistor T5; and the storage sub-circuit may include: a first capacitor C1. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected to the data signal line Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, and the first electrode of the third transistor T3 is electrically connected to the second node N2. The second terminal is electrically connected to the third node N3; the control terminal of the fourth transistor T4 is electrically connected to the first light-emitting signal line EM1, the first terminal of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second terminal of the fourth transistor T4 is electrically connected to the second node N2; the control terminal of the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2, the first terminal of the fifth transistor T5 is electrically connected to the third node N3, and the second terminal of the fifth transistor T5 is electrically connected to the fourth node N4; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3.

[0154] Figure 8 The diagram only shows one exemplary structure of the driver sub-circuit, the first control sub-circuit, the second control sub-circuit, and the storage sub-circuit. It is readily understood by those skilled in the art that the implementation of the driver sub-circuit, the first control sub-circuit, the second control sub-circuit, and the storage sub-circuit is not limited to this.

[0155] In an exemplary embodiment Figure 9 Equivalent circuit of pixel driving circuit Figure 1 , Figure 10 Equivalent circuit of pixel driving circuit Figure 2 , Figure 11 Equivalent circuit of pixel driving circuit Figure 3 , Figure 12 Equivalent circuit of pixel driving circuit Figure 4 .like Figures 9 to 12As shown, in an exemplary embodiment, the pixel driving circuit includes a first control sub-circuit comprising a first transistor T1 and a second transistor T2, a driving sub-circuit comprising a third transistor T3, a second control sub-circuit comprising a fourth transistor T4 and a fifth transistor T5, a storage sub-circuit comprising a first capacitor C1, a third control sub-circuit comprising a second capacitor C2 and a sixth transistor T6, and the third control sub-circuit further comprising at least one of a seventh transistor T7 and an eighth transistor T8. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first terminal of the first transistor T1 is electrically connected to the data signal line Data, and the second terminal of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, the first terminal of the second transistor T2 is electrically connected to the reference signal line REF, and the second terminal of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first light-emitting signal line EM1, the first terminal of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second terminal of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2, and the first terminal of the fifth transistor T5 is electrically connected to the third node N3. Next, the second terminal of the fifth transistor T5 is electrically connected to the fourth node N4; the control terminal of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, the first terminal of the sixth transistor T6 is electrically connected to the auxiliary signal line VX, and the second terminal of the sixth transistor T6 is electrically connected to the fifth node N5; the control terminal of the seventh transistor T7 is electrically connected to the second reset signal line Reset2, the first terminal of the seventh transistor T7 is electrically connected to the fifth node N5, and the second terminal of the seventh transistor T7 is electrically connected to the third node N3; the control terminal of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, the first terminal of the eighth transistor T8 is electrically connected to the initial signal line INIT, and the second terminal of the eighth transistor T8 is electrically connected to the fourth node N4; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fifth node N5, and the second terminal of the second capacitor C2 is electrically connected to the third node N3. Figure 9 and Figure 10 The explanation will be based on the example of the third control sub-circuit also including the seventh transistor T7 and the eighth transistor T8. Figure 11 The explanation will be based on the example of the third control sub-circuit also including the seventh transistor T7. Figure 12 The explanation will be based on the example of the third control sub-circuit, which also includes the eighth transistor T8.

[0156] In an exemplary implementation, such as Figure 9 and Figure 10 As shown, the third control sub-circuit also includes: the auxiliary signal line VX in the pixel driving circuit of the seventh transistor T7 and the eighth transistor T8 can be a DC signal or a non-DC signal. Figure 9 This explanation uses the example of the auxiliary signal line VX in the pixel driving circuit being a DC signal, and being identical to the signal of any one of the initial signal line INIT, the reference signal line REF, and the first power supply line VDD. Figure 10 This explanation is based on the example where the signal of the auxiliary signal line VX in the pixel driving circuit is a non-DC signal and is electrically connected to the fourth node N4.

[0157] In an exemplary implementation, such as Figure 11 As shown, the third control sub-circuit also includes the auxiliary signal line VX in the pixel driving circuit of the seventh transistor T7. The signal is a DC signal and is the same as the signal of any one of the initial signal line, reference signal line, and first power supply line.

[0158] In an exemplary implementation, such as Figure 12 As shown, the third control sub-circuit also includes the auxiliary signal line VX in the pixel driving circuit of the eighth transistor T8. The signal is a non-DC signal and is electrically connected to the fourth node N4.

[0159] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0160] In an exemplary embodiment, any one of the first transistors T1 to the eighth transistor T8 can be an oxide thin-film transistor. The active layer of an oxide thin-film transistor is made of oxide semiconductor. Oxide thin-film transistors have advantages such as low leakage current.

[0161] In an exemplary embodiment, any one of the first transistor T1 to the eighth transistor T8 is an N-type transistor.

[0162] In an exemplary embodiment Figure 13 Equivalent circuit of pixel driving circuit Figure 5 , Figure 14 Equivalent circuit of pixel driving circuit Figure 6 .like Figure 13 and Figure 14 As shown, the first control sub-circuit in the pixel driving circuit may include: a first transistor T1 and a second transistor T2; the driving sub-circuit may include: a third transistor T3; the second control sub-circuit may include: a fourth transistor T4 and a fifth transistor T5; the storage sub-circuit may include: a first capacitor C1; and the third control sub-circuit may include: a second capacitor C2, a sixth transistor T6, and an eighth transistor T8. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first terminal of the first transistor T1 is electrically connected to the data signal line Data, and the second terminal of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, the first terminal of the second transistor T2 is electrically connected to the reference signal line REF, and the second terminal of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first light emission signal line EM1, the first terminal of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second terminal of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the first light emission signal line EM1; the control electrode of the fifth transistor T5 is electrically connected to the first light emission signal line EM1; the first terminal of the fourth transistor T4 is electrically connected to the first power supply line VDD; and the second terminal of the fifth transistor T5 is electrically connected to the first node N2. The first terminal of the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2; the first terminal of the fifth transistor T5 is electrically connected to the third node N3; the second terminal of the fifth transistor T5 is electrically connected to the fourth node N4; the control terminal of the sixth transistor T6 is electrically connected to the first reset signal line Reset1; the first terminal of the sixth transistor T6 is electrically connected to the fifth node N5; the second terminal of the sixth transistor T6 is electrically connected to the third node N3; the control terminal of the eighth transistor T8 is electrically connected to the third reset signal line Reset3; the first terminal of the eighth transistor T8 is electrically connected to the initial signal line INIT; the second terminal of the eighth transistor T8 is electrically connected to the fourth node N4; the first terminal of the first capacitor C1 is electrically connected to the first node N1; the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the auxiliary signal line VX; the second terminal of the second capacitor C2 is electrically connected to the fifth node N5.

[0163] In an exemplary implementation, such as Figure 13 and Figure 14 As shown, the third control sub-circuit includes: the sixth transistor T6, the eighth transistor T8, and the second capacitor C2. The signal of the auxiliary signal line VX in the pixel driving circuit can be a DC signal or a non-DC signal. Figure 13 This explanation uses the example of the auxiliary signal line VX in the pixel driving circuit being a DC signal, and being identical to the signal of any one of the initial signal line INIT, the reference signal line REF, and the first power supply line VDD. Figure 14This explanation is based on the example where the signal of the auxiliary signal line VX in the pixel driving circuit is a non-DC signal and is electrically connected to the fourth node N4.

[0164] In an exemplary embodiment, any one of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 can be an oxide thin-film transistor. The active layer of the oxide thin-film transistor is made of oxide semiconductor. Oxide thin-film transistors have advantages such as low leakage current.

[0165] In an exemplary embodiment, any one of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 is an N-type transistor.

[0166] In an exemplary implementation, such as Figures 9 to 14 In the provided pixel driving circuit, the number of the first transistor T1, the second transistor T2, and the fourth transistor T4 can be at least one.

[0167] In an exemplary embodiment, when the number of first transistors T1 can be at least two, the control electrode of all first transistors is electrically connected to the first scan signal line, the at least two first transistors are connected in series, the first electrode of the first first transistor is electrically connected to the data signal line, and the second electrode of the last first transistor is electrically connected to the first node N1.

[0168] In an exemplary embodiment, when the number of second transistors T2 can be at least two, the control electrode of all second transistors T2 is electrically connected to the second scan signal line, the at least two second transistors are connected in series, the first electrode of the first second transistor is electrically connected to the reference signal line, and the second electrode of the last second transistor is electrically connected to the second node N2.

[0169] Figure 15 for Figure 9 and Figure 10 The provided timing diagram shows the operation of the pixel driving circuit. The following is a demonstration of its operation. Figure 9 and Figure 10 The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. Figure 9 and Figure 10 The pixel driving circuit in the image includes eight transistors (transistor T1 to transistor T8) and two capacitors (capacitor C1 and capacitor C2). All eight transistors are N-type transistors.

[0170] In an exemplary embodiment Figure 9 and Figure 10 The operation of the provided pixel driving circuit may include:

[0171] In the first stage P1, referred to as the first reset stage, the signals of the second scan signal line G2, the second light-emitting signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals, while the signals of the first scan signal line G1, the first light-emitting signal line EM1, and the second reset signal line Reset2 are low-level signals. When the signal of the second scan signal line G2 is high, the second transistor T2 is turned on, and the signal of the reference signal line REF is written to the second node N2, initializing (resetting) the signal of the second node N2 and clearing the original charge in the second node N2. When the signal of the first reset signal line Reset1 is high, the sixth transistor T6 is turned on, and the signal of the auxiliary signal line VX is written to the fifth node N5, initializing (resetting) the signal of the fifth node N5 and clearing the original charge in the fifth node N5. The signals of the second light-emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and the signal of the initial signal line INIT is written to the third node N3 and the fourth node N4 respectively. Since the voltage values ​​of the signals at the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal of the initial signal line INIT is written to the second node N2, initializing (resetting) the signals at the second node N2, the third node N3, and the fourth node N4, clearing the original charge in the second node N2, the third node N3, and the fourth node N4. The signals of the first scan signal line G1, the first light-emitting signal line EM1, and the second reset signal line Reset2 are low-level signals, and the first transistor T1, the fourth transistor T4, and the seventh transistor T7 are turned off. During this stage, the light-emitting device L does not emit light.

[0172] In the second stage, P2, the threshold compensation stage, the signals of the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the first light emission signal line EM1 are high-level signals, while the signals of the second reset signal line Reset2, the first scan signal line G1, and the second light emission signal line EM2 are low-level signals. When the first reset signal line Reset1 is high, the sixth transistor T6 is turned on, and the signal of the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal of the fifth node N5. When the third reset signal line Reset3 is high, the eighth transistor T8 is turned on, and the signal of the initial signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal of the fourth node N4. The second scan signal line G2 is high, the second transistor T2 is turned on, the reference signal line REF is continuously supplied to the second node N2, the first light-emitting signal line EM1 is high, the fourth transistor T4 is turned on, and the signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage of the signal at the third node N3 is V3 = Vref - Vth, where Vref is the initial voltage value of the signal line REF, and Vth is the threshold voltage of the third transistor T3. At this time, the first capacitor C1 stores the voltage difference Vth between the signals at the first node N1 and the third node N3. The second reset signal line Reset2, the first scan signal line G1, and the second light-emitting signal line EM2 are low, and the first transistor T1, the fifth transistor T5, and the seventh transistor are turned off. During this stage, the light-emitting device L does not emit light.

[0173] In the third stage (P3), the data writing stage, the signals of the first reset signal line Reset1, the third reset signal line Reset3, and the first scan signal line G1 are high-level signals, while the signals of the second reset signal line Reset2, the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals. The data signal line Data outputs the data voltage. When the first reset signal line Reset1 is high, the sixth transistor T6 is turned on, and the auxiliary signal line VX continuously writes to the fifth node N5, continuously initializing (resetting) the signal of the fifth node N5. When the third reset signal line Reset3 is high, the eighth transistor T8 is turned on, and the initial signal line INIT continuously writes to the fourth node N4, continuously initializing (resetting) the signal of the fourth node N4. The first scan signal line G1 is high, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value of the first node N1 is V1 = Vdata, where Vdata is the data voltage of the data signal line. The signal of the first node N1 changes from the voltage value of the previous stage to the current stage. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal of the third node N3 also changes. At this time, the voltage value of the third node N3 is V3 = Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance value of the first capacitor and C2 is the capacitance value of the second capacitor. The second reset signal line Reset2, the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are turned off. During this stage, the light-emitting device L does not emit light.

[0174] The fourth stage, P4, is called the second reset stage. The second reset signal line Reset2, the third reset signal line Reset3, and the second light-emitting signal line EM2 are high-level signals, while the first reset signal line Reset1, the first light-emitting signal line EM1, the first scan signal line G1, and the second scan signal line G2 are low-level signals. When the third reset signal line Reset3 is high, the eighth transistor T8 is turned on, and the initial signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signals at the fourth node N4. The signal on the second light-emitting signal line EM2 is high, the fifth transistor T5 is turned on, and the voltage of the signal at the third node N3 is V3 = Vinit, where Vinit is the initial signal line voltage value. At this time, the first node N1 is pulled low by the first capacitor C1, making the voltage of the signal at the first node N1 V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit. The signal on the second reset signal line Reset2 is high, the seventh transistor T7 is turned on, and the voltages of the signals at the third node N3 and the fifth node N5 are consistent. The signals on the first reset signal line Reset1, the first light-emitting signal line EM1, the first scan signal line G1, and the second scan signal line G2 are low, and the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are turned off. During this stage, the light-emitting device L does not emit light.

[0175] In the fifth stage (P5), the light-emitting stage, the signals of the second reset signal line Reset2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, while the signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. When the signals of the first light-emitting signal line EM1 and the second light-emitting signal line Reset2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on. The power supply voltage output from the first power line VDD provides a driving voltage to the first terminal of the light-emitting device L through the turned-on fourth transistor T4, third transistor T3, and fifth transistor T5, driving the light-emitting device L to emit light. When the signal of the second reset signal line Reset2 is high-level, the seventh transistor T7 is turned on, and the voltages of the signals at the third node N3 and the fifth node N5 remain consistent. When the signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals, the first transistor T1, the second transistor T2, the sixth transistor T6, and the eighth transistor T8 are turned off. In this stage, the light-emitting device L emits light.

[0176] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and its second electrode (also the third node N3). Since the voltage value of the signal at the first node is V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 is V3 = Vinit, the driving current of the third transistor T3 is:

[0177] I = K * (Vgs - Vth) 2 =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2 =

[0178] K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0179] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0180] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current. This ensures uniform display brightness of the display product and improves the overall display effect of the display product.

[0181] Figure 16 for Figure 11 The provided timing diagram shows the operation of the pixel driving circuit. The following is a demonstration of its operation. Figure 11 The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. Figure 11 The pixel driving circuit in the image includes seven transistors (transistor T1 to transistor T7) and two capacitors (capacitor C1 and capacitor C2). All seven transistors are N-type transistors.

[0182] In an exemplary embodiment Figure 11 The operation of the provided pixel driving circuit may include:

[0183] In the first stage P1, referred to as the first reset stage, the signals of the second scan signal line G2, the second light-emitting signal line EM2, the first reset signal line Reset1, and the second reset signal line Reset2 are high-level signals, while the signals of the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. When the second scan signal line G2 is high-level, the second transistor T2 is turned on, and the signal of the reference signal line REF is written to the second node N2, initializing (resetting) the signal of the second node N2 and clearing the original charge in the second node N2. When the signals of the first reset signal line Reset1, the second reset signal line Reset2, and the second light-emitting signal line EM2 are high-level, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned on, and the signal of the auxiliary signal line VX is sequentially written to the fifth node N5, the third node N3, and the fourth node N4, initializing (resetting) the signals of the third node N3, the fourth node N4, and the fifth node N5 and clearing the original charge in the third node N3, the fourth node N4, and the fifth node N5. The signals on the first scan signal line G1 and the first light-emitting signal line EM1 are at a low level, and the first transistor T1 and the fourth transistor T4 are disconnected. During this stage, the light-emitting device L does not emit light.

[0184] In the second stage P2, the threshold compensation stage, the signals of the first reset signal line Reset1, the second scan signal line G2, and the first light emission signal line EM1 are high-level signals, while the signals of the second reset signal line Reset2, the first scan signal line G1, and the second light emission signal line EM2 are low-level signals. When the first reset signal line Reset1 is high, the sixth transistor T6 is turned on, and the signal of the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal of the fifth node N5. The second scan signal line G2 is high, the second transistor T2 is turned on, the reference signal line REF is continuously supplied to the second node N2, the first light-emitting signal line EM1 is high, the fourth transistor T4 is turned on, and the signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage of the signal at the third node N3 is V3 = Vref - Vth, where Vref is the initial voltage value of the signal line REF, and Vth is the threshold voltage of the third transistor T3. At this time, the first capacitor C1 stores the voltage difference Vth between the signals at the first node N1 and the third node N3. The second reset signal line Reset2, the first scan signal line G1, and the second light-emitting signal line EM2 are low, and the first transistor T1, the fifth transistor T5, and the seventh transistor are turned off. During this stage, the light-emitting device L does not emit light.

[0185] In the third stage (P3), the data writing stage, the signals of the first reset signal line Reset1 and the first scan signal line G1 are high-level signals, while the signals of the second reset signal line Reset2, the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals. The data signal line Data outputs the data voltage. When the signal of the first reset signal line Reset1 is high, the sixth transistor T6 is turned on, and the signal of the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal of the fifth node N5. The first scan signal line G1 is high, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value of the first node N1 is V1 = Vdata, where Vdata is the data voltage of the data signal line. The signal of the first node N1 changes from the voltage value of the previous stage to the current stage. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal of the third node N3 also changes. At this time, the voltage value of the third node N3 is V3 = Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance value of the first capacitor and C2 is the capacitance value of the second capacitor. The second reset signal line Reset2, the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are turned off. During this stage, the light-emitting device L does not emit light.

[0186] In the fourth stage, P4, also known as the second reset stage, the second reset signal line Reset2 and the second light-emitting signal line EM2 are high-level signals, while the first reset signal line Reset1, the first light-emitting signal line EM1, the first scan signal line G1, and the second scan signal line G2 are low-level signals. When the second light-emitting signal line EM2 is high, the fifth transistor T5 is turned on, and the voltage of the signal at the third node N3 is V3 = Vinit, where Vinit is the initial signal line voltage value. At this time, the first node N1 is pulled low by the first capacitor C1, making the voltage of the signal at the first node N1 V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit. The second reset signal line Reset2 is high, the seventh transistor T7 is turned on, and the voltages of the signals at the third node N3 and the fifth node N5 remain consistent. The signals of the first reset signal line Reset1, the first light emission signal line EM1, the first scan signal line G1, and the second scan signal line G2 are all at low level, and the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are disconnected. During this stage, the light-emitting device L does not emit light.

[0187] In the fifth stage (P5), the light-emitting stage, the signals of the second reset signal line Reset2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, while the signals of the first reset signal line Reset1, the first scan signal line G1, and the second scan signal line G2 are low-level signals. When the signals of the first light-emitting signal line EM1 and the second light-emitting signal line Reset2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on. The power supply voltage output from the first power line VDD provides a driving voltage to the first terminal of the light-emitting device L through the turned-on fourth transistor T4, third transistor T3, and fifth transistor T5, driving the light-emitting device L to emit light. When the signal of the second reset signal line Reset2 is high-level, the seventh transistor T7 is turned on, and the voltages of the signals at the third node N3 and the fifth node N5 remain consistent. When the signals of the first reset signal line Reset1, the first scan signal line G1, and the second scan signal line G2 are low-level signals, the first transistor T1, the second transistor T2, and the sixth transistor T6 are turned off. In this stage, the light-emitting device L emits light.

[0188] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and its second electrode (also the third node N3). Since the voltage value of the signal at the first node is V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 is V3 = Vinit, the driving current of the third transistor T3 is:

[0189] I = K * (Vgs - Vth) 2 =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2 =

[0190] K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0191] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0192] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current. This ensures uniform display brightness of the display product and improves the overall display effect of the display product.

[0193] Figure 17 for Figure 12 The provided timing diagram shows the operation of the pixel driving circuit. The following is a demonstration of its operation. Figure 12 The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. Figure 12 The pixel driving circuit in the image includes seven transistors (transistor T1 to transistor T6 and transistor T8) and two capacitors (capacitor C1 and capacitor C2). All seven transistors are N-type transistors.

[0194] In an exemplary embodiment Figure 12 The operation of the provided pixel driving circuit may include:

[0195] In the first stage P1, also known as the first reset stage, the signals of the second scan signal line G2, the second light emission signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are all high-level signals, while the signals of the first scan signal line G1 and the first light emission signal line EM1 are low-level signals. When the second scan signal line G2 is high, the second transistor T2 is turned on, and the signal of the reference signal line REF is written to the second node N2, initializing (resetting) the signal of the second node N2 and clearing the original charge in the second node N2. When the first reset signal line Reset1 is high, the sixth transistor T6 is turned on, and the signal of the auxiliary signal line VX is written to the fifth node N5, initializing (resetting) the signal of the fifth node N5 and clearing the original charge in the fifth node N5. The signals of the second light-emitting signal line EM2 and the third reset signal line Reset3 are at a high level. The fifth transistor T5 and the eighth transistor T8 are turned on. The signal of the initial signal line INIT is written to the third node N3 and the fourth node N4, respectively. Since the voltage values ​​of the signals at the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on. The signal of the initial signal line INIT is written to the second node N2, initializing (resetting) the signals at the second node N2, the third node N3, and the fourth node N4, clearing the original charges in these nodes. The signals of the first scan signal line G1 and the first light-emitting signal line EM1 are at a low level. The first transistor T1 and the fourth transistor T4 are turned off. During this stage, the light-emitting device L does not emit light.

[0196] In the second stage, P2, the threshold compensation stage, the signals of the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the first light emission signal line EM1 are high-level signals, while the signals of the first scan signal line G1 and the second light emission signal line EM2 are low-level signals. When the first reset signal line Reset1 is high, the sixth transistor T6 is turned on, and the signal of the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal of the fifth node N5. When the third reset signal line Reset3 is high, the eighth transistor T8 is turned on, and the signal of the initial signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal of the fourth node N4. The second scan signal line G2 is high, the second transistor T2 is turned on, the reference signal line REF is continuously supplied to the second node N2, the first light-emitting signal line EM1 is high, the fourth transistor T4 is turned on, and the signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage of the signal at the third node N3 is V3 = Vref - Vth, where Vref is the initial voltage value of the signal line REF, and Vth is the threshold voltage of the third transistor T3. At this time, the first capacitor C1 stores the voltage difference Vth between the signals at the first node N1 and the third node N3. The signals of the first scan signal line G1 and the second light-emitting signal line EM2 are low, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0197] In the third stage (P3), the data writing stage, the signals of the first reset signal line Reset1, the third reset signal line Reset3, and the first scan signal line G1 are high-level signals, while the signals of the second scan signal line G2, the first light emission signal line EM1, and the second light emission signal line EM2 are low-level signals. The data signal line Data outputs the data voltage. When the first reset signal line Reset1 is high, the sixth transistor T6 is turned on, and the auxiliary signal line VX continuously writes to the fifth node N5, continuously initializing (resetting) the signal of the fifth node N5. When the third reset signal line Reset3 is high, the eighth transistor T8 is turned on, and the initial signal line INIT continuously writes to the fourth node N4, continuously initializing (resetting) the signal of the fourth node N4. The first scan signal line G1 is high, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value of the first node N1 is V1 = Vdata, where Vdata is the data voltage of the data signal line. The signal of the first node N1 changes from the voltage value of the previous stage to the current stage. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal of the third node N3 also changes. At this time, the voltage value of the third node N3 is V3 = Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance value of the first capacitor and C2 is the capacitance value of the second capacitor. The signals of the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0198] In the fourth stage, P4, also known as the second reset stage, the first reset signal line Reset1, the third reset signal line Reset3, and the second light-emitting signal line EM2 are high-level signals, while the first light-emitting signal line EM1, the first scan signal line G1, and the second scan signal line G2 are low-level signals. When the third reset signal line Reset3 is high, the eighth transistor T8 is turned on, and the initial signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal of the fourth node N4. When the second light-emitting signal line EM2 is high, the fifth transistor T5 is turned on, and the voltage V3 of the signal at the third node N3 is Vinit, where Vinit is the voltage value of the initial signal line. At this time, the first node N1 is pulled low by the first capacitor C1, making the voltage V1 of the signal at the first node N1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit. The first reset signal line Reset1 is high, the sixth transistor T6 is turned on, and the voltages of the signals at the third node N3 and the fifth node N5 remain consistent. The signals of the first reset signal line Reset1, the first light emission signal line EM1, the first scan signal line G1, and the second scan signal line G2 are all at low level, and the first transistor T1, the second transistor T2, and the fourth transistor T4 are disconnected. During this stage, the light-emitting device L does not emit light.

[0199] In the fifth stage (P5), the light-emitting stage, the signals of the first reset signal line Reset1, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, while the signals of the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. When the signals of the first light-emitting signal line EM1 and the second light-emitting signal line Reset2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on. The power supply voltage output from the first power line VDD provides a driving voltage to the first terminal of the light-emitting device L through the turned-on fourth transistor T4, third transistor T3, and fifth transistor T5, driving the light-emitting device L to emit light. When the signal of the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the voltages of the signals at the third node N3 and the fifth node N5 remain consistent. When the signals of the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals, the first transistor T1, the second transistor T2, and the eighth transistor T8 are turned off. In this stage, the light-emitting device L emits light.

[0200] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and its second electrode (also the third node N3). Since the voltage value of the signal at the first node is V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 is V3 = Vinit, the driving current of the third transistor T3 is:

[0201] I = K * (Vgs - Vth) 2 =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2 =

[0202] K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0203] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0204] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current. This ensures uniform display brightness of the display product and improves the overall display effect of the display product.

[0205] for Figures 9 to 12 In the fourth and fifth stages of the provided pixel driving circuit, the signals at the third node N3 and the fifth node N5 of the second capacitor C2 remain consistent, so that the third node of the pixel driving circuit will not be affected by the coupling effect of the second capacitor C2 in the fifth stage. This can improve the stability of the driving current of the pixel driving circuit and enhance its reliability.

[0206] Figure 18 for Figure 13 and Figure 14 The provided timing diagram shows the operation of the pixel driving circuit. The following is a demonstration of its operation. Figure 13 and Figure 14 The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. Figure 13 and Figure 14 The pixel driving circuit in the image includes seven transistors (transistor T1 to transistor T6 and transistor T8) and two capacitors (capacitor C1 and capacitor C2). All seven transistors are N-type transistors.

[0207] In an exemplary embodiment Figure 13 and Figure 14 The operation of the provided pixel driving circuit may include:

[0208] In the first stage P1, also known as the first reset stage, the signals of the second scan signal line G2, the second light emission signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are all high-level signals, while the signals of the first scan signal line G1 and the first light emission signal line EM1 are low-level signals. When the second scan signal line G2 is high, the second transistor T2 is turned on, and the signal of the reference signal line REF is written to the second node N2, initializing (resetting) the signal of the second node N2 and clearing the original charge in the second node N2. When the first reset signal line Reset1 is high, the sixth transistor T6 is turned on, and the signal of the auxiliary signal line VX is written to the fifth node N5, initializing (resetting) the signal of the fifth node N5 and clearing the original charge in the fifth node N5. The signals of the second light-emitting signal line EM2 and the third reset signal line Reset3 are at a high level. The fifth transistor T5 and the eighth transistor T8 are turned on. The signal of the initial signal line INIT is written to the third node N3 and the fourth node N4, respectively. Since the voltage values ​​of the signals at the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on. The signal of the initial signal line INIT is written to the second node N2, initializing (resetting) the signals at the second node N2, the third node N3, and the fourth node N4, clearing the original charges in these nodes. The signals of the first scan signal line G1 and the first light-emitting signal line EM1 are at a low level. The first transistor T1 and the fourth transistor T4 are turned off. During this stage, the light-emitting device L does not emit light.

[0209] In the second stage, P2, the threshold compensation stage, the signals of the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the first light emission signal line EM1 are high-level signals, while the signals of the first scan signal line G1 and the second light emission signal line EM2 are low-level signals. When the first reset signal line Reset1 is high, the sixth transistor T6 is turned on, and the signal of the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal of the fifth node N5. When the third reset signal line Reset3 is high, the eighth transistor T8 is turned on, and the signal of the initial signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal of the fourth node N4. The second scan signal line G2 is high, the second transistor T2 is turned on, the reference signal line REF is continuously supplied to the second node N2, the first light-emitting signal line EM1 is high, the fourth transistor T4 is turned on, and the signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage of the signal at the third node N3 is V3 = Vref - Vth, where Vref is the initial voltage value of the signal line REF, and Vth is the threshold voltage of the third transistor T3. At this time, the first capacitor C1 stores the voltage difference Vth between the signals at the first node N1 and the third node N3. The signals of the first scan signal line G1 and the second light-emitting signal line EM2 are low, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0210] In the third stage (P3), the data writing stage, the signals of the first reset signal line Reset1, the third reset signal line Reset3, and the first scan signal line G1 are high-level signals, while the signals of the second scan signal line G2, the first light emission signal line EM1, and the second light emission signal line EM2 are low-level signals. The data signal line Data outputs the data voltage. When the first reset signal line Reset1 is high, the sixth transistor T6 is turned on, and the auxiliary signal line VX continuously writes to the fifth node N5, continuously initializing (resetting) the signal of the fifth node N5. When the third reset signal line Reset3 is high, the eighth transistor T8 is turned on, and the initial signal line INIT continuously writes to the fourth node N4, continuously initializing (resetting) the signal of the fourth node N4. The first scan signal line G1 is high, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value of the first node N1 is V1 = Vdata, where Vdata is the data voltage of the data signal line. The signal of the first node N1 changes from the voltage value of the previous stage to the current stage. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal of the third node N3 also changes. At this time, the voltage value of the third node N3 is V3 = Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance value of the first capacitor and C2 is the capacitance value of the second capacitor. The signals of the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0211] In the fourth stage, P4, also known as the second reset stage, the third reset signal line Reset3 and the second light-emitting signal line EM2 are high-level signals, while the first reset signal line Reset1, the first light-emitting signal line EM1, the first scan signal line G1, and the second scan signal line G2 are low-level signals. When the third reset signal line Reset3 is high, the eighth transistor T8 is turned on, and the initial signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal of the fourth node N4. When the second light-emitting signal line EM2 is high, the fifth transistor T5 is turned on, and the voltage V3 of the signal at the third node N3 is Vinit, where Vinit is the voltage value of the initial signal line. At this time, the first node N1 is pulled low by the first capacitor C1, making the voltage V1 of the signal at the first node N1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit. The signals of the first reset signal line Reset1, the first light emission signal line EM1, the first scan signal line G1, and the second scan signal line G2 are all at low level, and the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are disconnected. During this stage, the light-emitting device L does not emit light.

[0212] In the fifth stage (P5), the light-emitting stage, the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, while the signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. When the signals of the first light-emitting signal line EM1 and the second light-emitting signal line Reset2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on. The power supply voltage output from the first power line VDD provides a driving voltage to the first terminal of the light-emitting device L through the turned-on fourth transistor T4, third transistor T3, and fifth transistor T5, driving the light-emitting device L to emit light. When the signal of the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the voltages of the signals at the third node N3 and the fifth node N5 remain consistent. When the signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals, the first transistor T1, the second transistor T2, the sixth transistor T6, and the eighth transistor T8 are turned off. In this stage, the light-emitting device L emits light.

[0213] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and its second electrode (also the third node N3). Since the voltage value of the signal at the first node is V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 is V3 = Vinit, the driving current of the third transistor T3 is:

[0214] I = K * (Vgs - Vth) 2 =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2 =

[0215] K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0216] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0217] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current. This ensures uniform display brightness of the display product and improves the overall display effect of the display product.

[0218] for Figure 13 and Figure 14 In the fourth and fifth stages of the provided pixel driving circuit, the second capacitor C2 is disconnected from the sixth transistor T6, which is disconnected from the third node N3. This ensures that the third node of the pixel driving circuit is not affected by the coupling effect of the second capacitor C2 in the fifth stage, thereby improving the stability of the driving current of the pixel driving circuit and enhancing its reliability.

[0219] This disclosure also provides a method for driving a pixel driving circuit, configured to drive the pixel driving circuit. The method for driving the pixel driving circuit may include:

[0220] Step 100: The driving sub-circuit provides driving current to the third node under the control of the signals from the first and second nodes.

[0221] Step 200: Under the control of the signals from the first scan signal line and the second scan signal line, the first control sub-circuit provides the data signal line or reference signal line to the first node N1.

[0222] Step 300: Under the control of the signals from the first and second light-emitting signal lines, the second control sub-circuit provides the signal from the first power line to the second node and the signal from the third node to the fourth node.

[0223] Step 400: The third control sub-circuit controls the signal of the third node under the control of the signal of the first reset signal line and the signal of the auxiliary signal line.

[0224] Step 500: The storage sub-circuit stores the voltage difference between the signals of the first node and the third node.

[0225] This disclosure also provides a method for driving a pixel driving circuit, configured to drive... Figure 11 The provided pixel driving circuit, the operation of the pixel driving circuit includes: the first stage to the fifth stage, for Figure 11 The driving method of the provided pixel driving circuit may include:

[0226] Step 110: In the first stage, valid level signals are provided to the signals of the second scan signal line, the second light emission signal line, the first reset signal line, and the second reset signal line. The first control sub-circuit provides the reference signal line signal to the first node. The third control sub-circuit provides the auxiliary signal line signal to the fifth node and provides the signal of the fifth node to the third node. The second control sub-circuit provides the signal of the fourth node to the third node.

[0227] Step 120: In the second stage, valid level signals are provided to the first reset signal line, the second scan signal line, and the first light emission signal line. The first control sub-circuit provides a reference signal line signal to the first node. The third control sub-circuit provides an auxiliary signal line signal to the fifth node. The second control sub-circuit provides a first power line signal to the second node to charge the first node. The storage sub-circuit stores the voltage difference between the signals of the first node and the third node.

[0228] Step 130: In the third stage, the signals to the first reset signal line and the first scan signal line are high-level signals, the first control sub-circuit provides the data signal line signal to the first node, and the third control sub-circuit provides the auxiliary signal line signal to the fifth node.

[0229] Step 140: In the fourth stage, provide an effective level signal to the second reset signal line and the second light emission signal line, the third control sub-circuit provides the signal of the third node to the fifth node, and the second control sub-circuit provides the signal of the fourth node to the third node.

[0230] Step 150: In the fifth stage, a valid level signal is provided to the second reset signal line, the first light-emitting signal line, and the second light-emitting signal line. The second control sub-circuit provides the first power line signal to the second node and the third node signal to the fourth node. Under the control of the signals from the first node and the second node, the drive sub-circuit provides the drive current to the third node. The third control sub-circuit provides the third node signal to the fifth node.

[0231] This disclosure also provides a method for driving a pixel driving circuit, configured to drive... Figure 12 The provided pixel driving circuit, the operation of the pixel driving circuit includes: the first stage to the fifth stage, for Figure 12 The driving method of the provided pixel driving circuit may include:

[0232] Step 210: In the first stage, valid level signals are provided to the signals of the second scan signal line, the second light emission signal line, the first reset signal line and the third reset signal line. The first control sub-circuit provides the reference signal line signal to the first node. The third control sub-circuit provides the auxiliary signal line signal to the fifth node and the initial signal line signal to the fourth node. The second control sub-circuit provides the signal of the fourth node to the third node.

[0233] Step 220: In the second stage, valid level signals are provided to the first reset signal line, the third reset signal line, the second scan signal line, and the first light emission signal line. The first control sub-circuit provides a reference signal line signal to the first node. The third control sub-circuit provides an auxiliary signal line signal to the fifth node and an initial signal line signal to the fourth node. The second control sub-circuit provides a first power line signal to the second node to charge the first node. The storage sub-circuit stores the voltage difference between the signals of the first node and the third node.

[0234] Step 230: In the third stage, the signals to the first reset signal line, the third reset signal line, and the first scan signal line are high-level signals. The first control sub-circuit provides the data signal line signal to the first node, the third control sub-circuit provides the auxiliary signal line signal to the fifth node, and provides the initial signal line signal to the fourth node.

[0235] Step 240: In the fourth stage, provide valid level signals to the first reset signal line, the third reset signal line, and the second light emission signal line; the third control sub-circuit provides the initial signal line signal to the fourth node and the auxiliary signal line signal to the fifth node; and the second control sub-circuit provides the fourth node signal to the third node.

[0236] Step 250: In the fifth stage, effective level signals are provided to the first reset signal line, the first light-emitting signal line, and the second light-emitting signal line. The second control sub-circuit provides the first power line signal to the second node and the third node signal to the fourth node. Under the control of the signals from the first and second nodes, the drive sub-circuit provides drive current to the third node. The third control sub-circuit provides the auxiliary signal line signal to the fifth node.

[0237] This disclosure also provides a method for driving a pixel driving circuit, configured to drive... Figure 9 and Figure 10 The provided pixel driving circuit, the operation of the pixel driving circuit includes: the first stage to the fifth stage, for Figure 9 and Figure 10 The driving method of the provided pixel driving circuit may include:

[0238] Step 310: In the first stage, valid level signals are provided to the signals of the second scan signal line, the second light emission signal line, the first reset signal line, and the third reset signal line. The first control sub-circuit provides the reference signal line signal to the first node. The third control sub-circuit provides the auxiliary signal line signal to the fifth node and the initial signal line signal to the fourth node. The second control sub-circuit provides the signal of the fourth node to the third node.

[0239] Step 320: In the second stage, valid level signals are provided to the first reset signal line, the third reset signal line, the second scan signal line, and the first light emission signal line. The first control sub-circuit provides a reference signal line signal to the first node. The third control sub-circuit provides an auxiliary signal line signal to the fifth node and an initial signal line signal to the fourth node. The second control sub-circuit provides a first power line signal to the second node to charge the first node. The storage sub-circuit stores the voltage difference between the signals of the first node and the third node.

[0240] Step 330: In the third stage, the signals to the first reset signal line, the third reset signal line, and the first scan signal line are high-level signals. The first control sub-circuit provides the data signal line signal to the first node, the third control sub-circuit provides the auxiliary signal line signal to the fifth node, and provides the initial signal line signal to the fourth node.

[0241] Step 340: In the fourth stage, provide valid level signals to the second reset signal line, the third reset signal line, and the second light emission signal line. The third control sub-circuit provides the initial signal line signal to the fourth node, provides the third node signal to the fifth node, and the second control sub-circuit provides the fourth node signal to the third node.

[0242] Step 350: In the fifth stage, valid level signals are provided to the second reset signal line, the first light-emitting signal line, and the second light-emitting signal line. The second control sub-circuit provides the first power line signal to the second node and the third node signal to the fourth node. Under the control of the signals from the first node and the second node, the drive sub-circuit provides drive current to the third node. The third control sub-circuit provides the third node signal to the fifth node.

[0243] This disclosure also provides a method for driving a pixel driving circuit, configured to drive... Figure 13 and Figure 14 The provided pixel driving circuit, the operation of the pixel driving circuit includes: the first stage to the fifth stage, for Figure 13 and Figure 14 The driving method of the provided pixel driving circuit may include:

[0244] Step 410: In the first stage, valid level signals are provided to the signals of the second scan signal line, the second light emission signal line, the first reset signal line, and the third reset signal line. The first control sub-circuit provides the reference signal line signal to the first node. The third control sub-circuit provides the signal of the third node to the fifth node and provides the signal of the initial signal line to the fourth node. The second control sub-circuit provides the signal of the fourth node to the third node.

[0245] Step 420: In the second stage, valid level signals are provided to the first reset signal line, the third reset signal line, the second scan signal line, and the first light emission signal line. The first control sub-circuit provides the reference signal line signal to the first node. The third control sub-circuit provides the signal of the third node to the fifth node and the signal of the initial signal line to the fourth node. The second control sub-circuit provides the signal of the first power line to the second node to charge the first node. The storage sub-circuit stores the voltage difference between the signals of the first node and the third node.

[0246] Step 430: In the third stage, the signals to the first reset signal line, the third reset signal line, and the first scan signal line are high-level signals. The first control sub-circuit provides the data signal line signal to the first node, the third control sub-circuit provides the initial signal line signal to the fourth node, and provides the third node signal to the fifth node.

[0247] Step 440: In the fourth stage, provide an effective level signal to the third reset signal line and the second light emission signal line, the third control sub-circuit provides the initial signal line signal to the fourth node, and the second control sub-circuit provides the fourth node signal to the third node.

[0248] Step 450: In the fifth stage, effective level signals are provided to the first and second light-emitting signal lines. The second control sub-circuit provides the first power line signal to the second node and the third node signal to the fourth node. Under the control of the signals from the first and second nodes, the drive sub-circuit provides drive current to the third node.

[0249] This disclosure also provides a display device having a display area, wherein the display area is provided with a plurality of pixel driving circuits.

[0250] The pixel driving circuit is the same as the pixel driving circuit provided in any of the foregoing embodiments, and the implementation method and effect are similar, so it will not be described again here.

[0251] In an exemplary embodiment, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to a plurality of data signal lines, the scan driver is connected to a plurality of scan signal lines, and the light-emitting driver is connected to a plurality of light-emitting signal lines. The pixel array may include a plurality of sub-pixels. At least one sub-pixel may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light-emitting signal lines, and the data signal lines, respectively.

[0252] The scan signal lines include: a first scan signal line, a second scan signal line, a first reset signal line, a second reset signal line, and a third reset signal line. The light emission signal lines include: a first light emission signal line and a second light emission signal line.

[0253] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver.

[0254] In an exemplary embodiment, the data driver may use grayscale values ​​and control signals received from a timing controller to generate a data voltage to be provided to the data signal line. For example, the data driver may use a clock signal to sample the grayscale values ​​and apply the data voltage corresponding to the grayscale values ​​to the data signal line on a pixel-by-pixel basis.

[0255] In an exemplary embodiment, the scan driver can generate scan signals to be provided to the scan signal lines by receiving clock signals, scan start signals, etc., from a timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to the scan signal lines. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal.

[0256] In an exemplary embodiment, the LED driver can generate a transmit signal to be provided to the LED signal line by receiving a clock signal, a transmit stop signal, etc., from a timing controller. For example, the LED driver can sequentially provide transmit signals with cutoff level pulses to the LED signal line. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal.

[0257] In an exemplary embodiment, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light. Each of the first, second, and third sub-pixels includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first, second, and third sub-pixels are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting devices in the first, second, and third sub-pixels are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0258] In an exemplary embodiment, the first sub-pixel may be a red sub-pixel (R) that emits red light, the second sub-pixel may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel may be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixel may be rectangular, rhomboid, pentagonal, or hexagonal.

[0259] In an exemplary embodiment, a pixel unit may include three sub-pixels, which may be arranged in a horizontal, vertical, or triangular manner, etc., and this disclosure does not limit the arrangement.

[0260] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0261] On a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on the substrate, a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate, and an encapsulation structure layer disposed on the side of the light-emitting structure layer away from the substrate. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0262] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate. The rigid substrate may be, but is not limited to, one or more of glass and conductive foil. The flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0263] In an exemplary embodiment, the driving structure layer may include a plurality of transistors and a storage capacitor constituting a pixel driving circuit, and the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode. The anode is connected to the drain electrode of the transistor therein through a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of the corresponding color under the driving of the anode and the cathode.

[0264] In an exemplary embodiment, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0265] In an exemplary embodiment, the touch structure layer may include a first touch insulating layer disposed on the encapsulation structure layer, a first touch metal layer disposed on the first touch insulating layer, a second touch insulating layer covering the first touch metal layer, a second touch metal layer disposed on the second touch insulating layer, and a touch protective layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridging electrodes, and the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes. The first touch electrodes or the second touch electrodes may be connected to the bridging electrodes through vias.

[0266] In an exemplary embodiment, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. This embodiment of the invention is not limited thereto.

[0267] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0268] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0269] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A pixel driving circuit, comprising: The circuit includes a driver sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a storage sub-circuit. The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide driving current to the third node under the control of the signals of the first node and the second node; The first control sub-circuit is electrically connected to the first scan signal line, the second scan signal line, the data signal line, the reference signal line, and the first node, respectively, and is configured to provide the data signal line or the reference signal line to the first node under the control of the signals of the first scan signal line and the second scan signal line; The second control sub-circuit is electrically connected to the first light-emitting signal line, the second light-emitting signal line, the first power supply line, the second node, the third node, and the fourth node, respectively. It is configured to provide the first power supply line signal to the second node and the third node signal to the fourth node under the control of the signals of the first light-emitting signal line and the second light-emitting signal line. The third control sub-circuit is electrically connected to the first reset signal line, the auxiliary signal line and the third node respectively, and is configured to control the signal of the third node under the control of the signal of the first reset signal line and the drive of the signal of the auxiliary signal line. The storage sub-circuit, which is electrically connected to the first node and the third node respectively, is configured to store the voltage difference of the signal between the first node and the third node; The third control sub-circuit includes: a sixth transistor and a second capacitor, wherein the sixth transistor and the second capacitor are connected through a fifth node; The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the auxiliary signal line, and the second electrode of the sixth transistor is electrically connected to the fifth node; the first terminal of the second capacitor is electrically connected to the fifth node, and the second terminal of the second capacitor is electrically connected to the third node. Alternatively, the control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the fifth node, and the second electrode of the sixth transistor is electrically connected to the third node; the first terminal of the second capacitor is electrically connected to the auxiliary signal line, and the second terminal of the second capacitor is electrically connected to the fifth node.

2. The pixel driving circuit according to claim 1, wherein, The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the auxiliary signal line, and the second electrode of the sixth transistor is electrically connected to the fifth node. When the first terminal of the second capacitor is electrically connected to the fifth node and the second terminal of the second capacitor is electrically connected to the third node, the third control sub-circuit is also electrically connected to the third reset signal line and the initial signal line respectively, and is configured to provide the signal of the initial signal line to the fourth node under the control of the signal of the third reset signal line.

3. The pixel driving circuit according to claim 2, wherein, The third control sub-circuit further includes: an eighth transistor, the control electrode of the eighth transistor being electrically connected to the third reset signal line, the first electrode of the eighth transistor being electrically connected to the initial signal line, and the second electrode of the eighth transistor being electrically connected to the fourth node. The signal on the auxiliary signal line is a non-DC signal and is electrically connected to the fourth node.

4. The pixel driving circuit according to claim 1, wherein, When the control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the auxiliary signal line, the second electrode of the sixth transistor is electrically connected to the fifth node, the first terminal of the second capacitor is electrically connected to the fifth node, and the second terminal of the second capacitor is electrically connected to the third node, the third control sub-circuit is also electrically connected to the second reset signal line and is configured to provide the signal of the fifth node to the third node under the control of the signal of the second reset signal line.

5. The pixel driving circuit according to claim 4, wherein, The third control sub-circuit also includes: a seventh transistor; The control electrode of the seventh transistor is electrically connected to the second reset signal line, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the third node.

6. The pixel driving circuit according to claim 5, wherein, The signal of the auxiliary signal line is a DC signal and is the same as the signal of any one of the initial signal line, reference signal line, and first power supply line.

7. The pixel driving circuit according to claim 1, wherein, The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the fifth node, and the second electrode of the sixth transistor is electrically connected to the third node. When the first terminal of the second capacitor is electrically connected to the auxiliary signal line and the second terminal of the second capacitor is electrically connected to the fifth node, the third control sub-circuit is also electrically connected to the third reset signal line and the initial signal line respectively, and is configured to provide the initial signal line signal to the fourth node under the control of the signal of the third reset signal line.

8. The pixel driving circuit according to claim 7, wherein, The third control sub-circuit further includes: an eighth transistor, the control electrode of the eighth transistor being electrically connected to the third reset signal line, the first electrode of the eighth transistor being electrically connected to the initial signal line, and the second electrode of the eighth transistor being electrically connected to the fourth node. The signal of the auxiliary signal line is a DC signal, and the signal of the auxiliary signal line is the same as the signal of any one of the initial signal line, the reference signal line, and the first power supply line. Alternatively, the signal of the auxiliary signal line is a non-DC signal, and the signal of the auxiliary signal line is electrically connected to the fourth node.

9. The pixel driving circuit according to claim 1, wherein, The first control sub-circuit includes: a first transistor and a second transistor; the driving sub-circuit includes: a third transistor; the second control sub-circuit includes: a fourth transistor and a fifth transistor; and the storage sub-circuit includes: a first capacitor. The control electrode of the first transistor is electrically connected to the first scan signal line, the first electrode of the first transistor is electrically connected to the data signal line, and the second electrode of the first transistor is electrically connected to the first node. The control electrode of the second transistor is electrically connected to the second scan signal line, the first electrode of the second transistor is electrically connected to the reference signal line, and the second electrode of the second transistor is electrically connected to the first node. The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fourth transistor is electrically connected to the first power supply line, and the second electrode of the fourth transistor is electrically connected to the second node. The control electrode of the fifth transistor is electrically connected to the second light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the fourth node. The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node.

10. The pixel driving circuit according to claim 1, wherein, The first control sub-circuit includes: a first transistor and a second transistor; the driving sub-circuit includes: a third transistor; the second control sub-circuit includes: a fourth transistor and a fifth transistor; the storage sub-circuit includes: a first capacitor; and the third control sub-circuit further includes: at least one of a seventh transistor and an eighth transistor. The control electrode of the first transistor is electrically connected to the first scan signal line, the first electrode of the first transistor is electrically connected to the data signal line, and the second electrode of the first transistor is electrically connected to the first node. The control electrode of the second transistor is electrically connected to the second scan signal line, the first electrode of the second transistor is electrically connected to the reference signal line, and the second electrode of the second transistor is electrically connected to the first node. The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fourth transistor is electrically connected to the first power supply line, and the second electrode of the fourth transistor is electrically connected to the second node. The control electrode of the fifth transistor is electrically connected to the second light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the fourth node. The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the auxiliary signal line, and the second electrode of the sixth transistor is electrically connected to the fifth node. The control electrode of the seventh transistor is electrically connected to the second reset signal line, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the third node. The control electrode of the eighth transistor is electrically connected to the third reset signal line, the first electrode of the eighth transistor is electrically connected to the initial signal line, and the second electrode of the eighth transistor is electrically connected to the fourth node. The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node. The first terminal of the second capacitor is electrically connected to the fifth node, and the second terminal of the second capacitor is electrically connected to the third node. Any one of the first to the eighth transistors is an N-type transistor.

11. The pixel driving circuit according to claim 10, wherein, The third control sub-circuit includes: a sixth transistor, a seventh transistor, and a second capacitor. During a portion of the time period when the signal of the first reset signal line is an effective level signal, the signals of the second reset signal line and the second light emission signal line are effective level signals. The signal of the second reset signal line is an effective level signal for at least a portion of the time period after the writing time period, wherein the writing time period is the time period during which the first scan signal line is an effective level signal.

12. The pixel driving circuit according to claim 10, wherein, The third control sub-circuit includes: a sixth transistor, an eighth transistor, and a second capacitor. During a portion of the time period when the signal of the third reset signal line is at an effective level, the signal of the second light emission signal line is at an effective level. The signals of the first reset signal line and the second light emission signal line are at least at an effective level for a portion of the time period after the writing time period, wherein the writing time period is the time period during which the first scan signal line is at an effective level.

13. The pixel driving circuit according to claim 10, wherein, The third control sub-circuit includes: a sixth transistor, a seventh transistor, an eighth transistor, and a second capacitor. When the signal of the first reset signal line is a valid level signal, the signal of the third reset signal line is a valid level signal, and the signal of the second reset signal line is an invalid level signal. When the signal of the second reset signal line is a valid level signal, the signal of the first reset signal line is an invalid level signal. During a certain period of time when the signal of the third reset signal line is a valid level signal, the signal of the second light emission signal line is a valid level signal. The signal of the second reset signal line is a valid level signal for at least a certain period of time after the writing period, wherein the writing period is the period during which the first scan signal line is a valid level signal.

14. The pixel driving circuit according to claim 1, wherein, The first control sub-circuit includes a first transistor and a second transistor; the driving sub-circuit includes a third transistor; the second control sub-circuit includes a fourth transistor and a fifth transistor; the storage sub-circuit includes a first capacitor; and the third control sub-circuit further includes an eighth transistor. The control electrode of the first transistor is electrically connected to the first scan signal line, the first electrode of the first transistor is electrically connected to the data signal line, and the second electrode of the first transistor is electrically connected to the first node. The control electrode of the second transistor is electrically connected to the second scan signal line, the first electrode of the second transistor is electrically connected to the reference signal line, and the second electrode of the second transistor is electrically connected to the first node. The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fourth transistor is electrically connected to the first power supply line, and the second electrode of the fourth transistor is electrically connected to the second node. The control electrode of the fifth transistor is electrically connected to the second light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the fourth node. The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the fifth node, and the second electrode of the sixth transistor is electrically connected to the third node. The control electrode of the eighth transistor is electrically connected to the third reset signal line, the first electrode of the eighth transistor is electrically connected to the initial signal line, and the second electrode of the eighth transistor is electrically connected to the fourth node. The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node. The first terminal of the second capacitor is electrically connected to the auxiliary signal line, and the second terminal of the second capacitor is electrically connected to the fifth node. Any one of the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the eighth transistor is an N-type transistor.

15. The pixel driving circuit according to claim 14, wherein, During a certain period of time when the signal of the third reset signal line is at an effective level, the signal of the second light-emitting signal line is at an effective level.

16. A display device having a display area, the display area being provided with a plurality of pixel driving circuits as described in any one of claims 1 to 15.

17. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit as claimed in any one of claims 1 to 15, the method comprising: The driving sub-circuit provides driving current to the third node under the control of the signals from the first and second nodes; The first control sub-circuit provides data signal line or reference signal line signals to the first node under the control of the signals of the first scan signal line and the second scan signal line; Under the control of the signals from the first and second light-emitting signal lines, the second control sub-circuit provides the signal from the first power line to the second node and the signal from the third node to the fourth node. The third control sub-circuit controls the signal of the third node under the control of the signal of the first reset signal line and the signal of the auxiliary signal line; The storage sub-circuit stores the voltage difference between the signals of the first node and the third node.

18. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit as described in claim 11, wherein the operation of the pixel driving circuit includes: The method, from the first stage to the fifth stage, includes: In the first stage, valid level signals are provided to the signals of the second scan signal line, the second light emission signal line, the first reset signal line and the second reset signal line. The first control sub-circuit provides the reference signal line signal to the first node. The third control sub-circuit provides the auxiliary signal line signal to the fifth node and provides the signal of the fifth node to the third node. The second control sub-circuit provides the signal of the fourth node to the third node. In the second stage, effective level signals are provided to the first reset signal line, the second scan signal line and the first light emission signal line. The first control sub-circuit provides the reference signal line signal to the first node. The third control sub-circuit provides the auxiliary signal line signal to the fifth node. The second control sub-circuit provides the first power line signal to the second node to charge the first node. The storage sub-circuit stores the voltage difference between the signals of the first node and the third node. In the third stage, the signals to the first reset signal line and the first scan signal line are high-level signals, the first control sub-circuit provides the data signal line signal to the first node, and the third control sub-circuit provides the auxiliary signal line signal to the fifth node; In the fourth stage, an effective level signal is provided to the second reset signal line and the second light emission signal line, the third control sub-circuit provides the signal of the third node to the fifth node, and the second control sub-circuit provides the signal of the fourth node to the third node; In the fifth stage, valid level signals are provided to the second reset signal line, the first light-emitting signal line, and the second light-emitting signal line. The second control sub-circuit provides the first power line signal to the second node and the third node signal to the fourth node. Under the control of the signals from the first and second nodes, the drive sub-circuit provides the drive current to the third node. The third control sub-circuit provides the third node signal to the fifth node.

19. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit as described in claim 12, wherein the operation of the pixel driving circuit includes: The method, from the first stage to the fifth stage, includes: In the first stage, valid level signals are provided to the signals of the second scan signal line, the second light emission signal line, the first reset signal line and the third reset signal line. The first control sub-circuit provides the reference signal line signal to the first node. The third control sub-circuit provides the auxiliary signal line signal to the fifth node and the initial signal line signal to the fourth node. The second control sub-circuit provides the signal of the fourth node to the third node. In the second stage, effective level signals are provided to the first reset signal line, the third reset signal line, the second scan signal line, and the first light emission signal line. The first control sub-circuit provides a reference signal line signal to the first node. The third control sub-circuit provides an auxiliary signal line signal to the fifth node and an initial signal line signal to the fourth node. The second control sub-circuit provides a first power line signal to the second node to charge the first node. The storage sub-circuit stores the voltage difference between the signals of the first node and the third node. In the third stage, the signals to the first reset signal line, the third reset signal line, and the first scan signal line are high-level signals. The first control sub-circuit provides the data signal line to the first node, the third control sub-circuit provides the auxiliary signal line to the fifth node, and provides the initial signal line to the fourth node. In the fourth stage, effective level signals are provided to the first reset signal line, the third reset signal line, and the second light emission signal line. The third control sub-circuit provides the initial signal line signal to the fourth node and the auxiliary signal line signal to the fifth node. The second control sub-circuit provides the fourth node signal to the third node. In the fifth stage, valid level signals are provided to the first reset signal line, the first light-emitting signal line, and the second light-emitting signal line. The second control sub-circuit provides the first power line signal to the second node and the third node signal to the fourth node. Under the control of the signals from the first and second nodes, the drive sub-circuit provides the drive current to the third node. The third control sub-circuit provides the auxiliary signal line signal to the fifth node.

20. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit as described in claim 13, wherein the operation of the pixel driving circuit includes: The method, from the first stage to the fifth stage, includes: In the first stage, valid level signals are provided to the signals of the second scan signal line, the second light emission signal line, the first reset signal line and the third reset signal line. The first control sub-circuit provides the reference signal line signal to the first node. The third control sub-circuit provides the auxiliary signal line signal to the fifth node and the initial signal line signal to the fourth node. The second control sub-circuit provides the signal of the fourth node to the third node. In the second stage, effective level signals are provided to the first reset signal line, the third reset signal line, the second scan signal line, and the first light emission signal line. The first control sub-circuit provides a reference signal line signal to the first node. The third control sub-circuit provides an auxiliary signal line signal to the fifth node and an initial signal line signal to the fourth node. The second control sub-circuit provides a first power line signal to the second node to charge the first node. The storage sub-circuit stores the voltage difference between the signals of the first node and the third node. In the third stage, the signals to the first reset signal line, the third reset signal line, and the first scan signal line are high-level signals. The first control sub-circuit provides the data signal line to the first node, the third control sub-circuit provides the auxiliary signal line to the fifth node, and provides the initial signal line to the fourth node. In the fourth stage, valid level signals are provided to the second reset signal line, the third reset signal line, and the second light emission signal line. The third control sub-circuit provides the initial signal line signal to the fourth node, provides the third node signal to the fifth node, and the second control sub-circuit provides the fourth node signal to the third node. In the fifth stage, valid level signals are provided to the second reset signal line, the first light-emitting signal line, and the second light-emitting signal line. The second control sub-circuit provides the first power line signal to the second node and the third node signal to the fourth node. Under the control of the signals from the first and second nodes, the drive sub-circuit provides the drive current to the third node. The third control sub-circuit provides the third node signal to the fifth node.

21. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit as described in claim 15, wherein the operation of the pixel driving circuit includes: The method, from the first stage to the fifth stage, includes: In the first stage, valid level signals are provided to the signals of the second scan signal line, the second light emission signal line, the first reset signal line and the third reset signal line. The first control sub-circuit provides the reference signal line signal to the first node. The third control sub-circuit provides the signal of the third node to the fifth node and provides the signal of the initial signal line to the fourth node. The second control sub-circuit provides the signal of the fourth node to the third node. In the second stage, effective level signals are provided to the first reset signal line, the third reset signal line, the second scan signal line, and the first light emission signal line. The first control sub-circuit provides the reference signal line signal to the first node. The third control sub-circuit provides the signal of the third node to the fifth node and the initial signal line signal to the fourth node. The second control sub-circuit provides the first power line signal to the second node to charge the first node. The storage sub-circuit stores the voltage difference between the signals of the first node and the third node. In the third stage, the signals to the first reset signal line, the third reset signal line, and the first scan signal line are high-level signals. The first control sub-circuit provides the data signal line signal to the first node, and the third control sub-circuit provides the initial signal line signal to the fourth node and the signal of the third node to the fifth node. In the fourth stage, an effective level signal is provided to the third reset signal line and the second light emission signal line. The third control sub-circuit provides the initial signal line signal to the fourth node, and the second control sub-circuit provides the signal of the fourth node to the third node. In the fifth stage, effective level signals are provided to the first and second light-emitting signal lines. The second control sub-circuit provides the first power line signal to the second node and the third node signal to the fourth node. Under the control of the signals from the first and second nodes, the drive sub-circuit provides drive current to the third node.

Images