Method for manufacturing array substrate, array substrate and display device

Abstract

The embodiment of the present application provides a preparation method of an array substrate, the array substrate and a display device, wherein the preparation method of the array substrate comprises the following steps: providing a substrate; forming a first metal layer on one side of the substrate, performing a patterning treatment on the first metal layer, and respectively forming a gate electrode and a solder layer on the substrate; forming a first insulating material layer on the side of the substrate where the gate electrode and the solder layer are located, performing a patterning treatment on the first insulating material layer, and forming a gate insulating layer covering the gate electrode and a first insulating layer covering the solder layer; forming a second metal layer on the side of the substrate where the gate insulating layer and the first insulating layer are located, performing a patterning treatment on the second metal layer, and forming a source electrode and a drain electrode and a ground layer located on the side of the first insulating layer away from the substrate. The preparation method of the array substrate, the array substrate and the display device provided by the embodiment of the present application effectively reduce the waste pollution generated by PCBA, save the material and equipment cost, effectively reduce the cost and improve the quality.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a method for preparing an array substrate, the array substrate, and a display device. Background Technology

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) is currently the most widely used and popular display panel on the market. Its features include low radiation, low space occupation, beautiful appearance, and excellent picture quality. After decades of development, its technology has also reached a very high level of maturity.

[0003] Currently, the structure of TFT-LCD displays on the market typically consists of a panel, a printed circuit board assembly (PCBA), a flexible printed circuit (FPC), and a backlight. The panel is surrounded by FPCs and PCBAs, whose function is to provide various display information to the screen after power is applied. However, as the panel size increases, the area of ​​the PCBA and FPC also increases, resulting in thicker bezels and making the PCBA more prone to warping. Furthermore, due to the materials used in PCBAs, primarily glass fiber and epoxy resin, the actual production process causes significant environmental pollution. Additionally, their heat dissipation is not ideal, and with long-term use, the PCBA boards will age under the influence of temperature and humidity, thus affecting the normal operation of the display. Summary of the Invention

[0004] In view of this, the present application provides a method for preparing an array substrate, an array substrate, and a display device to solve the technical problems of PCBA warping in existing LCD displays, waste pollution generated by PCBA, and PCBA aging affecting the normal use of the display.

[0005] In a first aspect, embodiments of this application provide a method for fabricating an array substrate, comprising the following steps:

[0006] Provide substrate;

[0007] A first metal layer is formed on one side of the substrate, and the first metal layer is patterned to form a gate and a solder layer respectively located on the substrate;

[0008] A first insulating material layer is formed on one side of the substrate where the gate and the solder layer are located. The first insulating material layer is patterned to form a gate insulating layer covering the gate and a first insulating layer covering the solder layer.

[0009] A second metal layer is formed on the side of the gate insulating layer and the first insulating layer located on the substrate. The second metal layer is patterned to form a source and a drain on the side of the gate insulating layer away from the substrate, and a ground layer on the side of the first insulating layer away from the substrate.

[0010] A second insulating material layer is formed on one side of the substrate where the source, drain, and ground layers are located. The second insulating material layer is patterned to form a passivation layer covering the source, drain, and gate insulating layers, and a second insulating layer covering the ground layer.

[0011] In some embodiments, after forming the gate insulating layer and the first insulating layer and before forming the second metal layer, the method further includes:

[0012] A silicon material layer is deposited on the side of the gate insulating layer and the first insulating layer located on the substrate. The silicon material layer is patterned, and an active layer is formed on the side of the gate insulating layer away from the substrate. The active layer is located between the gate insulating layer and the source and the drain.

[0013] In some embodiments, a silicon material layer is deposited on the side of the gate insulating layer and the first insulating layer located on the substrate, and the silicon material layer is patterned, including:

[0014] During the patterning process of the silicon material layer located on the first insulating layer, no photoresist is applied to the silicon material layer on the first insulating layer so that the silicon material layer located on the first insulating layer is etched away.

[0015] Alternatively, the silicon material layer located on the first insulating layer can be removed directly.

[0016] In some embodiments, the gate and the solder layer are configured to be spaced apart.

[0017] In some embodiments, it also includes:

[0018] A third metal layer is formed on one side of the passivation layer and the second insulating layer located on the substrate. The third metal layer is patterned to form a touch electrode layer located on the side of the passivation layer away from the substrate and a power layer located on the side of the second insulating layer away from the substrate.

[0019] In some embodiments, the patterning process includes, in sequence:

[0020] The process includes applying photoresist, exposure, development, etching, and photoresist removal.

[0021] In some embodiments, patterning the first metal layer includes: performing a light-shielding process on two portions of the first metal layer located on the substrate.

[0022] In some embodiments, patterning the first insulating material layer includes: applying a light-shielding treatment to the first insulating material layer located above and around the gate and the solder layer, respectively.

[0023] In some embodiments, the patterning process of the second metal layer includes: performing a light-shielding process on the second metal layer located in the orthographic projection along the thickness direction of the array substrate, respectively, on the gate insulating layer and the solder layer, and leaving the middle part of the second metal layer on the gate insulating layer blank and not performing a light-shielding process.

[0024] In some embodiments, patterning the second insulating material layer includes: performing a light-shielding treatment on the second insulating material layer located above and around the gate insulating layer, and performing a light-shielding treatment on the second insulating material layer located within the orthographic projection of the first insulating layer along the thickness direction of the array substrate.

[0025] In some embodiments, the substrate is made of one of glass and plastic;

[0026] When the substrate is made of glass, the substrate has the following performance parameters:

[0027] The thermal conductivity is 0.7–1.3 W / (m·K);

[0028] The coefficient of thermal expansion is 3–4 ppm / ℃;

[0029] The line width is 3-4 μm and the line spacing is 2-3 μm.

[0030] Secondly, embodiments of this application provide an array substrate, which is prepared using the fabrication method described in the first aspect.

[0031] Thirdly, embodiments of this application provide a display device, including a housing and a motherboard. The display device further includes the array substrate described in the second aspect. The motherboard and the array substrate are disposed within the housing, and the array substrate is electrically connected to the motherboard.

[0032] The array substrate fabrication method, array substrate, and display device provided in this application integrate the fabrication methods of PCBA boards and TFT-LCD array substrates. That is, both are fabricated simultaneously using a shared substrate. When the gate electrode is deposited using the array process, the solder layer in the PCBA board is simultaneously deposited. When the gate insulating layer is deposited, the insulating layer in the PCBA board is replaced with the same material. Similarly, when the drain / source electrode is deposited, the ground layer in the PCBA board can be deposited. This process continues, and the number of metal and insulating layers that can be deposited in the PCBA can be determined based on the number of metal layer processes and the number of insulating / passivation layer deposition processes required for the array. Compared to the traditional process of fabricating PCBA boards separately, this effectively reduces the number of processes. Since this application abandons the use of PCBA and FPC, most of the processes can be performed on the LCD equipment. Furthermore, LCD manufacturing materials can be used to achieve the functions of PCBA and FPC, achieving cost savings in materials and equipment requirements. It also reduces the overall module thickness and weight, improves heat dissipation performance, and reduces the risk of PCBA warpage. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the structure of a PCBA board in the prior art;

[0035] Figure 2 This is a schematic flowchart of the method for fabricating an array substrate provided in an embodiment of this application;

[0036] Figure 3 This is a schematic diagram of the process structure of steps S100 and S200 in the method for fabricating an array substrate provided in the embodiments of this application;

[0037] Figure 4 This is a schematic diagram of the process structure of step S300 in the method for fabricating an array substrate provided in this application embodiment;

[0038] Figure 5 This is a schematic diagram of the process structure of step S400 in the method for fabricating an array substrate provided in this application embodiment;

[0039] Figure 6This is a schematic diagram of the process structure of S310 in the method for fabricating the array substrate provided in this application;

[0040] Figure 7 This is a schematic diagram of the process structure of step S500 in the method for fabricating an array substrate provided in this application embodiment;

[0041] Figure 8 This is a schematic diagram of the structure of the array substrate provided in the embodiments of this application;

[0042] Figure 9 This is a schematic diagram of the structure of the display device provided in the embodiments of this application.

[0043] The attached icon numbers are as follows:

[0044] 001. Metal structural layer; 002. Insulating structural layer;

[0045] 10. Substrate;

[0046] 20. First metal layer; 21. Gate; 22. Solder layer;

[0047] 30. First insulating material layer; 31. Gate insulating layer; 32. First insulating layer;

[0048] 40. Second metal layer; 41. Source; 42. Drain; 43. Ground layer;

[0049] 50. Second insulating material layer; 51. Passivation layer; 52. Second insulating layer;

[0050] 60. Silicon material layer; 61. Active layer;

[0051] 70. Outer shell;

[0052] 80. Base. Detailed Implementation

[0053] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that the embodiments of this application can also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the embodiments of this application with unnecessary detail.

[0054] It should also be understood that the term "and / or" as used in the specification of embodiments of this application and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0055] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0056] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0057] Furthermore, in the description of the embodiments and the appended claims of this application, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0058] In the description of embodiments in this application, references to "some embodiments" or "some embodiments" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in some embodiments," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiments, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. "A plurality" refers to two or more.

[0059] With the continuous advancement of display technology, the design precision of traditional PCBAs is insufficient to meet the more complex wiring requirements of higher-density soldered products, further increasing costs by sourcing high-precision PCBAs from abroad. Moreover, as panel sizes increase, the area of ​​PCBAs and FPCs also increases, resulting in thicker display bezels and a greater susceptibility to PCBA warping. Furthermore, since PCBAs are primarily composed of fiberglass and epoxy resin, their production process generates significant environmental pollution, and their heat dissipation is inadequate. Over time, the PCBA boards will age due to temperature and humidity fluctuations, affecting the normal operation of the display.

[0060] The inventive concept of this application originates from a four-layer PCBA board as an example. The basic structure of existing PCBA boards is as follows: Figure 1As shown, it typically includes multiple metal structure layers 001, with an insulating structure layer 002 separating the metal structure layers 001. Since PCBA boards also achieve complex, multi-layered wiring through processes such as coating a metal film, exposure, development, and etching, the manufacturing process is similar to that of TFT-LCD array substrates. Therefore, by integrating the PCBA board fabrication process with the TFT-LCD array process, that is, realizing the wiring on the PCBA board through array processes and materials, an integrated design of PCBA, FPC, and array substrate is achieved. Therefore, this application provides a method for fabricating an array substrate, an array substrate, and a display device, which effectively solves the above problems, replaces traditional PCBAs, effectively reduces waste pollution generated by PCBAs, saves material and equipment costs, and effectively improves display quality.

[0061] It should be noted that the thickness direction of the array substrate mentioned in the embodiments of this application is the Y direction in the figure, and the X direction is the length / width direction of the array substrate. The above is only for the convenience of understanding the technical solutions of the embodiments of this application and should not be construed as limiting the scope of the embodiments of this application.

[0062] The first aspect of this application provides a method for fabricating an array substrate, such as... Figures 2 to 7 As shown, it includes the following steps:

[0063] S100, providing substrate 10;

[0064] S200: A first metal layer 20 is formed on one side of the substrate 10, and the first metal layer 20 is patterned to form a gate 21 and a solder layer 22 located on the substrate 10, respectively.

[0065] S300: A first insulating material layer 30 is formed on one side of the substrate 10 where the gate 21 and the solder layer 22 are located. The first insulating material layer 30 is patterned to form a gate insulating layer 32 covering the gate 21 and a first insulating layer 32 covering the solder layer 22.

[0066] S400, A second metal layer 40 is formed on one side of the gate insulating layer 31 and the first insulating layer 32 located on the substrate 10. The second metal layer 40 is patterned to form a source 41 and a drain 42 located on the side of the gate insulating layer 31 away from the substrate 10, and a ground layer 43 located on the side of the first insulating layer 32 away from the substrate 10.

[0067] S500, a second insulating material layer 50 is formed on one side of the substrate 10 where the source 41, drain 42 and ground layer 43 are located. The second insulating material layer 50 is patterned to form a passivation layer 51 covering the source 41, drain 42 and gate insulating layer 31, and a second insulating layer 52 covering the ground layer 43.

[0068] The array substrate fabrication method provided in this application provides a method for fabricating an array substrate by performing an array process on the same substrate. This process simultaneously forms the layer structure of a PCBA board, sharing the same processes and materials. This effectively reduces the overall fabrication process of the array substrate and eliminates the need for a PCBA board. It also prevents warping of the PCBA board in the array substrate and avoids environmental pollution caused by the selection of conventional PCBA materials (glass fiber and epoxy resin). Furthermore, traditional PCBA materials age under the influence of humidity and temperature after prolonged use, which can affect the normal operation of the display. This application avoids these issues by using the same processes and materials as the LCD array substrate.

[0069] The array process is a crucial step in the manufacturing of TFT-LCDs (Thin Film Transistor Liquid Crystal Displays). The array process is primarily used to manufacture the TFT-LCD array substrate, which is the core component responsible for controlling the switching of each pixel.

[0070] It should be noted that a first insulating material layer 30 is formed on the side of the substrate 10 where the gate 21 and solder layer 22 are located. "Located" means that the first insulating material layer 30, the gate 21, and the solder layer 22 are located on the same side of the substrate. Specifically, part of the first insulating material layer 30 is located on the gate 21 and solder layer 22, and part is located directly on the substrate 10.

[0071] In application, the array substrate fabrication method provided in this application integrates the PCBA board fabrication method and the TFT-LCD array substrate fabrication method, that is, both are fabricated simultaneously, sharing a substrate. When the gate is deposited using the array process, the solder layer in the PCBA board is deposited simultaneously. When the gate insulating layer is deposited, the insulating layer in the PCBA board is replaced with the same material. Similarly, when the drain / source is deposited, the ground layer in the PCBA board can be deposited. And so on, the number of metal layers and insulating layers that can be deposited in the PCBA can be determined according to the number of metal layer processes and the number of insulating / passivation layer depositions required by the array. By abandoning the use of conventional PCBA and FPC, most of the PCBA-related processes can be performed on LCD equipment. At the same time, LCD manufacturing materials can be used to achieve the functions of PCBA and FPC, achieving cost savings in terms of materials and equipment requirements, reducing the overall module thickness and weight, and improving heat dissipation performance.

[0072] In some embodiments, in step S100, the substrate material includes one of glass and plastic. In a preferred embodiment, the substrate material is glass, and when the substrate material is glass, the substrate has the following performance parameters:

[0073] The thermal conductivity is 0.7–1.3 W / (m·K);

[0074] The coefficient of thermal expansion is 3–4 ppm / ℃;

[0075] The line width is 3-4 μm and the line spacing is 2-3 μm.

[0076] In applications, conventional PCB substrates are made of glass fiber and epoxy resin, but their overall performance parameters are inferior to those of glass substrates. A comparison of specific parameters is shown in the table below:

[0077] Comparison of characteristics of PCBA boards made using conventional PCB substrates and glass substrates

[0078] parameter glass substrate conventional PCB substrate thermal conductivity 0.7–1.3 W(m·K) 0.25 W (m·k) coefficient of thermal expansion 3~4ppm / ℃ 12~18ppm / ℃ Line width 3~4μm 100μm Line spacing 2~3μm 100μm Material Cu, G-SiNx Cu, G-SiNx, glass fiber, epoxy resin

[0079] Note: Cu stands for copper, and G-SiNx refers to a specific layer structure used in the fabrication process of TFT-LCD (Thin Film Transistor Liquid Crystal Display) arrays. Here, "G" stands for "Gate," and "SiNx" stands for "Silicon Nitride."

[0080] As shown in the table above, PCBA boards made with glass substrates have higher thermal conductivity and heat dissipation capabilities. Therefore, components generate less heat when operating on glass substrates, improving product yield and lifespan. Furthermore, the superior mechanical properties of glass substrates result in greater overall stability, higher flatness, and ultimately, more precise PCBAs.

[0081] In the following embodiment, in step S200, as Figure 2 and Figure 3 As shown, a first metal layer 20 is formed on one side of a substrate 10, and then the first metal layer 20 is patterned to form a gate 21 and a solder layer 22 located on the substrate 10, respectively. In applications, the material of the first metal layer is selected from copper, molybdenum, and aluminum. In a preferred embodiment, the first metal layer is a copper layer. The first metal film layer is formed on one side of the substrate by a sputtering process, wherein the sputtering process includes: bombarding a copper target with high-energy particles in a vacuum, causing copper atoms to be sputtered from the target surface and deposited on the substrate to form a uniform thin film (first metal layer). In applications, the patterning process of the first metal layer includes: shielding two portions of the first metal layer on the substrate to allow the formation of the gate and solder layers in subsequent steps. In other embodiments, the patterning process of the first metal layer includes: applying photoresist only to the two portions of the first metal layer on the substrate to allow the formation of the gate and solder layers in subsequent steps.

[0082] In the application, after patterning the first metal layer 20, gate 21 and solder layer 22 spaced apart are formed on the substrate 10, wherein the solder layer 22 serves as a structural layer in the PCBA board. The spacing helps ensure that the two do not interfere with each other in subsequent processes, thus guaranteeing the normal function of the LCD array substrate, PCBA, and FPC.

[0083] In some embodiments, the patterning process sequentially includes: applying photoresist, exposure, development, etching, and photoresist removal. Applying photoresist refers to coating a layer of photoresist (PR) material onto the deposited thin film (first metal layer). PR is a photosensitive polymer and can be classified as positive or negative photoresist based on its reaction properties after exposure. Exposure involves transferring the pattern onto the PR layer using a mask and an exposure machine. Ultraviolet light emitted by the exposure machine passes through the transparent areas of the mask and irradiates the PR layer, causing changes in the PR properties of these areas. Development involves treating the PR layer with a developer to remove PR from exposed areas (for positive photoresist) or unexposed areas (for negative photoresist), thereby forming a patterned PR layer on the substrate. After development, the desired pattern is formed on the PR layer. Etching involves removing the underlying material not protected by PR using chemical etching or dry etching (such as plasma etching). The etching process etches away the underlying material according to the pattern of the PR layer, leaving the desired structure (gate). Photoresist removal involves removing the PR layer using solvents or other methods after etching to facilitate subsequent processes. Photoresist removal can be performed using either wet or dry processes.

[0084] In applications, this series of steps usually needs to be repeated multiple times to complete the fabrication of different layers of the entire TFT-LCD array substrate. For example, when fabricating gate lines, gate material needs to be sputtered first, followed by photoresist coating, exposure, development, etching, and photoresist removal; subsequently, this series of steps also needs to be repeated for source and drain materials.

[0085] In some embodiments, in step S300, such as Figure 2 and Figure 4 As shown, a first insulating material layer 30 is formed on one side of the substrate 10 where the gate 21 and solder layer 22 are located. The first insulating material layer 30 is then patterned to form a gate insulating layer 31 covering the gate 21 and a first insulating layer 32 covering the solder layer 22. In applications, the material of the first insulating material layer includes, but is not limited to, SiO2 or SiN. By selecting SiO2 or SiN as the material for the GI (gate insulating layer), and because GI has an insulating function, it can be used as an insulating layer in the PCBA board to separate the solder layer and the ground layer. This achieves shared fabrication processes for the gate insulating layer and the first insulating layer, effectively reducing material costs and simplifying process steps.

[0086] In applications, a first insulating material layer is formed on one side of the substrate where the gate and solder layer are located. Since the final gate insulating layer needs to isolate the gate, a first insulating material layer covering the substrate, gate, and solder layer needs to be formed on the substrate, i.e., as shown below. Figure 4As shown, the final result is a gate insulating layer that completely covers the exposed portion of the gate, and a first insulating layer that completely covers the exposed portion of the solder layer. The first insulating material layer is also formed as a thin film on the substrate, gate, and solder layer through a sputtering process.

[0087] In applications, such as Figure 4 As shown, the patterning process of the first insulating material layer 30 includes: applying a light-shielding treatment to the first insulating material layer 30 located above and around the gate 21 and the solder layer 22, respectively. This operation ensures that a gate insulating layer covering the gate and a first insulating layer covering the solder layer are ultimately formed. In other embodiments, photoresist is applied only to the first insulating material layer 30 located above and around the gate 21 and the solder layer 22, respectively, so that it is not etched away in subsequent steps.

[0088] In some embodiments, in step S400, such as Figure 2 and Figure 5 As shown, a second metal layer 40 is formed on one side of the gate insulating layer 31 and the first insulating layer 32 located on the substrate 10. The second metal layer 40 is then patterned to form a source 41 and a drain 42 on the side of the gate insulating layer 31 away from the substrate 10, and a ground layer 43 on the side of the first insulating layer 32 away from the substrate 10. The material of the second metal layer 40 is the same as that of the first metal layer 20, which is one of copper, aluminum, or molybdenum, preferably copper.

[0089] In applications, such as Figure 5 As shown, the patterning process for the second metal layer 40 includes: applying photoresist to the second metal layer 40 located within the orthographic projection of the gate insulating layer 31 and the solder layer 22 along the thickness direction of the array substrate, respectively, and leaving the middle part of the second metal layer 40 on the gate insulating layer 31 blank and without photoresist. This ensures the formation of mutually spaced source electrodes 41, drain electrodes 42, and ground layers 43.

[0090] It should be noted that a second metal layer 40 is formed on one side of the substrate 10 where the gate insulating layer 31 and the first insulating layer 32 are located. That is, the formed second metal layer 40, the gate insulating layer 31, and the first insulating layer 32 are all located on the same side of the substrate. Specifically, part of the second metal layer 40 is disposed on the gate insulating layer 31 and the first insulating layer 32, and part of the second metal layer 40 is in direct contact with the substrate 10.

[0091] In applications, the final source and drain are located on the gate insulating layer and within the orthogonal projection of the gate in the thickness direction of the array substrate. The source and drain are spaced apart to ensure that they remain independent of each other and do not affect normal operation.

[0092] In some embodiments, such as Figure 6 As shown, after step S300 and before step S400, step S310 is included: depositing a silicon material layer 60 on one side of the gate insulating layer 31 and the first insulating layer 32 located on the substrate 10; patterning the silicon material layer 60; and forming an active layer 61 on the side of the gate insulating layer 31 away from the substrate 10. The active layer 61 is located between the gate insulating layer 31 and the source electrode 41 and the drain electrode 42. The silicon material layer 60 includes amorphous silicon or polycrystalline silicon and serves as the active layer 61 of the array substrate. In applications, the active layer is the core component of the TFT, determining its conductivity. Under the influence of the gate voltage, charge carriers (electrons or holes) in the active layer flow between the source and drain electrodes.

[0093] In the application, a silicon material layer 60 is deposited on one side of the substrate 10 where the gate insulating layer 31 and the first insulating layer 32 are located, and then the silicon material layer 60 is patterned, including:

[0094] During the patterning process of the silicon material layer 60 located on the first insulating layer 32, no light-shielding treatment is applied to the silicon material layer 60 on the first insulating layer 32 to allow it to be etched away. In other embodiments, during the patterning process of the silicon material layer 60 located on the first insulating layer 32, no photoresist is applied to the silicon material layer 60 on the first insulating layer 32 to allow that portion to be etched away.

[0095] Because a silicon material layer is formed on the first insulating layer during the formation of the active layer on the gate insulating layer to ensure process simplicity and consistency, but this layer is not needed in PCBA board fabrication, it is not light-shielded during patterning. In subsequent exposure and etching steps, the silicon material layer on the first insulating layer is etched away. In other words, only the portion of the silicon material layer on the gate insulating layer needs normal patterning, and the silicon material layer on the gate insulating layer needs light-shielding to ensure that this portion of the silicon material layer is not removed in subsequent steps, ultimately forming the active layer. In other embodiments, the silicon material layer on the first insulating layer is directly removed.

[0096] In some embodiments, such as Figure 2 and Figure 7As shown, in step S500, a second insulating material layer 50 is formed on one side of the substrate 10 where the source 41, drain 42, and ground layer 43 are located. Then, the second insulating material layer 50 is patterned to form a passivation layer 51 covering the source 41, drain 42, and gate insulating layer 31, and a second insulating layer 52 covering the ground layer 43. The passivation layer 51 is partially embedded in the gap between the source 41 and drain 42, while the remaining portion covers the source 41, drain 42, and gate insulating layer 31, isolating them from the outside environment. The second insulating layer 52 completely covers the ground layer 43.

[0097] It should be noted that a second insulating material layer 50 is formed on one side of the substrate 10 where the source electrode 41, drain electrode 42, and ground layer 43 are located. This means that the formed second insulating material layer is on the same side of the substrate 10 as the source electrode 41, drain electrode 42, and ground layer 43. In some embodiments, a portion of the second insulating material layer 50 is located on the source electrode 41, drain electrode 42, and ground layer 43, and a portion of the second insulating material layer 50 is in direct contact with the substrate 10.

[0098] In the application, the patterning process of the second insulating material layer 50 includes: applying a photoresist to the second insulating material layer 50 located above and around the gate insulating layer 31, thereby forming a passivation layer 51 that ultimately covers the source 41, drain 42, and gate insulating layer 31; and applying a photoresist to the second insulating material layer 50 located within the orthogonal projection of the first insulating layer 32 along the thickness direction of the array substrate, thereby forming a second insulating layer 52 with a structure similar to the first insulating layer 32 and covering the ground layer 43.

[0099] In some embodiments, the method for fabricating the array substrate further includes step S600: forming a third metal layer (not shown) on the side of the passivation layer 51 and the second insulating layer 52 located on the substrate 10; then patterning the third metal layer to form a touch electrode layer on the side of the passivation layer 51 away from the substrate 10, and a power layer on the side of the second insulating layer 52 away from the substrate 10. The third metal layer is similar in configuration to the first metal layer 20 and the second metal layer 40. In some embodiments, for touch products with built-in touch, a third metal layer is also present above the passivation layer 51, so that the power layer can be deposited simultaneously. The second passivation layer above the third metal layer is an isolation layer, and a third insulating layer for isolating the power layer is deposited simultaneously.

[0100] In some embodiments, the method further includes S700, forming a third insulating material layer on one side of the substrate 10 where the touch electrode layer and the power layer are located, and then patterning the third insulating material layer to form an insulating layer covering the touch electrode layer and a third insulating layer covering the power layer. The third insulating material layer is similar in construction to the first insulating material layer 30 and the second insulating material layer 50, and the related processes are the same.

[0101] In application, the patterning processes in steps S300, S310, S400, S500, S600, and S700 are the same as those in step S200, and will not be elaborated further here. To ensure the consistency of the entire array process, the first metal layer, the first insulating material layer, the silicon material layer, the second metal layer, and the second insulating material layer are all formed by sputtering, followed by patterning, to finally obtain the corresponding layer structure.

[0102] In some embodiments, the method for fabricating the array substrate further includes soldering the electronic components, I / O interfaces, etc., required on the original PCBA board onto the substrate surface, thereby ultimately achieving the integration of the array substrate and the PCBA.

[0103] The second aspect of this application provides an array substrate, which is prepared using the preparation method described in the first aspect.

[0104] In some embodiments, such as Figure 8 As shown, the array substrate includes TFTs and PCBAs spaced apart, and the TFTs and PCBAs share a single substrate 10;

[0105] The TFT includes a substrate 10, a gate 21, a gate insulating layer 31, an active layer 61, a source 41, a drain 42, and a passivation layer 51. The gate insulating layer 31 covers the gate 21 and separates the gate 21 from other structures. The active layer 61 is located on the gate insulating layer 31 and within the orthogonal projection of the gate 21 in the thickness direction of the array substrate. The source 41 and the drain 42 are located on opposite sides of the active layer 61, and the passivation layer 51 covers the source 41, the drain 42, and the gate insulating layer 31.

[0106] The PCBA includes a substrate 10, a solder layer 22, a first insulating layer 32, a ground layer 43, and a second insulating layer 52. The first insulating layer 32 completely covers the solder layer 22, and the second insulating layer 52 completely covers the ground layer 43. The second insulating layer 52 is located within the orthogonal projection of the first insulating layer 32 in the thickness direction of the array substrate.

[0107] In some embodiments, the TFT further includes a touch electrode layer and an insulating layer covering the touch electrode layer, the touch electrode layer being located on one side of the passivation layer 51, and the PCBA further includes a power layer located on the second insulating layer 52 and a third insulating layer covering the power layer.

[0108] The array substrate provided in this application eliminates the use of conventional PCBA boards, naturally avoiding the problem of PCBA warping. It also reduces waste pollution generated during PCBA manufacturing and prevents aging that could affect the normal operation of the display. Furthermore, the PCBA circuitry fabricated on the glass substrate uses materials identical to those used in TFT-LCD production, saving on material and equipment costs and allowing for the production of PCBAs with higher precision.

[0109] A third aspect of the embodiments of this application provides a display device, such as... Figure 9 As shown, the display device includes the array substrate, housing 70, and motherboard (not shown) described in the second aspect of the present application. The array substrate and motherboard are disposed within the housing 70, and the array substrate and motherboard are electrically connected. In some embodiments, the display device further includes a base 80, which is connected to the housing 70. This provides stable support for the entire display device.

[0110] The display device provided in this application embodiment has a housing 70, which serves as the external protective structure for the display device. It not only provides physical protection for the internal components, preventing external environmental influences such as dust, moisture, and accidental impacts, but also contributes to aesthetics and ergonomics. The motherboard is the core control center of the display device, containing circuits for processing image signals, power management, and interface communication. It is responsible for receiving video signals from external devices (such as computers, TV boxes, etc.) and converting them into a format suitable for the display panel.

[0111] In applications, the housing 70 is made of plastic or metal, or a combination of both, to achieve optimal performance and cost-effectiveness. The housing has dedicated slots, screw holes, or other mechanical fasteners to secure the array substrate and motherboard, ensuring the stability of these critical components during transport and use. In other embodiments, the housing may also include vents, buttons, interfaces, etc., to meet heat dissipation requirements and facilitate user operation.

[0112] In applications, the motherboard may contain various chips, such as a graphics processor, a central processing unit, memory modules, and other control chips, as well as interfaces for connecting external devices, such as HDMI and USB. The array substrate, part of a flat panel display like an LCD or OLED, is located on the back of the display panel and is covered with thin-film transistors (TFTs) and other tiny circuit structures. These TFTs control the on / off state of each pixel, determining whether it should transmit light (for LCDs) or emit light (for OLEDs) to display an image.

[0113] In applications, the motherboard is connected to the array substrate via flexible cables or ribbon cables. This allows data signals to be transmitted from the motherboard to the individual TFTs on the array substrate, thereby controlling the display content. Simultaneously, power lines also transfer necessary power from the motherboard to the array substrate.

[0114] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0115] The above-described embodiments are only used to illustrate the technical solutions of the embodiments of this application, and are not intended to limit them. Although the embodiments of this application have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of the embodiments of this application.

Claims

1. A method for fabricating an array substrate, characterized in that, Includes the following steps: Provide substrate; A first metal layer is formed on one side of the substrate, and the first metal layer is patterned to form a gate and a solder layer located on the substrate, respectively. The gate and the solder layer are spaced apart from each other, and the solder layer serves as a structural layer in the PCBA board. A first insulating material layer is formed on one side of the substrate where the gate and the solder layer are located. The first insulating material layer is patterned to form a gate insulating layer covering the gate and a first insulating layer covering the solder layer. A silicon material layer is deposited on the side of the gate insulating layer and the first insulating layer located on the substrate, the silicon material layer is patterned, and an active layer is formed on the side of the gate insulating layer away from the substrate. A second metal layer is formed on the side of the gate insulating layer and the first insulating layer located on the substrate. The second metal layer is patterned to form a source and a drain on the side of the gate insulating layer away from the substrate, and a ground layer on the side of the first insulating layer away from the substrate. The active layer is located between the gate insulating layer and the source and the drain. A second insulating material layer is formed on one side of the substrate where the source, drain, and ground layers are located. The second insulating material layer is patterned to form a passivation layer covering the source, drain, and gate insulating layers, and a second insulating layer covering the ground layer. A third metal layer is formed on one side of the passivation layer and the second insulating layer located on the substrate. The third metal layer is patterned to form a touch electrode layer on the side of the passivation layer away from the substrate and a power layer on the side of the second insulating layer away from the substrate. The third metal layer is made of the same material as the first metal layer. A third insulating material layer is formed on one side of the substrate where the touch electrode layer and the power layer are located. The third insulating material layer is patterned to form an insulating layer covering the touch electrode layer and a third insulating layer covering the power layer. The third insulating material layer is made of the same material as the first insulating material layer. The patterning process includes, in sequence: The process includes applying photoresist, exposure, development, etching, and photoresist removal.

2. The preparation method according to claim 1, characterized in that, A silicon material layer is deposited on one side of the substrate where the gate insulating layer and the first insulating layer are located, and the silicon material layer is patterned, including: During the patterning process of the silicon material layer located on the first insulating layer, the silicon material layer on the first insulating layer is not shielded from light so that the silicon material layer located on the first insulating layer is etched away. Alternatively, the silicon material layer located on the first insulating layer can be removed directly.

3. The preparation method according to claim 1, characterized in that, The patterning process for the first metal layer includes: performing a light-shielding process on two portions of the first metal layer located on the substrate. And / or, the patterning process of the first insulating material layer includes: performing a light-shielding process on the first insulating material layer located above and around the gate and the solder layer, respectively; And / or, the patterning process of the second metal layer includes: performing a light-shielding process on the second metal layer located in the orthographic projection along the thickness direction of the array substrate of the gate insulating layer and the solder layer respectively, and leaving the middle part of the second metal layer on the gate insulating layer blank and not performing a light-shielding process; And / or, the patterning process of the second insulating material layer includes: performing a light-shielding process on the second insulating material layer located above and around the gate insulating layer, and performing a light-shielding process on the second insulating material layer located within the orthographic projection of the first insulating layer along the thickness direction of the array substrate.

4. The preparation method according to any one of claims 1 to 3, characterized in that, The substrate is made of either glass or plastic. When the substrate is made of glass, the substrate has the following performance parameters: The thermal conductivity is 0.7~1.3 W (m·K); The coefficient of thermal expansion is 3~4 ppm / ℃; The line width is 3~4μm and the line spacing is 2~3μm.

5. An array substrate, characterized in that, It is prepared by the preparation method described in any one of claims 1 to 4.

6. A display device, comprising a housing and a motherboard, characterized in that, The display device further includes the array substrate as described in claim 5, wherein the motherboard and the array substrate are disposed within the housing, and the array substrate is electrically connected to the motherboard.

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