Signaling circuit, chip and electronic device

Abstract

The application discloses a signal sending circuit, a chip and electronic equipment, and belongs to the technical field of display. The signal sending circuit comprises a first signal driving circuit and a second signal driving circuit; in the case where the first signal driving circuit and the second signal driving circuit are disconnected, the first signal driving circuit is used for sending an output differential signal in a CML driving mode according to a first input differential signal, and the second signal driving circuit does not work; in the case where the first signal driving circuit and the second signal driving circuit are connected, the first signal driving circuit and the second signal driving circuit are used for sending an output differential signal in an LVDS driving mode according to the first input differential signal. The signal sending circuit can support the switching of the two driving modes of the LVDS driving mode and the CML driving mode, so that the signal sending circuit can be compatible with electrical interface standards in different driving modes, and the flexibility of the signal sending circuit is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a signal transmitting circuit, chip, and electronic device. Background Technology

[0002] In SerDes (Serializer-Deserializer), the signal transmission circuit of the SerDes transmitter (TX) typically only supports a single drive mode. Therefore, if other drive modes are required, the signal transmission circuit needs to be redesigned. Summary of the Invention

[0003] This application provides a signal transmitting circuit, chip, and electronic device that can support two driving modes.

[0004] In a first aspect, a signal transmitting circuit is provided, the signal transmitting circuit including a first signal driving circuit and a second signal driving circuit;

[0005] When the first signal driving circuit and the second signal driving circuit are disconnected, the first signal driving circuit is used to send the output differential signal in CML (Current Mode Logic) driving mode according to the first input differential signal, and the second signal driving circuit does not work.

[0006] When the first signal driving circuit and the second signal driving circuit are connected, the first signal driving circuit and the second signal driving circuit are used to send the output differential signal in LVDS (Low Voltage Differential Signaling) driving mode according to the first input differential signal.

[0007] In one possible implementation, the signal transmitting circuit further includes a first control circuit and a second control circuit; the first control circuit is used to control the input signal of the second signal driving circuit; the second control circuit is used to control the connection mode of the first signal driving circuit; when the input signal of the second signal driving circuit is a first level and the connection mode of the first signal driving circuit is a first connection mode, the first signal driving circuit is disconnected from the second signal driving circuit; when the input signal of the second signal driving circuit is the first input differential signal and the connection mode of the first signal driving circuit is a second connection mode, the first signal driving circuit is connected to the second signal driving circuit.

[0008] In one possible implementation, the first control circuit includes a signal generation circuit, a first switch, and a second switch; the signal generation circuit is used to generate a signal at the first level; the first switch is used to control the connection and disconnection of the signal terminals of the second signal driving circuit and the first input differential signal; the second switch is used to control the connection and disconnection of the second signal driving circuit and the signal generation circuit.

[0009] In one possible implementation, the first input differential signal includes a first input positive signal and a first input negative signal, the first signal driving circuit includes a first negative signal driving circuit and a first positive signal driving circuit, the first negative signal driving circuit is connected to the signal terminal of the first input negative signal, and the first positive signal driving circuit is connected to the signal terminal of the first input positive signal; the first connection method is that both the first negative signal driving circuit and the first positive signal driving circuit are connected to ground, and the second connection method is that the first negative signal driving circuit and the first positive signal driving circuit are connected to each other.

[0010] In one possible implementation, the first input differential signal includes a first input positive signal and a first input negative signal, the second signal driving circuit includes a second negative signal driving circuit and a second positive signal driving circuit, and the first switch includes a first sub-switch and a second sub-switch; the first sub-switch is used to control the connection and disconnection of the signal terminals of the second negative signal driving circuit and the first input negative signal; the second sub-switch is used to control the connection and disconnection of the signal terminals of the second positive signal driving circuit and the first input positive signal.

[0011] In one possible implementation, the signal transmitting circuit further includes a pre-emphasis circuit; the pre-emphasis circuit is used to amplify the high-frequency component of the output differential signal according to the second input differential signal to compensate for the attenuation of the high-frequency component during transmission, wherein the second input differential signal is a differential signal of the first input differential signal delayed by one clock cycle. In one possible implementation, the second input differential signal includes a second positive input signal and a second negative input signal, and the pre-emphasis circuit includes a negative signal pre-emphasis circuit and a positive signal pre-emphasis circuit, wherein the negative signal pre-emphasis circuit is connected to the signal terminal of the second negative input signal, and the positive signal pre-emphasis circuit is connected to the signal terminal of the second positive input signal.

[0012] In one possible implementation, the signal transmitting circuit further includes a voltage conversion circuit; the voltage conversion circuit is used to receive an initial differential signal, the voltage amplitude of which is less than a voltage threshold; and to perform voltage conversion on the initial differential signal to obtain a first input differential signal, the voltage amplitude of which is greater than or equal to the voltage threshold.

[0013] In one possible implementation, the initial differential signal includes an initial positive signal and an initial negative signal, the first input differential signal includes a first input positive signal and a first input negative signal, and the voltage conversion circuit includes a first conversion circuit and a second conversion circuit; the first conversion circuit is used to convert the initial positive signal into the first input positive signal; the second conversion circuit is used to convert the initial negative signal into the first input negative signal.

[0014] On the other hand, a chip is provided that includes the signal transmitting circuit as described in the preceding aspect.

[0015] In another aspect, an electronic device is provided, the electronic device including the signal transmitting circuit as described in the preceding aspect.

[0016] In summary, the beneficial effects of the technical solution provided in this application can include at least the following:

[0017] The signal transmission circuit provided in this application can flexibly switch between LVDS drive mode and CML drive mode by controlling the connection relationship between the first signal drive circuit and the second signal drive circuit. This enables the signal transmission circuit to be compatible with electrical interface standards under different drive modes, thereby enabling it to be compatible with application scenarios of different signal transmission protocols and improving the flexibility of the signal transmission circuit. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a signal transmitting circuit provided in an embodiment of this application;

[0020] Figure 2 This is a schematic diagram of another signal transmitting circuit provided in an embodiment of this application;

[0021] Figure 3 This is a schematic diagram of the structure of a first voltage conversion circuit provided in an embodiment of this application;

[0022] Figure 4 This is a schematic diagram of the structure of a second voltage conversion circuit provided in an embodiment of this application;

[0023] Figure 5 This is a schematic diagram of another signal transmitting circuit provided in an embodiment of this application;

[0024] Figure 6 This is a schematic diagram of another signal transmitting circuit provided in an embodiment of this application;

[0025] Figure 7 This is a schematic diagram of another signal transmitting circuit provided in an embodiment of this application;

[0026] Figure 8 This is a schematic diagram of another signal transmitting circuit provided in an embodiment of this application;

[0027] Figure 9 This is a schematic diagram of another signal transmitting circuit provided in an embodiment of this application;

[0028] Figure 10 This is a schematic diagram of another signal transmitting circuit provided in an embodiment of this application;

[0029] Figure 11 This is a schematic diagram of another signal transmitting circuit provided in an embodiment of this application;

[0030] Figure 12 This is a schematic diagram of another signal transmitting circuit provided in an embodiment of this application;

[0031] Figure 13 This is a schematic diagram of the structure of a third voltage conversion circuit and a fourth voltage conversion circuit provided in the embodiments of this application;

[0032] Figure 14 This is a schematic diagram of another signal transmitting circuit provided in an embodiment of this application;

[0033] Figure 15 This is a schematic diagram of another signal transmitting circuit provided in an embodiment of this application;

[0034] Figure 16 This is a schematic diagram of a CML driving mode provided in an embodiment of this application;

[0035] Figure 17 This is a schematic diagram of another CML driving mode provided in the embodiments of this application;

[0036] Figure 18 This is a schematic diagram of another CML driving mode provided in the embodiments of this application;

[0037] Figure 19 This is a waveform diagram of a CML driving mode provided in an embodiment of this application;

[0038] Figure 20 This is a schematic diagram of a driver in LVDS driver mode provided in an embodiment of this application;

[0039] Figure 21 This is a schematic diagram of another LVDS driving mode provided in an embodiment of this application;

[0040] Figure 22 This is a schematic diagram of another LVDS driving mode provided in an embodiment of this application;

[0041] Figure 23 This is a waveform diagram of an LVDS driving mode provided in an embodiment of this application. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0043] In high-speed serial communication systems, especially in applications such as big data centers, high-performance computing, high-definition video transmission, and remote communication, SerDes (Serializer-Deserializer) plays a crucial role. The serializer converts parallel data into serial data, while the deserializer converts serial data into parallel data. However, with the continuous increase in data transmission rates and transmission distances, the signal transmission circuitry of the SerDes transmitter (TX) faces numerous challenges in terms of signal integrity, power consumption, compatibility, and flexibility.

[0044] The SerDes TX signal transmission circuit, often simply referred to as the SerDes TX circuit, is primarily used to convert parallel data into high-speed serial signals and transmit them in differential form for transmission in high-speed serial communication links. For example, in high-speed communication systems such as high-speed Ethernet, fiber optic communication, and high-speed backplanes, the SerDes TX circuit can serialize multiple low-speed parallel data streams (typically from the chip's internal parallel bus) to achieve high-speed data transmission, overcoming problems such as difficult wiring, high crosstalk between signals, and complex synchronization inherent in parallel transmission.

[0045] The SerDes TX circuit's workflow includes: First, parallel data from various functional modules within the system (such as the processor and memory controller) enters the SerDes TX circuit's data encoding module through the parallel data input port. The data encoding module encodes the parallel data to ensure data reliability and clock synchronization performance. The encoded parallel data is then multiplexed bit-by-bit into serial data. The serial data passes through a pre-emphasis and equalization module to optimize the signal and reduce distortion during transmission. Finally, the optimized signal is amplified to the required power level by the driver circuit and transmitted through the electrical interface.

[0046] Pre-emphasis is a signal processing technique that compensates for high-frequency components of a signal at the transmitting end. Because high-frequency components attenuate faster than low-frequency components during transmission through media (such as printed circuit board traces, cables, etc.), signal distortion occurs. Pre-emphasis technology enhances the high-frequency portion of the signal at the transmitting end to compensate for the excessive attenuation of high-frequency components during transmission, ensuring that the receiving end receives a waveform closer to the original signal, thus improving signal integrity and transmission distance.

[0047] In related technologies, SerDes TX circuits typically support a single electrical interface standard, such as the LVDS interface standard. The electrical interface standard defines the physical connection method between devices and the electrical characteristics of the physical layer. These electrical characteristics include signal voltage range, current range, impedance matching, transmission rate, and distance limitations, to ensure interoperability and safety between devices.

[0048] The LVDS interface standard transmits data in the form of low-voltage differential signals, representing data through the voltage difference between two signal lines (positive and negative). It offers advantages such as low power consumption, low noise, and good anti-interference capabilities. Differential signals refer to two signals with equal amplitude but opposite polarity transmitted through two lines. The receiving end reconstructs the data by comparing the difference between the two signals. For example, when the voltage on the positive signal line is higher than the voltage on the negative signal line, it represents logic "1"; conversely, when the voltage on the positive signal line is lower than the voltage on the negative signal line, it represents logic "0".

[0049] However, with the development of communication technology and changes in application requirements, supporting only a single LVDS interface standard is no longer sufficient to meet the diverse needs of various scenarios. For example, in TCON (Timing Controller) applications that support P2P (point-to-point) transmission protocols, support for the P2P interface standard is also required; or, in long-distance transmission scenarios that support the VBO (Video by One) transmission protocol, support for the VBO interface standard is also required.

[0050] Different electrical interface standards differ in signal levels, driving methods, and transmission rates. For example, the LVDS interface standard uses the LVDS driving mode, resulting in relatively low drive current and power consumption. It operates within a rate range of 155 Mbps (megabits per second) to 1.25 Gbps (gigabits per second), making it suitable for medium to high-speed transmission. In contrast, the P2P or VBO interface standards use the CML driving mode, which has relatively high drive current and power consumption. However, it can operate stably within a rate range of 600 Mbps to 10 Gbps and above, exhibiting high noise immunity and making it suitable for even higher-speed transmission.

[0051] Therefore, if the SerDes TX circuit is to be compatible with multiple electrical interface standards such as P2P / LVDS / BVO, the SerDes TX circuit needs to support LVDS drive mode and CML drive mode.

[0052] This application provides a signal transmitting circuit that supports both LVDS driving mode and CML driving mode. See also... Figure 1 , Figure 1 This is a schematic diagram of a signal transmission circuit provided in an embodiment of the present application. The signal transmission circuit 00 includes a first signal driving circuit 11 and a second signal driving circuit 12.

[0053] When the first signal driving circuit 11 and the second signal driving circuit 12 are disconnected, the first signal driving circuit 11 is used to send the output differential signal in CML driving mode according to the first input differential signal, and the second signal driving circuit 12 does not work; when the first signal driving circuit 11 and the second signal driving circuit 12 are connected, the first signal driving circuit 11 and the second signal driving circuit 12 are used to send the output differential signal in LVDS driving mode according to the first input differential signal. The transmission frequency of the output differential signal in CML driving mode is greater than the transmission frequency of the output differential signal in LVDS driving mode.

[0054] In this embodiment, the first signal driving circuit 11 corresponds to the driving circuit in the CML driving mode, and the combination of the first signal driving circuit 11 and the second signal driving circuit 12 corresponds to the driving circuit in the LVDS driving mode. Therefore, this embodiment combines the two driving circuits corresponding to the two driving modes in the same signal transmitting circuit 00. By controlling the connection relationship between the first signal driving circuit 11 and the second signal driving circuit 12, the signal transmitting circuit 00 can flexibly switch between the two driving modes, thus flexibly adapting to electrical interface standards under different driving modes.

[0055] In one possible implementation, the signal transmitting circuit further includes a voltage conversion circuit 16; the voltage conversion circuit 16 is used to receive an initial differential signal, the voltage amplitude of which is less than a voltage threshold; and to perform voltage conversion on the initial differential signal to obtain a first input differential signal, the voltage amplitude of which is greater than or equal to the voltage threshold. The voltage threshold is the minimum voltage required to drive the first signal driving circuit 11 or the second signal driving circuit 12.

[0056] Optionally, the initial differential signal is the differential signal after parallel data is converted into serial data in the SerDes circuit. It belongs to the digital domain, and the voltage amplitude of the digital domain signal is relatively small, making it difficult to drive devices in subsequent signal driving circuits. In this embodiment, the voltage conversion circuit 16 converts the initial differential signal in the digital domain into a first input differential signal in the analog domain, where the voltage amplitude is larger. For example, the voltage range of the initial differential signal is 0-0.9V, and the voltage range of the first input differential signal is 0.45-1.35V. The differential signal in the digital domain can refer to a specific analog voltage output after the digital signal is input in binary form to a digital-to-analog converter (DAC).

[0057] Therefore, the voltage conversion circuit 16 enables the differential signals input to the first signal driving circuit 11 and the second signal driving circuit 12 to match their requirements. In this embodiment, the differential signal includes both a positive signal and a negative signal; the first input differential signal includes a first input positive signal and a first input negative signal; the output differential signal includes an output positive signal and an output negative signal; and the initial differential signal includes an initial positive signal and an initial negative signal.

[0058] Optionally, see Figure 2 The signal transmitting circuit 00 shown includes a voltage conversion circuit 16 comprising a first conversion circuit 161 and a second conversion circuit 162. The first conversion circuit 161 converts an initial positive signal into a first input positive signal; the second conversion circuit 162 converts an initial negative signal into a first input negative signal. Thus, voltage conversion of the two signals in the differential signal is achieved through two independent conversion circuits.

[0059] In one possible implementation, the first conversion circuit 161 includes a first capacitor and a first bias circuit. One end of the first capacitor is connected to a first signal terminal, and the other end of the first capacitor is connected to a second signal terminal through a first node. The first bias circuit is connected to the first node. The first bias circuit controls the voltage of the first node to be a first common-mode voltage. The first capacitor controls the second signal terminal to output a first input positive signal based on the initial positive signal input to the first signal terminal. The voltage range of the first input positive signal fluctuates around the first common-mode voltage.

[0060] In this embodiment, the floating distance of the first input positive signal is the same as the floating distance of the initial positive signal. For example, if the voltage range of the initial differential signal is 0-0.9V, and the initial differential signal floats around 0.45V with a floating distance of 0.45V; if the voltage range of the first input differential signal is 0.45-1.35V, and the first input differential signal floats around 0.9V with a floating distance of 0.45V, then the first common-mode voltage is 0.9V. The circuit structure of the second conversion circuit 162 can be referred to the circuit of the first conversion circuit 161, and will not be described again here.

[0061] Optionally, the first bias circuit may include a first bias impedance and a second bias impedance. One end of the first bias impedance is connected to the power supply terminal, and the other end is connected to the first node. One end of the second bias impedance is connected to ground, and the other end is connected to the first node. The voltage at the power supply terminal is set to twice the first common-mode voltage, for example, 1.8V. The first and second bias impedances are set to have equal impedance values, so that they produce the same voltage drop. Then, the voltage at the first node between the first and second bias impedances is half the voltage at the power supply terminal, i.e., the first common-mode voltage, for example, 0.9V.

[0062] The first and second bias impedances can be implemented using devices such as PMOS and NMOS transistors. A PMOS transistor is a P-type MOS transistor, operating on the principle that when the gate receives a high-level signal, the source and drain of the PMOS transistor are not conducting; when the gate receives a low-level signal, the source and drain of the PMOS transistor are conducting. An NMOS transistor is an N-type MOS transistor, operating on the principle that when the gate receives a high-level signal, the source and drain of the NMOS transistor are conducting; when the gate receives a low-level signal, the source and drain of the NMOS transistor are not conducting. MOS transistor is an abbreviation for MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), also known as a metal-oxide-semiconductor field-effect transistor or field-effect transistor.

[0063] For example, the circuit structure of the first conversion circuit 161 can be as follows: Figure 3 As shown, INP is the first signal terminal, used to input the initial positive signal, and OUTP is the second signal terminal, used to output the first input positive signal. VDD is the power supply terminal, VSS is the ground terminal, C1 is the first capacitor, and X1 is the first node. MN3 and MN4 are two NMOS transistors, and MP5 and MP6 are two PMOS transistors. MP5 and MN3, and MP6 and MN4 are respectively configured with corresponding bias voltages, for example... Figure 3 V2, V3, V4, and V5, etc. Bias voltage, also known as bias voltage or bias, refers to an additional DC voltage applied to a circuit to enable transistors or other active devices to operate in a specific region.

[0064] This results in MP5 and MN3 forming a first bias impedance, and MP6 and MN4 forming a second bias impedance. The first and second bias impedances are equal in magnitude, thus making X1 the quiescent operating point of the first common-mode voltage. Similarly, the circuit structure of the second conversion circuit 162 can be as follows: Figure 4 As shown, INN is the third signal terminal, used to input the initial negative signal; OUTN is the fourth signal terminal, used to output the first input negative signal.

[0065] In one possible implementation, see Figure 5 The signal transmitting circuit 00 further includes a first control circuit 13 and a second control circuit 14; the first control circuit 13 is used to control the input signal of the second signal driving circuit 12; the second control circuit 14 is used to control the connection mode of the first signal driving circuit 11; when the input signal of the second signal driving circuit 12 is a first level and the connection mode of the first signal driving circuit 11 is a first connection mode, the first signal driving circuit 11 is disconnected from the second signal driving circuit 12; when the input signal of the second signal driving circuit 12 is a first input differential signal and the connection mode of the first signal driving circuit 11 is a second connection mode, the first signal driving circuit 11 is connected to the second signal driving circuit 12.

[0066] This application does not limit the manner in which the first control circuit 13 controls the input signal of the second signal driving circuit 12. Optionally, see... Figure 6The first control circuit 13 includes a signal generation circuit 131, a first switch 132, and a second switch 133. The signal generation circuit 131 is used to generate a signal at a first level. The first switch 132 is used to control the connection and disconnection of the signal terminals of the second signal driving circuit 12 and the first input differential signal. The second switch 133 is used to control the connection and disconnection of the second signal driving circuit 12 and the signal generation circuit.

[0067] Since the first input differential signal includes a first input positive signal and a first input negative signal, and the output differential signal includes an output positive signal and an output negative signal, the first signal driving circuit 11 and the second signal driving circuit 12 also correspondingly include driving circuits for both positive and negative parts. For example... Figure 7 As shown, the first signal driving circuit 11 includes a first negative signal driving circuit 111 and a first positive signal driving circuit 112. The first negative signal driving circuit 111 is connected to the signal terminal of the first input negative signal, and the first positive signal driving circuit 112 is connected to the signal terminal of the first input positive signal. In this configuration, the first connection method is that both the first negative signal driving circuit 111 and the first positive signal driving circuit 112 are connected to ground, and the second connection method is that the first negative signal driving circuit 111 and the first positive signal driving circuit 112 are connected to each other. The second control circuit 14 is located between the first negative signal driving circuit 111 and the first positive signal driving circuit 112, and is connected to both the first negative signal driving circuit 111 and the first positive signal driving circuit 112.

[0068] For example, see Figure 8 The first negative signal driving circuit 111 includes a first transistor and a first impedance, and the first positive signal driving circuit 112 includes a second transistor and a second impedance. The gate of the first transistor receives a first negative input signal, the source of the first transistor is connected to a first positive current source, and the drain of the first transistor is connected to one end of the first impedance through a first output terminal, which is used to send an output positive signal. The gate of the second transistor receives the first positive input signal, the source of the second transistor is connected to the first positive current source, and the drain of the second transistor is connected to one end of the second impedance through a second output terminal, which is used to send an output negative signal. The second control circuit 14 is connected to the other end of the first impedance and the other end of the second impedance, respectively, to control the connection method between the first impedance and the second impedance. In this mode, the first connection method is that both the first impedance and the second impedance are connected to ground, and the second connection method is that the first impedance and the second impedance are connected to each other.

[0069] like Figure 9As shown, the second signal driving circuit 12 includes a second negative signal driving circuit 121 and a second positive signal driving circuit 122. The first switch 132 includes a first sub-switch 1321 and a second sub-switch 1322. The first sub-switch 1321 is used to control the connection and disconnection of the signal terminals of the second negative signal driving circuit and the first input negative signal. The second sub-switch 1322 is used to control the connection and disconnection of the signal terminals of the second positive signal driving circuit and the first input positive signal.

[0070] For example, see Figure 10 The first negative signal driving circuit 111 includes a third transistor, and the first positive signal driving circuit 112 includes a fourth transistor. The gate of the third transistor is connected to the first sub-switch 1321, the source of the third transistor is connected to the negative current source, and the drain of the third transistor is connected to the first output terminal. The gate of the fourth transistor is connected to the second sub-switch 1322, the source of the fourth transistor is connected to the negative current source, and the drain of the fourth transistor is connected to the second output terminal. Optionally, the second switch 133 may also include two sub-switches: one sub-switch controls the switching between the signal generation circuit 131 and the third transistor, and the other sub-switch controls the switching between the signal generation circuit 131 and the fourth transistor.

[0071] In this embodiment, the first and second transistors are turned on when the gate input signal is at a first level and turned off when the gate input signal is at a second level, while the third and fourth transistors are turned off when the gate input signal is at the first level. That is, the first and second transistors are of a different type than the third and fourth transistors. For example, the first and second transistors are PMOS transistors, while the third and fourth transistors are NMOS transistors.

[0072] For example, a schematic diagram of a signal transmitting circuit can be shown as follows: Figure 11 As shown in the diagram. The first transistor corresponds to MP1, the second transistor to MP2 (MP is short for PMOS transistor); the third transistor corresponds to MN1, the fourth transistor to MN2 (MN is short for NMOS transistor); the first impedance corresponds to RON1, the second impedance to RON2; the first output terminal corresponds to OUT_P, and the second output terminal corresponds to OUT_N. AVDD represents the analog voltage, for example, AVDD is 1.8V, and AVSS represents analog ground.

[0073] like Figure 11As shown, the second control circuit 14 includes four switches: SW5, SW6, SW7, and SW8. When SW5 and SW7 are closed and SW6 and SW8 are open, RON1 and RON2 are connected. When SW5 and SW7 are open and SW6 and SW8 are closed, both RON1 and RON2 are connected to AVSS. The first switch 132 includes two switches: SW3 and SW4. The second switch 133 includes two switches: SW1 and SW2. The signal generation circuit 131 includes two resistors, each connected to AVSS. The resistance values ​​of the two resistors can be equal, and both are used to generate a first-level (i.e., low-level) signal. When SW1 and SW2 are closed and SW3 and SW4 are open, the gate voltages of MN1 and MN2 remain low, and MN1 and MN2 remain in the off state. When SW1 and SW2 are open and SW3 and SW4 are closed, the gate input of MN1 is OUTN, and the gate input of MN2 is OUTP. MN1 and MN2 are then turned on or off according to the changes in OUTN and OUTP.

[0074] Taking an NMOS transistor as an example, the gate-source voltage (VGS) of an NMOS transistor needs to be greater than the threshold voltage (Vth) to form a conductive channel and turn the transistor on. The typical value of the threshold voltage for an NMOS transistor varies depending on the manufacturing process and device parameters. For instance, when a first negative input signal is applied to the gate of MN1, the gate drive voltage, OUTN, must be at least greater than the threshold voltage to turn on MN1. Therefore, the minimum voltage required to drive the first signal drive circuit 11 is the threshold voltage of the NMOS transistor in the first signal drive circuit 11, and the minimum voltage required to drive the second signal drive circuit 12 is the threshold voltage of the NMOS transistor in the second signal drive circuit 12.

[0075] In one possible implementation, see Figure 12 The signal transmission circuit also includes a pre-emphasis circuit 15; the pre-emphasis circuit 15 is used to increase the high-frequency component of the output differential signal according to the second input differential signal, so as to compensate for the attenuation of the high-frequency component during transmission. The second input differential signal is the differential signal of the first input differential signal delayed by one clock cycle.

[0076] Optionally, the signal transmitting circuit also includes Figure 12 The pre-emphasis circuit 15 and shown Figure 2 In the case of the voltage conversion circuit 16 shown, the voltage conversion circuit 16 is also used to receive the initial differential signal after a delay of one clock cycle; to perform voltage conversion on the initial differential signal after a delay of one clock cycle to obtain the second input differential signal, the voltage amplitude of the second input differential signal being greater than or equal to the voltage threshold, and the voltage threshold at this time being the minimum voltage for driving the pre-emphasis circuit 15.

[0077] Consistent with the aforementioned differential signal, the second input differential signal includes a second input positive signal and a second input negative signal. Optionally, in addition to the first conversion circuit 161 and the second conversion circuit 162, the voltage conversion circuit 16 also includes a third conversion circuit and a fourth conversion circuit. The third conversion circuit is used to convert the initial positive signal after a one-clock-cycle delay into the second input positive signal; the fourth conversion circuit is used to convert the initial negative signal after a one-clock-cycle delay into the second input negative signal.

[0078] The structures of the third and fourth conversion circuits are similar to those of the first conversion circuit 161 and the second conversion circuit 162 described above, and will not be repeated here. For example, the third conversion circuit can be as follows: Figure 13 As shown in (a), INP_EM is used to input the initial positive signal after a one-clock-cycle delay, and OUTP_EM is used to output the second input positive signal. The fourth conversion circuit can be as follows: Figure 13 As shown in (b), INN_EM is used to input the initial negative signal after a one-clock-cycle delay; OUTN_EM is used to output the second input negative signal.

[0079] In one possible implementation, the pre-emphasis circuit 15 includes a negative signal pre-emphasis circuit and a positive signal pre-emphasis circuit. The negative signal pre-emphasis circuit is connected to the signal terminal of the second input negative signal, and the positive signal pre-emphasis circuit is connected to the signal terminal of the second input positive signal. Exemplarily, the negative signal pre-emphasis circuit includes a fifth transistor, and the positive signal pre-emphasis circuit includes a sixth transistor. The gate of the fifth transistor receives the second input positive signal, the source of the fifth transistor is connected to a second positive current source, and the drain of the fifth transistor is connected to a first output terminal, which is used to send an output positive signal with increased high-frequency components. The gate of the sixth transistor receives the second input negative signal, the source of the sixth transistor is connected to a second positive current source, and the drain of the sixth transistor is connected to a second output terminal, which is used to send an output negative signal with increased high-frequency components.

[0080] For example, in Figure 11 Based on the first signal driving circuit 11 and the second signal driving circuit 12 shown, the circuit structure after adding the pre-emphasis circuit 15 is as follows: Figure 14 As shown in the diagram. The fifth transistor corresponds to MP3, and the sixth transistor corresponds to MP4.

[0081] In the embodiments of this application, Figure 14 The function of switch SW in the circuit can be implemented using a transistor. In this case, such as... Figure 15As shown, SW3 and SW4 can be implemented by two transistors connected in parallel, where both the gate and source of the transistors are biased with voltages to enable the two transistors to function as switches. SW1 and SW2 can be implemented by a single transistor, achieving the switching function by applying corresponding bias voltages to the gate and source of the transistor.

[0082] Optionally, the gates of MP3 and MP4 are also connected to SW9 and SW10, which control whether the pre-emphasis circuit 15 operates. Figure 15 As shown, SW9 and SW10 can be implemented by a single transistor with a bias voltage applied. The magnitude of the bias voltage applied in this embodiment is not limited, as long as it enables the corresponding switching function. The applied bias voltage may be the same or different when implementing different switching functions.

[0083] by Figure 15 Taking the schematic diagram of the signal driving circuit shown as an example, the working mode of the signal driving circuit provided in this application embodiment is illustrated. In the CML driving mode, the first stage is as follows: Figure 16 As shown, MP2, MP3, SW1, SW2, SW6, and SW8 are on, while MP1, MP4, MN1, MN2, SW3, SW4, SW5, and SW7 are off. The current flow path is as follows. Figure 16 As shown by the dashed line, the output voltage of the first stage, V(OUT_P-OUT_N), is therefore I_EME*RON1-I_MAIN*RON2. Here, I_MAIN is the current value of the first positive current source, I_EME is the current value of the second positive current source, and RON1 and RON2 are impedance matching values.

[0084] When a signal is transmitted from one circuit section to another, impedance matching is required to achieve maximum power transmission or reduce signal reflection. Taking the transmission of high-speed digital signals in PCB (Printed Circuit Board) traces as an example, if the characteristic impedance of the PCB trace is designed to be 100Ω, and the input impedance of the connected chip is also 100Ω, then impedance matching is achieved. The signal can be effectively transmitted from the trace to the chip, reducing signal distortion and interference caused by reflection.

[0085] The second stage, as follows Figure 17 As shown, MP1, MP3, SW1, SW2, SW6, and SW8 are on, while MP2, MP4, MN1, MN2, SW3, SW4, SW5, and SW7 are off. The current flow path is as follows. Figure 17 As shown by the dashed line, the output voltage of the second stage is V(OUT_P-OUT_N) = I_MAIN*RON1 + I_EME*RON1. The third stage is as follows... Figure 18As shown, MP1, MP4, SW1, SW2, SW6, and SW8 are on, while MP2, MP3, MN1, MN2, SW3, SW4, SW5, and SW7 are off. The current flow path is as follows. Figure 18 As shown by the dashed line, the output voltage of the third stage is V(OUT_P-OUT_N)=I_MAIN*RON1-I_EME*RON2.

[0086] For example, Figure 19 This is a waveform diagram of the output differential signal sent in CML drive mode. Figure 19 The upper part shows the output differential signal in CML drive mode. The thin curve represents the positive output signal in the output differential signal, and the thick curve represents the negative output signal in the output differential signal. Figure 19 The lower half shows the output signal obtained based on the output differential signal conversion, where the output signal is the difference between the positive and negative output signals. For example, using... Figure 19 Taking the first stage as an example, the voltage value of the output positive signal is about 0.8 volts, the voltage value of the output negative signal is about 0.5 volts, and the voltage value of the output signal is about 0.3 volts.

[0087] In this embodiment, the pre-emphasis circuit enhances the signal by adjusting the drive current. Specifically, for a high-speed digital signal to be transmitted, additional drive current is added at the rising and falling edges of the signal (i.e., the parts where high-frequency components are concentrated), thereby enhancing the signal amplitude. For example, when transmitting a high-speed pulse sequence, the amplitude of the pulse is normally fixed, but in pre-emphasis mode, the amplitude of the rising and falling edges of each pulse is higher than that in the middle part.

[0088] In LVDS driver mode, the first stage is as follows: Figure 20 As shown, MP2, MP3, MN1, SW3, SW4, SW5, and SW7 are on, while MP1, MP4, MN2, SW1, SW2, SW6, and SW8 are off. Therefore, the output voltage of the first stage is V(OUT_P - OUT_N) = -I_MAIN * (RON1 + RON2). The second stage is as follows... Figure 21 As shown, MP1, MP3, MN2, SW3, SW4, SW5, and SW7 are on, while MP2, MP4, MN1, MN1, SW1, SW2, SW6, and SW8 are off. Therefore, the output voltage of the second stage is V(OUT_P - OUT_N) = (I_MAIN + I_EME) * (RON1 + RON2). The third stage is as follows... Figure 22As shown, MP1, MP4, MN2, SW3, SW4, SW5, and SW7 are turned on, while MP2, MP3, MN1, SW1, SW2, SW6, and SW8 are turned off. Therefore, V(OUT_P-OUT_N)=(I_MAIN)*(RON1+RON2).

[0089] Figure 23 This is a waveform diagram of the output differential signal sent in LVDS drive mode. Figure 23 The upper part shows the output differential signal in LVDS drive mode. The thin curve represents the positive output signal in the output differential signal, and the thick curve represents the negative output signal in the output differential signal. Figure 23 The lower half shows the output signal obtained based on the output differential signal conversion, where the output signal is the difference between the positive and negative output signals. For example, using... Figure 23 Taking the first stage as an example, the voltage value of the output positive signal is about 1 volt, the voltage value of the output negative signal is about 1.4 volts, and the voltage value of the output signal is about -0.4 volts.

[0090] For example, the signal transmission circuit provided in this application embodiment can be a SerDes TX circuit. In summary, the SerDes TX circuits in related technologies rely on a single electrical interface, failing to fully utilize the convenience of the P2P interface, the low-power advantage of the LVDS interface, and the electrical characteristics of the VBO interface. To address these technical bottlenecks, this application embodiment provides a SerDes TX circuit that not only is compatible with P2P / LVDS interfaces to ensure low power consumption and stable data transmission, but also integrates adaptability to VBO electrical characteristics, achieving seamless switching capabilities between different scenarios. Furthermore, through architectural adjustments and a unique voltage conversion design, an optimal area solution is achieved, thus ensuring compatibility with most transmission protocol application scenarios on the market.

[0091] This application provides a chip that includes any of the signal transmission circuits shown above. This enables the chip to support switching between LVDS and CML drive modes, thereby ensuring compatibility with electrical interface standards under different drive modes.

[0092] Optionally, the chip can be an interface chip, such as a High Definition Multimedia Interface (HDMI) chip, a DisplayPort (DP) chip, or a Mobile Industry Processor Interface (MIPI) chip.

[0093] This application provides an electronic device that includes any of the signal transmitting circuits shown above. Optionally, the electronic device includes the chip shown above, and the chip includes any of the signal transmitting circuits shown above.

[0094] It should be understood that the terminology used in the embodiments of this disclosure is for the purpose of explaining the embodiments of this disclosure only and is not intended to limit this disclosure. Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should be understood in their ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0095] For example, the terms “first,” “second,” or “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0096] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0097] The word “includes” or similar terms means that the elements or objects preceding “includes” or “include” cover the elements or objects listed after “includes” or “include” or their equivalents, and do not exclude other elements or objects.

[0098] Terms like "up," "down," "left," or "right" are used only to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. "Connection" or "coupled" refers to an electrical connection.

[0099] The "and / or" signifies that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0100] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the gate drive circuit, shift register unit, each circuit and each sub-circuit described above can be referred to the corresponding processes in the method embodiments, and will not be repeated here.

[0101] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A signal transmitting circuit, characterized in that, The signal transmitting circuit includes a first signal driving circuit and a second signal driving circuit. When the first signal driving circuit and the second signal driving circuit are disconnected, the first signal driving circuit is used to send the output differential signal in the current mode logic CML driving mode according to the first input differential signal, and the second signal driving circuit does not work. When the first signal driving circuit and the second signal driving circuit are connected, the first signal driving circuit and the second signal driving circuit are used to send the output differential signal in the low voltage differential signal LVDS driving mode according to the first input differential signal. The signal transmitting circuit further includes a first control circuit and a second control circuit; the first control circuit is used to control the input signal of the second signal driving circuit; the second control circuit is used to control the connection mode of the first signal driving circuit. When the input signal of the second signal driving circuit is at the first level and the connection method of the first signal driving circuit is the first connection method, the first signal driving circuit is disconnected from the second signal driving circuit. When the input signal of the second signal driving circuit is the first input differential signal, and the connection method of the first signal driving circuit is the second connection method, the first signal driving circuit and the second signal driving circuit are connected.

2. The signal transmitting circuit according to claim 1, characterized in that, The first control circuit includes a signal generation circuit, a first switch, and a second switch; The signal generation circuit is used to generate a signal of the first level; The first switch is used to control the connection and disconnection of the signal terminals of the second signal driving circuit and the first input differential signal; The second switch is used to control the connection and disconnection of the second signal driving circuit and the signal generation circuit.

3. The signal transmitting circuit according to claim 1, characterized in that, The first input differential signal includes a first input positive signal and a first input negative signal. The first signal driving circuit includes a first negative signal driving circuit and a first positive signal driving circuit. The first negative signal driving circuit is connected to the signal terminal of the first input negative signal, and the first positive signal driving circuit is connected to the signal terminal of the first input positive signal. The first connection method is that both the first negative signal driving circuit and the first positive signal driving circuit are connected to the ground terminal, and the second connection method is that the first negative signal driving circuit and the first positive signal driving circuit are connected to each other.

4. The signal transmitting circuit according to claim 2, characterized in that, The first input differential signal includes a first input positive signal and a first input negative signal; the second signal driving circuit includes a second negative signal driving circuit and a second positive signal driving circuit; and the first switch includes a first sub-switch and a second sub-switch. The first sub-switch is used to control the connection and disconnection of the signal terminal of the second negative signal driving circuit and the first input negative signal; The second sub-switch is used to control the connection and disconnection of the signal terminal of the second positive signal driving circuit and the first input positive signal.

5. The signal transmitting circuit according to any one of claims 1-4, characterized in that, The signal transmitting circuit also includes a pre-emphasis circuit; The pre-emphasis circuit is used to increase the high-frequency component of the output differential signal according to the second input differential signal to compensate for the attenuation of the high-frequency component during transmission. The second input differential signal is the differential signal of the first input differential signal delayed by one clock cycle.

6. The signal transmitting circuit according to claim 5, characterized in that, The second input differential signal includes a second input positive signal and a second input negative signal. The pre-emphasis circuit includes a negative signal pre-emphasis circuit and a positive signal pre-emphasis circuit. The negative signal pre-emphasis circuit is connected to the signal terminal of the second input negative signal, and the positive signal pre-emphasis circuit is connected to the signal terminal of the second input positive signal.

7. The signal transmitting circuit according to any one of claims 1-4, characterized in that, The signal transmitting circuit also includes a voltage conversion circuit; The voltage conversion circuit is used to receive an initial differential signal, the voltage amplitude of which is less than a voltage threshold; and to perform voltage conversion on the initial differential signal to obtain a first input differential signal, the voltage amplitude of which is greater than or equal to the voltage threshold.

8. The signal transmitting circuit according to claim 7, characterized in that, The initial differential signal includes an initial positive signal and an initial negative signal, the first input differential signal includes a first input positive signal and a first input negative signal, and the voltage conversion circuit includes a first conversion circuit and a second conversion circuit; The first conversion circuit is used to convert the initial positive signal into the first input positive signal; The second conversion circuit is used to convert the initial negative signal into the first input negative signal.

9. A chip, characterized in that, The chip includes the signal transmission circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, The electronic device includes a signal transmitting circuit as described in any one of claims 1 to 8.

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