Display panel

Abstract

This invention discloses a display panel, comprising: a substrate; multiple conductive layers stacked on one side of the substrate, the multiple conductive layers including a first conductive layer and a second conductive layer; an active layer located on the side of the second conductive layer away from the substrate; the active layer and the multiple conductive layers constituting at least one light-emitting control circuit, the light-emitting control circuit including a first output module, the first output module including a first transistor and a first capacitor, the first electrode of the first capacitor located on the first conductive layer, the second electrode of the first capacitor located on the second conductive layer; the first gate of the first transistor located on the second conductive layer, the second electrode of the first capacitor connected to the first gate of the first transistor; the ratio of the area of ​​the first capacitor to a second area being between 0.2 and 1.0; the second area being the area overlapping the orthographic projection of the active layer on the substrate and the orthographic projection of the first gate of the first transistor on the substrate. The display panel of this invention can solve the problem of unstable light-emitting control signals.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to display panels. Background Technology

[0002] With the development of display technology, medium and large-sized display panels have broad application prospects in automotive, tablet, laptop, and television fields. Display panels typically include a light-emitting control circuit to provide light-emitting control signals to the pixel circuits. This light-emitting control circuit usually includes pull-up and pull-down modules to output the light-emitting control signals.

[0003] The light emission control signals in existing medium and large-sized display panels are unstable, which affects the display effect. Summary of the Invention

[0004] This invention provides a display panel to solve the problem of unstable light emission control signals in existing display panels.

[0005] According to one aspect of the present invention, a display panel is provided, characterized in that it comprises:

[0006] Substrate;

[0007] A multilayer conductive layer is stacked on one side of the substrate, the multilayer conductive layer including a first conductive layer and a second conductive layer, the second conductive layer being located on the side of the first conductive layer away from the substrate;

[0008] An active layer is located on the side of the second conductive layer away from the substrate;

[0009] The active layer and the multilayer conductive layers constitute at least one light-emitting control circuit. The light-emitting control circuit includes a first output module. The first output module includes a first transistor and a first capacitor. The first electrode of the first capacitor is located on the first conductive layer, and the second electrode of the first capacitor is located on the second conductive layer.

[0010] The first gate of the first transistor is located in the second conductive layer, and the second plate of the first capacitor is connected to the first gate of the first transistor.

[0011] The ratio of the first area to the second area is between 0.2 and 1.0; wherein, the first area is the area where the orthographic projection of the first electrode plate of the first capacitor on the substrate overlaps with the orthographic projection of the second electrode plate of the first capacitor on the substrate, and the second area is the area where the orthographic projection of the active layer on the substrate overlaps with the orthographic projection of the first gate of the first transistor on the substrate.

[0012] In the technical solution of this invention, the light-emitting control circuit includes a first transistor for outputting a first potential and a first capacitor connected to the first gate of the first transistor. By setting the area of ​​the first capacitor and the area overlapping the orthographic projection of the active layer on the substrate and the orthographic projection of the first gate of the first transistor on the substrate within a reasonable range, that is, by defining the size ratio of the first capacitor to the first transistor, the first capacitor raises the potential of the first gate through coupling, thereby improving the driving capability of the first transistor. At the same time, the size of the first capacitor is limited to avoid the first capacitor being too large and easily coupled by other signals, which would affect the potential of the first gate of the first transistor and thus affect the first potential of the output light-emitting control signal. Therefore, in this application, by setting the size ratio of the first capacitor and the first transistor within a reasonable range, the influence of coupling on the output light-emitting control signal is suppressed, while the driving capability of the output level is maintained, making the output light-emitting control signal more stable and reliable.

[0013] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present invention;

[0016] Figure 2 A cross-sectional view of a display panel provided in an embodiment of the present invention;

[0017] Figure 3 A plan view of a first transistor provided in an embodiment of the present invention;

[0018] Figure 4 This is a schematic diagram of a light-emitting control circuit provided in an embodiment of the present invention;

[0019] Figure 5 A plan view of another display panel provided in an embodiment of the present invention;

[0020] Figure 6 This is a partial enlarged view of a display panel provided in an embodiment of the present invention;

[0021] Figure 7A plan view of a first conductive layer, a second conductive layer, and an active layer in a display panel provided in an embodiment of the present invention;

[0022] Figure 8 A planar schematic diagram of a second conductive layer, an active layer, and a third conductive layer in a display panel provided in an embodiment of the present invention;

[0023] Figure 9 A planar schematic diagram of a fourth transistor in a display panel provided in an embodiment of the present invention;

[0024] Figure 10 A cross-sectional view of another display panel provided in an embodiment of the present invention;

[0025] Figure 11 This is a signal waveform diagram of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0026] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] Figure 1 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a cross-sectional view of a display panel provided in an embodiment of the present invention. Figure 2 For along Figure 1 Cross-sectional view of AA' (see reference) Figure 1 and Figure 2 The display panel includes:

[0029] Substrate 10;

[0030] A multilayer conductive layer is stacked on one side of a substrate. The multilayer conductive layer includes a first conductive layer 11 and a second conductive layer 12, with the second conductive layer 12 located on the side of the first conductive layer 11 away from the substrate 10.

[0031] Active layer 13 is located on the side of the second conductive layer 12 away from the substrate;

[0032] The active layer 13 and the multilayer conductive layers constitute at least one light-emitting control circuit. The light-emitting control circuit includes a first output module. The first output module includes a first transistor T1 and a first capacitor C1. The first electrode 101 of the first capacitor C1 is located in the first conductive layer 11, and the second electrode 102 of the first capacitor C1 is located in the second conductive layer 12.

[0033] The first gate of the first transistor T1 is located on the second conductive layer 12, and the second plate 102 of the first capacitor C1 is connected to the first gate of the first transistor T1.

[0034] The ratio of the first area to the second area is between 0.2 and 1.0. The first area is the area where the orthographic projections of the first electrode 101 of the first capacitor C1 on the substrate 10 overlap with the orthographic projections of the second electrode 102 of the first capacitor C1 on the substrate 10. The second area is the area where the orthographic projection of the first active layer on the substrate 10 overlaps with the orthographic projection of the first gate of the first transistor T1 on the substrate 10. The channel region of the first transistor T1 is located in the active layer, and the second area can be considered as the area of ​​the channel region of the first transistor T1.

[0035] Specifically, the substrate 10 serves to provide protection and support for the display panel. The substrate 10 can be a flexible substrate formed of materials such as polyimide (PI), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET), or a rigid substrate formed of materials such as glass. Multiple conductive layers are disposed on one side of the substrate 10, and these conductive layers are isolated from each other by insulating layers. Multiple light-emitting control circuits and pixel circuits are formed in the display panel. The pixel circuits respond to the light-emitting control signal during the light-emitting phase, transmitting driving current to the light-emitting element to drive it to emit light. The light-emitting control circuits provide the light-emitting control signal to the pixel circuits. The light-emitting control circuit includes a first output module for outputting a first potential and a second output module for outputting a second potential. The first potential and the second potential are high and low potentials respectively, with the first potential being high and the second potential being low. Optionally, the first terminal of the first transistor T1 is connected to the first potential, and the second terminal of the first transistor T1 is connected to the output terminal OUT of the light-emitting control circuit. The first transistor T1 includes a first gate and a second gate. The first gate can be a bottom gate and the second gate can be a top gate, or the first gate can be a top gate and the second gate can be a bottom gate. In this embodiment, the first gate is a bottom gate and the second gate is a top gate. The first transistor T1 is used to transmit a first potential to the output terminal OUT of the light-emitting control circuit in response to the potential of the second gate. The first gate G11 of the first transistor T1 is connected to the first capacitor C1.

[0036] The first gate G11 of the first transistor T1 is connected to the second plate 102 of the first capacitor C1. The first gate and the second plate 102 are located on the same layer and can be connected by the thirty-sixth connection line L36 located on the second conductive layer 12.

[0037] The orthographic projection of the first plate 101 of the first capacitor C1 onto the substrate 10 at least partially overlaps with the orthographic projection of the second plate 102 of the first capacitor C1 onto the substrate 10. The overlapping area constitutes the effective capacitance of the first capacitor C1. Optionally, if the orthographic projection of the first plate 101 of the first capacitor C1 onto the substrate 10 covers the orthographic projection of the second plate 102 of the first capacitor C1 onto the substrate 10, then the area of ​​the first capacitor C1 is equal to the area of ​​the second plate 102 of the first capacitor C1. Optionally, the material of the active layer 13 includes metal oxide, which is beneficial for reducing the leakage current of the light-emitting control circuit.

[0038] Setting the ratio of the area of ​​the first capacitor C1 to the area of ​​the channel region of the first transistor T1 within a reasonable range can balance suppressing the coupling effect on the output light-emitting control signal of the light-emitting control circuit and maintaining the driving capability of the first transistor T1, ensuring a more stable and reliable output light-emitting control signal. Specifically, if the ratio of the area of ​​the first capacitor C1 to the area of ​​the channel region of the first transistor T1 is too large, the area of ​​the first capacitor C1 will be too large, resulting in strong coupling. This makes the first capacitor C1 highly susceptible to potential changes in the potential of the first gate G11 of the first transistor T1 due to the potential changes of other signals. Under the effect of the parasitic capacitance of the first transistor T1, this in turn affects the potential of the second terminal of the first transistor T1. Since the second terminal of the first transistor T1 is connected to the output terminal OUT, this affects the potential of the output light-emitting control signal, leading to instability and large waveform fluctuations in the light-emitting control signal. If the ratio of the area of ​​the first capacitor C1 to the channel area of ​​the first transistor T1 is too small, the coupling effect of the first capacitor C1 is weak, and the degree to which the potential of the first plate 101 is raised by the potential change of the second plate 102 of the first capacitor C1 is small. This results in a smaller rise in the potential of the first gate of the first transistor T1, thus reducing the driving capability of the first transistor T1. Therefore, the ratio of the area of ​​the first capacitor C1 to the channel area of ​​the first transistor T1 is set between 0.2 and 1.0, such as 0.4, 0.6, or 0.8. Preferably, the ratio of the area of ​​the first capacitor C1 to the channel area of ​​the first transistor T1 is set to 0.6, which, while ensuring a high driving capability of the first transistor T1, also reduces the influence of coupling from other signals on the output light-emitting control signal.

[0039] In the technical solution of this invention, the light-emitting control circuit includes a first transistor for outputting a first potential and a first capacitor connected to the first gate of the first transistor. By setting the area of ​​the first capacitor and the area overlapping the orthographic projection of the active layer on the substrate and the orthographic projection of the first gate of the first transistor on the substrate within a reasonable range, that is, by defining the size ratio of the first capacitor to the first transistor, the first capacitor raises the potential of the first gate through coupling, thereby improving the driving capability of the first transistor. At the same time, the size of the first capacitor is limited to avoid the first capacitor being too large and easily coupled by other signals, which would affect the potential of the first gate of the first transistor and thus affect the first potential of the output light-emitting control signal. Therefore, in this application, by setting the size ratio of the first capacitor and the first transistor within a reasonable range, the influence of coupling on the output light-emitting control signal is suppressed, while the driving capability of the output level is maintained, making the output light-emitting control signal more stable and reliable.

[0040] Continue to refer to Figure 1 and Figure 2Optionally, the first transistor T1 is used to transmit the first potential VGH to the output terminal OUT of the light-emitting control circuit;

[0041] The multilayer conductive layer also includes a third conductive layer and a fourth conductive layer 15. The third conductive layer is located on the side of the active layer 13 away from the substrate, and the fourth conductive layer 15 is located on the side of the third conductive layer away from the substrate 10. The fourth conductive layer includes a first clock signal line ECK1 for transmitting a first clock signal and a second power supply line for transmitting a second potential, the second potential being lower than the first potential. The first clock signal line ECK1 and the second power supply line both extend along the second direction Y and along the first direction X, with the first clock signal line ECK1 and the second power supply line located on both sides of the first transistor, respectively.

[0042] The first output module also includes a second transistor T2. The first terminal of the second transistor T2 is connected to the second power supply line. The second terminal of the second transistor T2 is connected to the second plate of the first capacitor C1 through the first connection line L1 located in the fourth conductive layer. The gate of the second transistor T2 is connected to the first clock signal line ECK1 in sequence through the second connection line L2 located in the fourth conductive layer, the third connection line L3 located in the second conductive layer, and the fourth connection line L4 located in the second conductive layer.

[0043] The display panel includes a first type of via 1 and a second type of via 2. The first type of via 1 is a via that penetrates from the fourth conductive layer 15 to the active layer 13 or from the fourth conductive layer 15 to the third conductive layer. The second type of via 2 is a via that penetrates from the fourth conductive layer 15 to the first conductive layer 11 or the second conductive layer 12. The first and second terminals of the second transistor T2 are both located in the fourth conductive layer. The source and drain regions of the second transistor T2 are both located in the active layer 13. The first terminal (source) of the second transistor T2 is connected to the source region of the second transistor T2 through the first type of via 1 that penetrates from the fourth conductive layer 15 to the active layer 13, and the second terminal (drain) of the second transistor T2 is connected to the drain region of the second transistor T2 through the first type of via 1 that penetrates from the fourth conductive layer 15 to the active layer 13. In the following text, the first and second terminals of each transistor are connected to the corresponding source and drain regions in the active layer through the first type of via 1 described above, which will not be repeated here. The first electrode of the second transistor T2 is connected to the second power supply line, which can be achieved through at least one connection line located in the fourth conductive layer 15. When the second electrode of the second transistor T2 is connected to the second plate of the first capacitor C1 through the first connection line L1 located in the fourth conductive layer, specifically, one end of the second electrode of the second transistor T2 overlaps with one end of the first connection line L1. Since both the second electrode of the second transistor T2 and the first connection line L1 are located in the fourth metal layer 15, the connection can be achieved through this overlap. The other end of the first connection line L1 is connected to the second plate 102 of the first capacitor C1 through a second type of via 2 extending from the fourth conductive layer 15 to the second conductive layer 12, thus connecting the second plate 102 of the first capacitor C1 to the first connection line L1.

[0044] The second transistor T2 can be a dual-gate transistor, including a top gate and a bottom gate. The bottom gate of the second transistor T2 is located in the second conductive layer 12, and the top gate of the second transistor T2 is located in the third conductive layer 14. The top gate and bottom gate of the second transistor T2 are connected through vias. All transistors mentioned below, except for the fourth transistor and the first transistor, are also dual-gate transistors as described for the second transistor T2, with gate structures similar to those of the second transistor T2, and will not be described again later. In an optional embodiment, the connection between the top gate and bottom gate of the second transistor T1 can be achieved by connecting both the bottom gate and top gate of the second transistor T2 to the same structure in the fourth conductive layer through vias, thereby achieving the connection between the top gate and bottom gate. Specifically, the bottom gate of the second transistor T2 is connected to the forty-fourth connection line L44 located in the fourth conductive layer 15 through a second-type via 2 penetrating from the fourth conductive layer 15 to the second conductive layer 12, and the top gate of the second transistor T2 is connected to the forty-fourth connection line L44 through a first-type via 1 penetrating from the fourth conductive layer 15 to the third conductive layer 14. The forty-fourth connection line L44 overlaps with one end of the second connection line L2. The other end of the second connection line L2 is connected to one end of the third connection line L3 through a second type via 2 that passes through the fourth conductive layer 15 to the second conductive layer 12. The other end of the third connection line L3 is overlapped with one end of the fourth connection line L4 through a trace on the same layer as the third connection line L3. The other end of the fourth connection line L4 is connected to the first clock signal line ECK1 through a second type via 2 that passes through the fourth conductive layer 15 to the second conductive layer 12.

[0045] The second potential is lower than the low level of the high and low levels output by the light emission control signal. The gate of the second transistor T2 is connected to the first clock signal, which is a pulse signal that alternately outputs high and low levels. After the second transistor T2 turns on in response to the high level of the first clock signal, it transmits the second potential to the first gate of the first transistor T1 to adjust the threshold voltage of the first transistor T1, so that the threshold voltage of the first transistor T1 is greater than zero. Thus, when the gate-source difference of the first transistor T1 is 0, the first transistor T1 can be completely turned off, and the off-state current of the first transistor T1 is suppressed.

[0046] Figure 3 A plan view of a first transistor provided in an embodiment of the present invention, with reference to... Figure 1 , Figure 2 and Figure 3 Optionally, the light-emitting control circuit further includes a first output control module, which is connected to the second gate of the first transistor T1. The first output control module is used to control the potential of the second gate of the first transistor T1, and the first transistor T1 turns on or off in response to the potential of its own second gate.

[0047] The second gate of the first transistor T1 is located on the third conductive layer 14, and the first gate and the second gate of the first transistor T1 are insulated from each other. The orthogonal projection of the first gate of the first transistor T1 on the substrate 10 at least partially overlaps with the orthogonal projection of the second gate of the first transistor T1 on the substrate, so that the threshold voltage of the first transistor T1 can be adjusted by the potential of the first gate. Preferably, the orthogonal projection of the first gate of the first transistor T1 on the substrate covers the orthogonal projection of the second gate of the first transistor T1 on the substrate.

[0048] Continue to refer to Figure 1 , Figure 2 and Figure 3 Optionally, the first transistor and all transistors mentioned below include an active region located in the active layer. The active region includes a channel region, a source region, and a drain region. The orthographic projections of the top gate and bottom gate of the first transistor and any of the transistors mentioned below onto the substrate at least partially overlap with the orthographic projection of the channel region of the transistor onto the substrate. For any transistor, the orthographic projection of the top gate of the transistor onto the substrate at least partially overlaps with the orthographic projection of the active region of the transistor onto the substrate, and the overlap forms a channel region. The active regions located at both ends of the channel region form a source region and a drain region. The active layer includes the active region of the first transistor, and the active region of the first transistor includes at least two source and drain portions extending along a first direction X. The at least two source and drain portions are arranged along a second direction Y, and along the second direction Y, each source and drain portion is spaced apart to prevent excessive current flowing through the first transistor during operation from breaking down the active layer.

[0049] Furthermore, the first gate and the second gate of the first transistor T1 each include a first sub-section, a second sub-section and a third sub-section connected in sequence. The first sub-section and the third sub-section extend along the first direction X, and the second sub-section extends along the second direction Y. The first sub-section and the third sub-section are arranged along the second direction Y. The first direction X and the second direction Y intersect. The third sub-section 123 of the first gate of the first transistor T1 is connected to the second plate 102 of the first capacitor C1.

[0050] The first sub-section 121, the second sub-section 122, and the third sub-section 123 of the first gate of the first transistor T1 are sequentially connected to form a U-shaped structure, with the first sub-section 121 and the third sub-section 123 of the first gate of the first transistor T1 being parallel. Similarly, the first sub-section 141, the second sub-section 142, and the third sub-section 143 of the second gate of the first transistor T1 are sequentially connected to form a U-shaped structure, with the first sub-section 141 and the third sub-section 143 of the second gate of the first transistor T1 being parallel. The third sub-section 123 of the first gate of the first transistor T1 and the second plate 102 of the first capacitor C1 are located on the same layer, both on the second conductive layer 12. Therefore, they can be connected via traces on the second conductive layer 12, thereby connecting the first gate of the first transistor T1 to the second plate 102 of the first capacitor C1.

[0051] The fourth conductive layer includes a first power line VGH for transmitting a first potential, and also includes a first source / drain portion 151, a second source / drain portion 152, and a third source / drain portion 153, all extending along a first direction X, and a fourth source / drain portion 154 extending along a second direction Y. The first source / drain portion 151, the second source / drain portion 152, and the third source / drain portion 153 are arranged sequentially along the second direction Y. Both the first sub-part 121 of the first gate of the first transistor T1 and the first sub-part 141 of the second gate are located between the first source / drain portion 151 and the second source / drain portion 152. Both the third sub-part 123 of the first gate of the first transistor T1 and the third sub-part 143 of the second gate are located between the second source / drain portion 152 and the third source / drain portion 153. The first source / drain portion 151 and the third source / drain portion 153 are connected to the fourth source / drain portion 154. The second source / drain portion 152 is connected to the first power line VGH through a fifth connection line L5 located in the fourth conductive layer.

[0052] In this embodiment, the first transistor T1 can be composed of two transistors connected in parallel. The first source-drain portion 151, the first sub-portion, and the second source-drain portion 152 constitute one transistor, and the second source-drain portion 152, the third sub-portion, and the third source-drain portion 153 constitute another transistor. The second source-drain portion 152 serves as the first terminal (source) of the first transistor T1 and is connected to the first power supply line VGH via the fifth connection line L5. The first source-drain portion 151 and the third source-drain portion 153 serve as the second terminal (drain) of the first transistor T1 and are connected to the output terminal OUT of the light-emitting control circuit. The fourth source-drain portion 154 can serve as the output terminal OUT of the light-emitting control circuit.

[0053] Continue to refer to Figure 1 , Figure 2 and Figure 3Optionally, the orthographic projection of the first sub-portion 121 of the first gate of the first transistor T1 onto the substrate covers the orthographic projection of the first sub-portion 141 of the second gate of the first transistor T1 onto the substrate, the orthographic projection of the second sub-portion 122 of the first gate of the first transistor T1 onto the substrate covers the orthographic projection of the second sub-portion 142 of the second gate of the first transistor T1 onto the substrate, and the orthographic projection of the third sub-portion 123 of the first gate of the first transistor T1 onto the substrate covers the orthographic projection of the third sub-portion 143 of the second gate of the first transistor T1 onto the substrate. The orthographic projection of the first gate of the first transistor T1 onto the substrate at least covers the orthographic projection of the second gate onto the substrate, allowing for better adjustment of the threshold voltage of the first transistor T1 by adjusting the potential of the first gate. Furthermore, the length of the first sub-portion 121 of the first gate of the first transistor T1 along the first direction X exceeds the length of the first sub-portion 141 of the second gate of the first transistor T1 along the first direction X by a first preset length a1, and / or, the length of the first sub-portion 121 of the first gate of the first transistor T1 along the second direction Y exceeds the length of the first sub-portion 141 of the second gate of the first transistor T1 along the second direction Y by a second preset length, and / or, the length of the second sub-portion 122 of the first gate of the first transistor T1 along the first direction X exceeds the length of the second sub-portion 142 of the second gate of the first transistor T1 along the first direction X by a third preset length. The length of the second sub-section 122 of the first gate of the first transistor T1 along the second direction Y exceeds the length of the second sub-section 142 of the second gate of the first transistor T1 along the second direction Y by a fourth preset length, and / or the length of the third sub-section 123 of the first gate of the first transistor T1 along the first direction X exceeds the length of the third sub-section 143 of the second gate of the first transistor T1 along the first direction X by a fifth preset length, and / or the length of the third sub-section 123 of the first gate of the first transistor T1 along the second direction Y exceeds the length of the third sub-section 143 of the second gate of the first transistor T1 along the second direction Y by a sixth preset length.

[0054] Preferably, the length of each sub-section of the first gate of the first transistor is greater than the length of the corresponding sub-section of the second gate, whether along the first direction X or the second direction Y, so as to ensure that the orthogonal projection of the first gate of the first transistor T1 on the substrate completely covers the orthogonal projection of the second gate of the first transistor T1 on the substrate. Figure 3The first preset length a1 is exemplarily shown; other preset lengths can be referenced from the first preset length and are not shown again. Optionally, along the first direction X, the lengths of the first sub-part 121 and the third sub-part 123 of the first gate of the first transistor T1 are equal; along the second direction Y, the lengths of the first sub-part 121 and the third sub-part 123 of the first gate of the first transistor T1 are equal; along the first direction X, the lengths of the first sub-part 141 and the third sub-part 143 of the second gate of the first transistor T1 are equal; along the second direction Y, the lengths of the first sub-part 141 and the third sub-part 143 of the second gate of the first transistor T1 are equal. Optionally, the first preset length, the second preset length, the third preset length, the fourth preset length, the fifth preset length, and the sixth preset length are all greater than or equal to 1 micrometer and less than or equal to 3 micrometers; preferably, the first preset length to the sixth preset length are all equal to 2 micrometers. Optionally, the length of the first sub-section 121 of the first gate of the first transistor T1 along the first direction X is greater than the length of the first sub-section 121 of the first gate along the second direction Y, and the length of the first sub-section 141 of the second gate of the first transistor T1 along the first direction X is greater than the length of the first sub-section 141 of the second gate along the second direction Y. Here, the second direction Y is the direction of the source-drain connection of the first transistor T1, which is also the direction of the channel length of the first transistor T1; the first direction X is the direction of the channel width of the first transistor T1; the width-to-length ratio of the first transistor T1 is equal to the ratio of the channel width to the channel length; the channel width of the first transistor T1 is equal to the sum of the length of the first sub-section 141 of the second gate along the first direction X and the length of the third sub-section 143 of the second gate along the first direction X; and the channel length of the first transistor T1 is equal to the length of either the first sub-section 141 or the third sub-section 143 of the second gate along the second direction Y. Regarding the second gate of the first transistor T1, the length of its first sub-section 141 along the first direction X is much greater than the length of its first sub-section 141 along the second direction Y, resulting in a large width-to-length ratio of the first transistor T1, which in turn causes the scan lines transmitting the light emission control signal in the display panel to change rapidly.

[0055] Figure 4 This is a schematic diagram of a light-emitting control circuit provided in an embodiment of the present invention, with reference to... Figure 4Optionally, the light-emitting control circuit includes a first output module 3, a second output module 4, a first output control module, and a second output control module 5. The second output control module 5 is connected to the control terminal of the second output module 4 and is used to control the potential of the control terminal of the second output module 4. The first output control module includes a forward transmission unit 6 and a gate control unit 7. The output terminal N2 of the forward transmission unit 6 is directly or indirectly connected to the second gate of the first transistor T1 and is used to transmit a start signal SIN to the second gate of the first transistor T1. The gate control unit 7 is connected to the second gate of the first transistor T1 and includes a second capacitor C2, which is used to raise the potential of the second gate of the first transistor T1 through the coupling effect of the second capacitor C2.

[0056] Optionally, the gate control unit 7 further includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14. The first terminal of the eleventh transistor T11 is connected to the second gate of the first transistor T1, and the second terminal of the eleventh transistor T11 is connected to the second plate of the second capacitor C2. The second terminal of the eleventh transistor T11 is also connected to its gate. The first terminal of the tenth transistor T10 is connected to the second clock signal line ECK2, which transmits the second clock signal, and the second terminal of the tenth transistor T10 is connected to the first plate of the second capacitor C2. The first terminal of the fourteenth transistor T14 is connected to the third power supply line VGL, and the gate of the fourteenth transistor T14 is connected to the control terminal of the second output module 4. The second terminals of transistor T12 are connected to the second terminal of transistor T10 and the first plate of capacitor C2, respectively. The first terminal of transistor T12 is connected to the start signal line SIN for transmitting the start signal, and the second terminal is connected to the first terminal of transistor T13. The gate of transistor T12 is connected to the first clock signal line ECK1 for transmitting the first clock signal. The second terminal of transistor T13 is connected to the gate and second terminal of transistor T11, and the second plate of capacitor C2, respectively. The gate of transistor T13 is connected to the first power supply line. The first terminal of transistor T9 is connected to the output terminal N2 of forward transmission unit 6. The second terminal of transistor T9 is connected to the second gate of transistor T1, and the gate of transistor T9 is connected to the first power supply line VGH. The structures of other modules are as follows: Figure 4 As shown, no further details will be provided.

[0057] Figure 5 This is a plan view of another display panel provided in an embodiment of the present invention. Figure 6 This is a partial enlarged view of a display panel provided in an embodiment of the present invention, wherein, Figure 6 To Figure 5 A magnified view of region 8 in the middle. Figure 7 This is a plan view of a display panel containing a first conductive layer, a second conductive layer, and an active layer, provided by an embodiment of the present invention. Figure 8 This is a planar schematic diagram of a second conductive layer, an active layer, and a third conductive layer in a display panel according to an embodiment of the present invention. Figure 9 This is a planar schematic diagram of a fourth transistor in a display panel according to an embodiment of the present invention, with reference to... Figures 4-9 Optionally, the first plate of the second capacitor C2 is located in the first conductive layer, and the second plate of the second capacitor C2 is located in the second conductive layer.

[0058] The difference between the area of ​​the second capacitor C2 and the area of ​​the first capacitor is less than a preset threshold; wherein, the area of ​​the second capacitor C2 is the area of ​​the overlapping part of the orthographic projection of the first plate of the second capacitor C2 on the substrate and the orthographic projection of the second plate of the second capacitor C2 on the substrate.

[0059] To save layout space, this embodiment exemplarily shows the orthogonal projection of the first plate of the second capacitor C2 onto the substrate, covering the orthogonal projection of the second plate of the second capacitor C2 onto the substrate, to ensure that the area of ​​the second capacitor C2 is larger. When the first clock signal transitions from a low potential to a high potential, the second capacitor C2, through its own coupling, raises the potential of the second gate of the first transistor T1 via the eleventh transistor T11, thereby enhancing the driving capability of the first transistor T1. The larger the area of ​​the second capacitor C2, the more beneficial it is to enhancing the driving capability of the first transistor T1. Therefore, the function of the second capacitor C2 is the same as that of the first capacitor C1, both used to enhance the driving capability of the first transistor T1. The difference between the area of ​​the second capacitor C2 and the area of ​​the first capacitor C1 is less than a preset threshold to ensure that the area of ​​the second capacitor C2 is similar to that of the first capacitor C1. In an optional embodiment, the area of ​​the second capacitor C2 is the same as that of the first capacitor C1.

[0060] The first output module 3 also includes a third transistor T3. The fourth conductive layer includes a second clock signal line ECK2 for transmitting a second clock signal. The first terminal of the third transistor T3 is connected to the second clock signal line ECK2 via a sixth connection line L6 located on the fourth conductive layer and a seventh connection line L7 located on the first conductive layer. Specifically, the first terminal of the third transistor T3 is located on the fourth conductive layer and is directly connected to one end of the sixth connection line L6. The other end of the sixth connection line L6 is connected to one end of the seventh connection line L7 via a second-type via 2 penetrating from the fourth conductive layer to the first conductive layer. The other end of the seventh connection line L7 is connected to the second clock signal line ECK2 via a second-type via 2 penetrating from the fourth conductive layer to the first conductive layer, thereby realizing the connection between the first terminal of the third transistor T3 and the second clock signal line ECK2. The second electrode of the third transistor T3 is connected to the first plate of the first capacitor C1 through a second-type via 2 penetrating from the fourth conductive layer to the first conductive layer. The gate of the third transistor T3 is connected to the output terminal N2 of the forward transmission unit sequentially through the eighth connection line L8 located in the fourth conductive layer, the thirty-seventh connection line L37 located in the second conductive layer, and the ninth connection line L9 located in the second conductive layer. Specifically, the gate of the third transistor T3 is directly connected to one end of the eighth connection line L8, the other end of the eighth connection line L8 is connected to the thirty-seventh connection line L37 through the second-type via 2 penetrating from the fourth conductive layer to the second conductive layer, the thirty-seventh connection line L37 is connected to one end of the ninth connection line L9, and the other end of the ninth connection line L9 is connected to the output terminal N2 of the forward transmission unit 6. (Referring to...) Figure 4 In the circuit shown, the gate of the seventh transistor T7 serves as the output terminal N2 of the forward transmission unit 6.

[0061] Continue to refer to Figures 4-9 Optionally, the light-emitting control circuit also includes a second output module 4, which includes a fourth transistor T4. The fourth transistor T4 is used to output a third potential to the output terminal OUT of the light-emitting control circuit. The third potential is greater than the second potential, and the first potential is greater than the third potential.

[0062] The first gate of the fourth transistor T4 is located on the second conductive layer, and is connected to the second power supply line VGLL via the thirty-eighth connection line L38. Specifically, one end of the first gate of the fourth transistor T4 is connected to the thirty-eighth connection line L38, and the other end of the thirty-eighth connection line L38 is connected to the second power supply line VGLL via a second type of via 2 that extends from the fourth conductive layer to the second conductive layer, thus enabling the first gate of the fourth transistor T4 to be connected to the second potential. The fourth transistor T4 also includes a second gate, which is located on the third conductive layer. The first and second gates of the fourth transistor T4 are insulated from each other. The first gate of the fourth transistor T4 is connected to the second potential to regulate the threshold voltage of the fourth transistor T4, making its threshold voltage positively biased and greater than zero. This ensures that when the potential of the second gate of the fourth transistor T4 is low, the fourth transistor T4 can be completely turned off.

[0063] Optionally, the active layer includes a fourth transistor active region, which includes at least two source / drain portions extending along a first direction X. These at least two source / drain portions are arranged along a second direction Y, and are spaced apart to prevent excessive current flowing through the fourth transistor during operation from damaging the active layer. At least one source / drain portion of the fourth transistor active region is shared with at least one source / drain portion of the first transistor active region, such that at least a portion of the drain region of the fourth transistor active region is shared with at least a portion of the drain region of the first transistor active region.

[0064] The first and second gates of the fourth transistor T4 each include a fourth sub-section, a fifth sub-section, a sixth sub-section, and a seventh sub-section. The fourth, fifth, and sixth sub-sections extend along a first direction X, and the seventh sub-section extends along a second direction Y. The fourth, fifth, and sixth sub-sections are arranged sequentially along the second direction Y, and each of the fourth, fifth, and sixth sub-sections is connected to the seventh sub-section. Any two of the fourth sub-sections 124, 125, and 126 of the first gate of the fourth transistor T4 are parallel to each other, and each of the sub-sections 124 to 126 directly overlaps with the seventh sub-section 127 of the first gate of the fourth transistor T4. Similarly, any two of the fourth sub-sections 144, 145, and 146 of the second gate of the fourth transistor T4 are parallel to each other, and each of the sub-sections 144 to 146 directly overlaps with the seventh sub-section 147 of the second gate of the fourth transistor T4. The fourth sub-section 124 of the first gate of the fourth transistor T4 is connected to the second power supply line VGLL via the thirty-eighth connection line L38, thereby enabling the first gate of the fourth transistor T4 to be connected to the second potential. The sixth sub-section 126 of the first gate of the fourth transistor T4 is located on the side of the fifth sub-section 125 of the first gate of the fourth transistor T4 that is close to the first sub-section 121 of the first gate of the first transistor T1, and the sixth sub-section 146 of the second gate of the fourth transistor T4 is located on the side of the fifth sub-section 145 of the second gate of the fourth transistor T4 that is close to the first sub-section 141 of the second gate of the first transistor T1.

[0065] The fourth conductive layer includes a fifth source / drain portion 155, a sixth source / drain portion 156, a seventh source / drain portion 157, and an eighth source / drain portion 158 arranged sequentially along the second direction Y, and a ninth source / drain portion 159 and a tenth source / drain portion 1510 extending along the second direction Y. The fifth source / drain portion 155, the sixth source / drain portion 156, the seventh source / drain portion 157, and the eighth source / drain portion 158 are all located between the extension lines of the ninth source / drain portion 159 along the second direction Y and the extension lines of the tenth source / drain portion 1510 along the second direction Y. The fifth source / drain portion 155 and the seventh source / drain portion 157 are both connected to the ninth source / drain portion 159, and the sixth source / drain portion 156 and the eighth source / drain portion 158 are both connected to the tenth source / drain portion 1510. Any two of the fifth source / drain portions 155, the sixth source / drain portion 156, the seventh source / drain portion 157, and the eighth source / drain portion 158 are parallel to each other.

[0066] Both the fourth sub-section 124 of the first gate and the fourth sub-section 144 of the second gate of the fourth transistor T4 are located between the fifth source / drain section 155 and the sixth source / drain section 156. Similarly, both the fifth sub-section 125 of the first gate and the fifth sub-section 145 of the second gate of the fourth transistor T4 are located between the sixth source / drain section 156 and the seventh source / drain section 157. Furthermore, both the sixth sub-section 126 of the first gate and the sixth sub-section 146 of the second gate of the fourth transistor T4 are located between the seventh source / drain section 157 and the eighth source / drain section 158. The fourth transistor T4 can be considered as being composed of three transistors connected in parallel. Specifically, the fifth source / drain section 155, the fourth sub-section, and the sixth source / drain section 156 constitute one transistor; the sixth source / drain section 156, the fifth sub-section, and the seventh source / drain section 157 constitute one transistor; and the seventh source / drain section 157, the sixth sub-section, and the eighth source / drain section 158 constitute one transistor.

[0067] The fourth conductive layer also includes a third power line VGL for transmitting a third potential. The third power line VGL is connected to the seventh source / drain portion 157 via a tenth connection line L10 located in the first conductive layer. Specifically, the third power line VGL is connected to one end of the tenth connection line L10 via a second-type via 2 penetrating from the fourth conductive layer to the first conductive layer. The other end of the tenth connection line L10 is connected to the seventh source / drain portion 157 via a second-type via 2 penetrating from the fourth conductive layer to the first conductive layer. That is, either the fifth source / drain portion 155 or the seventh source / drain portion 157 serves as the first electrode of the fourth transistor T4 connected to the third potential. The tenth source / drain portion 1510 is connected to the output terminal OUT of the light-emitting control circuit. The sixth source / drain portion 156 or the eighth source / drain portion 158 can serve as the second electrode of the fourth transistor T4 connected to the output terminal OUT of the light-emitting control circuit. Figure 3 The first source-drain part 151 in the middle can be reused as the eighth source-drain part 158.

[0068] Optionally, the length of the fourth sub-portion 124 of the first gate of the fourth transistor T4 along the first direction X exceeds the length of the fourth sub-portion 144 of the second gate of the fourth transistor T4 along the first direction X by a first preset length, and / or, the length of the fourth sub-portion 124 of the first gate of the fourth transistor T4 along the second direction Y exceeds the length of the fourth sub-portion 144 of the second gate of the fourth transistor T4 along the second direction Y by a second preset length, and / or, the length of the fifth sub-portion 125 of the first gate of the fourth transistor T4 along the first direction X exceeds the length of the fifth sub-portion 145 of the second gate of the fourth transistor T4 along the first direction X by a third preset length. And / or, the length of the fifth sub-section 125 of the first gate of the fourth transistor T4 along the second direction Y exceeds the length of the fifth sub-section 145 of the second gate of the fourth transistor T4 along the second direction Y by a fourth preset length, and / or, the length of the sixth sub-section 126 of the first gate of the fourth transistor T4 along the first direction X exceeds the length of the sixth sub-section 146 of the second gate of the fourth transistor T4 along the first direction X by a fifth preset length, and / or, the length of the sixth sub-section 126 of the first gate of the fourth transistor T4 along the second direction Y exceeds the length of the sixth sub-section 146 of the second gate of the fourth transistor T4 along the second direction Y by a sixth preset length.

[0069] Each sub-section of the first gate of the fourth transistor T4 has a length greater than the length of the corresponding sub-section of the second gate, both along the first direction X and the second direction Y, to ensure that the orthographic projection of the first gate of the fourth transistor T4 on the substrate completely covers the orthographic projection of the second gate of the fourth transistor T4 on the substrate. Optionally, along the first direction X, the lengths of the fourth sub-sections 124, 125, and 126 of the first gate of the fourth transistor T4 are equal, and along the second direction Y, the lengths of the fourth sub-sections 124, 125, and 126 of the first gate of the fourth transistor T4 are equal. Similarly, along the first direction X, the lengths of the fourth sub-sections 144, 145, and 146 of the second gate of the fourth transistor T4 are equal, and along the second direction Y, the lengths of the fourth sub-sections 144, 145, and 146 of the second gate of the fourth transistor T4 are equal. Optionally, the first preset length, second preset length, third preset length, fourth preset length, fifth preset length, and sixth preset length are all greater than or equal to 1 micrometer and less than or equal to 3 micrometers. Preferably, the first preset length to the sixth preset length are all equal to 2 micrometers. Optionally, the length of any sub-section of the fourth transistor T4 along the first direction X is greater than the length along the second direction Y. The second direction Y is the direction of the source-drain connection of the fourth transistor T4, which is also the direction of the channel length of the fourth transistor T4. The first direction X is the direction of the channel width of the fourth transistor T4. The width-to-length ratio of the fourth transistor T4 is equal to the ratio of the channel width to the channel length. The channel width of the fourth transistor T4 is equal to the sum of the lengths of the fourth sub-section 144, the fifth sub-section 145, and the sixth sub-section 146 of its second gate along the first direction X. The channel length of the fourth transistor T4 is equal to the length of the fourth sub-section 144, the fifth sub-section 145, or the sixth sub-section 146 of its second gate along the second direction Y. The length of the fourth sub-part 144 along the first direction X is much greater than its length along the second direction Y, resulting in a larger width-to-length ratio of the fourth transistor T4. This, in turn, allows the scan lines transmitting the light-emitting control signals in the display panel to switch faster, ensuring the normal display of the display panel.

[0070] Optionally, the second output module 4 also includes a third capacitor C3, the first plate of the third capacitor C3 being located on the first conductive layer, and the second plate of the third capacitor C3 being located on the second conductive layer.

[0071] The first plate of the third capacitor C3 is connected to the ninth source / drain portion 159 via the eleventh connecting line L11 located on the fourth conductive layer. Specifically, the first plate of the third capacitor C3 is connected to one end of the eleventh connecting line L11 via a second-type via 2 penetrating from the fourth conductive layer to the first conductive layer, and the other end of the eleventh connecting line L11 is directly connected to the ninth source / drain portion 159, thereby connecting the first plate of the third capacitor C3 to the first electrode of the fourth transistor T4 via the ninth source / drain portion 159. The second plate of the third capacitor C2 is connected to the fourth sub-section 144 of the second gate of the fourth transistor T4 via the twelfth connecting line L12 located on the third conductive layer. Specifically, the second plate of the third capacitor C3 is first connected to the forty-fifth connecting line located on the fourth conductive layer via a via penetrating from the fourth conductive layer to the second conductive layer, and the forty-fifth connecting line is then connected to the twelfth connecting line L12 via a first-type via penetrating from the fourth conductive layer to the third conductive layer, thereby connecting the second plate of the third capacitor to the twelfth connecting line L12. The twelfth connecting line L12 connects to the fourth sub-section 144 of the second gate of the fourth transistor T4, thus finally connecting the second plate of the third capacitor C3 to the second gate of the fourth transistor T4.

[0072] Optionally, the area of ​​the third capacitor C3 is smaller than the area of ​​the first capacitor C1. The area of ​​the third capacitor C3 is the overlapping area of ​​the orthographic projection of the first plate of the third capacitor C3 onto the substrate and the orthographic projection of the second plate of the third capacitor C3 onto the substrate. To save layout area, in this embodiment, the orthographic projection of the first plate of the third capacitor C3 onto the substrate covers the orthographic projection of the second plate of the third capacitor C3 onto the substrate, that is, the area of ​​the third capacitor C3 is equal to the area of ​​the second plate of the third capacitor C3. The third capacitor C3 is only used to store the potential of the second gate of the fourth transistor T4, therefore, its area does not need to be too large to save layout space. Optionally, the ratio of the area of ​​the third capacitor C3 to the area of ​​the first capacitor C1 is greater than or equal to 0.4 and less than or equal to 0.6, preferably 0.5.

[0073] In this embodiment, the first terminal of the second transistor T2 is connected to the seventh sub-section 127 of the first gate of the fourth transistor T4 via the thirteenth connection line L13 located in the second conductive layer. Specifically, the first terminal of the second transistor T2 is connected to one end of the thirteenth connection line L13 via a second type of via 2 extending from the fourth conductive layer to the second conductive layer, and the other end of the thirteenth connection line L13 overlaps with the seventh sub-section 127 of the first gate of the fourth transistor T4, thereby enabling the first terminal of the second transistor T2 to be connected to the second power line through the seventh sub-section 127 and the fourth sub-section 124 of the first gate of the fourth transistor T4.

[0074] Continue to refer to Figures 4-9Optionally, the light-emitting control circuit also includes a second output control module 5, which is used to transmit an inverted signal of the start signal to the second gate of the fourth transistor T4.

[0075] The second output control module includes a fifth transistor T5 and a fourth capacitor C4. The first plate of the fourth capacitor C4 is located on the first conductive layer, and the second plate of the fourth capacitor T4 is located on the second conductive layer. The first plate of the fourth capacitor C4 is connected to the gate of the fifth transistor T5. Specifically, the first plate of the fourth capacitor C4 is connected to the thirty-ninth connection line L39 located on the first conductive layer. The thirty-ninth connection line L39 is connected to one end of the fortieth connection line L40 located on the fourth conductive layer through a second type of via 2 that passes through the fourth conductive layer to the first conductive layer. The fortieth connection line L40 is then connected to the gate of the fifth transistor T5 through a via, thus achieving the connection between the first plate of the fourth capacitor C4 and the gate of the fifth transistor T5. The second plate of the fourth capacitor C4 is connected to the first clock signal line ECK1 in sequence through the third connection line L3 and the fourth connection line L4. Specifically, the second plate of the fourth capacitor C4 is connected to the third connection line L3. The third connection line L3 is connected to the fourth connection line L4 through the gates of the subsequent eighth transistor T8 and twelfth transistor T12. The fourth connection line L4 is connected to the first clock signal line ECK1 through a second type of via 2 that extends from the fourth conductive layer to the second conductive layer, thus enabling the second plate of the fourth capacitor C4 to be connected to the first clock signal.

[0076] The first terminal of the fifth transistor T5 is connected to one end of the seventeenth connection line L17 located on the second conductive layer through a second type of via 2. The other end of the seventeenth connection line L17 is connected to the second plate of the fourth capacitor C4, thereby realizing the connection between the first terminal of the fifth transistor T5 and the second plate of the fourth capacitor C4 through the seventeenth connection line L17 located on the second conductive layer. The second terminal of the fifth transistor T5 is connected to the fourth sub-section 144 of the second gate of the fourth transistor T4 in sequence through the fourteenth connection line L14, the fifteenth connection line L15, the sixteenth connection line L16, and the twelfth connection line L12 located on the fourth conductive layer. Specifically, the second terminal of the fifth transistor T5 is connected to one end of the fourteenth connection line L14, the other end of the fourteenth connection line L14 is connected to one end of the fifteenth connection line L15, the other end of the fifteenth connection line L15 is connected to one end of the sixteenth connection line L16, and the other end of the sixteenth connection line L16 is connected to the twelfth connection line L12 through a first-type via 1 that extends from the fourth conductive layer to the third conductive layer, thus ultimately connecting the second terminal of the fifth transistor T5 to the second gate of the fourth transistor T4. In this embodiment, the twelfth connection line L12 is connected to the gate of the fourteenth transistor T14 (described later), and the sixteenth connection line L16 is connected to the twelfth connection line L12 through the gate of the fourteenth transistor T14.

[0077] The area of ​​the fourth capacitor C4 is smaller than that of the first capacitor, i.e., smaller than that of the first capacitor C1. The area of ​​the fourth capacitor C4 is the overlapping area of ​​the orthographic projection of its first plate onto the substrate and the orthographic projection of its second plate onto the substrate. To save layout area, the orthographic projection of the first plate of the fourth capacitor C4 onto the substrate covers the orthographic projection of its second plate onto the substrate; therefore, the area of ​​the fourth capacitor C4 is the area of ​​its second plate. The fifth transistor T5 does not need to have the same strong driving capability as the first transistor T1. Therefore, to save layout area, the area of ​​the fourth capacitor C4 can be set to be smaller than that of the first capacitor C1 to reduce layout space. Optionally, the ratio of the area of ​​the fourth capacitor C4 to the area of ​​the first capacitor is greater than or equal to 0.5 and less than or equal to 0.7. If the area of ​​the fourth capacitor C4 is too large, the charging and discharging amount of the first clock signal to it will be large, resulting in increased power consumption. If the area of ​​the fourth capacitor C4 is too small, when the first clock signal transitions to a high level, the weak coupling capability of the fourth capacitor C4 results in a low gate potential of the raised fifth transistor T5, leading to weak driving capability of the fifth transistor T5 and insufficient low-level driving capability of the output signal. Therefore, the area of ​​the fourth capacitor C4 needs to be set within a reasonable range to balance layout size and driving capability. Preferably, the ratio of the area of ​​the fourth capacitor C4 to the area of ​​the first capacitor is equal to 0.6.

[0078] Continue to refer to Figures 4-9Optionally, the fourth conductive layer includes a start signal line EIN for transmitting a start signal. The second output control module 5 also includes a sixth transistor T6. The first electrode of the sixth transistor T6 is connected to the first plate of the third capacitor C3 via the eighteenth connection line L18 located on the fourth conductive layer and the forty-first connection line L41 located on the first conductive layer. Specifically, the first electrode of the sixth transistor T6 is connected to one end of the eighteenth connection line L18, and the other end of the eighteenth connection line L18 is connected to one end of the forty-first connection line L41 via a second type of via 2 that extends from the fourth conductive layer to the first conductive layer. The other end of the forty-first connection line L41 is connected to the first plate of the third capacitor C3, thus achieving the connection of the first electrode of the sixth transistor T6 to the third power line VGL via the first plate of the third capacitor C3. The second terminal of the sixth transistor T6 is connected to the first plate of the fourth capacitor C4 via the nineteenth connection line L19 located on the fourth conductive layer and the forty-second connection line L42 located on the first conductive layer. Specifically, one end of the second terminal of the sixth transistor T6 is connected to the nineteenth connection line L19, and the other end of the nineteenth connection line L19 is connected to the forty-second connection line L42 through a second type of via 2 that runs from the fourth conductive layer to the first conductive layer. The forty-second connection line L42 is then connected to the first plate of the fourth capacitor C4, thus connecting the second terminal of the fourth transistor T4 to the first plate of the fourth capacitor C4 and the gate of the fifth transistor T5. The gate of the sixth transistor T6 is connected to the start signal line EIN via the twentieth connection line L20 located on the fourth conductive layer. Specifically, the sixth transistor T6 is a dual-gate transistor. The bottom gate is located on the second conductive layer and is connected to the twentieth connection line L20 through a via. The top gate is located on the third conductive layer and is connected to the twentieth connection line L20 through a via. The twentieth connection line L20 is connected to the start signal line EIN, thereby enabling the gate of the sixth transistor T6 to be connected to the start signal.

[0079] The channel regions of the fifth transistor T5, the sixth transistor T6, the second transistor T2, and the third transistor T3 are all located in the active layer. The channel length of the sixth transistor T6 is greater than the channel length of each of the fifth transistor T5, the second transistor T2, and the third transistor T3. The channel lengths of the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are all in the second direction Y, while the channel length of the third transistor T3 is in the first direction X. The channel length is the direction of the connection between the first and second terminals of the transistor, i.e., the source and drain. Since all transistors in this embodiment are dual-gate transistors, the channel length can be considered as the length of the overlapping portion of the orthogonal projection of the active layer on the substrate and the orthogonal projection of the top gate of the transistor on the substrate along the direction of the connection between the source and drain. The channel length is positively correlated with the threshold voltage of the transistor. A larger channel length will cause the threshold voltage of the transistor to be positively biased, ensuring that the sixth transistor T6 can be completely turned off. This prevents the leakage current from affecting the gate potential of the fifth transistor T5 when the sixth transistor T6 cannot be completely turned off, thus preventing the fifth transistor T5 from being turned off when it is supposed to be on. Under the influence of the unrelated current, the coupling effect of the fourth capacitor C4 is strong. When the first clock signal is high, the coupling effect of the fourth capacitor C4 raises the gate potential of the fifth transistor T5, causing the fifth transistor T5 to turn on fully. This rapidly transmits the high level of the first clock signal to the gate of the fourth transistor T4, controlling the fourth transistor T4 to turn on. This results in the output signal being low, enhancing the drop-down speed of the output signal of the light-emitting control circuit. Optionally, the channel length of the sixth transistor T6 is greater than or equal to 6 micrometers and less than or equal to 8 micrometers, preferably 7 micrometers.

[0080] Continue to refer to Figures 4-9 Optionally, the second output control module 5 also includes a seventh transistor T7, the forward transmission unit 6 includes an eighth transistor T8, and the gate control unit 7 includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14.

[0081] The first terminal of the seventh transistor T7 is connected to the first plate of the third capacitor C3 via the eighteenth connecting line L18 and the forty-first connecting line L41. The first plate is then connected to the seventh source-drain section 157 via the eleventh connecting line L11 and the ninth source-drain section 159. The seventh source-drain section 157 is connected to the third power supply line VGL, thus connecting the first terminal of the seventh transistor T7 to the third potential. The second terminal of the seventh transistor T7 is connected to the fourth sub-section 144 of the second gate of the fourth transistor T4 via the fifteenth connecting line L15, the sixteenth connecting line L16, and the twelfth connecting line L12, thus connecting the second terminal of the seventh transistor T7 to the second gate of the fourth transistor T4. The gate of the seventh transistor T7 is connected to the gate of the third transistor T3 via the ninth connecting line L9 and the eighth connecting line L8.

[0082] The first terminal of the eighth transistor T8 is connected to the start signal line EIN via the twenty-first connection line L21 located on the fourth conductive layer. The twenty-first connection line L21 connects to both the first terminal of the eighth transistor T8 and the start signal line EIN, thereby enabling the first terminal of the eighth transistor T8 to receive the start signal. The second terminal of the eighth transistor T8 is connected to the gate of the seventh transistor T7 via the twenty-second connection line L22, the twenty-third connection line L23, and the twenty-fourth connection line L24 located on the third conductive layer. Specifically, the second terminal of the eighth transistor T8 is connected to one end of the twenty-second connection line L22, and the other end of the twenty-second connection line L22 is connected to the twenty-third connection line L23. The twenty-third connection line L23 is connected to the twenty-fourth connection line L24 through a first-type via 1 that extends from the fourth conductive layer to the third conductive layer. The twenty-fourth connection line L24 is then connected to the gate of the seventh transistor T7, specifically the top gate. This ultimately connects the second terminal of the eighth transistor T8 to the gate of the seventh transistor T7, where the second terminal of the eighth transistor T8 serves as the output terminal N2 of the forward transmission unit 6. The gate of the eighth transistor T8 is specifically the bottom gate, connected to the fourth connection line L4. The fourth connection line L4 is then connected to the first clock signal line ECK1, and thus connected to the first clock signal line ECK1 through the fourth connection line L4.

[0083] The first terminal of the ninth transistor T9 is connected to the gate of the seventh transistor T7 (specifically, the top gate) via the twenty-third connection line L23 and the fourteenth connection line L14. The first terminal of the ninth transistor T9 is directly connected to the twenty-third connection line L23, thereby connecting the first terminal of the ninth transistor T9 to the gate of the seventh transistor T7 and the second terminal of the eighth transistor T8. The second terminal of the ninth transistor T9 is connected to the second gate of the first transistor T1 via the forty-third connection line L43 located in the fourth conductive layer and the twenty-fifth connection line L25 located in the third conductive layer. Specifically, the second terminal of the ninth transistor T9 is connected to the forty-third connection line L43. The forty-third connection line L43 is connected to one end of the twenty-fifth connection line L25 through a first-type via 1 that extends from the fourth conductive layer to the third conductive layer. The other end of the twenty-fifth connection line L25 is connected to the third sub-section 143 of the second gate of the first transistor T1, thereby connecting the second terminal of the ninth transistor T9 to the second gate of the first transistor T1. The gate of the ninth transistor T9 is specifically a bottom gate connected to the first power line VGH via the twenty-sixth connection line L26 and the fifth connection line L5 located on the second conductive layer. Specifically, the bottom gate of the ninth transistor T9 is directly connected to the twenty-sixth connection line L26, which is connected to the fifth connection line L5 through a second type of via 2 that extends from the fourth conductive layer to the second conductive layer. The fifth connection line L5 is then connected to the first power line VGH, ultimately enabling the gate of the ninth transistor T9 to be connected to the first potential.

[0084] The first terminal of the tenth transistor T10 is connected to the second clock signal line ECK2 via the sixth connection line L6 and the seventh connection line L7, thus enabling the first terminal of the tenth transistor T10 to receive the second clock signal. The second terminal of the tenth transistor T10 is connected to the first plate of the second capacitor C2 via the twenty-seventh connection line L27 located on the fourth conductive layer. Specifically, the twenty-seventh connection line L27 directly connects to the second terminal of the tenth transistor T10, and also connects to the first plate of the second capacitor C2 via a second-type via 2 that extends from the fourth conductive layer to the first conductive layer, thus connecting the second terminal of the tenth transistor T10 to the first plate of the second capacitor C2. The gate of the tenth transistor T10 is connected to the second plate of the second capacitor C2 via the twenty-eighth connection line L28 located on the second conductive layer. Specifically, the bottom gate of the tenth transistor T10 directly connects to the twenty-eighth connection line L28, which in turn connects to the second plate of the second capacitor C2, thereby connecting the gate of the tenth transistor T10 to the second plate of the second capacitor C2.

[0085] The first terminal of the eleventh transistor T11 is connected to the second gate of the first transistor T1 via the forty-third connection line L43 and the twenty-fifth connection line L25. The first terminal of the eleventh transistor T11 is directly connected to the forty-third connection line L43, which in turn is connected to the twenty-fifth connection line L25. The twenty-fifth connection line L25 is connected to the second gate of the first transistor T1, thus achieving the connection between the first terminal of the eleventh transistor T11 and the second gate of the first transistor T1. The second terminal of the eleventh transistor T11 is connected to the second plate of the second capacitor C2 via the twenty-ninth connection line L29 and the thirtieth connection line L30 located on the fourth conductive layer. Specifically, the second terminal of the eleventh transistor T11 is connected to the twenty-ninth connection line L29, which in turn is connected to one end of the thirtieth connection line L30. The other end of the thirtieth connection line L30 is connected to the second plate of the second capacitor C2 via a second type of via that extends from the fourth conductive layer to the second conductive layer, thus achieving the connection between the second terminal of the eleventh transistor T11 and the second plate of the second capacitor C2. The gate of the eleventh transistor T11 is specifically the bottom gate, which is connected to the gate of the tenth transistor T10 (specifically the bottom gate) and the second plate of the second capacitor C2 via the twenty-eighth connecting line L28. The twenty-eighth connecting line L28 is connected to the gate of the eleventh transistor T11, the gate of the tenth transistor T10, and the second plate of the second capacitor C2.

[0086] The first terminal of the twelfth transistor T12 is directly connected to the start signal line EIN via a lap connection. The second terminal of the twelfth transistor T12 is connected to the first terminal of the thirteenth transistor T13 via the thirty-first connection line L31 located on the fourth conductive layer. The thirty-first connection line L31 is lapped to both the second terminal of the twelfth transistor T12 and the first terminal of the thirteenth transistor T13. The gate of the twelfth transistor T12 is connected to the first clock signal line ECK1 via the fourth connection line L4. Specifically, the gate of the twelfth transistor T12 is directly lapped to the fourth connection line L4, and the fourth connection line L4 is connected to the first clock signal line ECK1 via a second type of via 2, ultimately enabling the gate of the twelfth transistor T12 to access the first clock signal.

[0087] The second terminal of the thirteenth transistor T13 is connected to the second plate of the second capacitor C2 via the thirty-second connection line L32 located on the fourth conductive layer and the thirty-third connection line L33 located on the second conductive layer. Specifically, the second terminal of the thirteenth transistor T13 is directly connected to the thirty-second connection line L32. The thirty-second connection line L32 is connected to the thirty-third connection line L33 through a second type of via 2 that runs from the fourth conductive layer to the second conductive layer. The thirty-third connection line L33 is connected to the second plate of the second capacitor C2, thus achieving the connection between the thirteenth transistor T13 and the second plate of the second capacitor C2. The gate of the thirteenth transistor T13 is specifically a bottom gate, which is connected to the first power line VGH via the twenty-sixth connection line L26 and the fifth connection line L5.

[0088] The first electrode of the fourteenth transistor T14 is connected to the first plate of the third capacitor C3 via the eighteenth connecting line L18 and the forty-first connecting line L41. Specifically, the fourteenth transistor T14 is directly connected to the eighteenth connecting line L18, the eighteenth connecting line L18 is connected to the forty-first connecting line L41 through a second type via 2, the forty-first connecting line L41 is connected to the first plate of the third capacitor C3, and the first plate of the third capacitor C3 is connected to the third power line VGL, thus achieving the connection between the first electrode of the fourteenth transistor T14 and the third power line VGL. The second electrode of the fourteenth transistor T14 is connected to the first plate of the second capacitor C2 via the thirty-fourth connecting line L34 located on the fourth conductive layer, the thirty-fifth connecting line L35 located on the second conductive layer, and the twenty-seventh connecting line L27. Specifically, the second terminal of the fourteenth transistor T14 is connected to one end of the thirty-fourth connection line L34. The other end of the thirty-fourth connection line L34 is connected to the thirty-fifth connection line L35 through a second-type via 2. The thirty-fifth connection line L35 is then connected to the twenty-seventh connection line L27 through the second-type via 2. The twenty-seventh connection line L27 is then connected to the first plate of the second capacitor C2, thus connecting the second terminal of the fourteenth transistor T14 to the first plate of the second capacitor C2. The gate of the fourteenth transistor T14 is connected to the seventh sub-section 147 of the second gate of the fourth transistor T4 through the twelfth connection line L12.

[0089] Figure 10 This is a cross-sectional view of another display panel provided in an embodiment of the present invention. Figure 10 For along Figure 6 Cross-sectional view of BB' (see reference) Figure 6 and Figure 10The second transistor T2 is a dual-gate transistor, with the bottom gate located on the second conductive layer 12 and the top gate located on the third conductive layer 14. The active layer 13 is located between the second conductive layer 12 and the third conductive layer 14. The source and drain of the second transistor T2 are both located on the fourth conductive layer 15. The source (first terminal) of the second transistor T2 is connected to the active layer 13 through a first-type via 1 that extends from the fourth conductive layer 15 to the third conductive layer 14. The drain (second terminal) of the second transistor T2 is also connected to the active layer 13 through a first-type via 1 that extends from the fourth conductive layer 15 to the third conductive layer 14. The second terminal of the second transistor T2 is also connected to the active layer 13 through a second-type via 2 that extends from the fourth conductive layer 15 to the second conductive layer 12. Figure 7 The thirteenth connecting line L13 is shown in the diagram.

[0090] refer to Figure 5 and Figure 6 Optionally, the fourth conductive layer includes a trace setting area, which includes a first power line VGH, a start signal line EIN, a first clock signal line ECK1, and a second clock signal line ECK2. The first power line VGH, the start signal line EIN, the first clock signal line ECK1, and the second clock signal line ECK2 all extend along the second direction Y and are arranged along the first direction X.

[0091] Transistors T2, T3, T5, and T14 all include active regions located in the active layer, and the active regions of these transistors are all located between the active region of the first transistor and the wiring area. Specifically, the active regions of transistors T3, T5, T9, T11, and T13 extend along a first direction X, while the active regions of transistors T2, T6, T7, T8, T10, T12, and T14 extend along a second direction Y. Transistors T12 and T8 share a source and drain region, and their active regions have the same length along the second direction Y. To save area of ​​the first capacitor C1, the first capacitor C1 includes a first capacitor sub-section and a second capacitor sub-section. The orthographic projection of the first capacitor sub-section on the substrate is located between the orthographic projection of the tenth transistor T10 on the substrate and the orthographic projection of the second transistor T2 on the substrate. The orthographic projection of the second capacitor sub-section on the substrate is located between the orthographic projection of the third transistor T3 on the substrate and the orthographic projection of the first transistor T1 on the substrate.

[0092] Both the first transistor T1 and the fourth transistor T4 are located on the side of the wiring area closer to the display area;

[0093] The sixth transistor T6, the eighth transistor T8, and the twelfth transistor T12 are all located between the first transistor T1 or the fourth transistor T4 and the wiring area.

[0094] Since the first transistor T1 and the fourth transistor T4 are output transistors, they have a large width-to-length ratio in order to drive the scan line to change rapidly, and are therefore placed closer to the display area. The sixth transistor T6, the eighth transistor T8, and the twelfth transistor T12 all require a start signal, so they need to be placed closer to the routing area than the first transistor T1 and the fourth transistor T4.

[0095] Optionally, the sixth transistor T6 and the eighth transistor T8 are arranged along the second direction Y, and the twelfth transistor T12 and the eighth transistor T8 are arranged along the first direction X.

[0096] Along the first direction X, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are all located between the eighth transistor T8 and the first transistor T1. Furthermore, along the first direction X, the first capacitor C1 and the third capacitor C3 are both located on the side of the second capacitor C2 or the fourth capacitor C4 closest to the display area. Because the first capacitor C1 needs to be connected to the first transistor T1, and the third capacitor C3 needs to be connected to the fourth transistor T4, the first capacitor C1 and the third capacitor C3 also need to be placed near the display area, that is, near the first transistor T1 and the fourth transistor T4, to allow for better layout. In this embodiment, the display panel includes a gate driving circuit, which includes multiple cascaded shift registers. Each shift register includes the light-emitting control circuit described in the above embodiment. Odd-numbered shift registers are connected to the first clock signal line ECK1 and the second clock signal line ECK2, while even-numbered shift registers are connected to the third clock signal line ECK3, which transmits the third clock signal, and the fourth clock signal line ECK2, which transmits the fourth clock signal. The third clock signal is the same as the first clock signal ECK1, and the fourth clock signal is the same as the second clock signal ECK2.

[0097] This embodiment adopts Figure 5 The light emission control circuit fabricated according to the layout shown was used in experiments to output a light emission control signal. Figure 11 This invention provides a signal waveform diagram of a display panel, derived from... Figure 11 It can be seen that the light-emitting control signal is a shifted waveform of the starting signal, and the shift time difference is equal to the phase difference between the second clock signal and the first clock signal. Furthermore, from... Figure 11 It can be seen that during the high-level period of the light-emitting control signal EM output by the existing n-type 9T3C light-emitting control circuit, the signal waveform fluctuates significantly, and the transition to the low level is relatively slow. Figure 5During the high-level period of the light-emitting control signal EM' output by the light-emitting control circuit fabricated in the middle layout, the waveform has almost no fluctuations, and the transition to the low level is relatively rapid. Because the capacitor size in the circuit layout of this embodiment is set within a certain range, and the transistor layout conforms to the input and output directions, and the influence of transistor size design on characteristics is considered, the light-emitting control circuit in this embodiment can enhance the descent speed of the light-emitting control signal, and the signal is more stable and reliable.

[0098] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0099] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: Substrate; A multilayer conductive layer is stacked on one side of the substrate, the multilayer conductive layer including a first conductive layer and a second conductive layer, the second conductive layer being located on the side of the first conductive layer away from the substrate; An active layer is located on the side of the second conductive layer away from the substrate; The active layer and the multilayer conductive layers constitute at least one light-emitting control circuit. The light-emitting control circuit includes a first output module. The first output module includes a first transistor and a first capacitor. The first electrode of the first capacitor is located on the first conductive layer, and the second electrode of the first capacitor is located on the second conductive layer. The first gate of the first transistor is located in the second conductive layer, and the second plate of the first capacitor is connected to the first gate of the first transistor. The ratio of the first area to the second area is between 0.2 and 1.0; wherein, the first area is the area where the orthographic projection of the first electrode plate of the first capacitor on the substrate overlaps with the orthographic projection of the second electrode plate of the first capacitor on the substrate, and the second area is the area where the orthographic projection of the active layer on the substrate overlaps with the orthographic projection of the first gate of the first transistor on the substrate.

2. The display panel according to claim 1, characterized in that, The first transistor is used to transmit the first potential to the output terminal of the light-emitting control circuit; The multilayer conductive layer further includes a third conductive layer and a fourth conductive layer. The third conductive layer is located on the side of the active layer away from the substrate, and the fourth conductive layer is located on the side of the third conductive layer away from the substrate. The fourth conductive layer includes a first clock signal line for transmitting a first clock signal and a second power line for transmitting a second potential, wherein the second potential is less than the first potential. The first output module further includes a second transistor, the first terminal of which is connected to the second power line, the second terminal of which is connected to the second plate of the first capacitor through a first connection line located on the fourth conductive layer, and the gate of which is connected to the first clock signal line in sequence through a second connection line located on the fourth conductive layer, a third connection line located on the second conductive layer, and a fourth connection line located on the second conductive layer.

3. The display panel according to claim 2, characterized in that, The second electrode of the second transistor is connected to the first end of the first connection line, and the second plate of the first capacitor is connected to the second end of the first connection line through a second type of via.

4. The display panel according to claim 2, characterized in that, The light-emitting control circuit further includes a first output control module, which is connected to the second gate of the first transistor. The second gate of the first transistor is located in the third conductive layer, and the orthographic projection of the first gate of the first transistor on the substrate at least partially overlaps with the orthographic projection of the second gate of the first transistor on the substrate.

5. The display panel according to claim 4, characterized in that, The orthogonal projection of the first gate of the first transistor onto the substrate overlaps the orthogonal projection of the second gate of the first transistor onto the substrate.

6. The display panel according to claim 4, characterized in that, The first gate and the second gate of the first transistor each include a first sub-section, a second sub-section, and a third sub-section connected in sequence. The first sub-section and the third sub-section extend along a first direction, and the second sub-section extends along a second direction. The first sub-section and the third sub-section are arranged along the second direction, and the first direction and the second direction intersect. The third sub-section of the first gate of the first transistor is connected to the second plate of the first capacitor.

7. The display panel according to claim 6, characterized in that, The fourth conductive layer includes a first power line for transmitting a first potential, and also includes a first source / drain portion, a second source / drain portion, and a third source / drain portion all extending along the first direction, and a fourth source / drain portion extending along the second direction. The first source / drain portion, the second source / drain portion, and the third source / drain portion are arranged sequentially along the second direction. The first sub-part is located between the first source / drain portion and the second source / drain portion, and the third sub-part is located between the second source / drain portion and the third source / drain portion. The first source / drain portion and the third source / drain portion are both connected to the fourth source / drain portion. The second source / drain portion is connected to the first power line through a fifth connecting line located on the fourth conductive layer.

8. The display panel according to claim 6, characterized in that, The orthographic projection of the first sub-part of the first gate of the first transistor onto the substrate covers the orthographic projection of the first sub-part of the second gate of the first transistor onto the substrate, the orthographic projection of the second sub-part of the first gate of the first transistor onto the substrate covers the orthographic projection of the second sub-part of the second gate of the first transistor onto the substrate, and the orthographic projection of the third sub-part of the first gate of the first transistor onto the substrate covers the orthographic projection of the third sub-part of the second gate of the first transistor onto the substrate.

9. The display panel according to claim 6, characterized in that, The length of the first sub-part of the first gate of the first transistor along the first direction exceeds the length of the first sub-part of the second gate of the first transistor along the first direction by a first preset length, and / or, the length of the first sub-part of the first gate of the first transistor along the second direction exceeds the length of the first sub-part of the second gate of the first transistor along the second direction by a second preset length, and / or, the length of the second sub-part of the first gate of the first transistor along the first direction exceeds the length of the second sub-part of the second gate of the first transistor along the first direction by a third preset length, and / or, the length of the second sub-part of the first gate of the first transistor along the second direction exceeds the length of the second sub-part of the second gate of the first transistor along the second direction by a fourth preset length, and / or, the length of the third sub-part of the first gate of the first transistor along the first direction exceeds the length of the third sub-part of the second gate of the first transistor along the first direction by a fifth preset length, and / or, the length of the third sub-part of the first gate of the first transistor along the second direction exceeds the length of the third sub-part of the second gate region of the first transistor along the second direction by a sixth preset length.

10. The display panel according to claim 9, characterized in that, The first preset length, the second preset length, the third preset length, the fourth preset length, the fifth preset length, and the sixth preset length are all greater than or equal to 1 micrometer and less than or equal to 3 micrometers.

11. The display panel according to claim 6, characterized in that, Along the first direction, the lengths of the first sub-part and the third sub-part are equal; along the second direction, the lengths of the first sub-part and the third sub-part are equal. The length of the first sub-part along the first direction is greater than the length of the first sub-part along the second direction.

12. The display panel according to claim 7, characterized in that, The first output control module includes a forward transmission unit and a gate control unit. The output terminal of the forward transmission unit is connected to the second gate of the first transistor and is used to transmit a start signal to the second gate of the first transistor. The gate control unit is connected to the second gate of the first transistor and includes a second capacitor for raising the potential of the second gate of the first transistor through the coupling effect of the second capacitor. The first plate of the second capacitor is located on the first conductive layer, and the second plate of the second capacitor is located on the second conductive layer; The difference between the area of ​​the second capacitor and the area of ​​the first capacitor is less than a preset threshold; wherein, the area of ​​the second capacitor is the area of ​​the overlapping portion of the orthographic projection of the first plate of the second capacitor on the substrate and the orthographic projection of the second plate of the second capacitor on the substrate.

13. The display panel according to claim 12, characterized in that, The first output module further includes a third transistor. The fourth conductive layer includes a second clock signal line for transmitting a second clock signal. The first electrode of the third transistor is connected to the second clock signal line in sequence through a sixth connection line located on the fourth conductive layer and a seventh connection line located on the first conductive layer. The second electrode of the third transistor is connected to the first plate of the first capacitor through a second type of via. The gate of the third transistor is connected to the output terminal of the forward transmission unit in sequence through an eighth connection line located on the fourth conductive layer, a thirty-seventh connection line located on the second conductive layer, and a ninth connection line located on the second conductive layer.

14. The display panel according to claim 13, characterized in that, The light-emitting control circuit further includes a second output module, which includes a fourth transistor. The fourth transistor is used to output a third potential to the output terminal of the light-emitting control circuit. The third potential is greater than the second potential, and the first potential is greater than the third potential. The first gate of the fourth transistor is located in the second conductive layer, and the first gate of the fourth transistor is connected to the second power line through the thirty-eighth connection line.

15. The display panel according to claim 14, characterized in that, The second gate of the fourth transistor is located in the third conductive layer.

16. The display panel according to claim 14, characterized in that, The first gate and the second gate of the fourth transistor each include a fourth sub-section, a fifth sub-section, a sixth sub-section, and a seventh sub-section. The fourth sub-section, the fifth sub-section, and the sixth sub-section all extend along a first direction, and the seventh sub-section extends along a second direction. The fourth sub-section, the fifth sub-section, and the sixth sub-section are arranged sequentially along the second direction. The first direction and the second direction intersect. The fourth sub-section, the fifth sub-section, and the sixth sub-section are all connected to the seventh sub-section. The sixth sub-section is located on the side of the fifth sub-section closer to the first sub-section. The fourth sub-section of the first gate of the fourth transistor is connected to the second power line via the thirty-eighth connection line; The fourth conductive layer includes a fifth source / drain portion, a sixth source / drain portion, a seventh source / drain portion, and an eighth source / drain portion arranged sequentially along the second direction, and a ninth source / drain portion and a tenth source / drain portion extending along the second direction. The fifth source / drain portion, the sixth source / drain portion, the seventh source / drain portion, and the eighth source / drain portion are all located between the extension line of the ninth source / drain portion along the second direction and the extension line of the tenth source / drain portion along the second direction. The fifth source / drain portion and the seventh source / drain portion are all connected to the ninth source / drain portion, and the sixth source / drain portion and the eighth source / drain portion are all connected to the tenth source / drain portion. The fourth sub-part is located between the fifth source / drain part and the sixth source / drain part; the fifth sub-part is located between the sixth source / drain part and the seventh source / drain part; and the sixth sub-part is located between the seventh source / drain part and the eighth source / drain part. The fourth conductive layer further includes a third power line for transmitting the third potential. The third power line is connected to the seventh source / drain portion via a tenth connection line located in the first conductive layer. The tenth source / drain portion is connected to the output terminal of the light-emitting control circuit.

17. The display panel according to claim 16, characterized in that, The length of the fourth sub-part of the first gate of the fourth transistor along the first direction exceeds the length of the fourth sub-part of the second gate of the fourth transistor along the first direction by a first preset length, and / or, the length of the fourth sub-part of the first gate of the fourth transistor along the second direction exceeds the length of the fourth sub-part of the second gate of the fourth transistor along the second direction by a second preset length, and / or, the length of the fifth sub-part of the first gate of the fourth transistor along the first direction exceeds the length of the fifth sub-part of the second gate of the fourth transistor along the first direction by a third preset length, and / or, the length of the fifth sub-part of the first gate of the fourth transistor along the second direction exceeds the length of the fifth sub-part of the second gate of the fourth transistor along the second direction by a fourth preset length, and / or, the length of the sixth sub-part of the first gate of the fourth transistor along the first direction exceeds the length of the sixth sub-part of the second gate of the fourth transistor along the first direction by a fifth preset length, and / or, the length of the sixth sub-part of the first gate of the fourth transistor along the second direction exceeds the length of the sixth sub-part of the second gate of the fourth transistor along the second direction by a sixth preset length.

18. The display panel according to claim 17, characterized in that, The first preset length, the second preset length, the third preset length, the fourth preset length, the fifth preset length, and the sixth preset length are all greater than or equal to 1 micrometer and less than or equal to 3 micrometers.

19. The display panel according to claim 16, characterized in that, The second output module further includes a third capacitor, wherein the first plate of the third capacitor is located on the first conductive layer, and the second plate of the third capacitor is located on the second conductive layer. The first plate of the third capacitor is connected to the ninth source / drain portion via the eleventh connection line located on the fourth conductive layer, and the second plate of the third capacitor is connected to the fourth sub-port of the second gate of the fourth transistor via the twelfth connection line located on the third conductive layer.

20. The display panel according to claim 19, characterized in that, The area of ​​the third capacitor is smaller than that of the first capacitor. The area of ​​the third capacitor is the area of ​​the overlapping projection of the first plate of the third capacitor onto the substrate and the projection of the second plate of the third capacitor onto the substrate.

21. The display panel according to claim 20, characterized in that, The ratio of the area of ​​the third capacitor to the area of ​​the first capacitor is greater than or equal to 0.4 and less than or equal to 0.

6.

22. The display panel according to claim 16, characterized in that, The first terminal of the second transistor is connected to the seventh sub-terminal of the first gate of the fourth transistor via the thirteenth connection line located in the second conductive layer.

23. The display panel according to claim 19, characterized in that, The light-emitting control circuit further includes a second output control module, which is used to transmit an inverted signal of the start signal to the second gate of the fourth transistor; The second output control module includes a fifth transistor and a fourth capacitor. The first plate of the fourth capacitor is located on the first conductive layer, and the second plate of the fourth capacitor is located on the second conductive layer. The first plate of the fourth capacitor is connected to the gate of the fifth transistor, and the second plate of the fourth capacitor is connected to the first clock signal line through the third connection line and the fourth connection line. The first electrode of the fifth transistor is connected to the second plate of the fourth capacitor through the seventeenth connection line located in the second conductive layer, and the second electrode of the fifth transistor is connected to the fourth sub-section of the second gate of the fourth transistor through the fourteenth connection line, the fifteenth connection line, the sixteenth connection line and the twelfth connection line located in the fourth conductive layer in sequence. The area of ​​the fourth capacitor is smaller than the area of ​​the first capacitor; the area of ​​the fourth capacitor is the area of ​​the overlap between the orthographic projection of the first plate of the fourth capacitor on the substrate and the orthographic projection of the second plate of the fourth capacitor on the substrate.

24. The display panel according to claim 23, characterized in that, The ratio of the area of ​​the fourth capacitor to the area of ​​the first capacitor is greater than or equal to 0.5 and less than or equal to 0.

7.

25. The display panel according to claim 23, characterized in that, The fourth conductive layer includes a start signal line for transmitting a start signal. The second output control module also includes a sixth transistor. The first electrode of the sixth transistor is connected to the first plate of the third capacitor via the eighteenth connection line located on the fourth conductive layer and the forty-first connection line located on the first conductive layer. The second electrode of the sixth transistor is connected to the first plate of the fourth capacitor via the nineteenth connection line located on the fourth conductive layer and the forty-second connection line located on the first conductive layer. The gate of the sixth transistor is connected to the start signal line via the twentieth connection line located on the fourth conductive layer. The channel length of the sixth transistor is greater than the channel length of each of the fifth transistor, the second transistor, and the third transistor.

26. The display panel according to claim 25, characterized in that, The channel length of the sixth transistor is greater than or equal to 6 micrometers and less than or equal to 8 micrometers.

27. The display panel according to claim 25, characterized in that, The second output control module further includes a seventh transistor, the forward transmission unit includes an eighth transistor, and the gate control unit includes a ninth, tenth, eleventh, twelfth, thirteenth, and fourteenth transistors. The first electrode of the seventh transistor is connected to the first plate of the third capacitor in sequence through the eighteenth connecting line and the forty-first connecting line. The second electrode of the seventh transistor is connected to the fourth sub-section of the second gate of the fourth transistor in sequence through the fifteenth connecting line, the sixteenth connecting line and the twelfth connecting line. The gate of the seventh transistor is connected to the gate of the third transistor in sequence through the ninth connecting line and the eighth connecting line. The first terminal of the eighth transistor is connected to the start signal line through the twenty-first connection line located on the fourth conductive layer. The second terminal of the eighth transistor is connected to the gate of the seventh transistor through the twenty-second connection line located on the fourth conductive layer, the twenty-third connection line located on the fourth conductive layer, and the twenty-fourth connection line located on the third conductive layer in sequence. The gate of the eighth transistor is connected to the first clock signal line through the fourth connection line. The first terminal of the ninth transistor is connected to the twenty-third connection line, and the second terminal of the ninth transistor is connected to the second gate of the first transistor through the forty-third connection line located on the fourth conductive layer and the twenty-fifth connection line located on the third conductive layer in sequence. The gate of the ninth transistor is connected to the first power line through the twenty-sixth connection line located on the second conductive layer and the fifth connection line in sequence. The first terminal of the tenth transistor is connected to the second clock signal line in sequence through the sixth connection line and the seventh connection line. The second terminal of the tenth transistor is connected to the first plate of the second capacitor through the twenty-seventh connection line located on the fourth conductive layer. The gate of the tenth transistor is connected to the second plate of the second capacitor through the twenty-eighth connection line located on the second conductive layer. The first terminal of the eleventh transistor is connected to the second gate of the first transistor in sequence through the forty-third connection line and the twenty-fifth connection line. The second terminal of the eleventh transistor is connected to the second plate of the second capacitor in sequence through the twenty-ninth connection line located on the fourth conductive layer and the thirtieth connection line located on the fourth conductive layer. The gate of the eleventh transistor is connected to the gate of the tenth transistor and the second plate of the second capacitor in sequence through the twenty-eighth connection line. The first terminal of the twelfth transistor is connected to the start signal line, the second terminal of the twelfth transistor is connected to the first terminal of the thirteenth transistor through the thirty-first connection line located on the fourth conductive layer, and the gate of the twelfth transistor is connected to the first clock signal line through the fourth connection line. The second electrode of the thirteenth transistor is connected to the second plate of the second capacitor in sequence through the thirty-second connection line located on the fourth conductive layer and the thirty-third connection line located on the second conductive layer. The gate of the thirteenth transistor is connected to the first power line through the twenty-sixth connection line and the fifth connection line. The first electrode of the fourteenth transistor is connected to the first plate of the third capacitor in sequence through the eighteenth and fourteenth connecting lines. The second electrode of the fourteenth transistor is connected to the first plate of the second capacitor in sequence through the thirty-fourth connecting line located on the fourth conductive layer, the thirty-fifth connecting line located on the second conductive layer, and the twenty-seventh connecting line. The gate of the fourteenth transistor is connected to the second gate of the fourth transistor through the twelfth connecting line.

28. The display panel according to claim 27, characterized in that, The fourth conductive layer includes a trace setting area, which includes a first power line, a start signal line, a first clock signal line, and a second clock signal line. The first power line, the start signal line, the first clock signal line, and the second clock signal line all extend along the second direction and are arranged along the first direction. Both the first transistor and the fourth transistor are located on the side of the wiring area closer to the display area; The sixth transistor, the eighth transistor, and the twelfth transistor are all located between the first transistor or the fourth transistor and the wiring area.

29. The display panel according to claim 28, characterized in that, The sixth transistor and the eighth transistor are arranged along the second direction, and the twelfth transistor and the eighth transistor are arranged along the first direction; Along the first direction, the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are all located between the eighth transistor and the first transistor, and along the first direction, the first capacitor and the second capacitor are both located on the side of the third capacitor or the fourth capacitor closer to the display area.

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