Method and apparatus for data retention in non-volatile two-terminal memory

Abstract

The disclosure discloses a method and device for non-volatile two-terminal memory data retention, the method comprising: starting a write data state machine, writing data to a storage unit in the non-volatile two-terminal memory by the write data state machine; determining whether the storage unit meets a strengthening processing condition using a write data time determination condition, the write data time determination condition being used to determine whether the write data time of the storage unit exceeds a write data time threshold; the storage unit meeting the strengthening processing condition comprising that the write data time of the storage unit does not exceed the write data time threshold; and performing strengthening processing on the storage unit in response to meeting the strengthening processing condition. By using the scheme of the present application, the degradation problem of non-volatile two-terminal memory data in the storage process can be improved without occupying the write data time by performing strengthening processing on the storage unit meeting the condition that the write data time does not exceed the write data time threshold, so that strengthening processing is only performed when the write data time is sufficient.

Description

Technical Field

[0001] This disclosure generally relates to the field of non-volatile dual-ended memory data processing technology. More specifically, this disclosure relates to a method and apparatus for data retention in non-volatile dual-ended memory. Background Technology

[0002] Non-volatile two-ended memories represent a recent innovation in the field of integrated circuit technology. While many non-volatile two-ended memory technologies are still under development, several proposed technical concepts for non-volatile two-ended memory devices have been demonstrated by inventors and are in one or more verification phases to falsify related theories or technologies. Inventors believe that various two-ended memory technologies (e.g., resistive switching memories, magnetoresistive memories, ferroelectric memories, phase-change memories, and conductive bridged memories) have compelling evidence to demonstrate significant advantages over competing technologies in the semiconductor electronics industry.

[0003] Non-volatile two-terminal memories typically include resistive random access memories (RRAMs) and polarized memory, both of which are susceptible to degradation.

[0004] Taking resistive random access memory (RRAM) as an example, in existing technologies, data can be written, read, and stored using RRAM. RRAM has advantages such as high density, low power consumption, and fast read / write speeds, thus it has broad application prospects in the field of data storage.

[0005] However, data retention in resistive random access memory (RRAM) can experience degradation. Specifically, data is initially stored reliably and accurately in specific data cells within the RRAM. Over time, and influenced by external environmental factors (such as temperature fluctuations, electromagnetic interference, and material aging), some data cells begin to degrade, becoming marginal cells. Marginal cells are those memory cells located at the edge of their normal operating range; their data retention capability weakens, and their sensitivity to external interference and internal physical changes increases. This degradation often accelerates over time. When this degradation reaches a certain point, especially when data stability drops below the limit threshold of the sense amplifier, the sense amplifier may fail to accurately distinguish between signal and noise, leading to read errors.

[0006] Similarly, polarized memory also exhibits this type of degradation, which will not be discussed in detail here.

[0007] In view of this, there is an urgent need to provide a scheme for data retention in non-volatile two-ended memory, so as to enhance the edge cells of non-volatile two-ended memory and improve the degradation problem of non-volatile two-ended memory data during storage. Summary of the Invention

[0008] In order to at least address one or more of the technical problems mentioned above, this disclosure proposes a scheme for data retention in non-volatile end-to-end memory in several aspects.

[0009] According to a first aspect of this application, a method for data retention in a non-volatile dual-ended memory is provided, characterized in that the method includes: activating a write data state machine, writing data to a storage cell in the non-volatile dual-ended memory through the write data state machine; determining whether the storage cell meets an enhanced processing condition using a write data time judgment condition, wherein the write data time judgment condition is used to determine whether the write data time of the storage cell exceeds a write data time threshold; the storage cell meeting the enhanced processing condition includes: the write data time of the storage cell does not exceed the write data time threshold; and in response to meeting the enhanced processing condition, performing enhanced processing on the storage cell.

[0010] According to one embodiment of this application, a state verification condition is used to determine whether the storage unit meets the enhanced processing condition. The state verification condition is used to determine whether the state of the storage unit is weak or strong. The storage unit meeting the enhanced processing condition includes: the state of the storage unit is weak.

[0011] According to one embodiment of this application, in the process of determining whether the storage unit meets the enhanced processing conditions, the write data time judgment condition is executed first, and then the status verification condition is executed.

[0012] According to one embodiment of this application, in the process of determining whether the storage unit meets the enhanced processing conditions, the state verification condition is executed first, and then the write data time judgment condition is executed.

[0013] According to one embodiment of this application, after the storage cell is enhanced, the following steps are performed: it is determined again whether the enhanced storage cell meets the enhancement conditions; in response to meeting the enhancement conditions, the step of enhancing the storage cell is returned until the storage cell no longer meets the enhancement conditions.

[0014] According to one embodiment of this application, the non-volatile dual-end memory stores an enhanced region address; a state verification condition is used to determine whether the memory cell meets the enhanced processing condition, the state verification condition being used to determine whether the state of the memory cell is weak or strong; before using the state verification condition to determine whether the memory cell meets the enhanced processing condition, the enhanced region address is loaded into the non-volatile dual-end memory, and the enhanced region address stored in the non-volatile dual-end memory is incremented by 1 to obtain the address of the memory cell.

[0015] According to one embodiment of this application, when the state of the storage cell is strong, the address of the storage cell is recorded.

[0016] According to one embodiment of this application, the method further includes: exiting the write data state machine in response to the failure to meet the enhanced processing conditions.

[0017] According to one embodiment of this application, the state verification conditions include: a first storage state verification condition and a second storage state verification condition, wherein the first storage state verification condition is used to verify that the storage cell is a first high state or a second high state, and the second storage state verification condition is used to verify that the storage cell is a first low state or a second low state.

[0018] According to one embodiment of this application, the non-volatile two-terminal memory is a resistive variable memory, and the state verification conditions include: a first resistive state verification condition and a second resistive state verification condition, wherein the first resistive state verification condition is used to verify that the memory cell is a first high-resistance state or a second high-resistance state, and the second resistive state verification condition is used to verify that the memory cell is a first low-resistance state or a second low-resistance state.

[0019] According to one embodiment of this application, the first resistive state verification condition includes a first erase verification condition and a first edge erase verification condition, wherein the current of the memory cell in the first high-resistivity state is greater than the first erase verification current and less than the first edge erase verification current.

[0020] According to one embodiment of this application, the second resistance state verification condition includes a first programming verification condition and a first edge programming verification condition, wherein the current of the memory cell in the first low resistance state is less than the first programming verification current and greater than the first edge programming verification current.

[0021] According to one embodiment of this application, the enhanced processing of the storage cell includes: performing an enhanced erase operation on the storage cell when the storage cell is in a first high-resistivity state; and performing an enhanced programming operation on the storage cell when the storage cell is in a first low-resistivity state.

[0022] According to one embodiment of this application, the resistive switching memory includes one or more of the following: resistive switching memory, phase change memory, magnetoresistive memory, and conductive bridge memory.

[0023] According to one embodiment of this application, the non-volatile dual-end memory is a polarized state memory, and the state verification conditions include: a first polarized state verification condition and a second polarized state verification condition, wherein the first polarized state verification condition is used to verify that the memory cell is a first negative polarized state or a second negative polarized state, and the second polarized state verification condition is used to verify that the memory cell is a first positive polarized state or a second positive polarized state.

[0024] According to one embodiment of this application, the first polarization state verification condition includes a second erase verification condition and a second edge erase verification condition, wherein the polarization amount of the memory cell in the first negative polarization state is between the second erase verification polarization amount and the second edge erase verification polarization amount.

[0025] According to one embodiment of this application, the second polarization state verification condition includes a second programming verification condition and a second edge programming verification condition, wherein the polarization amount of the memory cell in the first positive polarization state is between the second programming verification polarization amount and the second edge programming verification polarization amount.

[0026] According to one embodiment of this application, the enhanced processing of the storage cell includes: performing an enhanced erase operation on the storage cell when the storage cell is in a first negative polarization state; and performing an enhanced programming operation on the storage cell when the storage cell is in a first positive polarization state.

[0027] According to one embodiment of this application, the polarization state memory includes a ferroelectric random access memory (FeRAM).

[0028] According to a second aspect of this application, an apparatus for non-volatile end-to-end memory data retention is provided, characterized in that it comprises: a processor; a memory for storing a computer program; wherein the processor is configured to execute the computer program to implement the method described above.

[0029] According to a third aspect of this application, a computer-readable storage medium is provided having a computer program stored thereon, characterized in that, when the computer program is executed by one or more processors, it implements the method described above.

[0030] According to a fourth aspect of this application, a data writing system is provided, characterized in that the data writing system comprises: a data writing module, the data writing module being configured to initiate a data writing state machine and write data to a storage unit in a non-volatile end-to-end memory through the data writing state machine; a judgment module, the judgment module being configured to determine whether the storage unit meets an enhanced processing condition using a data writing time judgment condition, the data writing time judgment condition being configured to determine whether the data writing time of the storage unit exceeds a data writing time threshold, the storage unit meeting the enhanced processing condition including: the data writing time of the storage unit not exceeding the data writing time threshold; and an enhanced processing module, the enhanced processing module being configured to perform enhanced processing on the storage unit in response to meeting the enhanced processing condition.

[0031] By employing the above-described scheme for data retention in non-volatile end-to-end memory, this disclosed embodiment enhances the processing of memory cells whose write time does not exceed a write time threshold. This improves the degradation problem of data in non-volatile end-to-end memory during storage without consuming write time. Enhancement processing is only performed when write time is sufficient, thus avoiding excessive system resource consumption or processing delays caused by excessive write time due to enhancement processing. Furthermore, it fully utilizes write time, improving the efficiency of memory cell processing. In some embodiments, before using state verification conditions to determine whether a memory cell meets the enhancement processing conditions, an enhancement region address is loaded into the non-volatile end-to-end memory, and this address is incremented by 1. This allows the address of the memory cell currently requiring strength / weakness assessment to be located, enabling the enhancement processing of memory cells meeting the enhancement processing conditions to be performed sequentially. Furthermore, in some embodiments, when the state of the memory cell is determined to be strong, the address of the memory cell is recorded. This can provide a start address for the next strengthening operation, so that the memory cells that meet the strengthening conditions can be strengthened in sequence. This ensures that the strength judgment and strengthening operation can traverse the addresses of all memory cells in the non-volatile end memory, avoiding the need to reacquire the strengthening region address, thereby significantly improving the efficiency of the strengthening process. Attached Figure Description

[0032] The above and other objects, features, and advantages of exemplary embodiments of this disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0033] Figure 1a An exemplary flowchart of the data writing process of a resistive random access memory (RRAM) in the prior art is shown;

[0034] Figure 1b A schematic diagram illustrating the degradation of resistive random access memory is shown.

[0035] Figure 1c A schematic diagram illustrating the degradation of polarized memory is shown.

[0036] Figure 2 An exemplary flowchart of a method for data retention in resistive random access memory (RRAM) according to some embodiments of this application is shown;

[0037] Figure 3 An exemplary flowchart illustrating the process of writing data to a memory cell in a resistive random access memory (RAM) according to an embodiment of this application is shown.

[0038] Figure 4 An exemplary flowchart illustrating a method for determining whether a storage unit meets enhanced processing conditions is shown in one embodiment of this application;

[0039] Figure 5 An exemplary flowchart illustrating a method for determining whether a storage unit meets enhanced processing conditions, as shown in another embodiment of this application, is illustrated.

[0040] Figure 6 An exemplary structural block diagram of an apparatus for data retention in resistive random access memory (RRAM) according to an embodiment of this application is shown;

[0041] Figure 7 An exemplary structural block diagram of a data writing system according to an embodiment of this application is shown;

[0042] Figure 8 An exemplary structural block diagram of the electronic operating environment of resistive switching memory according to an embodiment of this application is shown. Detailed Implementation

[0043] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0044] It should be understood that the terms “comprising” and “including” used in this disclosure and claims indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0045] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0046] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0047] This invention relates to non-volatile two-terminal memories for storing digital information. In some embodiments, a non-volatile two-terminal memory cell may include a memory based on resistance technology and a memory based on polarization technology, the former being, for example, a non-volatile resistive-switch two-terminal memory cell, or, for example, a polarized memory. A non-volatile resistive-switch two-terminal memory cell (also referred to herein as a resistive-switch memory cell or resistive-variable memory) as used herein includes a circuit element having two conductive contacts (also referred to herein as electrodes or terminals) with a storage functional region (also referred to as a switching layer) between the two conductive contacts. In the context of resistive-variable memory, the storage functional region of a two-terminal memory device exhibits multiple stable or semi-stable resistance states, each with a different resistance. Examples of resistive-switch two-terminal memory devices may include, but are not limited to, resistive random access memories currently being developed by the assignee of this patent application.

[0048] In addition to resistive characteristics, multiple states can be formed or activated in response to a suitable electrical signal applied to the two conductive contacts. This suitable electrical signal can be a voltage value, current value, pulse width, pulse height, or current polarity, or a suitable combination thereof.

[0049] Therefore, the non-volatile two-terminal memory of this application mainly includes resistive random access memory (RRAM) and polarized random access memory (PRAM). The RRAM includes resistive random access memory (RRAM), phase change random access memory (PCRAM), magnetoresistive random access memory (MRAM), and conductive bridging random access memory (CBRAM), or combinations thereof. The PRAM includes ferroelectric random access memory (FeRAM).

[0050] The specific embodiments disclosed herein will now be described in detail with reference to the accompanying drawings.

[0051] Figure 1a An exemplary flowchart of the write data process 100 of a resistive random access memory (RRAM) in the prior art is shown.

[0052] like Figure 1a As shown, in the prior art, during the data writing process of a resistive random access memory (RRAM), firstly, in step S110, the data writing state machine is started. Then, in step S120, the process enters the PGM stage or the ERS stage, i.e., data programming or data erasure. Specifically, data programming is the process of writing "1" to a memory cell of the RRAM, at which time the memory cell transitions from a high-resistance state to a low-resistance state. The PGM stage covers the entire data programming process, including writing data to the specified cell of the RRAM and performing a verification process to ensure that the data is stored accurately. Data erasure is the process of writing "0" to a memory cell of the RRAM, at which time the memory cell transitions from a low-resistance state to a high-resistance state. In the ERS stage, the target data is erased from the memory cell, and the thoroughness of the erasure operation is verified through a verification process. After completing the above operations, in step S130, the data writing state machine executes the end process, marking the successful completion of the entire data writing process.

[0053] However, during the data writing process of the resistive random access memory (RRAM) shown above, over time and due to external environmental factors (such as temperature fluctuations, electromagnetic interference, and material aging), some data cells begin to degrade, becoming marginal cells. This causes a gradual decrease in the RRAM's storage performance. Furthermore, this degradation is continuous and intensifies. When the degradation level falls below the limit threshold of the sense amplifier, it will trigger data read errors, severely impacting data integrity and reliability.

[0054] Figure 1b A schematic diagram illustrating the degradation of resistive random access memory is shown.

[0055] like Figure 1b As shown, the horizontal axis represents the current intensity in the memory cell. When the memory cell stores "0", it is in a high-resistivity state with a low current; while when the memory cell stores "1", it is in a low-resistivity state with a high current.

[0056] Let EV be the lower threshold and PV be the upper threshold of the current in a resistive random access memory (RRAM) cell. Then, ideally, when a RRAM cell stores "0", its low current value should not exceed EV (in the context of the RRAM cell storing a value of "0"). Figure 1b This is referred to as "strong 0" in the context of the variable resistor memory (VRM), and ideally, when a VRM cell stores a "1", its high current value should not be lower than the PV value (in the context of the VRM). Figure 1b (referred to as "Strong 1" in China).

[0057] However, if the resistive random access memory (RRAM) degrades, the following situation may occur: when the RRAM cell stores "0", the low current value may gradually increase and exceed the lower threshold EV; while when the RRAM cell stores "1", its high current value may gradually decrease and fall below the upper threshold PV. Therefore, if the RRAM degradation becomes more severe, the low and high current values ​​will gradually converge towards the middle, and when this convergence reaches a certain level, it will be impossible to distinguish whether the cell stores "0" or "1".

[0058] Let MEV be the lower critical threshold and MPV be the upper critical threshold for the current in the storage cell of the resistive random access memory (RRAM). When the RRAM storage cell stores "0", if its low current value exceeds the lower critical threshold MEV, the data stored in the storage cell may not be recognized and cannot be recovered. When the RRAM storage cell stores "1", if its high current value is lower than the upper critical threshold MPV, the data stored in the storage cell may not be recognized and cannot be recovered.

[0059] To prevent the memory cells of the resistive switching memory from degrading further to the point of being unrecognizable or unrecoverable, a low current value can be maintained between EV and MEV (in... Figure 1b When the current is referred to as "weak 0" in the standard, it is strengthened so that the low current value is restored to no higher than EV; furthermore, the high current value can be strengthened when it is between MPV and PV (in the standard). Figure 1b When the current is referred to as "weak 1", it is strengthened so that the high current value is restored to no less than PV.

[0060] It can be seen that the degradation of resistive random access memory (RRAM) causes low current values ​​and high current values ​​to be so close that they are indistinguishable; while strengthening the RRAM will push the low current values ​​and high current values ​​apart, making them more distinguishable.

[0061] Figure 1c A schematic diagram illustrating the degradation of polarized memory is shown.

[0062] like Figure 1c As shown, the vertical axis represents a schematic diagram of the electric field strength or electrode voltage in the memory cell, and the horizontal axis represents the polarization of the memory cell. When a "0" is stored in the memory cell, it is negatively polarized (as described in this application). Figure 1c The leftward direction represents "negative" and the rightward direction represents "positive" polarization; when a "1" is stored in a memory cell, it is positively polarized.

[0063] Let P0 be the negative threshold for negative polarization and P1 be the positive threshold in the storage cell of the polarized memory. Then, when the storage cell of the polarized memory stores "0", ideally its polarization should be to the left of point P0 (in...). Figure 1c This is referred to as "strong 0," where the absolute value of the polarization of the memory cell is greater than the absolute value of the polarization at P0. Ideally, when a memory cell in a polarized state stores "1," its polarization should be to the right of point P1 (in...). Figure 1c This is referred to as "strong 1", where the absolute value of the polarization of the memory cell is greater than the absolute value of the polarization at P1.

[0064] However, if the polarization memory degrades, the following situation may occur: when a cell in the polarization memory stores "0", its negative polarization may gradually weaken and exceed point P0; while when a cell in the polarization memory stores "1", its positive polarization may gradually weaken and exceed point P1. Therefore, if the degradation of the polarization memory becomes more and more severe, the negative and positive polarization values ​​will gradually converge towards the middle, and when this convergence reaches a certain level, it will be impossible to distinguish whether the cell stores "0" or "1".

[0065] Let MP0 be the negative critical threshold and MP1 be the positive critical threshold for the current in the storage cell of the polarized memory. Then, when the storage cell of the polarized memory stores "0", if its negative polarization exceeds the negative critical threshold MP0, the data stored in the storage cell may not be recognized and may not be recovered. When the storage cell of the polarized memory stores "1", if its positive polarization exceeds the positive critical threshold MP1, the data stored in the storage cell may not be recognized and may not be recovered.

[0066] To prevent the storage cells of polarized memory from further degrading to the point of being unrecognizable or unrecoverable, the negative polarization can be positioned between P0 and MP0 (in... Figure 1c When the polarization is referred to as "weak 0" in the equation, it is strengthened so that the negative polarization does not exceed P0; furthermore, the positive polarization can be strengthened when it is between MP1 and P1 (in the equation). Figure 1c When the polarization is referred to as "weak 1", it is strengthened so that the positive polarization is restored to no more than P1.

[0067] It can be seen that the degradation of polarization memory causes negative and positive polarizations to get so close that they become indistinguishable; while strengthening polarization memory will push negative and positive polarizations apart, making them more distinguishable.

[0068] In view of this, the present disclosure provides a scheme for data retention in non-volatile dual-ended memory, which can improve the degradation problem of data in non-volatile dual-ended memory during storage without occupying write data time.

[0069] According to one aspect of this disclosure, a method for data retention in a non-volatile dual-ended memory is provided, comprising: initiating a write data state machine, writing data to a storage cell in the non-volatile dual-ended memory through the write data state machine; determining whether the storage cell meets an enhanced processing condition using a write data time judgment condition, wherein the write data time judgment condition is used to determine whether the write data time of the storage cell exceeds a write data time threshold; the storage cell meeting the enhanced processing condition includes: the write data time of the storage cell does not exceed the write data time threshold; and in response to meeting the enhanced processing condition, performing enhanced processing on the storage cell.

[0070] The following will begin with an example of resistive random access memory.

[0071] According to one embodiment of this disclosure, this disclosure provides a scheme for data retention in resistive random access memory (RRAM), which can improve the degradation problem of RRAM data during storage without occupying write data time.

[0072] Figure 2An exemplary flowchart of a method 200 for data retention in resistive random access memory (RRAM) according to an embodiment of this application is shown.

[0073] like Figure 2 As shown, in step S210, the write data state machine is started, and data is written to the storage cell in the resistive random access memory through the write data state machine.

[0074] In one embodiment of this application, during the process of writing data to the storage cell in the resistive random access memory via the write data state machine, steps S310-S330 are executed sequentially.

[0075] Figure 3 An exemplary flowchart illustrating the process of writing data to a storage cell in a resistive random access memory (RRAM) according to an embodiment of this application is shown.

[0076] like Figure 3 As shown, in step S310, a write data operation is performed. In step S320, it is determined whether the storage unit meets the write data completion condition based on the status verification condition. In response to meeting the write data completion condition, the write data operation ends in step S330. In response to not meeting the write data completion condition, the process returns to step S310 and continues to execute the write data operation until the write data completion condition is met.

[0077] In the embodiments of this application, the states of the memory cells include a high-resistance state (0) and a low-resistance state (1). Specifically, the high-resistance state (0) includes a first high-resistance state (weak 0) and a second high-resistance state (strong 0), and the low-resistance state (1) includes a first low-resistance state (weak 1) and a second low-resistance state (strong 1). The current of the memory cell in the first high-resistance state is greater than the erase verification current and less than the edge erase verification current, and the current of the memory cell in the second high-resistance state is less than the erase verification current. The current of the memory cell in the first low-resistance state is less than the programming verification current and greater than the edge programming verification current, and the current of the memory cell in the second low-resistance state is greater than the programming verification current.

[0078] Specifically, the erase verification current is the current threshold that the storage cell should reach after performing a data erase operation. The edge erase verification current is the current threshold that the storage cell reaches when excessive data erasure is performed. The programming verification current is the current threshold that the storage cell should reach after performing a data programming operation. The edge programming verification current is the current threshold that the storage cell reaches when excessive data programming is performed. In the embodiments of this application, the values ​​of the erase verification current, the edge erase verification current, the programming verification current, and the edge programming verification current can be set according to actual needs and application scenarios, and are not limited here.

[0079] Specifically, the state verification conditions are used to determine whether the state of the memory cell is strong or weak. The state verification conditions include: a first memory state verification condition and a second memory state verification condition. The first memory state verification condition is used to verify that the memory cell is in a first high state or a second high state, and the second memory state verification condition is used to verify that the memory cell is in a first low state or a second low state.

[0080] Specifically, taking resistive random access memory as an example, the state of a memory cell that meets the conditions for completing the write data is a strong state, which includes a second high-resistivity state and a second low-resistivity state.

[0081] When writing data, the charge of the memory cell is usually reduced. After the data erase operation is performed on a memory cell, if the current of the memory cell is less than the erase verification current, it means that the charge state of the memory cell is close to the logic 0 level. At this time, the memory cell changes from the second low impedance state to the second high impedance state, and the state of the memory cell is the second high impedance state.

[0082] When writing data to program data, the charge of the memory cell is usually increased. After performing a data programming operation on a memory cell, if the current of the memory cell is greater than the programming verification current, it means that the charge state of the memory cell is high enough to be reliably identified as logic 1. At this time, the memory cell changes from the second high-resistance state to the second low-resistance state, and thus the state of the memory cell is the second low-resistance state.

[0083] Specifically, the state verification conditions include programming verification conditions and erase verification conditions. The erase verification condition can be whether the current of the memory cell is less than the erase verification current, and the programming verification condition can be whether the current of the memory cell is greater than the programming verification current. During a write operation (data erase), the erase verification condition verifies whether the state of the memory cell is in the second high-resistance state. During a write operation (data programming), the programming verification condition verifies whether the state of the memory cell is in the second low-resistance state.

[0084] In the embodiments of this application, instructions provided to the write data state machine can be implemented according to the control logic configuration, enabling the write data state machine to manage the write data process of the resistive random access memory (RRAM) and other functions related to the RRAM. Specifically, the write data process includes data programming, data erasure, data enhancement, and recording the enhanced region address. During data programming and data erasure, verification conditions can be used to verify the state of each memory cell, and enhancement operations can be performed on memory cells in a weak state. Other functions related to the RRAM include data reading, data input, and data output. Furthermore, the write data state machine can send and receive acknowledgments and negative acknowledgments regarding the successful reception or execution of various commands, and can also decode and implement commands related to the write data process.

[0085] In the embodiments of this application, the aforementioned resistive random access memory (RRAM) stores an enhanced region address, which is used as user data stored in a specific area of ​​the RRAM. Specifically, this specific area may be an area for recording user information. The enhanced region address is the address of the most recently recorded memory cell with a strong state. Before the address of a memory cell with a strong state is recorded, the enhanced region address is 0. Specifically, memory cells with a strong state include memory cells that do not require enhanced processing after judgment and memory cells with a weak state that become strong after enhanced processing.

[0086] By storing the enhanced region address as user data in a specific area of ​​the resistive random access memory (RRAM), during data writing, before using state verification conditions to determine whether a memory cell meets the enhanced processing conditions, the enhanced region address is loaded into the RRAM and incremented by 1. This directly locates the address of the memory cell that needs to be determined for enhanced strength assessment. For example, if the enhanced region address stored in the RRAM is 15, before using state verification conditions to determine whether a memory cell meets the enhanced processing conditions, enhanced region address 15 is loaded, and then 1 is incremented. The resulting enhanced region address 16 is the address of the memory cell that needs to be determined for enhanced strength assessment.

[0087] By directly locating the address of the memory cell that needs to be determined for strength or weakness, the efficiency of strengthening processing is significantly improved by avoiding the need to reacquire the strengthening region address.

[0088] Next, in step S220, it is determined whether the storage cell meets the enhanced processing conditions.

[0089] In the embodiments of this application, write data time judgment conditions and state verification conditions are used to determine whether a storage unit meets the enhanced processing conditions. Specifically, the write data time judgment condition is used to determine whether the write data time of the storage unit exceeds a write data time threshold, and the state verification condition is used to determine whether the state of the storage unit is weak or strong. A storage unit meeting the enhanced processing conditions includes: the write data time of the storage unit does not exceed the write data time threshold and the state of the storage unit is weak. Therefore, even if the state of the storage unit is weak, enhanced processing cannot be performed on the storage unit if the write data time exceeds the write data time threshold. This setting ensures that enhanced processing is only performed when there is sufficient write data time, thereby avoiding the problem of excessive system resource consumption or processing delay caused by excessively long write data times due to enhanced processing, and enabling full utilization of write data time to improve the efficiency of storage unit processing.

[0090] Specifically, the aforementioned data writing time threshold can be set according to actual needs and application scenarios, and is not limited here.

[0091] In one embodiment of this application, in determining whether a storage unit meets the enhanced processing conditions, a write data time judgment condition is executed first, followed by a status verification condition. That is, the write data time judgment condition is first used to determine whether the write data time exceeds a write data time threshold, and then the status verification condition is used to determine whether the storage unit is in a weak or strong state. Specifically, steps S410-S460 are executed sequentially.

[0092] Figure 4 An exemplary flowchart illustrating a method for determining whether a storage unit meets enhanced processing conditions is shown in one embodiment of this application.

[0093] like Figure 4 As shown, in step S410, the write data time judgment condition is used to determine whether the write data time exceeds the write data time threshold. In response to the write data time exceeding the write data time threshold, in step S420, it is determined that the memory cell does not meet the strengthening processing condition, and the write data state machine exits. In response to the write data time not exceeding the write data time threshold, in step S430, the strengthening region address is loaded into the resistive random access memory (RRAM), and the strengthening region address stored in the RRAM is incremented by 1 to obtain the address of the memory cell currently requiring a strength / weakness judgment. In step S440, the state verification condition is used to determine whether the state of the memory cell is weak or strong. In response to the memory cell being in a strong state, in step S450, it is determined that the memory cell does not meet the strengthening processing condition, and the address of the memory cell is recorded. That is, when it is determined that the memory cell does not meet the strengthening processing condition, the address obtained by incrementing the strengthening region address stored in the RRAM by 1 is recorded. In response to the memory cell being in a weak state, in step S460, it is determined that the memory cell meets the strengthening processing condition.

[0094] Therefore, in this embodiment, it is first determined whether the write data time exceeds the write data time threshold. If the write data time exceeds the write data time threshold, it is directly determined that the storage unit does not meet the enhanced processing conditions. Thus, it is no longer necessary to locate the address of the storage unit that needs to be evaluated for strength or weakness and to judge the state of the storage unit, saving judgment time.

[0095] In another embodiment of this application, in determining whether a storage unit meets the enhanced processing conditions, a state verification condition is executed first, followed by a write data time judgment condition. That is, the state verification condition is first used to determine whether the storage unit is in a weak or strong state, and then the write data time judgment condition is used to determine whether the write data time exceeds the write data time threshold. Specifically, steps S510-S560 are executed sequentially.

[0096] Figure 5 An exemplary flowchart illustrating a method for determining whether a storage unit meets enhanced processing conditions is shown in another embodiment of this application.

[0097] like Figure 5 As shown, in step S510, the address of the enhanced region is loaded into the resistive random access memory (RRAM), and the address of the enhanced region stored in the RRAM is incremented by 1 to obtain the address of the memory cell that needs to be determined for strength / weakness assessment. Next, in step S520, a state verification condition is used to determine whether the state of the memory cell is weak or strong. If the state of the memory cell is strong, in step S530, it is determined that the memory cell does not meet the enhancement processing condition, and the address of the memory cell is recorded. That is, when it is determined that the memory cell does not meet the enhancement processing condition, the address of the enhanced region stored in the RRAM, incremented by 1, is recorded. If the state of the memory cell is weak, in step S540, a write data time judgment condition is used to determine whether the write data time exceeds the write data time threshold. If the write data time exceeds the write data time threshold, it is determined that the memory cell does not meet the enhancement processing condition, and in step S550, the write data state machine is exited. If the write data time does not exceed the write data time threshold, in step S560, it is determined that the memory cell meets the enhancement processing condition.

[0098] Therefore, in this embodiment, the address of the enhanced region is loaded into the resistive random access memory (RRAM), and 1 is incremented by the enhanced region address stored in the RRAM to obtain the address of the memory cell that needs to be determined for strength / weakness assessment. First, it is determined whether the memory cell is in a weak or strong state. If the memory cell is in a strong state, it is directly determined that the memory cell does not meet the enhancement processing conditions. This eliminates the need to check whether the write time exceeds the write time threshold, saving assessment time.

[0099] In both embodiments above, during the process of determining whether a storage unit meets the enhancement processing conditions, regardless of whether the write data time judgment condition is executed first and then the state verification condition, or vice versa, before using the state verification condition to determine whether a storage unit meets the enhancement processing conditions, the enhancement region address is loaded into the resistive random access memory (RRAM), and the enhanced region address stored in the RRAM is incremented by 1. This allows direct location of the address of the storage unit currently requiring strength / weakness judgment. Therefore, when the state of the storage unit is subsequently determined to be strong, the address of the storage unit is recorded to provide a start address for the next enhancement processing operation.

[0100] In the two embodiments above, during the process of determining whether a storage unit meets the enhanced processing conditions, if the write data time exceeds the write data time threshold, it is determined that the enhanced processing conditions are not met, and the write data state machine is exited. This ensures that enhanced processing is only performed when there is sufficient write data time, thereby avoiding the problem of excessive system resource consumption or processing delays caused by excessively long write data times due to enhanced processing. Furthermore, it allows for full utilization of write data time, improving the efficiency of storage unit processing.

[0101] In the two embodiments above, during the process of determining whether a memory cell meets the enhancement processing conditions, if the memory cell is in a strong state, it is determined that the enhancement processing conditions are not met, and the address of the memory cell is recorded. When the memory cell is determined to be in a strong state, the memory cell does not need to undergo enhancement processing; that is, the memory cell is already in a strong state. By recording the address of the memory cell, a starting address can be provided for the next enhancement processing operation, ensuring that the strength determination and processing operation can traverse the addresses of all memory cells in the resistive random access memory, avoiding the need to reacquire the enhancement region address, thereby significantly improving the efficiency of the enhancement processing.

[0102] Specifically, in the two embodiments above, during the process of recording the address of the memory cell (i.e., recording the address after adding 1 to the address of the enhanced region stored in the resistive random access memory), the previously stored enhanced region address in the resistive random access memory is erased. Then, the address after adding 1 to the previously stored enhanced region address is recorded in a specific area of ​​the resistive random access memory. In other words, the enhanced region address stored in a specific area of ​​the resistive random access memory is updated based on the address of the memory cell whose latest state is determined to be strong. For example, when the enhanced region address stored in the resistive random access memory is 15, 1 is added to enhanced region address 15 to obtain address 16. When the state of the memory cell is determined to be strong, enhanced region address 15 stored in a specific area of ​​the resistive random access memory is erased, and address 16 is stored in the specific area of ​​the resistive random access memory.

[0103] By updating the enhanced region address stored in a specific area of ​​the resistive random access memory (RRAM), there is only one enhanced region address stored in that specific area of ​​the RRAM. This allows the enhanced region address to be loaded at a faster speed during subsequent enhancement processing.

[0104] In the embodiments of this application, the aforementioned weak state includes a first high-resistivity state and a first low-resistivity state.

[0105] During data erasure (or write operation), the charge of the memory cell is typically reduced. After erasing a memory cell, if the current in that cell is greater than the erase verification current but less than the edge erase verification current, it means the charge state of the cell is not low enough, and the cell's state is unstable. In this case, the cell cannot completely transition from the second low-resistance state to the second high-resistance state, and thus the cell's state can only be identified as the first high-resistance state.

[0106] When writing data to program data, the charge of the memory cell is typically increased. After performing a data programming operation on a memory cell, if the current of that cell is less than the programming verification current but greater than the edge programming verification current, it means that the charge state of the memory cell is not high enough, and the state of the memory cell is unstable. In this case, the memory cell cannot completely transition from the second high-resistance state to the second low-resistance state, and thus the state of the memory cell can only be identified as the first low-resistance state.

[0107] In embodiments of this application, the state verification conditions include: a first resistance state verification condition and a second resistance state verification condition. The first resistance state verification condition is used to verify that the memory cell is in a first high-resistance state or a second high-resistance state. The first resistance state verification condition includes a first erase verification condition and a first edge erase verification condition. The first erase verification condition may be whether the current of the memory cell is less than the erase verification current, and the first edge erase verification condition may be whether the current of the memory cell is less than the first edge erase verification current. The second resistance state verification condition is used to verify that the memory cell is in a first low-resistance state or a second low-resistance state. The second resistance state verification condition includes a first programming verification condition and a first edge programming verification condition. The programming verification condition may be whether the current of the memory cell is greater than the first programming verification current, and the first edge programming verification condition may be whether the current of the memory cell is greater than the first edge programming verification current.

[0108] During a data erase operation, the state of the memory cell is verified to be either a first high-impedance state or a second high-impedance state using a first resistance state verification condition. Specifically, the state of the memory cell is verified to be either a first high-impedance state or a second high-impedance state using a first erase verification condition and a first edge erase verification condition. Since the state of a memory cell is unstable after a data erase operation, a read operation on that memory cell will determine that the unstable state of the memory cell is normal. Therefore, verifying the state of each memory cell to be either a first high-impedance state or a second high-impedance state using the first erase verification condition and the first edge erase verification condition accurately identifies memory cells that are unstable after a data erase operation, avoiding misjudgments when reading memory cells that are unstable after a data erase operation.

[0109] During data writing operations, the state of the memory cell is verified to be either a first low-resistance state or a second low-resistance state using a second resistance state verification condition. Specifically, the state of the memory cell is verified to be either a first low-resistance state or a second low-resistance state using both a first programming verification condition and a first edge programming verification condition. Since the state of a memory cell is unstable after the data programming operation, when a read operation is performed on that memory cell, the unstable state is determined to be normal. Therefore, by verifying that the state of each memory cell is either a first low-resistance state or a second low-resistance state using both the first programming verification condition and the first edge programming verification condition, memory cells with unstable states after the data programming operation can be accurately identified, avoiding misjudgments when reading memory cells with unstable states after the data programming operation.

[0110] In response to the failure to meet the enhancement processing conditions, step S230 is executed, and no enhancement processing is performed on the storage unit. Specifically, as described in the two embodiments above, if it is determined that the write data time exceeds the write data time threshold, the write data state machine is exited. If it is determined that the state of the storage unit is strong, the address of the storage unit is recorded.

[0111] In response to the fulfillment of the enhancement processing conditions, the storage cell is enhanced in step S240.

[0112] In the embodiments of this application, during the enhanced processing of the storage cell, when the storage cell is in a first high-resistivity state, an enhanced erase operation is performed on the storage cell. Specifically, the enhanced erase operation refers to performing a second data erase operation on the storage cell that is in the first high-resistivity state after the data erase operation, so that the state of the storage cell in the first high-resistivity state changes to the second high-resistivity state.

[0113] Specifically, during the enhanced erase operation process, the voltage of the bit line (BL), the voltage of the word line (WL), the voltage of the source line (SL), and the pulse time can be set and adjusted according to actual needs.

[0114] In the embodiments of this application, during the enhancement processing of the storage cell, when the storage cell is in a first low-resistivity state, an enhancement programming operation is performed on the storage cell. Specifically, the enhancement programming operation refers to performing a second data programming operation on the storage cell in the first low-resistivity state after the data programming operation, so that the state of the storage cell in the first low-resistivity state changes to a second low-resistivity state.

[0115] Specifically, during the enhanced programming process, the voltage of the bit line (BL), the voltage of the word line (WL), the voltage of the source line (SL), and the pulse time can be set and adjusted according to actual needs.

[0116] By changing the state of a memory cell in a first high-resistivity state to a second high-resistivity state, or changing the state of a memory cell in a first low-resistivity state to a second low-resistivity state, the degradation problem of data in resistive random access memory (RRAM) during storage can be improved.

[0117] In the embodiments of this application, after the aforementioned storage unit is enhanced, the write data time judgment condition and the status verification condition are used to determine again whether the enhanced storage unit meets the enhanced processing conditions.

[0118] Specifically, the process of determining whether the enhanced storage cell meets the enhanced processing conditions again is the same as the determination process used in step S220 above, and will not be repeated here.

[0119] By re-evaluating whether the enhanced storage cell meets the enhanced processing conditions, it can be determined whether the enhanced processing step is effective, thus avoiding classifying a storage cell that is still in a weak state as a strong state when the enhanced processing step is ineffective.

[0120] In the embodiments of this application, in response to the storage cell meeting the enhancement processing conditions after enhancement processing, the step of enhancing the storage cell is returned, that is, step S240 is returned, until the enhancement processing conditions are no longer met.

[0121] Specifically, when it is determined that the enhancement processing condition is met, i.e. the enhancement processing is invalid, the process returns to the step of enhancing the storage unit and continues to enhance the storage unit. This ensures that the state of the storage unit after enhancement processing is indeed strong or that the write data time exceeds the write data time threshold before the enhancement processing ends.

[0122] In the embodiments of this application, if it is determined that the storage cell still does not meet the enhancement processing conditions after enhancement processing, no enhancement processing is performed on the storage cell. If it is determined that the write data time exceeds the write data time threshold, the write data state machine is exited. If it is determined that the state of the enhanced storage cell is strong, the address of the storage cell is recorded. Therefore, if it is determined that the write data time exceeds the write data time threshold, the write data state machine is exited, and the address of the storage cell is not recorded. Only when the state of the enhanced storage cell is strong is the enhanced region address corresponding to the storage cell recorded, providing a start address for the next enhancement processing operation, ensuring that the state of the storage cell corresponding to the recorded enhanced region address is strong.

[0123] In summary, by utilizing the above-described scheme for data retention in resistive random access memory (RRAM), this disclosed embodiment enhances the processing of memory cells whose write time does not exceed a write time threshold. This improves the degradation problem of RRAM data during storage without consuming write time, ensuring that enhancement processing is only performed when write time is sufficient. This avoids excessive system resource consumption or processing delays caused by excessive write time due to enhancement processing, and fully utilizes write time, improving the efficiency of memory cell processing. Furthermore, in some embodiments, before using state verification conditions to determine whether a memory cell meets the enhancement processing conditions, an enhancement region address is loaded into the RRAM, and this enhancement region address is incremented by 1, enabling the location of the memory cell currently requiring strength / weakness assessment. Furthermore, in some embodiments, when the state of the memory cell is determined to be strong, the address of the memory cell is recorded. This can provide a start address for the next strengthening process operation, so that memory cells that meet the strengthening process conditions can be strengthened in sequence. This ensures that the strength judgment and strengthening process operation can traverse the addresses of all memory cells in the resistive random access memory, avoiding the need to reacquire the strengthening region address, thereby significantly improving the efficiency of the strengthening process.

[0124] The above describes some implementation methods of this application using resistive random access memory as an example. According to other implementation methods of this application, the non-volatile two-terminal memory is a polarization state memory, and the state verification conditions include: a first polarization state verification condition and a second polarization state verification condition. The first polarization state verification condition is used to verify that the memory cell is a first negative polarization state or a second negative polarization state, and the second polarization state verification condition is used to verify that the memory cell is a first positive polarization state or a second positive polarization state.

[0125] According to one embodiment of this application, the first polarization state verification condition includes a second erase verification condition (e.g., Figure 1c P0 as shown) and the second edge erasure verification condition (e.g. Figure 1c As shown in MP0), the polarization of the memory cell in the first negative polarization state is between the second erase verification polarization and the second edge erase verification polarization.

[0126] According to one embodiment of this application, the second polarization state verification condition includes a second programming verification condition (e.g., as shown in the figure). Figure 1c P1 as shown) and the second edge programming verification condition (e.g. Figure 1c As shown in MP1), the polarization of the memory cell in the first positive polarization state is between the second programming verification polarization and the second edge programming verification polarization.

[0127] According to one embodiment of this application, strengthening the storage cell includes: when the storage cell is in a first negative polarization state, performing a strengthened erase operation on the storage cell; and when the storage cell is in a first positive polarization state, performing a strengthened programming operation on the storage cell.

[0128] According to one embodiment of this application, the polarization state memory includes a ferroelectric random access memory (FeRAM).

[0129] It should be understood that in this application, the negative polarization state representation memory cell stores "0" and the positive polarization state representation memory cell stores "1". However, this is just an example. Those skilled in the art can also store "1" in the negative polarization state representation memory cell and "0" in the positive polarization state representation memory cell.

[0130] The resistive random access memory has already been described in detail above, so the description of polarized state memory will be omitted here.

[0131] Figure 6 An exemplary structural block diagram of an apparatus 600 for non-volatile end-to-end memory data retention according to an embodiment of this application is shown.

[0132] like Figure 6 As shown, the device 600 includes a processor 610 and a memory 620. The memory 620 may include, but is not limited to, resistive random access memory (RRAM), polarized memory, dynamic random access memory (DRAM), static random access memory (SRAM), and enhanced dynamic random access memory (EDRAM). The processor 610 may include, for example, a general-purpose processor (“CPU”), a dedicated graphics processor (“GPU”), or a microcontroller (“MCU”). The memory 620 stores at least a computer program, which is executed by the processor 610 to implement the method 200 for non-volatile end-memory data retention as described above. Since this method has been described in detail above, it will not be repeated here.

[0133] In another aspect of the invention, a computer storage medium is also provided, on which a computer program for non-volatile end-to-end memory data retention is stored, the instructions of which are executed by one or more processors to implement the method 200 for non-volatile end-to-end memory data retention as described above. Specifically, the aforementioned readable storage medium can be any tangible medium containing or storing a program that can be used or combined with an instruction execution system, apparatus, or device. For example, the computer-readable storage medium can be any suitable magnetic or magneto-optical storage medium, such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), etc., or any other medium that can be used to store desired information and can be accessed by an application program, module, or both. Any such computer storage medium may be part of a device or accessible to or connected to a device. Any application or module described in this invention may be implemented using computer-readable / executable instructions that may be stored or otherwise maintained by such a computer-readable medium.

[0134] Figure 7 An exemplary structural block diagram of a system 700 according to an embodiment of this application is shown.

[0135] like Figure 7 As shown, system 700 includes a data writing module 710, a judgment module 720, and an enhanced processing module 730.

[0136] Specifically, the data writing system 700 can employ application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), microcontroller units (MCUs), or digital signal processors (DSPs), etc.

[0137] In the embodiments of this application, the write data module 710 is used to start the write data state machine and write data to the storage unit in the non-volatile dual-end memory through the write data state machine, wherein the non-volatile dual-end memory stores the enhanced region address.

[0138] In the embodiments of this application, the judgment module 720 can be connected to the write data module 710. The judgment module 720 is used to determine whether the storage unit meets the enhanced processing conditions, wherein the enhanced processing conditions include: the write data time does not exceed the write data time threshold.

[0139] In an embodiment of this application, the enhancement processing module 730 can be connected to the judgment module 720. In response to the satisfaction of the enhancement processing conditions, the enhancement processing module is used to perform enhancement processing on the storage unit.

[0140] Specifically, the data writing module 710, the judgment module 720, and the enhancement processing module 730 can be integrated into a single integrated circuit or connected as independent units.

[0141] In one embodiment of this application, the write data system 700 may execute a method 200 for maintaining data in a non-volatile dual-ended memory as described in any embodiment of this application. In other embodiments of this application, the write data system 700 may also execute other methods for maintaining data in a non-volatile dual-ended memory, which are not limited herein.

[0142] Figure 8 An exemplary structural block diagram of a non-volatile dual-end memory electronic operating environment 800 according to an embodiment of this application is shown.

[0143] like Figure 8 As shown, the electronic operating environment 800 can be formed within a single semiconductor die, but this disclosure is not limited thereto, and in other embodiments, some components of the electronic operating environment 800 can be formed on separate semiconductor dies.

[0144] The electronic operating environment 800 may include the aforementioned memory 620, column controller 810, sense amplifier 820, reference and control signal generator 830, row controller 840, input / output buffer 850, clock source 860, address register 870, write data state machine 880, and command interface 890.

[0145] Specifically, column controller 810 and sense amplifier 820 may be adjacent to memory 620. Column controller 810 may be configured to activate (or identify to activate) a subset of bit lines of memory 620. Column controller 810 may utilize control signals provided by reference and control signal generator 830 to activate and operate corresponding bit lines in the subset of bit lines, applying appropriate program, erase, or read voltages to these bit lines. Inactive bit lines in memory 620 may be maintained at a suppression voltage (also applied by reference and control signal generator 830) to mitigate or avoid bit interference effects on these inactive bit lines.

[0146] Specifically, the row controller 840 can be adjacent to and electrically connected to the word lines of the memory 620. Utilizing control signals from the reference and control signal generator 830, the row controller 840 can select a specific row of the memory cell with an appropriate selection voltage. Furthermore, the row controller 840 can facilitate programming, erasing, or reading operations by applying an appropriate voltage at the selected word line.

[0147] Specifically, the sensing amplifier 820 can read data from or write data to the active memory cell of the memory 620 selected by the column controller 810 and the row controller 840. Data read from the memory 620 can be provided to the input / output buffer 850. Similarly, data to be written to the memory 620 can be received from the input / output buffer 850 and written to the active memory cell of the memory 620.

[0148] Specifically, clock source 860 can provide corresponding clock pulses to facilitate the timing of read, write, and programming operations of row controller 840 and column controller 810. Clock source 860 can respond to external or internal commands received by electronic operating environment 800, further facilitating word line or bit line selection. Input / output buffer 850 can include command and address inputs, as well as bidirectional data inputs and outputs. Instructions are provided via command and address inputs, and data to be written to memory 620 and data read from memory 620 are transferred on bidirectional data inputs and outputs, thereby facilitating connection to external host devices such as device 600.

[0149] Specifically, the input / output buffer 850 can be configured to receive write data, receive erase commands, receive status or maintenance commands, output read data, output status information, receive address data and command data, and address data of corresponding commands. Address data can be transferred to the row controller 840 and column controller 810 via the address register 870. Furthermore, input data is transferred to the memory 620 via the signal input line between the sense amplifier 820 and the input / output buffer 850, and output data is received from the memory 620 via the signal output line from the sense amplifier 820 to the input / output buffer 850. Input data can be received from a host device such as device 600, and output data can be transferred to the host device such as device 600 via the I / O bus.

[0150] Specifically, commands received from a host device such as device 600 can be provided to command interface 890. Command interface 890 can be configured to receive external control signals from a host device such as device 600 and determine whether the data input to input / output buffer 850 is write data, a command, or an address. Input commands can be transmitted to write data state machine 880.

[0151] Specifically, the write data state machine 880 manages the write data process of the non-volatile dual-ended memory and other functions related to the non-volatile dual-ended memory. Specifically, the write data process includes data programming, data erasure, data recovery, and recording of reinforced region addresses. During data programming and data erasure, verification conditions can be used to verify the state of each memory cell and the write data time. Reinforcement operations can also be performed on memory cells in a weak state. Other functions related to the non-volatile dual-ended memory include data reading, data writing, data input, and data output. In some aspects, the write data state machine 880 can send and receive acknowledgments and denials regarding the successful reception or execution of various commands. In a further embodiment, the write data state machine 880 can decode and implement state-related commands, decode and implement configuration commands, etc.

[0152] Specifically, to implement functions such as read, write, erase, program, input, and output, the write data state machine 880 can control the clock source 860 or the reference and control signal generator 830. Control of the clock source 860 can generate output pulses configured to facilitate specific functions of the row controller 840 and column controller 810. For example, the output pulses can be transmitted to selected bit lines via the column controller 810. Similarly, the output pulses can be transmitted to selected word lines via the row controller 840.

[0153] While numerous embodiments of this disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and intent of this disclosure. It should be understood that various alternatives to the embodiments of this disclosure described herein may be employed in the practice of this disclosure. The appended claims are intended to define the scope of this disclosure and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for data retention in a non-volatile two-dimensional memory, characterized in that, The method includes: Start the write data state machine, and write data to the storage unit in the non-volatile two-end memory through the write data state machine; The write data time judgment condition is used to determine whether the storage unit meets the enhanced processing conditions. The write data time judgment condition is used to determine whether the write data time of the storage unit exceeds the write data time threshold. The storage unit satisfies the enhanced processing condition as follows: the write data time of the storage unit does not exceed the write data time threshold. In response to the fulfillment of the enhancement processing conditions, the storage unit is subjected to enhancement processing; The state verification condition is used to determine whether the storage cell meets the enhanced processing condition. The state verification condition is used to determine whether the state of the storage cell is weak or strong. The storage unit satisfies the enhanced processing condition as follows: the state of the storage unit is weak.

2. The method according to claim 1, characterized in that, In determining whether a storage unit meets the enhanced processing conditions, the write data time judgment condition is executed first, followed by the status verification condition.

3. The method according to claim 1, characterized in that, In determining whether a storage unit meets the enhanced processing conditions, the status verification condition is executed first, followed by the write data time judgment condition.

4. The method according to any one of claims 1-3, characterized in that, After enhancing the storage unit, the following steps are performed: The enhanced storage unit is then reassessed to determine whether it meets the enhanced processing conditions. In response to the fulfillment of the enhancement processing condition, the step of performing enhancement processing on the storage cell is returned until the storage cell no longer meets the enhancement processing condition.

5. The method according to claim 4, characterized in that, The non-volatile two-terminal memory stores the address of the enhanced region; A state verification condition is used to determine whether the storage unit meets the enhanced processing condition. The state verification condition is used to determine whether the state of the storage unit is weak or strong. Before using state verification conditions to determine whether the storage cell meets the enhanced processing conditions, the enhanced region address is loaded into the non-volatile end-to-end memory, and the enhanced region address stored in the non-volatile end-to-end memory is incremented by 1 to obtain the address of the storage cell.

6. The method according to claim 5, characterized in that, When the state of the storage unit is strong, the address of the storage unit is recorded.

7. The method according to claim 1, characterized in that, The method further includes: exiting the write data state machine in response to the failure to meet the enhanced processing conditions.

8. The method according to claim 1, characterized in that, The state verification conditions include: a first storage state verification condition and a second storage state verification condition. The first storage state verification condition is used to verify that the storage cell is in a first high state or a second high state, and the second storage state verification condition is used to verify that the storage cell is in a first low state or a second low state.

9. The method according to claim 8, characterized in that, The non-volatile two-terminal memory is a resistive variable memory, and the state verification conditions include: a first resistive state verification condition and a second resistive state verification condition. The first resistive state verification condition is used to verify that the memory cell is in a first high-resistance state or a second high-resistance state, and the second resistive state verification condition is used to verify that the memory cell is in a first low-resistance state or a second low-resistance state.

10. The method according to claim 9, characterized in that, The first resistance state verification condition includes a first erase verification condition and a first edge erase verification condition. The current of the memory cell in the first high resistance state is greater than the first erase verification current and less than the first edge erase verification current.

11. The method according to claim 9, characterized in that, The second resistance state verification condition includes a first programming verification condition and a first edge programming verification condition. The current of the memory cell in the first low resistance state is less than the first programming verification current and greater than the first edge programming verification current.

12. The method according to claim 9, characterized in that, The enhancement process for the storage unit includes: When the state of the memory cell is the first high-resistivity state, an enhanced erase operation is performed on the memory cell; When the memory cell is in the first low-resistance state, the memory cell is subjected to enhanced programming operations.

13. The method according to any one of claims 9-12, characterized in that, The resistive switching memory includes one or more of the following: resistive switching memory, phase change memory, magnetoresistive memory, and conductive bridge memory.

14. The method according to claim 8, characterized in that, The non-volatile two-terminal memory is a polarized state memory, and the state verification conditions include: a first polarized state verification condition and a second polarized state verification condition. The first polarized state verification condition is used to verify that the memory cell is a first negative polarized state or a second negative polarized state, and the second polarized state verification condition is used to verify that the memory cell is a first positive polarized state or a second positive polarized state.

15. The method according to claim 14, characterized in that, The first polarization state verification condition includes a second erase verification condition and a second edge erase verification condition. The polarization of the memory cell in the first negative polarization state is between the second erase verification polarization and the second edge erase verification polarization.

16. The method according to claim 14, characterized in that, The second polarization state verification condition includes a second programming verification condition and a second edge programming verification condition. The polarization of the memory cell in the first positive polarization state is between the second programming verification polarization and the second edge programming verification polarization.

17. The method according to claim 14, characterized in that, The enhancement process for the storage unit includes: When the state of the memory cell is the first negative polarization state, the memory cell is subjected to an enhanced erase operation. When the state of the memory cell is the first positive polarization state, the memory cell is subjected to enhanced programming operations.

18. The method according to any one of claims 14-17, characterized in that, The polarization state memory includes ferroelectric random access memory (FeRAM).

19. A device for storing data in a non-volatile dual-ended memory, characterized in that, include: processor; Memory, used to store computer programs; The processor is configured to execute the computer program to implement the method as described in any one of claims 1-18.

20. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by one or more processors, it implements the method as described in any one of claims 1-18.

21. A data writing system, characterized in that, The data writing system includes: A write data module is used to start a write data state machine and write data to a storage unit in a non-volatile two-terminal memory. The judgment module is used to determine whether the storage unit meets the enhanced processing conditions by using the write data time judgment condition. The write data time judgment condition is used to determine whether the write data time of the storage unit exceeds the write data time threshold. The storage unit meets the enhanced processing conditions including: the write data time of the storage unit does not exceed the write data time threshold. An enhancement processing module, in response to meeting enhancement processing conditions, is used to perform enhancement processing on the storage unit; The enhancement processing module is specifically used to: determine whether the storage unit meets the enhancement processing conditions using state verification conditions, wherein the state verification conditions are used to determine whether the state of the storage unit is weak or strong; the storage unit meeting the enhancement processing conditions includes: the state of the storage unit is weak.

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